1 /* Target-dependent code for Hitachi Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 Contributed by Steve Chamberlain
37 #include "inferior.h" /* for BEFORE_TEXT_END etc. */
38 #include "gdb_string.h"
39 #include "arch-utils.h"
40 #include "floatformat.h"
46 #include "solib-svr4.h"
51 /* registers numbers shared with the simulator */
52 #include "gdb/sim-sh64.h"
55 #define XMALLOC(TYPE) ((TYPE*) xmalloc (sizeof (TYPE)))
57 void (*sh_show_regs
) (void);
58 CORE_ADDR (*skip_prologue_hard_way
) (CORE_ADDR
);
59 void (*do_pseudo_register
) (int);
61 #define SH_DEFAULT_NUM_REGS 59
63 /* Define other aspects of the stack frame.
64 we keep a copy of the worked out return pc lying around, since it
65 is a useful bit of info */
67 struct frame_extra_info
75 sh_generic_register_name (int reg_nr
)
77 static char *register_names
[] =
79 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
80 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
81 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
83 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
84 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
86 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
87 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
91 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
93 return register_names
[reg_nr
];
97 sh_sh_register_name (int reg_nr
)
99 static char *register_names
[] =
101 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
102 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
103 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
105 "", "", "", "", "", "", "", "",
106 "", "", "", "", "", "", "", "",
108 "", "", "", "", "", "", "", "",
109 "", "", "", "", "", "", "", "",
113 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
115 return register_names
[reg_nr
];
119 sh_sh3_register_name (int reg_nr
)
121 static char *register_names
[] =
123 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
124 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
125 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
127 "", "", "", "", "", "", "", "",
128 "", "", "", "", "", "", "", "",
130 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
131 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
135 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
137 return register_names
[reg_nr
];
141 sh_sh3e_register_name (int reg_nr
)
143 static char *register_names
[] =
145 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
146 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
147 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
149 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
150 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
152 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
153 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
157 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
159 return register_names
[reg_nr
];
163 sh_sh_dsp_register_name (int reg_nr
)
165 static char *register_names
[] =
167 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
168 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
169 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
171 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
172 "y0", "y1", "", "", "", "", "", "mod",
174 "rs", "re", "", "", "", "", "", "",
175 "", "", "", "", "", "", "", "",
179 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
181 return register_names
[reg_nr
];
185 sh_sh3_dsp_register_name (int reg_nr
)
187 static char *register_names
[] =
189 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
190 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
191 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
193 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
194 "y0", "y1", "", "", "", "", "", "mod",
196 "rs", "re", "", "", "", "", "", "",
197 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
198 "", "", "", "", "", "", "", "",
202 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
204 return register_names
[reg_nr
];
208 sh_sh4_register_name (int reg_nr
)
210 static char *register_names
[] =
212 /* general registers 0-15 */
213 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
214 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
216 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
219 /* floating point registers 25 - 40 */
220 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
221 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
225 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
227 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
228 /* double precision (pseudo) 59 - 66 */
229 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
230 /* vectors (pseudo) 67 - 70 */
231 "fv0", "fv4", "fv8", "fv12",
232 /* FIXME: missing XF 71 - 86 */
233 /* FIXME: missing XD 87 - 94 */
237 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
239 return register_names
[reg_nr
];
243 sh_sh64_register_name (int reg_nr
)
245 static char *register_names
[] =
247 /* SH MEDIA MODE (ISA 32) */
248 /* general registers (64-bit) 0-63 */
249 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
250 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
251 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
252 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
253 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
254 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
255 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
256 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
261 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
264 /* target registers (64-bit) 68-75*/
265 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
267 /* floating point state control register (32-bit) 76 */
270 /* single precision floating point registers (32-bit) 77-140*/
271 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
272 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
273 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
274 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
275 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
276 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
277 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
278 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
280 /* double precision registers (pseudo) 141-172 */
281 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
282 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
283 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
284 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
286 /* floating point pairs (pseudo) 173-204*/
287 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
288 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
289 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
290 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
292 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
293 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
294 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
296 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
297 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
298 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
300 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
302 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
303 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
304 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
305 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
306 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
311 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
313 return register_names
[reg_nr
];
316 #define NUM_PSEUDO_REGS_SH_MEDIA 80
317 #define NUM_PSEUDO_REGS_SH_COMPACT 51
319 static const unsigned char *
320 sh_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
322 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
323 static unsigned char breakpoint
[] = {0xc3, 0xc3};
325 *lenptr
= sizeof (breakpoint
);
329 /* Macros and functions for setting and testing a bit in a minimal
330 symbol that marks it as 32-bit function. The MSB of the minimal
331 symbol's "info" field is used for this purpose. This field is
332 already being used to store the symbol size, so the assumption is
333 that the symbol size cannot exceed 2^31.
335 ELF_MAKE_MSYMBOL_SPECIAL
336 tests whether an ELF symbol is "special", i.e. refers
337 to a 32-bit function, and sets a "special" bit in a
338 minimal symbol to mark it as a 32-bit function
339 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol
340 MSYMBOL_SIZE returns the size of the minimal symbol, i.e.
341 the "info" field with the "special" bit masked out */
343 #define MSYMBOL_IS_SPECIAL(msym) \
344 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
347 sh64_elf_make_msymbol_special (asymbol
*sym
, struct minimal_symbol
*msym
)
352 if (((elf_symbol_type
*)(sym
))->internal_elf_sym
.st_other
== STO_SH5_ISA32
)
354 MSYMBOL_INFO (msym
) = (char *) (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
355 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
359 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
360 are some macros to test, set, or clear bit 0 of addresses. */
361 #define IS_ISA32_ADDR(addr) ((addr) & 1)
362 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
363 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
366 pc_is_isa32 (bfd_vma memaddr
)
368 struct minimal_symbol
*sym
;
370 /* If bit 0 of the address is set, assume this is a
371 ISA32 (shmedia) address. */
372 if (IS_ISA32_ADDR (memaddr
))
375 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
376 the high bit of the info field. Use this to decide if the function is
378 sym
= lookup_minimal_symbol_by_pc (memaddr
);
380 return MSYMBOL_IS_SPECIAL (sym
);
385 static const unsigned char *
386 sh_sh64_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
388 /* The BRK instruction for shmedia is
389 01101111 11110101 11111111 11110000
390 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
391 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
393 /* The BRK instruction for shcompact is
395 which translates in big endian mode to 0x0, 0x3b
396 and in little endian mode to 0x3b, 0x0*/
398 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
400 if (pc_is_isa32 (*pcptr
))
402 static unsigned char big_breakpoint_media
[] = {0x6f, 0xf5, 0xff, 0xf0};
403 *pcptr
= UNMAKE_ISA32_ADDR (*pcptr
);
404 *lenptr
= sizeof (big_breakpoint_media
);
405 return big_breakpoint_media
;
409 static unsigned char big_breakpoint_compact
[] = {0x0, 0x3b};
410 *lenptr
= sizeof (big_breakpoint_compact
);
411 return big_breakpoint_compact
;
416 if (pc_is_isa32 (*pcptr
))
418 static unsigned char little_breakpoint_media
[] = {0xf0, 0xff, 0xf5, 0x6f};
419 *pcptr
= UNMAKE_ISA32_ADDR (*pcptr
);
420 *lenptr
= sizeof (little_breakpoint_media
);
421 return little_breakpoint_media
;
425 static unsigned char little_breakpoint_compact
[] = {0x3b, 0x0};
426 *lenptr
= sizeof (little_breakpoint_compact
);
427 return little_breakpoint_compact
;
432 /* Prologue looks like
433 [mov.l <regs>,@-r15]...
438 Actually it can be more complicated than this. For instance, with
456 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
457 with l=1 and n = 18 0110101111110001010010100aaa0000 */
458 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
460 /* STS.L PR,@-r0 0100000000100010
461 r0-4-->r0, PR-->(r0) */
462 #define IS_STS_R0(x) ((x) == 0x4022)
464 /* STS PR, Rm 0000mmmm00101010
466 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
468 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
470 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
472 /* MOV.L R14,@(disp,r15) 000111111110dddd
473 R14-->(dispx4+r15) */
474 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
476 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
477 R18-->(dispx8+R14) */
478 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
480 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
481 R18-->(dispx8+R15) */
482 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
484 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
485 R18-->(dispx4+R15) */
486 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
488 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
489 R14-->(dispx8+R15) */
490 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
492 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
493 R14-->(dispx4+R15) */
494 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
496 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
498 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
500 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
502 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
504 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
506 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
508 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
510 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
512 #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
514 /* MOV #imm, R0 1110 0000 ssss ssss
516 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
518 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
519 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
521 /* ADD r15,r0 0011 0000 1111 1100
523 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
525 /* MOV.L R14 @-R0 0010 0000 1110 0110
526 R14-->(R0-4), R0-4-->R0 */
527 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
529 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
530 where Rm is one of r2-r9 which are the argument registers. */
531 /* FIXME: Recognize the float and double register moves too! */
532 #define IS_MEDIA_IND_ARG_MOV(x) \
533 ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
535 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
536 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
537 where Rm is one of r2-r9 which are the argument registers. */
538 #define IS_MEDIA_ARG_MOV(x) \
539 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
540 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
542 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
543 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
544 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
545 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
546 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
547 #define IS_MEDIA_MOV_TO_R14(x) \
548 ((((x) & 0xfffffc0f) == 0xa0e00000) \
549 || (((x) & 0xfffffc0f) == 0xa4e00000) \
550 || (((x) & 0xfffffc0f) == 0xa8e00000) \
551 || (((x) & 0xfffffc0f) == 0xb4e00000) \
552 || (((x) & 0xfffffc0f) == 0xbce00000))
554 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
556 #define IS_COMPACT_IND_ARG_MOV(x) \
557 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
559 /* compact direct arg move!
560 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
561 #define IS_COMPACT_ARG_MOV(x) \
562 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
564 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
565 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
566 #define IS_COMPACT_MOV_TO_R14(x) \
567 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
569 #define IS_JSR_R0(x) ((x) == 0x400b)
570 #define IS_NOP(x) ((x) == 0x0009)
573 /* STS.L PR,@-r15 0100111100100010
574 r15-4-->r15, PR-->(r15) */
575 #define IS_STS(x) ((x) == 0x4f22)
577 /* MOV.L Rm,@-r15 00101111mmmm0110
578 r15-4-->r15, Rm-->(R15) */
579 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
581 #define GET_PUSHED_REG(x) (((x) >> 4) & 0xf)
583 /* MOV r15,r14 0110111011110011
585 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
587 /* ADD #imm,r15 01111111iiiiiiii
589 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
591 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
592 #define IS_SHLL_R3(x) ((x) == 0x4300)
594 /* ADD r3,r15 0011111100111100
596 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
598 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
599 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
600 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
601 #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b)
603 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011
604 MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd
605 MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010
606 where Rm is one of r4,r5,r6,r7 which are the argument registers. */
607 #define IS_ARG_MOV(x) \
608 (((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
609 || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
610 || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)))
612 /* MOV.L Rm,@(disp,r14) 00011110mmmmdddd
613 Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */
614 #define IS_MOV_TO_R14(x) \
615 ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))
617 #define FPSCR_SZ (1 << 20)
619 /* Skip any prologue before the guts of a function */
621 /* Skip the prologue using the debug information. If this fails we'll
622 fall back on the 'guess' method below. */
624 after_prologue (CORE_ADDR pc
)
626 struct symtab_and_line sal
;
627 CORE_ADDR func_addr
, func_end
;
629 /* If we can not find the symbol in the partial symbol table, then
630 there is no hope we can determine the function's start address
632 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
635 /* Get the line associated with FUNC_ADDR. */
636 sal
= find_pc_line (func_addr
, 0);
638 /* There are only two cases to consider. First, the end of the source line
639 is within the function bounds. In that case we return the end of the
640 source line. Second is the end of the source line extends beyond the
641 bounds of the current function. We need to use the slow code to
642 examine instructions in that case. */
643 if (sal
.end
< func_end
)
649 /* Here we look at each instruction in the function, and try to guess
650 where the prologue ends. Unfortunately this is not always
653 sh_skip_prologue_hard_way (CORE_ADDR start_pc
)
661 for (here
= start_pc
, end
= start_pc
+ (2 * 28); here
< end
;)
663 int w
= read_memory_integer (here
, 2);
665 if (IS_FMOV (w
) || IS_PUSH (w
) || IS_STS (w
) || IS_MOV_R3 (w
)
666 || IS_ADD_R3SP (w
) || IS_ADD_SP (w
) || IS_SHLL_R3 (w
)
667 || IS_ARG_MOV (w
) || IS_MOV_TO_R14 (w
))
671 else if (IS_MOV_SP_FP (w
))
677 /* Don't bail out yet, if we are before the copy of sp. */
686 look_for_args_moves (CORE_ADDR start_pc
, int media_mode
)
690 int insn_size
= (media_mode
? 4 : 2);
692 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
696 w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
), insn_size
);
698 if (IS_MEDIA_IND_ARG_MOV (w
))
700 /* This must be followed by a store to r14, so the argument
701 is where the debug info says it is. This can happen after
702 the SP has been saved, unfortunately. */
704 int next_insn
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
707 if (IS_MEDIA_MOV_TO_R14 (next_insn
))
710 else if (IS_MEDIA_ARG_MOV (w
))
712 /* These instructions store directly the argument in r14. */
720 w
= read_memory_integer (here
, insn_size
);
723 if (IS_COMPACT_IND_ARG_MOV (w
))
725 /* This must be followed by a store to r14, so the argument
726 is where the debug info says it is. This can happen after
727 the SP has been saved, unfortunately. */
729 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
);
731 if (IS_COMPACT_MOV_TO_R14 (next_insn
))
734 else if (IS_COMPACT_ARG_MOV (w
))
736 /* These instructions store directly the argument in r14. */
739 else if (IS_MOVL_R0 (w
))
741 /* There is a function that gcc calls to get the arguments
742 passed correctly to the function. Only after this
743 function call the arguments will be found at the place
744 where they are supposed to be. This happens in case the
745 argument has to be stored into a 64-bit register (for
746 instance doubles, long longs). SHcompact doesn't have
747 access to the full 64-bits, so we store the register in
748 stack slot and store the address of the stack slot in
749 the register, then do a call through a wrapper that
750 loads the memory value into the register. A SHcompact
751 callee calls an argument decoder
752 (GCC_shcompact_incoming_args) that stores the 64-bit
753 value in a stack slot and stores the address of the
754 stack slot in the register. GCC thinks the argument is
755 just passed by transparent reference, but this is only
756 true after the argument decoder is called. Such a call
757 needs to be considered part of the prologue. */
759 /* This must be followed by a JSR @r0 instruction and by
760 a NOP instruction. After these, the prologue is over! */
762 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
);
764 if (IS_JSR_R0 (next_insn
))
766 next_insn
= 0xffff & read_memory_integer (here
, insn_size
);
769 if (IS_NOP (next_insn
))
782 sh64_skip_prologue_hard_way (CORE_ADDR start_pc
)
792 if (pc_is_isa32 (start_pc
) == 0)
798 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
803 int w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
), insn_size
);
805 if (IS_STQ_R18_R14 (w
) || IS_STQ_R18_R15 (w
) || IS_STQ_R14_R15 (w
)
806 || IS_STL_R14_R15 (w
) || IS_STL_R18_R15 (w
)
807 || IS_ADDIL_SP_MEDIA (w
) || IS_ADDI_SP_MEDIA (w
) || IS_PTABSL_R18 (w
))
811 else if (IS_MOV_SP_FP (w
) || IS_MOV_SP_FP_MEDIA(w
))
819 /* Don't bail out yet, we may have arguments stored in
820 registers here, according to the debug info, so that
821 gdb can print the frames correctly. */
822 start_pc
= look_for_args_moves (here
- insn_size
, media_mode
);
828 int w
= 0xffff & read_memory_integer (here
, insn_size
);
831 if (IS_STS_R0 (w
) || IS_STS_PR (w
)
832 || IS_MOV_TO_R15 (w
) || IS_MOV_R14 (w
)
833 || IS_MOV_R0 (w
) || IS_ADD_SP_R0 (w
) || IS_MOV_R14_R0 (w
))
837 else if (IS_MOV_SP_FP (w
))
845 /* Don't bail out yet, we may have arguments stored in
846 registers here, according to the debug info, so that
847 gdb can print the frames correctly. */
848 start_pc
= look_for_args_moves (here
- insn_size
, media_mode
);
858 sh_skip_prologue (CORE_ADDR pc
)
860 CORE_ADDR post_prologue_pc
;
862 /* See if we can determine the end of the prologue via the symbol table.
863 If so, then return either PC, or the PC after the prologue, whichever
865 post_prologue_pc
= after_prologue (pc
);
867 /* If after_prologue returned a useful address, then use it. Else
868 fall back on the instruction skipping code. */
869 if (post_prologue_pc
!= 0)
870 return max (pc
, post_prologue_pc
);
872 return (skip_prologue_hard_way (pc
));
875 /* Immediately after a function call, return the saved pc.
876 Can't always go through the frames for this because on some machines
877 the new frame is not set up until the new function executes
880 The return address is the value saved in the PR register + 4 */
882 sh_saved_pc_after_call (struct frame_info
*frame
)
884 return (ADDR_BITS_REMOVE (read_register (gdbarch_tdep (current_gdbarch
)->PR_REGNUM
)));
887 /* Should call_function allocate stack space for a struct return? */
889 sh_use_struct_convention (int gcc_p
, struct type
*type
)
891 return (TYPE_LENGTH (type
) > 1);
895 sh64_use_struct_convention (int gcc_p
, struct type
*type
)
897 return (TYPE_LENGTH (type
) > 8);
900 /* Store the address of the place in which to copy the structure the
901 subroutine will return. This is called from call_function.
903 We store structs through a pointer passed in R2 */
905 sh_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
907 write_register (STRUCT_RETURN_REGNUM
, (addr
));
910 /* Disassemble an instruction. */
912 gdb_print_insn_sh (bfd_vma memaddr
, disassemble_info
*info
)
914 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
915 return print_insn_sh (memaddr
, info
);
917 return print_insn_shl (memaddr
, info
);
920 /* Disassemble an instruction. */
922 gdb_print_insn_sh64 (bfd_vma memaddr
, disassemble_info
*info
)
924 if (pc_is_isa32 (memaddr
))
926 /* Round down the instruction address to the appropriate boundary
927 before disassembling it. */
928 return print_insn_sh64x_media (UNMAKE_ISA32_ADDR (memaddr
), info
);
932 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
933 return print_insn_sh (memaddr
, info
);
935 return print_insn_shl (memaddr
, info
);
939 /* Given a GDB frame, determine the address of the calling function's frame.
940 This will be used to create a new GDB frame struct, and then
941 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
943 For us, the frame address is its stack pointer value, so we look up
944 the function prologue to determine the caller's sp value, and return it. */
946 sh_frame_chain (struct frame_info
*frame
)
948 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
949 return frame
->frame
; /* dummy frame same as caller's frame */
950 if (frame
->pc
&& !inside_entry_file (frame
->pc
))
951 return read_memory_integer (FRAME_FP (frame
) + frame
->extra_info
->f_offset
, 4);
956 /* Given a register number RN as it appears in an assembly
957 instruction, find the corresponding register number in the GDB
960 translate_insn_rn (int rn
, int media_mode
)
962 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
964 /* FIXME: this assumes that the number rn is for a not pseudo
970 /* These registers don't have a corresponding compact one. */
971 /* FIXME: This is probably not enough. */
973 if ((rn
>= 16 && rn
<= 63) || (rn
>= 93 && rn
<= 140))
976 if (rn
>= 0 && rn
<= tdep
->R0_C_REGNUM
)
977 return tdep
->R0_C_REGNUM
+ rn
;
984 sh64_frame_chain (struct frame_info
*frame
)
986 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
987 return frame
->frame
; /* dummy frame same as caller's frame */
988 if (frame
->pc
&& !inside_entry_file (frame
->pc
))
990 int media_mode
= pc_is_isa32 (frame
->pc
);
992 if (gdbarch_tdep (current_gdbarch
)->sh_abi
== SH_ABI_32
)
995 size
= REGISTER_RAW_SIZE (translate_insn_rn (FP_REGNUM
, media_mode
));
996 return read_memory_integer (FRAME_FP (frame
) + frame
->extra_info
->f_offset
, size
);
1002 /* Find REGNUM on the stack. Otherwise, it's in an active register. One thing
1003 we might want to do here is to check REGNUM against the clobber mask, and
1004 somehow flag it as invalid if it isn't saved on the stack somewhere. This
1005 would provide a graceful failure mode when trying to get the value of
1006 caller-saves registers for an inner frame. */
1008 sh_find_callers_reg (struct frame_info
*fi
, int regnum
)
1010 for (; fi
; fi
= fi
->next
)
1011 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1012 /* When the caller requests PR from the dummy frame, we return PC because
1013 that's where the previous routine appears to have done a call from. */
1014 return generic_read_register_dummy (fi
->pc
, fi
->frame
, regnum
);
1017 FRAME_INIT_SAVED_REGS (fi
);
1020 if (fi
->saved_regs
[regnum
] != 0)
1021 return read_memory_integer (fi
->saved_regs
[regnum
],
1022 REGISTER_RAW_SIZE (regnum
));
1024 return read_register (regnum
);
1028 sh64_get_saved_pr (struct frame_info
*fi
, int pr_regnum
)
1032 for (; fi
; fi
= fi
->next
)
1033 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1034 /* When the caller requests PR from the dummy frame, we return PC because
1035 that's where the previous routine appears to have done a call from. */
1036 return generic_read_register_dummy (fi
->pc
, fi
->frame
, pr_regnum
);
1039 FRAME_INIT_SAVED_REGS (fi
);
1043 media_mode
= pc_is_isa32 (fi
->pc
);
1045 if (fi
->saved_regs
[pr_regnum
] != 0)
1047 int gdb_reg_num
= translate_insn_rn (pr_regnum
, media_mode
);
1048 int size
= ((gdbarch_tdep (current_gdbarch
)->sh_abi
== SH_ABI_32
)
1050 : REGISTER_RAW_SIZE (gdb_reg_num
));
1051 return read_memory_integer (fi
->saved_regs
[pr_regnum
], size
);
1054 return read_register (pr_regnum
);
1057 /* Put here the code to store, into a struct frame_saved_regs, the
1058 addresses of the saved registers of frame described by FRAME_INFO.
1059 This includes special registers such as pc and fp saved in special
1060 ways in the stack frame. sp is even more special: the address we
1061 return for it IS the sp for the next frame. */
1063 sh_nofp_frame_init_saved_regs (struct frame_info
*fi
)
1065 int *where
= (int *) alloca ((NUM_REGS
+ NUM_PSEUDO_REGS
) * sizeof(int));
1073 char *dummy_regs
= generic_find_dummy_frame (fi
->pc
, fi
->frame
);
1075 if (fi
->saved_regs
== NULL
)
1076 frame_saved_regs_zalloc (fi
);
1078 memset (fi
->saved_regs
, 0, SIZEOF_FRAME_SAVED_REGS
);
1082 /* DANGER! This is ONLY going to work if the char buffer format of
1083 the saved registers is byte-for-byte identical to the
1084 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1085 memcpy (fi
->saved_regs
, dummy_regs
, sizeof (fi
->saved_regs
));
1089 fi
->extra_info
->leaf_function
= 1;
1090 fi
->extra_info
->f_offset
= 0;
1092 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1097 /* Loop around examining the prologue insns until we find something
1098 that does not appear to be part of the prologue. But give up
1099 after 20 of them, since we're getting silly then. */
1101 pc
= get_pc_function_start (fi
->pc
);
1108 for (opc
= pc
+ (2 * 28); pc
< opc
; pc
+= 2)
1110 insn
= read_memory_integer (pc
, 2);
1111 /* See where the registers will be saved to */
1114 rn
= GET_PUSHED_REG (insn
);
1118 else if (IS_STS (insn
))
1120 where
[gdbarch_tdep (current_gdbarch
)->PR_REGNUM
] = depth
;
1121 /* If we're storing the pr then this isn't a leaf */
1122 fi
->extra_info
->leaf_function
= 0;
1125 else if (IS_MOV_R3 (insn
))
1127 r3_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
1129 else if (IS_SHLL_R3 (insn
))
1133 else if (IS_ADD_R3SP (insn
))
1137 else if (IS_ADD_SP (insn
))
1139 depth
-= ((insn
& 0xff) ^ 0x80) - 0x80;
1141 else if (IS_MOV_SP_FP (insn
))
1143 #if 0 /* This used to just stop when it found an instruction that
1144 was not considered part of the prologue. Now, we just
1145 keep going looking for likely instructions. */
1151 /* Now we know how deep things are, we can work out their addresses */
1153 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1157 if (rn
== FP_REGNUM
)
1160 fi
->saved_regs
[rn
] = fi
->frame
- where
[rn
] + depth
- 4;
1164 fi
->saved_regs
[rn
] = 0;
1170 fi
->saved_regs
[SP_REGNUM
] = read_memory_integer (fi
->saved_regs
[FP_REGNUM
], 4);
1174 fi
->saved_regs
[SP_REGNUM
] = fi
->frame
- 4;
1177 fi
->extra_info
->f_offset
= depth
- where
[FP_REGNUM
] - 4;
1178 /* Work out the return pc - either from the saved pr or the pr
1182 /* For vectors of 4 floating point registers. */
1184 fv_reg_base_num (int fv_regnum
)
1188 fp_regnum
= FP0_REGNUM
+
1189 (fv_regnum
- gdbarch_tdep (current_gdbarch
)->FV0_REGNUM
) * 4;
1193 /* For double precision floating point registers, i.e 2 fp regs.*/
1195 dr_reg_base_num (int dr_regnum
)
1199 fp_regnum
= FP0_REGNUM
+
1200 (dr_regnum
- gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
) * 2;
1204 /* For pairs of floating point registers */
1206 fpp_reg_base_num (int fpp_regnum
)
1210 fp_regnum
= FP0_REGNUM
+
1211 (fpp_regnum
- gdbarch_tdep (current_gdbarch
)->FPP0_REGNUM
) * 2;
1216 is_media_pseudo (int rn
)
1218 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1220 return (rn
>= tdep
->DR0_REGNUM
1221 && rn
<= tdep
->FV_LAST_REGNUM
);
1225 sh64_get_gdb_regnum (int gcc_regnum
, CORE_ADDR pc
)
1227 return translate_insn_rn (gcc_regnum
, pc_is_isa32 (pc
));
1231 sh64_media_reg_base_num (int reg_nr
)
1233 int base_regnum
= -1;
1234 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1236 if (reg_nr
>= tdep
->DR0_REGNUM
1237 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
1238 base_regnum
= dr_reg_base_num (reg_nr
);
1240 else if (reg_nr
>= tdep
->FPP0_REGNUM
1241 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
1242 base_regnum
= fpp_reg_base_num (reg_nr
);
1244 else if (reg_nr
>= tdep
->FV0_REGNUM
1245 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
1246 base_regnum
= fv_reg_base_num (reg_nr
);
1253 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1254 GDB_REGNUM BASE_REGNUM
1314 sh64_compact_reg_base_num (int reg_nr
)
1316 int base_regnum
= -1;
1317 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1319 /* general register N maps to general register N */
1320 if (reg_nr
>= tdep
->R0_C_REGNUM
1321 && reg_nr
<= tdep
->R_LAST_C_REGNUM
)
1322 base_regnum
= reg_nr
- tdep
->R0_C_REGNUM
;
1324 /* floating point register N maps to floating point register N */
1325 else if (reg_nr
>= tdep
->FP0_C_REGNUM
1326 && reg_nr
<= tdep
->FP_LAST_C_REGNUM
)
1327 base_regnum
= reg_nr
- tdep
->FP0_C_REGNUM
+ FP0_REGNUM
;
1329 /* double prec register N maps to base regnum for double prec register N */
1330 else if (reg_nr
>= tdep
->DR0_C_REGNUM
1331 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
)
1332 base_regnum
= dr_reg_base_num (tdep
->DR0_REGNUM
1333 + reg_nr
- tdep
->DR0_C_REGNUM
);
1335 /* vector N maps to base regnum for vector register N */
1336 else if (reg_nr
>= tdep
->FV0_C_REGNUM
1337 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
1338 base_regnum
= fv_reg_base_num (tdep
->FV0_REGNUM
1339 + reg_nr
- tdep
->FV0_C_REGNUM
);
1341 else if (reg_nr
== tdep
->PC_C_REGNUM
)
1342 base_regnum
= PC_REGNUM
;
1344 else if (reg_nr
== tdep
->GBR_C_REGNUM
)
1347 else if (reg_nr
== tdep
->MACH_C_REGNUM
1348 || reg_nr
== tdep
->MACL_C_REGNUM
)
1351 else if (reg_nr
== tdep
->PR_C_REGNUM
)
1354 else if (reg_nr
== tdep
->T_C_REGNUM
)
1357 else if (reg_nr
== tdep
->FPSCR_C_REGNUM
)
1358 base_regnum
= tdep
->FPSCR_REGNUM
; /*???? this register is a mess. */
1360 else if (reg_nr
== tdep
->FPUL_C_REGNUM
)
1361 base_regnum
= FP0_REGNUM
+ 32;
1366 /* Given a register number RN (according to the gdb scheme) , return
1367 its corresponding architectural register. In media mode, only a
1368 subset of the registers is pseudo registers. For compact mode, all
1369 the registers are pseudo. */
1371 translate_rn_to_arch_reg_num (int rn
, int media_mode
)
1376 if (!is_media_pseudo (rn
))
1379 return sh64_media_reg_base_num (rn
);
1382 /* All compact registers are pseudo. */
1383 return sh64_compact_reg_base_num (rn
);
1387 sign_extend (int value
, int bits
)
1389 value
= value
& ((1 << bits
) - 1);
1390 return (value
& (1 << (bits
- 1))
1391 ? value
| (~((1 << bits
) - 1))
1396 sh64_nofp_frame_init_saved_regs (struct frame_info
*fi
)
1398 int *where
= (int *) alloca ((NUM_REGS
+ NUM_PSEUDO_REGS
) * sizeof(int));
1410 int gdb_register_number
;
1411 int register_number
;
1412 char *dummy_regs
= generic_find_dummy_frame (fi
->pc
, fi
->frame
);
1413 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1415 if (fi
->saved_regs
== NULL
)
1416 frame_saved_regs_zalloc (fi
);
1418 memset (fi
->saved_regs
, 0, SIZEOF_FRAME_SAVED_REGS
);
1422 /* DANGER! This is ONLY going to work if the char buffer format of
1423 the saved registers is byte-for-byte identical to the
1424 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1425 memcpy (fi
->saved_regs
, dummy_regs
, sizeof (fi
->saved_regs
));
1429 fi
->extra_info
->leaf_function
= 1;
1430 fi
->extra_info
->f_offset
= 0;
1432 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1437 /* Loop around examining the prologue insns until we find something
1438 that does not appear to be part of the prologue. But give up
1439 after 20 of them, since we're getting silly then. */
1441 pc
= get_pc_function_start (fi
->pc
);
1448 if (pc_is_isa32 (pc
))
1459 /* The frame pointer register is general register 14 in shmedia and
1460 shcompact modes. In sh compact it is a pseudo register. Same goes
1461 for the stack pointer register, which is register 15. */
1462 fp_regnum
= translate_insn_rn (FP_REGNUM
, media_mode
);
1463 sp_regnum
= translate_insn_rn (SP_REGNUM
, media_mode
);
1465 for (opc
= pc
+ (insn_size
* 28); pc
< opc
; pc
+= insn_size
)
1467 insn
= read_memory_integer (media_mode
? UNMAKE_ISA32_ADDR (pc
) : pc
,
1470 if (media_mode
== 0)
1472 if (IS_STS_PR (insn
))
1474 int next_insn
= read_memory_integer (pc
+ insn_size
, insn_size
);
1475 if (IS_MOV_TO_R15 (next_insn
))
1477 int reg_nr
= tdep
->PR_C_REGNUM
;
1479 where
[reg_nr
] = depth
- ((((next_insn
& 0xf) ^ 0x8) - 0x8) << 2);
1480 fi
->extra_info
->leaf_function
= 0;
1484 else if (IS_MOV_R14 (insn
))
1486 where
[fp_regnum
] = depth
- ((((insn
& 0xf) ^ 0x8) - 0x8) << 2);
1489 else if (IS_MOV_R0 (insn
))
1491 /* Put in R0 the offset from SP at which to store some
1492 registers. We are interested in this value, because it
1493 will tell us where the given registers are stored within
1495 r0_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
1497 else if (IS_ADD_SP_R0 (insn
))
1499 /* This instruction still prepares r0, but we don't care.
1500 We already have the offset in r0_val. */
1502 else if (IS_STS_R0 (insn
))
1504 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
1505 int reg_nr
= tdep
->PR_C_REGNUM
;
1506 where
[reg_nr
] = depth
- (r0_val
- 4);
1508 fi
->extra_info
->leaf_function
= 0;
1510 else if (IS_MOV_R14_R0 (insn
))
1512 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
1513 where
[fp_regnum
] = depth
- (r0_val
- 4);
1517 else if (IS_ADD_SP (insn
))
1519 depth
-= ((insn
& 0xff) ^ 0x80) - 0x80;
1521 else if (IS_MOV_SP_FP (insn
))
1526 if (IS_ADDIL_SP_MEDIA (insn
)
1527 || IS_ADDI_SP_MEDIA (insn
))
1529 depth
-= sign_extend ((((insn
& 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
1532 else if (IS_STQ_R18_R15 (insn
))
1534 where
[tdep
->PR_REGNUM
] =
1535 depth
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 3);
1536 fi
->extra_info
->leaf_function
= 0;
1539 else if (IS_STL_R18_R15 (insn
))
1541 where
[tdep
->PR_REGNUM
] =
1542 depth
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 2);
1543 fi
->extra_info
->leaf_function
= 0;
1546 else if (IS_STQ_R14_R15 (insn
))
1548 where
[fp_regnum
] = depth
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 3);
1551 else if (IS_STL_R14_R15 (insn
))
1553 where
[fp_regnum
] = depth
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 2);
1556 else if (IS_MOV_SP_FP_MEDIA (insn
))
1561 /* Now we know how deep things are, we can work out their addresses. */
1562 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1564 register_number
= translate_rn_to_arch_reg_num (rn
, media_mode
);
1568 if (rn
== fp_regnum
)
1571 /* Watch out! saved_regs is only for the real registers, and
1572 doesn't include space for the pseudo registers. */
1573 fi
->saved_regs
[register_number
]= fi
->frame
- where
[rn
] + depth
;
1577 fi
->saved_regs
[register_number
] = 0;
1582 /* SP_REGNUM is 15. For shmedia 15 is the real register. For
1583 shcompact 15 is the arch register corresponding to the pseudo
1584 register r15 which still is the SP register. */
1585 /* The place on the stack where fp is stored contains the sp of
1587 /* Again, saved_registers contains only space for the real registers,
1588 so we store in FP_REGNUM position. */
1590 if (tdep
->sh_abi
== SH_ABI_32
)
1593 size
= REGISTER_RAW_SIZE (fp_regnum
);
1594 fi
->saved_regs
[sp_regnum
] = read_memory_integer (fi
->saved_regs
[fp_regnum
], size
);
1597 fi
->saved_regs
[sp_regnum
] = fi
->frame
;
1599 fi
->extra_info
->f_offset
= depth
- where
[fp_regnum
];
1603 sh_fp_frame_init_saved_regs (struct frame_info
*fi
)
1605 int where
[NUM_REGS
+ NUM_PSEUDO_REGS
];
1613 char *dummy_regs
= generic_find_dummy_frame (fi
->pc
, fi
->frame
);
1614 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1616 if (fi
->saved_regs
== NULL
)
1617 frame_saved_regs_zalloc (fi
);
1619 memset (fi
->saved_regs
, 0, SIZEOF_FRAME_SAVED_REGS
);
1623 /* DANGER! This is ONLY going to work if the char buffer format of
1624 the saved registers is byte-for-byte identical to the
1625 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1626 memcpy (fi
->saved_regs
, dummy_regs
, sizeof (fi
->saved_regs
));
1630 fi
->extra_info
->leaf_function
= 1;
1631 fi
->extra_info
->f_offset
= 0;
1633 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1638 /* Loop around examining the prologue insns until we find something
1639 that does not appear to be part of the prologue. But give up
1640 after 20 of them, since we're getting silly then. */
1642 pc
= get_pc_function_start (fi
->pc
);
1649 for (opc
= pc
+ (2 * 28); pc
< opc
; pc
+= 2)
1651 insn
= read_memory_integer (pc
, 2);
1652 /* See where the registers will be saved to */
1655 rn
= GET_PUSHED_REG (insn
);
1659 else if (IS_STS (insn
))
1661 where
[tdep
->PR_REGNUM
] = depth
;
1662 /* If we're storing the pr then this isn't a leaf */
1663 fi
->extra_info
->leaf_function
= 0;
1666 else if (IS_MOV_R3 (insn
))
1668 r3_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
1670 else if (IS_SHLL_R3 (insn
))
1674 else if (IS_ADD_R3SP (insn
))
1678 else if (IS_ADD_SP (insn
))
1680 depth
-= ((insn
& 0xff) ^ 0x80) - 0x80;
1682 else if (IS_FMOV (insn
))
1684 if (read_register (tdep
->FPSCR_REGNUM
) & FPSCR_SZ
)
1693 else if (IS_MOV_SP_FP (insn
))
1695 #if 0 /* This used to just stop when it found an instruction that
1696 was not considered part of the prologue. Now, we just
1697 keep going looking for likely instructions. */
1703 /* Now we know how deep things are, we can work out their addresses */
1705 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1709 if (rn
== FP_REGNUM
)
1712 fi
->saved_regs
[rn
] = fi
->frame
- where
[rn
] + depth
- 4;
1716 fi
->saved_regs
[rn
] = 0;
1722 fi
->saved_regs
[SP_REGNUM
] =
1723 read_memory_integer (fi
->saved_regs
[FP_REGNUM
], 4);
1727 fi
->saved_regs
[SP_REGNUM
] = fi
->frame
- 4;
1730 fi
->extra_info
->f_offset
= depth
- where
[FP_REGNUM
] - 4;
1731 /* Work out the return pc - either from the saved pr or the pr
1735 /* Initialize the extra info saved in a FRAME */
1737 sh_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1740 fi
->extra_info
= (struct frame_extra_info
*)
1741 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1744 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
1746 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1748 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1749 by assuming it's always FP. */
1750 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
,
1752 fi
->extra_info
->return_pc
= generic_read_register_dummy (fi
->pc
,
1755 fi
->extra_info
->f_offset
= -(CALL_DUMMY_LENGTH
+ 4);
1756 fi
->extra_info
->leaf_function
= 0;
1761 FRAME_INIT_SAVED_REGS (fi
);
1762 fi
->extra_info
->return_pc
=
1763 sh_find_callers_reg (fi
, gdbarch_tdep (current_gdbarch
)->PR_REGNUM
);
1768 sh64_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1770 int media_mode
= pc_is_isa32 (fi
->pc
);
1772 fi
->extra_info
= (struct frame_extra_info
*)
1773 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1776 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
1778 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1780 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1781 by assuming it's always FP. */
1782 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
,
1784 fi
->extra_info
->return_pc
=
1785 generic_read_register_dummy (fi
->pc
, fi
->frame
, PC_REGNUM
);
1786 fi
->extra_info
->f_offset
= -(CALL_DUMMY_LENGTH
+ 4);
1787 fi
->extra_info
->leaf_function
= 0;
1792 FRAME_INIT_SAVED_REGS (fi
);
1793 fi
->extra_info
->return_pc
=
1794 sh64_get_saved_pr (fi
, gdbarch_tdep (current_gdbarch
)->PR_REGNUM
);
1799 sh64_get_saved_register (char *raw_buffer
, int *optimized
, CORE_ADDR
*addrp
,
1800 struct frame_info
*frame
, int regnum
,
1801 enum lval_type
*lval
)
1804 int live_regnum
= regnum
;
1805 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1807 if (!target_has_registers
)
1808 error ("No registers.");
1810 /* Normal systems don't optimize out things with register numbers. */
1811 if (optimized
!= NULL
)
1814 if (addrp
) /* default assumption: not found in memory */
1818 memset (raw_buffer
, 0, sizeof (raw_buffer
));
1820 /* We must do this here, before the following while loop changes
1821 frame, and makes it NULL. If this is a media register number,
1822 but we are in compact mode, it will become the corresponding
1823 compact pseudo register. If there is no corresponding compact
1824 pseudo-register what do we do?*/
1825 media_mode
= pc_is_isa32 (frame
->pc
);
1826 live_regnum
= translate_insn_rn (regnum
, media_mode
);
1828 /* Note: since the current frame's registers could only have been
1829 saved by frames INTERIOR TO the current frame, we skip examining
1830 the current frame itself: otherwise, we would be getting the
1831 previous frame's registers which were saved by the current frame. */
1833 while (frame
&& ((frame
= frame
->next
) != NULL
))
1835 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
1837 if (lval
) /* found it in a CALL_DUMMY frame */
1841 generic_find_dummy_frame (frame
->pc
, frame
->frame
) +
1842 REGISTER_BYTE (regnum
),
1843 REGISTER_RAW_SIZE (regnum
));
1847 FRAME_INIT_SAVED_REGS (frame
);
1848 if (frame
->saved_regs
!= NULL
1849 && frame
->saved_regs
[regnum
] != 0)
1851 if (lval
) /* found it saved on the stack */
1852 *lval
= lval_memory
;
1853 if (regnum
== SP_REGNUM
)
1855 if (raw_buffer
) /* SP register treated specially */
1856 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
1857 frame
->saved_regs
[regnum
]);
1860 { /* any other register */
1863 *addrp
= frame
->saved_regs
[regnum
];
1867 if (tdep
->sh_abi
== SH_ABI_32
1868 && (live_regnum
== FP_REGNUM
1869 || live_regnum
== tdep
->PR_REGNUM
))
1872 size
= REGISTER_RAW_SIZE (live_regnum
);
1873 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
1874 read_memory (frame
->saved_regs
[regnum
], raw_buffer
, size
);
1876 read_memory (frame
->saved_regs
[regnum
],
1878 + REGISTER_RAW_SIZE (live_regnum
)
1887 /* If we get thru the loop to this point, it means the register was
1888 not saved in any frame. Return the actual live-register value. */
1890 if (lval
) /* found it in a live register */
1891 *lval
= lval_register
;
1893 *addrp
= REGISTER_BYTE (live_regnum
);
1895 read_register_gen (live_regnum
, raw_buffer
);
1898 /* Extract from an array REGBUF containing the (raw) register state
1899 the address in which a function should return its structure value,
1900 as a CORE_ADDR (or an expression that can be used as one). */
1902 sh_extract_struct_value_address (char *regbuf
)
1904 return (extract_address ((regbuf
), REGISTER_RAW_SIZE (0)));
1908 sh64_extract_struct_value_address (char *regbuf
)
1910 return (extract_address ((regbuf
+ REGISTER_BYTE (STRUCT_RETURN_REGNUM
)),
1911 REGISTER_RAW_SIZE (STRUCT_RETURN_REGNUM
)));
1915 sh_frame_saved_pc (struct frame_info
*frame
)
1917 return ((frame
)->extra_info
->return_pc
);
1920 /* Discard from the stack the innermost frame,
1921 restoring all saved registers. */
1925 register struct frame_info
*frame
= get_current_frame ();
1926 register CORE_ADDR fp
;
1927 register int regnum
;
1929 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
1930 generic_pop_dummy_frame ();
1933 fp
= FRAME_FP (frame
);
1934 FRAME_INIT_SAVED_REGS (frame
);
1936 /* Copy regs from where they were saved in the frame */
1937 for (regnum
= 0; regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
1938 if (frame
->saved_regs
[regnum
])
1939 write_register (regnum
,
1940 read_memory_integer (frame
->saved_regs
[regnum
], 4));
1942 write_register (PC_REGNUM
, frame
->extra_info
->return_pc
);
1943 write_register (SP_REGNUM
, fp
+ 4);
1945 flush_cached_frames ();
1948 /* Used in the 'return' command. */
1950 sh64_pop_frame (void)
1952 register struct frame_info
*frame
= get_current_frame ();
1953 register CORE_ADDR fp
;
1954 register int regnum
;
1955 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1957 int media_mode
= pc_is_isa32 (frame
->pc
);
1959 if (PC_IN_CALL_DUMMY (frame
->pc
, frame
->frame
, frame
->frame
))
1960 generic_pop_dummy_frame ();
1963 fp
= FRAME_FP (frame
);
1964 FRAME_INIT_SAVED_REGS (frame
);
1966 /* Copy regs from where they were saved in the frame */
1967 for (regnum
= 0; regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
1968 if (frame
->saved_regs
[regnum
])
1971 if (tdep
->sh_abi
== SH_ABI_32
1972 && (regnum
== FP_REGNUM
1973 || regnum
== tdep
->PR_REGNUM
))
1976 size
= REGISTER_RAW_SIZE (translate_insn_rn (regnum
,
1978 write_register (regnum
,
1979 read_memory_integer (frame
->saved_regs
[regnum
],
1983 write_register (PC_REGNUM
, frame
->extra_info
->return_pc
);
1984 write_register (SP_REGNUM
, fp
+ 8);
1986 flush_cached_frames ();
1989 /* Function: push_arguments
1990 Setup the function arguments for calling a function in the inferior.
1992 On the Hitachi SH architecture, there are four registers (R4 to R7)
1993 which are dedicated for passing function arguments. Up to the first
1994 four arguments (depending on size) may go into these registers.
1995 The rest go on the stack.
1997 Arguments that are smaller than 4 bytes will still take up a whole
1998 register or a whole 32-bit word on the stack, and will be
1999 right-justified in the register or the stack word. This includes
2000 chars, shorts, and small aggregate types.
2002 Arguments that are larger than 4 bytes may be split between two or
2003 more registers. If there are not enough registers free, an argument
2004 may be passed partly in a register (or registers), and partly on the
2005 stack. This includes doubles, long longs, and larger aggregates.
2006 As far as I know, there is no upper limit to the size of aggregates
2007 that will be passed in this way; in other words, the convention of
2008 passing a pointer to a large aggregate instead of a copy is not used.
2010 An exceptional case exists for struct arguments (and possibly other
2011 aggregates such as arrays) if the size is larger than 4 bytes but
2012 not a multiple of 4 bytes. In this case the argument is never split
2013 between the registers and the stack, but instead is copied in its
2014 entirety onto the stack, AND also copied into as many registers as
2015 there is room for. In other words, space in registers permitting,
2016 two copies of the same argument are passed in. As far as I can tell,
2017 only the one on the stack is used, although that may be a function
2018 of the level of compiler optimization. I suspect this is a compiler
2019 bug. Arguments of these odd sizes are left-justified within the
2020 word (as opposed to arguments smaller than 4 bytes, which are
2023 If the function is to return an aggregate type such as a struct, it
2024 is either returned in the normal return value register R0 (if its
2025 size is no greater than one byte), or else the caller must allocate
2026 space into which the callee will copy the return value (if the size
2027 is greater than one byte). In this case, a pointer to the return
2028 value location is passed into the callee in register R2, which does
2029 not displace any of the other arguments passed in via registers R4
2033 sh_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
2034 int struct_return
, CORE_ADDR struct_addr
)
2036 int stack_offset
, stack_alloc
;
2044 int odd_sized_struct
;
2045 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2047 /* first force sp to a 4-byte alignment */
2050 /* The "struct return pointer" pseudo-argument has its own dedicated
2053 write_register (STRUCT_RETURN_REGNUM
, struct_addr
);
2055 /* Now make sure there's space on the stack */
2056 for (argnum
= 0, stack_alloc
= 0; argnum
< nargs
; argnum
++)
2057 stack_alloc
+= ((TYPE_LENGTH (VALUE_TYPE (args
[argnum
])) + 3) & ~3);
2058 sp
-= stack_alloc
; /* make room on stack for args */
2060 /* Now load as many as possible of the first arguments into
2061 registers, and push the rest onto the stack. There are 16 bytes
2062 in four registers available. Loop thru args from first to last. */
2064 argreg
= tdep
->ARG0_REGNUM
;
2065 for (argnum
= 0, stack_offset
= 0; argnum
< nargs
; argnum
++)
2067 type
= VALUE_TYPE (args
[argnum
]);
2068 len
= TYPE_LENGTH (type
);
2069 memset (valbuf
, 0, sizeof (valbuf
));
2072 /* value gets right-justified in the register or stack word */
2073 memcpy (valbuf
+ (4 - len
),
2074 (char *) VALUE_CONTENTS (args
[argnum
]), len
);
2078 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
2080 if (len
> 4 && (len
& 3) != 0)
2081 odd_sized_struct
= 1; /* such structs go entirely on stack */
2083 odd_sized_struct
= 0;
2086 if (argreg
> tdep
->ARGLAST_REGNUM
2087 || odd_sized_struct
)
2089 /* must go on the stack */
2090 write_memory (sp
+ stack_offset
, val
, 4);
2093 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2094 That's because some *&^%$ things get passed on the stack
2095 AND in the registers! */
2096 if (argreg
<= tdep
->ARGLAST_REGNUM
)
2098 /* there's room in a register */
2099 regval
= extract_address (val
, REGISTER_RAW_SIZE (argreg
));
2100 write_register (argreg
++, regval
);
2102 /* Store the value 4 bytes at a time. This means that things
2103 larger than 4 bytes may go partly in registers and partly
2105 len
-= REGISTER_RAW_SIZE (argreg
);
2106 val
+= REGISTER_RAW_SIZE (argreg
);
2112 /* R2-R9 for integer types and integer equivalent (char, pointers) and
2113 non-scalar (struct, union) elements (even if the elements are
2115 FR0-FR11 for single precision floating point (float)
2116 DR0-DR10 for double precision floating point (double)
2118 If a float is argument number 3 (for instance) and arguments number
2119 1,2, and 4 are integer, the mapping will be:
2120 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
2122 If a float is argument number 10 (for instance) and arguments number
2123 1 through 10 are integer, the mapping will be:
2124 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
2125 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
2126 I.e. there is hole in the stack.
2128 Different rules apply for variable arguments functions, and for functions
2129 for which the prototype is not known. */
2132 sh64_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
2133 int struct_return
, CORE_ADDR struct_addr
)
2135 int stack_offset
, stack_alloc
;
2139 int float_arg_index
= 0;
2140 int double_arg_index
= 0;
2150 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2152 memset (fp_args
, 0, sizeof (fp_args
));
2154 /* first force sp to a 8-byte alignment */
2157 /* The "struct return pointer" pseudo-argument has its own dedicated
2161 write_register (STRUCT_RETURN_REGNUM
, struct_addr
);
2163 /* Now make sure there's space on the stack */
2164 for (argnum
= 0, stack_alloc
= 0; argnum
< nargs
; argnum
++)
2165 stack_alloc
+= ((TYPE_LENGTH (VALUE_TYPE (args
[argnum
])) + 7) & ~7);
2166 sp
-= stack_alloc
; /* make room on stack for args */
2168 /* Now load as many as possible of the first arguments into
2169 registers, and push the rest onto the stack. There are 64 bytes
2170 in eight registers available. Loop thru args from first to last. */
2172 int_argreg
= tdep
->ARG0_REGNUM
;
2173 float_argreg
= FP0_REGNUM
;
2174 double_argreg
= tdep
->DR0_REGNUM
;
2176 for (argnum
= 0, stack_offset
= 0; argnum
< nargs
; argnum
++)
2178 type
= VALUE_TYPE (args
[argnum
]);
2179 len
= TYPE_LENGTH (type
);
2180 memset (valbuf
, 0, sizeof (valbuf
));
2182 if (TYPE_CODE (type
) != TYPE_CODE_FLT
)
2184 argreg_size
= REGISTER_RAW_SIZE (int_argreg
);
2186 if (len
< argreg_size
)
2188 /* value gets right-justified in the register or stack word */
2189 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2190 memcpy (valbuf
+ argreg_size
- len
,
2191 (char *) VALUE_CONTENTS (args
[argnum
]), len
);
2193 memcpy (valbuf
, (char *) VALUE_CONTENTS (args
[argnum
]), len
);
2198 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
2202 if (int_argreg
> tdep
->ARGLAST_REGNUM
)
2204 /* must go on the stack */
2205 write_memory (sp
+ stack_offset
, val
, argreg_size
);
2206 stack_offset
+= 8;/*argreg_size;*/
2208 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2209 That's because some *&^%$ things get passed on the stack
2210 AND in the registers! */
2211 if (int_argreg
<= tdep
->ARGLAST_REGNUM
)
2213 /* there's room in a register */
2214 regval
= extract_address (val
, argreg_size
);
2215 write_register (int_argreg
, regval
);
2217 /* Store the value 8 bytes at a time. This means that
2218 things larger than 8 bytes may go partly in registers
2219 and partly on the stack. FIXME: argreg is incremented
2220 before we use its size. */
2228 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
2231 /* Where is it going to be stored? */
2232 while (fp_args
[float_arg_index
])
2235 /* Now float_argreg points to the register where it
2236 should be stored. Are we still within the allowed
2238 if (float_arg_index
<= tdep
->FLOAT_ARGLAST_REGNUM
)
2240 /* Goes in FR0...FR11 */
2241 write_register_gen (FP0_REGNUM
+ float_arg_index
, val
);
2242 fp_args
[float_arg_index
] = 1;
2243 /* Skip the corresponding general argument register. */
2248 /* Store it as the integers, 8 bytes at the time, if
2249 necessary spilling on the stack. */
2254 /* Where is it going to be stored? */
2255 while (fp_args
[double_arg_index
])
2256 double_arg_index
+= 2;
2257 /* Now double_argreg points to the register
2258 where it should be stored.
2259 Are we still within the allowed register set? */
2260 if (double_arg_index
< tdep
->FLOAT_ARGLAST_REGNUM
)
2262 /* Goes in DR0...DR10 */
2263 /* The numbering of the DRi registers is consecutive,
2264 i.e. includes odd numbers. */
2265 int double_register_offset
= double_arg_index
/ 2;
2266 int regnum
= tdep
->DR0_REGNUM
+
2267 double_register_offset
;
2269 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
2271 memset (valbuf_tmp
, 0, sizeof (valbuf_tmp
));
2272 REGISTER_CONVERT_TO_VIRTUAL (regnum
,
2273 type
, val
, valbuf_tmp
);
2277 /* Note: must use write_register_gen here instead
2278 of regcache_write, because regcache_write works
2279 only for real registers, not pseudo.
2280 write_register_gen will call the gdbarch
2281 function to do register writes, and that will
2282 properly know how to deal with pseudoregs. */
2283 write_register_gen (regnum
, val
);
2284 fp_args
[double_arg_index
] = 1;
2285 fp_args
[double_arg_index
+ 1] = 1;
2286 /* Skip the corresponding general argument register. */
2291 /* Store it as the integers, 8 bytes at the time, if
2292 necessary spilling on the stack. */
2299 /* Function: push_return_address (pc)
2300 Set up the return address for the inferior function call.
2301 Needed for targets where we don't actually execute a JSR/BSR instruction */
2304 sh_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
2306 write_register (gdbarch_tdep (current_gdbarch
)->PR_REGNUM
,
2307 CALL_DUMMY_ADDRESS ());
2311 /* Function: fix_call_dummy
2312 Poke the callee function's address into the destination part of
2313 the CALL_DUMMY. The address is actually stored in a data word
2314 following the actualy CALL_DUMMY instructions, which will load
2315 it into a register using PC-relative addressing. This function
2316 expects the CALL_DUMMY to look like this:
2327 sh_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
2328 struct value
**args
, struct type
*type
, int gcc_p
)
2330 *(unsigned long *) (dummy
+ 8) = fun
;
2335 sh_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
2340 /* Find a function's return value in the appropriate registers (in
2341 regbuf), and copy it into valbuf. Extract from an array REGBUF
2342 containing the (raw) register state a function return value of type
2343 TYPE, and copy that, in virtual format, into VALBUF. */
2345 sh_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2347 int len
= TYPE_LENGTH (type
);
2348 int return_register
= R0_REGNUM
;
2353 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2354 offset
= REGISTER_BYTE (return_register
) + 4 - len
;
2356 offset
= REGISTER_BYTE (return_register
);
2357 memcpy (valbuf
, regbuf
+ offset
, len
);
2361 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2362 offset
= REGISTER_BYTE (return_register
) + 8 - len
;
2364 offset
= REGISTER_BYTE (return_register
);
2365 memcpy (valbuf
, regbuf
+ offset
, len
);
2368 error ("bad size for return value");
2372 sh3e_sh4_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2374 int return_register
;
2376 int len
= TYPE_LENGTH (type
);
2378 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2379 return_register
= FP0_REGNUM
;
2381 return_register
= R0_REGNUM
;
2383 if (len
== 8 && TYPE_CODE (type
) == TYPE_CODE_FLT
)
2386 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
2387 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
2388 (char *) regbuf
+ REGISTER_BYTE (return_register
),
2391 floatformat_to_doublest (&floatformat_ieee_double_big
,
2392 (char *) regbuf
+ REGISTER_BYTE (return_register
),
2394 store_floating (valbuf
, len
, val
);
2398 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2399 offset
= REGISTER_BYTE (return_register
) + 4 - len
;
2401 offset
= REGISTER_BYTE (return_register
);
2402 memcpy (valbuf
, regbuf
+ offset
, len
);
2406 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2407 offset
= REGISTER_BYTE (return_register
) + 8 - len
;
2409 offset
= REGISTER_BYTE (return_register
);
2410 memcpy (valbuf
, regbuf
+ offset
, len
);
2413 error ("bad size for return value");
2417 sh64_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2420 int return_register
;
2421 int len
= TYPE_LENGTH (type
);
2422 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2424 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2428 /* Return value stored in FP0_REGNUM */
2429 return_register
= FP0_REGNUM
;
2430 offset
= REGISTER_BYTE (return_register
);
2431 memcpy (valbuf
, (char *) regbuf
+ offset
, len
);
2435 /* return value stored in DR0_REGNUM */
2438 return_register
= tdep
->DR0_REGNUM
;
2439 offset
= REGISTER_BYTE (return_register
);
2441 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
2442 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
2443 (char *) regbuf
+ offset
, &val
);
2445 floatformat_to_doublest (&floatformat_ieee_double_big
,
2446 (char *) regbuf
+ offset
, &val
);
2447 store_floating (valbuf
, len
, val
);
2454 /* Result is in register 2. If smaller than 8 bytes, it is padded
2455 at the most significant end. */
2456 return_register
= tdep
->RETURN_REGNUM
;
2457 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2458 offset
= REGISTER_BYTE (return_register
) +
2459 REGISTER_RAW_SIZE (return_register
) - len
;
2461 offset
= REGISTER_BYTE (return_register
);
2462 memcpy (valbuf
, (char *) regbuf
+ offset
, len
);
2465 error ("bad size for return value");
2469 /* Write into appropriate registers a function return value
2470 of type TYPE, given in virtual format.
2471 If the architecture is sh4 or sh3e, store a function's return value
2472 in the R0 general register or in the FP0 floating point register,
2473 depending on the type of the return value. In all the other cases
2474 the result is stored in r0, left-justified. */
2476 sh_default_store_return_value (struct type
*type
, char *valbuf
)
2478 char buf
[32]; /* more than enough... */
2480 if (TYPE_LENGTH (type
) < REGISTER_RAW_SIZE (R0_REGNUM
))
2482 /* Add leading zeros to the value. */
2483 memset (buf
, 0, REGISTER_RAW_SIZE (R0_REGNUM
));
2484 memcpy (buf
+ REGISTER_RAW_SIZE (R0_REGNUM
) - TYPE_LENGTH (type
),
2485 valbuf
, TYPE_LENGTH (type
));
2486 write_register_bytes (REGISTER_BYTE (R0_REGNUM
), buf
,
2487 REGISTER_RAW_SIZE (R0_REGNUM
));
2490 write_register_bytes (REGISTER_BYTE (R0_REGNUM
), valbuf
,
2491 TYPE_LENGTH (type
));
2495 sh3e_sh4_store_return_value (struct type
*type
, char *valbuf
)
2497 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2498 write_register_bytes (REGISTER_BYTE (FP0_REGNUM
),
2499 valbuf
, TYPE_LENGTH (type
));
2501 sh_default_store_return_value (type
, valbuf
);
2505 sh64_store_return_value (struct type
*type
, char *valbuf
)
2507 char buf
[64]; /* more than enough... */
2508 int len
= TYPE_LENGTH (type
);
2510 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2514 /* Return value stored in FP0_REGNUM */
2515 write_register_gen (FP0_REGNUM
, valbuf
);
2519 /* return value stored in DR0_REGNUM */
2520 /* FIXME: Implement */
2525 int return_register
= gdbarch_tdep (current_gdbarch
)->RETURN_REGNUM
;
2528 if (len
<= REGISTER_RAW_SIZE (return_register
))
2530 /* Pad with zeros. */
2531 memset (buf
, 0, REGISTER_RAW_SIZE (return_register
));
2532 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
2533 offset
= 0; /*REGISTER_RAW_SIZE (return_register) - len;*/
2535 offset
= REGISTER_RAW_SIZE (return_register
) - len
;
2537 memcpy (buf
+ offset
, valbuf
, len
);
2538 write_register_gen (return_register
, buf
);
2541 write_register_gen (return_register
, valbuf
);
2545 /* Print the registers in a form similar to the E7000 */
2548 sh_generic_show_regs (void)
2550 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2552 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2553 paddr (read_register (PC_REGNUM
)),
2554 (long) read_register (tdep
->SR_REGNUM
),
2555 (long) read_register (tdep
->PR_REGNUM
),
2556 (long) read_register (MACH_REGNUM
),
2557 (long) read_register (MACL_REGNUM
));
2559 printf_filtered ("GBR=%08lx VBR=%08lx",
2560 (long) read_register (GBR_REGNUM
),
2561 (long) read_register (VBR_REGNUM
));
2563 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2564 (long) read_register (0),
2565 (long) read_register (1),
2566 (long) read_register (2),
2567 (long) read_register (3),
2568 (long) read_register (4),
2569 (long) read_register (5),
2570 (long) read_register (6),
2571 (long) read_register (7));
2572 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2573 (long) read_register (8),
2574 (long) read_register (9),
2575 (long) read_register (10),
2576 (long) read_register (11),
2577 (long) read_register (12),
2578 (long) read_register (13),
2579 (long) read_register (14),
2580 (long) read_register (15));
2584 sh3_show_regs (void)
2586 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2588 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2589 paddr (read_register (PC_REGNUM
)),
2590 (long) read_register (tdep
->SR_REGNUM
),
2591 (long) read_register (tdep
->PR_REGNUM
),
2592 (long) read_register (MACH_REGNUM
),
2593 (long) read_register (MACL_REGNUM
));
2595 printf_filtered ("GBR=%08lx VBR=%08lx",
2596 (long) read_register (GBR_REGNUM
),
2597 (long) read_register (VBR_REGNUM
));
2598 printf_filtered (" SSR=%08lx SPC=%08lx",
2599 (long) read_register (tdep
->SSR_REGNUM
),
2600 (long) read_register (tdep
->SPC_REGNUM
));
2602 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2603 (long) read_register (0),
2604 (long) read_register (1),
2605 (long) read_register (2),
2606 (long) read_register (3),
2607 (long) read_register (4),
2608 (long) read_register (5),
2609 (long) read_register (6),
2610 (long) read_register (7));
2611 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2612 (long) read_register (8),
2613 (long) read_register (9),
2614 (long) read_register (10),
2615 (long) read_register (11),
2616 (long) read_register (12),
2617 (long) read_register (13),
2618 (long) read_register (14),
2619 (long) read_register (15));
2624 sh3e_show_regs (void)
2626 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2628 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2629 paddr (read_register (PC_REGNUM
)),
2630 (long) read_register (tdep
->SR_REGNUM
),
2631 (long) read_register (tdep
->PR_REGNUM
),
2632 (long) read_register (MACH_REGNUM
),
2633 (long) read_register (MACL_REGNUM
));
2635 printf_filtered ("GBR=%08lx VBR=%08lx",
2636 (long) read_register (GBR_REGNUM
),
2637 (long) read_register (VBR_REGNUM
));
2638 printf_filtered (" SSR=%08lx SPC=%08lx",
2639 (long) read_register (tdep
->SSR_REGNUM
),
2640 (long) read_register (tdep
->SPC_REGNUM
));
2641 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
2642 (long) read_register (tdep
->FPUL_REGNUM
),
2643 (long) read_register (tdep
->FPSCR_REGNUM
));
2645 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2646 (long) read_register (0),
2647 (long) read_register (1),
2648 (long) read_register (2),
2649 (long) read_register (3),
2650 (long) read_register (4),
2651 (long) read_register (5),
2652 (long) read_register (6),
2653 (long) read_register (7));
2654 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2655 (long) read_register (8),
2656 (long) read_register (9),
2657 (long) read_register (10),
2658 (long) read_register (11),
2659 (long) read_register (12),
2660 (long) read_register (13),
2661 (long) read_register (14),
2662 (long) read_register (15));
2664 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2665 (long) read_register (FP0_REGNUM
+ 0),
2666 (long) read_register (FP0_REGNUM
+ 1),
2667 (long) read_register (FP0_REGNUM
+ 2),
2668 (long) read_register (FP0_REGNUM
+ 3),
2669 (long) read_register (FP0_REGNUM
+ 4),
2670 (long) read_register (FP0_REGNUM
+ 5),
2671 (long) read_register (FP0_REGNUM
+ 6),
2672 (long) read_register (FP0_REGNUM
+ 7));
2673 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2674 (long) read_register (FP0_REGNUM
+ 8),
2675 (long) read_register (FP0_REGNUM
+ 9),
2676 (long) read_register (FP0_REGNUM
+ 10),
2677 (long) read_register (FP0_REGNUM
+ 11),
2678 (long) read_register (FP0_REGNUM
+ 12),
2679 (long) read_register (FP0_REGNUM
+ 13),
2680 (long) read_register (FP0_REGNUM
+ 14),
2681 (long) read_register (FP0_REGNUM
+ 15));
2685 sh3_dsp_show_regs (void)
2687 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2689 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2690 paddr (read_register (PC_REGNUM
)),
2691 (long) read_register (tdep
->SR_REGNUM
),
2692 (long) read_register (tdep
->PR_REGNUM
),
2693 (long) read_register (MACH_REGNUM
),
2694 (long) read_register (MACL_REGNUM
));
2696 printf_filtered ("GBR=%08lx VBR=%08lx",
2697 (long) read_register (GBR_REGNUM
),
2698 (long) read_register (VBR_REGNUM
));
2700 printf_filtered (" SSR=%08lx SPC=%08lx",
2701 (long) read_register (tdep
->SSR_REGNUM
),
2702 (long) read_register (tdep
->SPC_REGNUM
));
2704 printf_filtered (" DSR=%08lx",
2705 (long) read_register (tdep
->DSR_REGNUM
));
2707 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2708 (long) read_register (0),
2709 (long) read_register (1),
2710 (long) read_register (2),
2711 (long) read_register (3),
2712 (long) read_register (4),
2713 (long) read_register (5),
2714 (long) read_register (6),
2715 (long) read_register (7));
2716 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2717 (long) read_register (8),
2718 (long) read_register (9),
2719 (long) read_register (10),
2720 (long) read_register (11),
2721 (long) read_register (12),
2722 (long) read_register (13),
2723 (long) read_register (14),
2724 (long) read_register (15));
2726 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2727 (long) read_register (tdep
->A0G_REGNUM
) & 0xff,
2728 (long) read_register (tdep
->A0_REGNUM
),
2729 (long) read_register (tdep
->M0_REGNUM
),
2730 (long) read_register (tdep
->X0_REGNUM
),
2731 (long) read_register (tdep
->Y0_REGNUM
),
2732 (long) read_register (tdep
->RS_REGNUM
),
2733 (long) read_register (tdep
->MOD_REGNUM
));
2734 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2735 (long) read_register (tdep
->A1G_REGNUM
) & 0xff,
2736 (long) read_register (tdep
->A1_REGNUM
),
2737 (long) read_register (tdep
->M1_REGNUM
),
2738 (long) read_register (tdep
->X1_REGNUM
),
2739 (long) read_register (tdep
->Y1_REGNUM
),
2740 (long) read_register (tdep
->RE_REGNUM
));
2744 sh4_show_regs (void)
2746 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2748 int pr
= read_register (tdep
->FPSCR_REGNUM
) & 0x80000;
2749 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2750 paddr (read_register (PC_REGNUM
)),
2751 (long) read_register (tdep
->SR_REGNUM
),
2752 (long) read_register (tdep
->PR_REGNUM
),
2753 (long) read_register (MACH_REGNUM
),
2754 (long) read_register (MACL_REGNUM
));
2756 printf_filtered ("GBR=%08lx VBR=%08lx",
2757 (long) read_register (GBR_REGNUM
),
2758 (long) read_register (VBR_REGNUM
));
2759 printf_filtered (" SSR=%08lx SPC=%08lx",
2760 (long) read_register (tdep
->SSR_REGNUM
),
2761 (long) read_register (tdep
->SPC_REGNUM
));
2762 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
2763 (long) read_register (tdep
->FPUL_REGNUM
),
2764 (long) read_register (tdep
->FPSCR_REGNUM
));
2766 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2767 (long) read_register (0),
2768 (long) read_register (1),
2769 (long) read_register (2),
2770 (long) read_register (3),
2771 (long) read_register (4),
2772 (long) read_register (5),
2773 (long) read_register (6),
2774 (long) read_register (7));
2775 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2776 (long) read_register (8),
2777 (long) read_register (9),
2778 (long) read_register (10),
2779 (long) read_register (11),
2780 (long) read_register (12),
2781 (long) read_register (13),
2782 (long) read_register (14),
2783 (long) read_register (15));
2785 printf_filtered ((pr
2786 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2787 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2788 (long) read_register (FP0_REGNUM
+ 0),
2789 (long) read_register (FP0_REGNUM
+ 1),
2790 (long) read_register (FP0_REGNUM
+ 2),
2791 (long) read_register (FP0_REGNUM
+ 3),
2792 (long) read_register (FP0_REGNUM
+ 4),
2793 (long) read_register (FP0_REGNUM
+ 5),
2794 (long) read_register (FP0_REGNUM
+ 6),
2795 (long) read_register (FP0_REGNUM
+ 7));
2796 printf_filtered ((pr
2797 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2798 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2799 (long) read_register (FP0_REGNUM
+ 8),
2800 (long) read_register (FP0_REGNUM
+ 9),
2801 (long) read_register (FP0_REGNUM
+ 10),
2802 (long) read_register (FP0_REGNUM
+ 11),
2803 (long) read_register (FP0_REGNUM
+ 12),
2804 (long) read_register (FP0_REGNUM
+ 13),
2805 (long) read_register (FP0_REGNUM
+ 14),
2806 (long) read_register (FP0_REGNUM
+ 15));
2810 sh_dsp_show_regs (void)
2812 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2814 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2815 paddr (read_register (PC_REGNUM
)),
2816 (long) read_register (tdep
->SR_REGNUM
),
2817 (long) read_register (tdep
->PR_REGNUM
),
2818 (long) read_register (MACH_REGNUM
),
2819 (long) read_register (MACL_REGNUM
));
2821 printf_filtered ("GBR=%08lx VBR=%08lx",
2822 (long) read_register (GBR_REGNUM
),
2823 (long) read_register (VBR_REGNUM
));
2825 printf_filtered (" DSR=%08lx",
2826 (long) read_register (tdep
->DSR_REGNUM
));
2828 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2829 (long) read_register (0),
2830 (long) read_register (1),
2831 (long) read_register (2),
2832 (long) read_register (3),
2833 (long) read_register (4),
2834 (long) read_register (5),
2835 (long) read_register (6),
2836 (long) read_register (7));
2837 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2838 (long) read_register (8),
2839 (long) read_register (9),
2840 (long) read_register (10),
2841 (long) read_register (11),
2842 (long) read_register (12),
2843 (long) read_register (13),
2844 (long) read_register (14),
2845 (long) read_register (15));
2847 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2848 (long) read_register (tdep
->A0G_REGNUM
) & 0xff,
2849 (long) read_register (tdep
->A0_REGNUM
),
2850 (long) read_register (tdep
->M0_REGNUM
),
2851 (long) read_register (tdep
->X0_REGNUM
),
2852 (long) read_register (tdep
->Y0_REGNUM
),
2853 (long) read_register (tdep
->RS_REGNUM
),
2854 (long) read_register (tdep
->MOD_REGNUM
));
2855 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2856 (long) read_register (tdep
->A1G_REGNUM
) & 0xff,
2857 (long) read_register (tdep
->A1_REGNUM
),
2858 (long) read_register (tdep
->M1_REGNUM
),
2859 (long) read_register (tdep
->X1_REGNUM
),
2860 (long) read_register (tdep
->Y1_REGNUM
),
2861 (long) read_register (tdep
->RE_REGNUM
));
2865 sh64_show_media_regs (void)
2868 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2870 printf_filtered ("PC=%s SR=%016llx \n",
2871 paddr (read_register (PC_REGNUM
)),
2872 (long long) read_register (tdep
->SR_REGNUM
));
2874 printf_filtered ("SSR=%016llx SPC=%016llx \n",
2875 (long long) read_register (tdep
->SSR_REGNUM
),
2876 (long long) read_register (tdep
->SPC_REGNUM
));
2877 printf_filtered ("FPSCR=%016lx\n ",
2878 (long) read_register (tdep
->FPSCR_REGNUM
));
2880 for (i
= 0; i
< 64; i
= i
+ 4)
2881 printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
2883 (long long) read_register (i
+ 0),
2884 (long long) read_register (i
+ 1),
2885 (long long) read_register (i
+ 2),
2886 (long long) read_register (i
+ 3));
2888 printf_filtered ("\n");
2890 for (i
= 0; i
< 64; i
= i
+ 8)
2891 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2893 (long) read_register (FP0_REGNUM
+ i
+ 0),
2894 (long) read_register (FP0_REGNUM
+ i
+ 1),
2895 (long) read_register (FP0_REGNUM
+ i
+ 2),
2896 (long) read_register (FP0_REGNUM
+ i
+ 3),
2897 (long) read_register (FP0_REGNUM
+ i
+ 4),
2898 (long) read_register (FP0_REGNUM
+ i
+ 5),
2899 (long) read_register (FP0_REGNUM
+ i
+ 6),
2900 (long) read_register (FP0_REGNUM
+ i
+ 7));
2904 sh64_show_compact_regs (void)
2907 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2909 printf_filtered ("PC=%s \n",
2910 paddr (read_register (tdep
->PC_C_REGNUM
)));
2912 printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
2913 (long) read_register (tdep
->GBR_C_REGNUM
),
2914 (long) read_register (tdep
->MACH_C_REGNUM
),
2915 (long) read_register (tdep
->MACL_C_REGNUM
),
2916 (long) read_register (tdep
->PR_C_REGNUM
),
2917 (long) read_register (tdep
->T_C_REGNUM
));
2918 printf_filtered ("FPSCR=%08lx FPUL=%08lx\n",
2919 (long) read_register (tdep
->FPSCR_REGNUM
),
2920 (long) read_register (tdep
->FPUL_REGNUM
));
2922 for (i
= 0; i
< 16; i
= i
+ 4)
2923 printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
2925 (long) read_register (i
+ 0),
2926 (long) read_register (i
+ 1),
2927 (long) read_register (i
+ 2),
2928 (long) read_register (i
+ 3));
2930 printf_filtered ("\n");
2932 for (i
= 0; i
< 16; i
= i
+ 8)
2933 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2935 (long) read_register (FP0_REGNUM
+ i
+ 0),
2936 (long) read_register (FP0_REGNUM
+ i
+ 1),
2937 (long) read_register (FP0_REGNUM
+ i
+ 2),
2938 (long) read_register (FP0_REGNUM
+ i
+ 3),
2939 (long) read_register (FP0_REGNUM
+ i
+ 4),
2940 (long) read_register (FP0_REGNUM
+ i
+ 5),
2941 (long) read_register (FP0_REGNUM
+ i
+ 6),
2942 (long) read_register (FP0_REGNUM
+ i
+ 7));
2945 /*FIXME!!! This only shows the registers for shmedia, excluding the
2946 pseudo registers. */
2948 sh64_show_regs (void)
2950 if (pc_is_isa32 (selected_frame
->pc
))
2951 sh64_show_media_regs ();
2953 sh64_show_compact_regs ();
2956 void sh_show_regs_command (char *args
, int from_tty
)
2962 /* Index within `registers' of the first byte of the space for
2965 sh_default_register_byte (int reg_nr
)
2967 return (reg_nr
* 4);
2971 sh_sh4_register_byte (int reg_nr
)
2973 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2975 if (reg_nr
>= tdep
->DR0_REGNUM
2976 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
2977 return (dr_reg_base_num (reg_nr
) * 4);
2978 else if (reg_nr
>= tdep
->FV0_REGNUM
2979 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
2980 return (fv_reg_base_num (reg_nr
) * 4);
2982 return (reg_nr
* 4);
2987 SH MEDIA MODE (ISA 32)
2988 general registers (64-bit) 0-63
2989 0 r0, r1, r2, r3, r4, r5, r6, r7,
2990 64 r8, r9, r10, r11, r12, r13, r14, r15,
2991 128 r16, r17, r18, r19, r20, r21, r22, r23,
2992 192 r24, r25, r26, r27, r28, r29, r30, r31,
2993 256 r32, r33, r34, r35, r36, r37, r38, r39,
2994 320 r40, r41, r42, r43, r44, r45, r46, r47,
2995 384 r48, r49, r50, r51, r52, r53, r54, r55,
2996 448 r56, r57, r58, r59, r60, r61, r62, r63,
3001 status reg., saved status reg., saved pc reg. (64-bit) 65-67
3004 target registers (64-bit) 68-75
3005 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
3007 floating point state control register (32-bit) 76
3010 single precision floating point registers (32-bit) 77-140
3011 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
3012 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
3013 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
3014 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
3015 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
3016 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
3017 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
3018 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
3020 TOTAL SPACE FOR REGISTERS: 868 bytes
3022 From here on they are all pseudo registers: no memory allocated.
3023 REGISTER_BYTE returns the register byte for the base register.
3025 double precision registers (pseudo) 141-172
3026 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
3027 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
3028 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
3029 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
3031 floating point pairs (pseudo) 173-204
3032 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
3033 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
3034 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
3035 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
3037 floating point vectors (4 floating point regs) (pseudo) 205-220
3038 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
3039 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
3041 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
3042 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
3043 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
3045 gbr_c, mach_c, macl_c, pr_c, t_c,
3047 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
3048 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
3049 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
3050 fv0_c, fv4_c, fv8_c, fv12_c
3054 sh_sh64_register_byte (int reg_nr
)
3056 int base_regnum
= -1;
3057 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3059 /* If it is a pseudo register, get the number of the first floating
3060 point register that is part of it. */
3061 if (reg_nr
>= tdep
->DR0_REGNUM
3062 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3063 base_regnum
= dr_reg_base_num (reg_nr
);
3065 else if (reg_nr
>= tdep
->FPP0_REGNUM
3066 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3067 base_regnum
= fpp_reg_base_num (reg_nr
);
3069 else if (reg_nr
>= tdep
->FV0_REGNUM
3070 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3071 base_regnum
= fv_reg_base_num (reg_nr
);
3073 /* sh compact pseudo register. FPSCR is a pathological case, need to
3074 treat it as special. */
3075 else if ((reg_nr
>= tdep
->R0_C_REGNUM
3076 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
3077 && reg_nr
!= tdep
->FPSCR_C_REGNUM
)
3078 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3080 /* Now return the offset in bytes within the register cache. */
3081 /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */
3082 if (reg_nr
>= tdep
->DR0_REGNUM
3083 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3084 return (base_regnum
- FP0_REGNUM
+ 1) * 4
3085 + (tdep
->TR7_REGNUM
+ 1) * 8;
3087 /* sh compact pseudo register: general register */
3088 if ((reg_nr
>= tdep
->R0_C_REGNUM
3089 && reg_nr
<= tdep
->R_LAST_C_REGNUM
))
3090 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3091 ? base_regnum
* 8 + 4
3094 /* sh compact pseudo register: */
3095 if (reg_nr
== tdep
->PC_C_REGNUM
3096 || reg_nr
== tdep
->GBR_C_REGNUM
3097 || reg_nr
== tdep
->MACL_C_REGNUM
3098 || reg_nr
== tdep
->PR_C_REGNUM
)
3099 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3100 ? base_regnum
* 8 + 4
3103 if (reg_nr
== tdep
->MACH_C_REGNUM
)
3104 return base_regnum
* 8;
3106 if (reg_nr
== tdep
->T_C_REGNUM
)
3107 return base_regnum
* 8; /* FIXME??? how do we get bit 0? Do we have to? */
3109 /* sh compact pseudo register: floating point register */
3110 else if (reg_nr
>=tdep
->FP0_C_REGNUM
3111 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
3112 return (base_regnum
- FP0_REGNUM
) * 4
3113 + (tdep
->TR7_REGNUM
+ 1) * 8 + 4;
3115 else if (reg_nr
== tdep
->FPSCR_C_REGNUM
)
3116 /* This is complicated, for now return the beginning of the
3117 architectural FPSCR register. */
3118 return (tdep
->TR7_REGNUM
+ 1) * 8;
3120 else if (reg_nr
== tdep
->FPUL_C_REGNUM
)
3121 return ((base_regnum
- FP0_REGNUM
) * 4 +
3122 (tdep
->TR7_REGNUM
+ 1) * 8 + 4);
3124 /* It is not a pseudo register. */
3125 /* It is a 64 bit register. */
3126 else if (reg_nr
<= tdep
->TR7_REGNUM
)
3129 /* It is a 32 bit register. */
3131 if (reg_nr
== tdep
->FPSCR_REGNUM
)
3132 return (tdep
->FPSCR_REGNUM
* 8);
3134 /* It is floating point 32-bit register */
3136 return ((tdep
->TR7_REGNUM
+ 1) * 8
3137 + (reg_nr
- FP0_REGNUM
+ 1) * 4);
3140 /* Number of bytes of storage in the actual machine representation for
3143 sh_default_register_raw_size (int reg_nr
)
3149 sh_sh4_register_raw_size (int reg_nr
)
3151 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3153 if (reg_nr
>= tdep
->DR0_REGNUM
3154 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3156 else if (reg_nr
>= tdep
->FV0_REGNUM
3157 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3164 sh_sh64_register_raw_size (int reg_nr
)
3166 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3168 if ((reg_nr
>= tdep
->DR0_REGNUM
3169 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3170 || (reg_nr
>= tdep
->FPP0_REGNUM
3171 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3172 || (reg_nr
>= tdep
->DR0_C_REGNUM
3173 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
)
3174 || (reg_nr
<= tdep
->TR7_REGNUM
))
3177 else if ((reg_nr
>= tdep
->FV0_REGNUM
3178 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3179 || (reg_nr
>= tdep
->FV0_C_REGNUM
3180 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
))
3183 else /* this covers also the 32-bit SH compact registers. */
3187 /* Number of bytes of storage in the program's representation
3190 sh_register_virtual_size (int reg_nr
)
3197 sh_sh64_register_virtual_size (int reg_nr
)
3199 if (reg_nr
>= FP0_REGNUM
3200 && reg_nr
<= gdbarch_tdep (current_gdbarch
)->FP_LAST_REGNUM
)
3206 /* Return the GDB type object for the "standard" data type
3207 of data in register N. */
3208 static struct type
*
3209 sh_sh3e_register_virtual_type (int reg_nr
)
3211 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3213 if ((reg_nr
>= FP0_REGNUM
3214 && (reg_nr
<= tdep
->FP_LAST_REGNUM
))
3215 || (reg_nr
== tdep
->FPUL_REGNUM
))
3216 return builtin_type_float
;
3218 return builtin_type_int
;
3221 static struct type
*
3222 sh_sh4_build_float_register_type (int high
)
3226 temp
= create_range_type (NULL
, builtin_type_int
, 0, high
);
3227 return create_array_type (NULL
, builtin_type_float
, temp
);
3230 static struct type
*
3231 sh_sh4_register_virtual_type (int reg_nr
)
3233 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3235 if ((reg_nr
>= FP0_REGNUM
3236 && (reg_nr
<= tdep
->FP_LAST_REGNUM
))
3237 || (reg_nr
== tdep
->FPUL_REGNUM
))
3238 return builtin_type_float
;
3239 else if (reg_nr
>= tdep
->DR0_REGNUM
3240 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3241 return builtin_type_double
;
3242 else if (reg_nr
>= tdep
->FV0_REGNUM
3243 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3244 return sh_sh4_build_float_register_type (3);
3246 return builtin_type_int
;
3249 static struct type
*
3250 sh_sh64_register_virtual_type (int reg_nr
)
3252 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3254 if ((reg_nr
>= FP0_REGNUM
3255 && reg_nr
<= tdep
->FP_LAST_REGNUM
)
3256 || (reg_nr
>= tdep
->FP0_C_REGNUM
3257 && reg_nr
<= tdep
->FP_LAST_C_REGNUM
))
3258 return builtin_type_float
;
3259 else if ((reg_nr
>= tdep
->DR0_REGNUM
3260 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3261 || (reg_nr
>= tdep
->DR0_C_REGNUM
3262 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
))
3263 return builtin_type_double
;
3264 else if (reg_nr
>= tdep
->FPP0_REGNUM
3265 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3266 return sh_sh4_build_float_register_type (1);
3267 else if ((reg_nr
>= tdep
->FV0_REGNUM
3268 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3269 ||(reg_nr
>= tdep
->FV0_C_REGNUM
3270 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
))
3271 return sh_sh4_build_float_register_type (3);
3272 else if (reg_nr
== tdep
->FPSCR_REGNUM
)
3273 return builtin_type_int
;
3274 else if (reg_nr
>= tdep
->R0_C_REGNUM
3275 && reg_nr
< tdep
->FP0_C_REGNUM
)
3276 return builtin_type_int
;
3278 return builtin_type_long_long
;
3281 static struct type
*
3282 sh_default_register_virtual_type (int reg_nr
)
3284 return builtin_type_int
;
3287 /* On the sh4, the DRi pseudo registers are problematic if the target
3288 is little endian. When the user writes one of those registers, for
3289 instance with 'ser var $dr0=1', we want the double to be stored
3291 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3292 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3294 This corresponds to little endian byte order & big endian word
3295 order. However if we let gdb write the register w/o conversion, it
3296 will write fr0 and fr1 this way:
3297 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3298 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3299 because it will consider fr0 and fr1 as a single LE stretch of memory.
3301 To achieve what we want we must force gdb to store things in
3302 floatformat_ieee_double_littlebyte_bigword (which is defined in
3303 include/floatformat.h and libiberty/floatformat.c.
3305 In case the target is big endian, there is no problem, the
3306 raw bytes will look like:
3307 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
3308 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3310 The other pseudo registers (the FVs) also don't pose a problem
3311 because they are stored as 4 individual FP elements. */
3314 sh_sh4_register_convertible (int nr
)
3316 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3318 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
3319 return (tdep
->DR0_REGNUM
<= nr
3320 && nr
<= tdep
->DR_LAST_REGNUM
);
3326 sh_sh4_register_convert_to_virtual (int regnum
, struct type
*type
,
3327 char *from
, char *to
)
3329 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3331 if (regnum
>= tdep
->DR0_REGNUM
3332 && regnum
<= tdep
->DR_LAST_REGNUM
)
3335 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
, from
, &val
);
3336 store_floating (to
, TYPE_LENGTH (type
), val
);
3339 error ("sh_register_convert_to_virtual called with non DR register number");
3343 sh_sh64_register_convert_to_virtual (int regnum
, struct type
*type
,
3344 char *from
, char *to
)
3346 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3348 if (TARGET_BYTE_ORDER
!= BFD_ENDIAN_LITTLE
)
3350 /* It is a no-op. */
3351 memcpy (to
, from
, REGISTER_RAW_SIZE (regnum
));
3355 if ((regnum
>= tdep
->DR0_REGNUM
3356 && regnum
<= tdep
->DR_LAST_REGNUM
)
3357 || (regnum
>= tdep
->DR0_C_REGNUM
3358 && regnum
<= tdep
->DR_LAST_C_REGNUM
))
3361 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
, from
, &val
);
3362 store_floating(to
, TYPE_LENGTH(type
), val
);
3365 error("sh_register_convert_to_virtual called with non DR register number");
3369 sh_sh4_register_convert_to_raw (struct type
*type
, int regnum
,
3370 char *from
, char *to
)
3372 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3374 if (regnum
>= tdep
->DR0_REGNUM
3375 && regnum
<= tdep
->DR_LAST_REGNUM
)
3377 DOUBLEST val
= extract_floating (from
, TYPE_LENGTH(type
));
3378 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
, &val
, to
);
3381 error("sh_register_convert_to_raw called with non DR register number");
3385 sh_sh64_register_convert_to_raw (struct type
*type
, int regnum
,
3386 char *from
, char *to
)
3388 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3390 if (TARGET_BYTE_ORDER
!= BFD_ENDIAN_LITTLE
)
3392 /* It is a no-op. */
3393 memcpy (to
, from
, REGISTER_RAW_SIZE (regnum
));
3397 if ((regnum
>= tdep
->DR0_REGNUM
3398 && regnum
<= tdep
->DR_LAST_REGNUM
)
3399 || (regnum
>= tdep
->DR0_C_REGNUM
3400 && regnum
<= tdep
->DR_LAST_C_REGNUM
))
3402 DOUBLEST val
= extract_floating (from
, TYPE_LENGTH(type
));
3403 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
, &val
, to
);
3406 error("sh_register_convert_to_raw called with non DR register number");
3410 sh_pseudo_register_read (int reg_nr
, char *buffer
)
3412 int base_regnum
, portion
;
3413 char *temp_buffer
= (char*) alloca (MAX_REGISTER_RAW_SIZE
);
3414 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3416 if (reg_nr
>= tdep
->DR0_REGNUM
3417 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3419 base_regnum
= dr_reg_base_num (reg_nr
);
3421 /* Build the value in the provided buffer. */
3422 /* Read the real regs for which this one is an alias. */
3423 for (portion
= 0; portion
< 2; portion
++)
3424 regcache_read (base_regnum
+ portion
,
3426 + REGISTER_RAW_SIZE (base_regnum
) * portion
);
3427 /* We must pay attention to the endiannes. */
3428 sh_sh4_register_convert_to_virtual (reg_nr
,
3429 REGISTER_VIRTUAL_TYPE (reg_nr
),
3430 temp_buffer
, buffer
);
3432 else if (reg_nr
>= tdep
->FV0_REGNUM
3433 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3435 base_regnum
= fv_reg_base_num (reg_nr
);
3437 /* Read the real regs for which this one is an alias. */
3438 for (portion
= 0; portion
< 4; portion
++)
3439 regcache_read (base_regnum
+ portion
,
3440 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3445 sh4_register_read (struct gdbarch
*gdbarch
, int reg_nr
, char *buffer
)
3447 if (reg_nr
>= 0 && reg_nr
< gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
)
3448 /* It is a regular register. */
3449 regcache_read (reg_nr
, buffer
);
3451 /* It is a pseudo register and we need to construct its value */
3452 sh_pseudo_register_read (reg_nr
, buffer
);
3456 sh64_pseudo_register_read (int reg_nr
, char *buffer
)
3461 char *temp_buffer
= (char*) alloca (MAX_REGISTER_RAW_SIZE
);
3462 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3464 if (reg_nr
>= tdep
->DR0_REGNUM
3465 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3467 base_regnum
= dr_reg_base_num (reg_nr
);
3469 /* Build the value in the provided buffer. */
3470 /* DR regs are double precision registers obtained by
3471 concatenating 2 single precision floating point registers. */
3472 for (portion
= 0; portion
< 2; portion
++)
3473 regcache_read (base_regnum
+ portion
,
3475 + REGISTER_RAW_SIZE (base_regnum
) * portion
);
3477 /* We must pay attention to the endiannes. */
3478 sh_sh64_register_convert_to_virtual (reg_nr
, REGISTER_VIRTUAL_TYPE (reg_nr
),
3479 temp_buffer
, buffer
);
3483 else if (reg_nr
>= tdep
->FPP0_REGNUM
3484 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3486 base_regnum
= fpp_reg_base_num (reg_nr
);
3488 /* Build the value in the provided buffer. */
3489 /* FPP regs are pairs of single precision registers obtained by
3490 concatenating 2 single precision floating point registers. */
3491 for (portion
= 0; portion
< 2; portion
++)
3492 regcache_read (base_regnum
+ portion
,
3493 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3496 else if (reg_nr
>= tdep
->FV0_REGNUM
3497 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3499 base_regnum
= fv_reg_base_num (reg_nr
);
3501 /* Build the value in the provided buffer. */
3502 /* FV regs are vectors of single precision registers obtained by
3503 concatenating 4 single precision floating point registers. */
3504 for (portion
= 0; portion
< 4; portion
++)
3505 regcache_read (base_regnum
+ portion
,
3506 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3509 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
3510 else if (reg_nr
>= tdep
->R0_C_REGNUM
3511 && reg_nr
<= tdep
->T_C_REGNUM
)
3513 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3515 /* Build the value in the provided buffer. */
3516 regcache_read (base_regnum
, temp_buffer
);
3517 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3519 memcpy (buffer
, temp_buffer
+ offset
, 4); /* get LOWER 32 bits only????*/
3522 else if (reg_nr
>= tdep
->FP0_C_REGNUM
3523 && reg_nr
<= tdep
->FP_LAST_C_REGNUM
)
3525 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3527 /* Build the value in the provided buffer. */
3528 /* Floating point registers map 1-1 to the media fp regs,
3529 they have the same size and endienness. */
3530 regcache_read (base_regnum
, buffer
);
3533 else if (reg_nr
>= tdep
->DR0_C_REGNUM
3534 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
)
3536 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3538 /* DR_C regs are double precision registers obtained by
3539 concatenating 2 single precision floating point registers. */
3540 for (portion
= 0; portion
< 2; portion
++)
3541 regcache_read (base_regnum
+ portion
,
3543 + REGISTER_RAW_SIZE (base_regnum
) * portion
);
3545 /* We must pay attention to the endiannes. */
3546 sh_sh64_register_convert_to_virtual (reg_nr
, REGISTER_VIRTUAL_TYPE (reg_nr
),
3547 temp_buffer
, buffer
);
3550 else if (reg_nr
>= tdep
->FV0_C_REGNUM
3551 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
3553 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3555 /* Build the value in the provided buffer. */
3556 /* FV_C regs are vectors of single precision registers obtained by
3557 concatenating 4 single precision floating point registers. */
3558 for (portion
= 0; portion
< 4; portion
++)
3559 regcache_read (base_regnum
+ portion
,
3560 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3563 else if (reg_nr
== tdep
->FPSCR_C_REGNUM
)
3565 int fpscr_base_regnum
;
3567 unsigned int fpscr_value
;
3568 unsigned int sr_value
;
3569 unsigned int fpscr_c_value
;
3570 unsigned int fpscr_c_part1_value
;
3571 unsigned int fpscr_c_part2_value
;
3573 fpscr_base_regnum
= tdep
->FPSCR_REGNUM
;
3574 sr_base_regnum
= tdep
->SR_REGNUM
;
3576 /* Build the value in the provided buffer. */
3577 /* FPSCR_C is a very weird register that contains sparse bits
3578 from the FPSCR and the SR architectural registers.
3585 2-17 Bit 2-18 of FPSCR
3586 18-20 Bits 12,13,14 of SR
3590 /* Get FPSCR into a local buffer */
3591 regcache_read (fpscr_base_regnum
, temp_buffer
);
3592 /* Get value as an int. */
3593 fpscr_value
= extract_unsigned_integer (temp_buffer
, 4);
3594 /* Get SR into a local buffer */
3595 regcache_read (sr_base_regnum
, temp_buffer
);
3596 /* Get value as an int. */
3597 sr_value
= extract_unsigned_integer (temp_buffer
, 4);
3598 /* Build the new value. */
3599 fpscr_c_part1_value
= fpscr_value
& 0x3fffd;
3600 fpscr_c_part2_value
= (sr_value
& 0x7000) << 6;
3601 fpscr_c_value
= fpscr_c_part1_value
| fpscr_c_part2_value
;
3602 /* Store that in out buffer!!! */
3603 store_unsigned_integer (buffer
, 4, fpscr_c_value
);
3604 /* FIXME There is surely an endianness gotcha here. */
3607 else if (reg_nr
== tdep
->FPUL_C_REGNUM
)
3609 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3611 /* FPUL_C register is floating point register 32,
3612 same size, same endianness. */
3613 regcache_read (base_regnum
, buffer
);
3618 sh64_register_read (struct gdbarch
*gdbarch
, int reg_nr
, char *buffer
)
3621 if (reg_nr
>= 0 && reg_nr
< gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
)
3622 /* It is a regular register. */
3623 regcache_read (reg_nr
, buffer
);
3625 /* It is a pseudo register and we need to construct its value */
3626 sh64_pseudo_register_read (reg_nr
, buffer
);
3630 sh_pseudo_register_write (int reg_nr
, char *buffer
)
3632 int base_regnum
, portion
;
3633 char *temp_buffer
= (char*) alloca (MAX_REGISTER_RAW_SIZE
);
3634 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3636 if (reg_nr
>= tdep
->DR0_REGNUM
3637 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3639 base_regnum
= dr_reg_base_num (reg_nr
);
3641 /* We must pay attention to the endiannes. */
3642 sh_sh4_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr
), reg_nr
,
3643 buffer
, temp_buffer
);
3645 /* Write the real regs for which this one is an alias. */
3646 for (portion
= 0; portion
< 2; portion
++)
3647 regcache_write (base_regnum
+ portion
,
3648 temp_buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3650 else if (reg_nr
>= tdep
->FV0_REGNUM
3651 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3653 base_regnum
= fv_reg_base_num (reg_nr
);
3655 /* Write the real regs for which this one is an alias. */
3656 for (portion
= 0; portion
< 4; portion
++)
3657 regcache_write (base_regnum
+ portion
,
3658 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3663 sh4_register_write (struct gdbarch
*gdbarch
, int reg_nr
, char *buffer
)
3665 if (reg_nr
>= 0 && reg_nr
< gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
)
3666 /* It is a regular register. */
3667 regcache_write (reg_nr
, buffer
);
3669 /* It is a pseudo register and we need to construct its value */
3670 sh_pseudo_register_write (reg_nr
, buffer
);
3674 sh64_pseudo_register_write (int reg_nr
, char *buffer
)
3676 int base_regnum
, portion
;
3678 char *temp_buffer
= (char*) alloca (MAX_REGISTER_RAW_SIZE
);
3679 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3681 if (reg_nr
>= tdep
->DR0_REGNUM
3682 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3684 base_regnum
= dr_reg_base_num (reg_nr
);
3685 /* We must pay attention to the endiannes. */
3686 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr
), reg_nr
,
3687 buffer
, temp_buffer
);
3690 /* Write the real regs for which this one is an alias. */
3691 for (portion
= 0; portion
< 2; portion
++)
3692 regcache_write (base_regnum
+ portion
,
3693 temp_buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3696 else if (reg_nr
>= tdep
->FPP0_REGNUM
3697 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3699 base_regnum
= fpp_reg_base_num (reg_nr
);
3701 /* Write the real regs for which this one is an alias. */
3702 for (portion
= 0; portion
< 2; portion
++)
3703 regcache_write (base_regnum
+ portion
,
3704 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3707 else if (reg_nr
>= tdep
->FV0_REGNUM
3708 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3710 base_regnum
= fv_reg_base_num (reg_nr
);
3712 /* Write the real regs for which this one is an alias. */
3713 for (portion
= 0; portion
< 4; portion
++)
3714 regcache_write (base_regnum
+ portion
,
3715 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3718 /* sh compact general pseudo registers. 1-to-1 with a shmedia
3719 register but only 4 bytes of it. */
3720 else if (reg_nr
>= tdep
->R0_C_REGNUM
3721 && reg_nr
<= tdep
->T_C_REGNUM
)
3723 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3724 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
3725 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3729 /* Let's read the value of the base register into a temporary
3730 buffer, so that overwriting the last four bytes with the new
3731 value of the pseudo will leave the upper 4 bytes unchanged. */
3732 regcache_read (base_regnum
, temp_buffer
);
3733 /* Write as an 8 byte quantity */
3734 memcpy (temp_buffer
+ offset
, buffer
, 4);
3735 regcache_write (base_regnum
, temp_buffer
);
3738 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
3739 registers. Both are 4 bytes. */
3740 else if (reg_nr
>= tdep
->FP0_C_REGNUM
3741 && reg_nr
<= tdep
->FP_LAST_C_REGNUM
)
3743 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3744 regcache_write (base_regnum
, buffer
);
3747 else if (reg_nr
>= tdep
->DR0_C_REGNUM
3748 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
)
3750 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3751 for (portion
= 0; portion
< 2; portion
++)
3753 /* We must pay attention to the endiannes. */
3754 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr
), reg_nr
,
3755 buffer
, temp_buffer
);
3757 regcache_write (base_regnum
+ portion
,
3758 temp_buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3762 else if (reg_nr
>= tdep
->FV0_C_REGNUM
3763 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
3765 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3767 for (portion
= 0; portion
< 4; portion
++)
3769 regcache_write (base_regnum
+ portion
,
3770 buffer
+ REGISTER_RAW_SIZE (base_regnum
) * portion
);
3774 else if (reg_nr
== tdep
->FPSCR_C_REGNUM
)
3776 int fpscr_base_regnum
;
3778 unsigned int fpscr_value
;
3779 unsigned int sr_value
;
3780 unsigned int old_fpscr_value
;
3781 unsigned int old_sr_value
;
3782 unsigned int fpscr_c_value
;
3783 unsigned int fpscr_mask
;
3784 unsigned int sr_mask
;
3786 fpscr_base_regnum
= tdep
->FPSCR_REGNUM
;
3787 sr_base_regnum
= tdep
->SR_REGNUM
;
3789 /* FPSCR_C is a very weird register that contains sparse bits
3790 from the FPSCR and the SR architectural registers.
3797 2-17 Bit 2-18 of FPSCR
3798 18-20 Bits 12,13,14 of SR
3802 /* Get value as an int. */
3803 fpscr_c_value
= extract_unsigned_integer (buffer
, 4);
3805 /* Build the new values. */
3806 fpscr_mask
= 0x0003fffd;
3807 sr_mask
= 0x001c0000;
3809 fpscr_value
= fpscr_c_value
& fpscr_mask
;
3810 sr_value
= (fpscr_value
& sr_mask
) >> 6;
3812 regcache_read (fpscr_base_regnum
, temp_buffer
);
3813 old_fpscr_value
= extract_unsigned_integer (temp_buffer
, 4);
3814 old_fpscr_value
&= 0xfffc0002;
3815 fpscr_value
|= old_fpscr_value
;
3816 store_unsigned_integer (temp_buffer
, 4, fpscr_value
);
3817 regcache_write (fpscr_base_regnum
, temp_buffer
);
3819 regcache_read (sr_base_regnum
, temp_buffer
);
3820 old_sr_value
= extract_unsigned_integer (temp_buffer
, 4);
3821 old_sr_value
&= 0xffff8fff;
3822 sr_value
|= old_sr_value
;
3823 store_unsigned_integer (temp_buffer
, 4, sr_value
);
3824 regcache_write (sr_base_regnum
, temp_buffer
);
3827 else if (reg_nr
== tdep
->FPUL_C_REGNUM
)
3829 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3830 regcache_write (base_regnum
, buffer
);
3835 sh64_register_write (struct gdbarch
*gdbarch
, int reg_nr
, char *buffer
)
3837 if (reg_nr
>= 0 && reg_nr
< gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
)
3838 /* It is a regular register. */
3839 regcache_write (reg_nr
, buffer
);
3841 /* It is a pseudo register and we need to construct its value */
3842 sh64_pseudo_register_write (reg_nr
, buffer
);
3845 /* Floating point vector of 4 float registers. */
3847 do_fv_register_info (int fv_regnum
)
3849 int first_fp_reg_num
= fv_reg_base_num (fv_regnum
);
3850 printf_filtered ("fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3851 fv_regnum
- gdbarch_tdep (current_gdbarch
)->FV0_REGNUM
,
3852 (int) read_register (first_fp_reg_num
),
3853 (int) read_register (first_fp_reg_num
+ 1),
3854 (int) read_register (first_fp_reg_num
+ 2),
3855 (int) read_register (first_fp_reg_num
+ 3));
3858 /* Floating point vector of 4 float registers, compact mode. */
3860 do_fv_c_register_info (int fv_regnum
)
3862 int first_fp_reg_num
= sh64_compact_reg_base_num (fv_regnum
);
3863 printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3864 fv_regnum
- gdbarch_tdep (current_gdbarch
)->FV0_C_REGNUM
,
3865 (int) read_register (first_fp_reg_num
),
3866 (int) read_register (first_fp_reg_num
+ 1),
3867 (int) read_register (first_fp_reg_num
+ 2),
3868 (int) read_register (first_fp_reg_num
+ 3));
3871 /* Pairs of single regs. The DR are instead double precision
3874 do_fpp_register_info (int fpp_regnum
)
3876 int first_fp_reg_num
= fpp_reg_base_num (fpp_regnum
);
3878 printf_filtered ("fpp%d\t0x%08x\t0x%08x\n",
3879 fpp_regnum
- gdbarch_tdep (current_gdbarch
)->FPP0_REGNUM
,
3880 (int) read_register (first_fp_reg_num
),
3881 (int) read_register (first_fp_reg_num
+ 1));
3884 /* Double precision registers. */
3886 do_dr_register_info (int dr_regnum
)
3888 int first_fp_reg_num
= dr_reg_base_num (dr_regnum
);
3890 printf_filtered ("dr%d\t0x%08x%08x\n",
3891 dr_regnum
- gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
,
3892 (int) read_register (first_fp_reg_num
),
3893 (int) read_register (first_fp_reg_num
+ 1));
3896 /* Double precision registers, compact mode. */
3898 do_dr_c_register_info (int dr_regnum
)
3900 int first_fp_reg_num
= sh64_compact_reg_base_num (dr_regnum
);
3902 printf_filtered ("dr%d_c\t0x%08x%08x\n",
3903 dr_regnum
- gdbarch_tdep (current_gdbarch
)->DR0_C_REGNUM
,
3904 (int) read_register (first_fp_reg_num
),
3905 (int) read_register (first_fp_reg_num
+1));
3908 /* General register in compact mode. */
3910 do_r_c_register_info (int r_c_regnum
)
3912 int regnum
= sh64_compact_reg_base_num (r_c_regnum
);
3914 printf_filtered ("r%d_c\t0x%08x\n",
3915 r_c_regnum
- gdbarch_tdep (current_gdbarch
)->R0_C_REGNUM
,
3916 /*FIXME!!!*/ (int) read_register (regnum
));
3919 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
3920 shmedia REGISTERS. */
3921 /* Control registers, compact mode. */
3923 do_cr_c_register_info (int cr_c_regnum
)
3925 switch (cr_c_regnum
)
3927 case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3929 case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3931 case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3933 case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3935 case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3937 case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3939 case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3941 case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum
));
3947 sh_do_pseudo_register (int regnum
)
3949 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3951 if (regnum
< NUM_REGS
|| regnum
>= NUM_REGS
+ NUM_PSEUDO_REGS
)
3952 internal_error (__FILE__
, __LINE__
,
3953 "Invalid pseudo register number %d\n", regnum
);
3954 else if (regnum
>= tdep
->DR0_REGNUM
3955 && regnum
< tdep
->DR_LAST_REGNUM
)
3956 do_dr_register_info (regnum
);
3957 else if (regnum
>= tdep
->FV0_REGNUM
3958 && regnum
<= tdep
->FV_LAST_REGNUM
)
3959 do_fv_register_info (regnum
);
3963 sh_do_fp_register (int regnum
)
3964 { /* do values for FP (float) regs */
3966 double flt
; /* double extracted from raw hex data */
3970 /* Allocate space for the float. */
3971 raw_buffer
= (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
3973 /* Get the data in raw format. */
3974 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
3975 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
3977 /* Get the register as a number */
3978 flt
= unpack_double (builtin_type_float
, raw_buffer
, &inv
);
3980 /* Print the name and some spaces. */
3981 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
3982 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum
)), gdb_stdout
);
3984 /* Print the value. */
3986 printf_filtered ("<invalid float>");
3988 printf_filtered ("%-10.9g", flt
);
3990 /* Print the fp register as hex. */
3991 printf_filtered ("\t(raw 0x");
3992 for (j
= 0; j
< REGISTER_RAW_SIZE (regnum
); j
++)
3994 register int idx
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? j
3995 : REGISTER_RAW_SIZE (regnum
) - 1 - j
;
3996 printf_filtered ("%02x", (unsigned char) raw_buffer
[idx
]);
3998 printf_filtered (")");
3999 printf_filtered ("\n");
4003 sh64_do_pseudo_register (int regnum
)
4005 /* All the sh64-compact mode registers are pseudo registers. */
4006 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4008 if (regnum
< NUM_REGS
4009 || regnum
>= NUM_REGS
+ NUM_PSEUDO_REGS_SH_MEDIA
+ NUM_PSEUDO_REGS_SH_COMPACT
)
4010 internal_error (__FILE__
, __LINE__
,
4011 "Invalid pseudo register number %d\n", regnum
);
4013 else if ((regnum
>= tdep
->DR0_REGNUM
4014 && regnum
<= tdep
->DR_LAST_REGNUM
))
4015 do_dr_register_info (regnum
);
4017 else if ((regnum
>= tdep
->DR0_C_REGNUM
4018 && regnum
<= tdep
->DR_LAST_C_REGNUM
))
4019 do_dr_c_register_info (regnum
);
4021 else if ((regnum
>= tdep
->FV0_REGNUM
4022 && regnum
<= tdep
->FV_LAST_REGNUM
))
4023 do_fv_register_info (regnum
);
4025 else if ((regnum
>= tdep
->FV0_C_REGNUM
4026 && regnum
<= tdep
->FV_LAST_C_REGNUM
))
4027 do_fv_c_register_info (regnum
);
4029 else if (regnum
>= tdep
->FPP0_REGNUM
4030 && regnum
<= tdep
->FPP_LAST_REGNUM
)
4031 do_fpp_register_info (regnum
);
4033 else if (regnum
>= tdep
->R0_C_REGNUM
4034 && regnum
<= tdep
->R_LAST_C_REGNUM
)
4035 do_r_c_register_info (regnum
); /* FIXME, this function will not print the right format */
4037 else if (regnum
>= tdep
->FP0_C_REGNUM
4038 && regnum
<= tdep
->FP_LAST_C_REGNUM
)
4039 sh_do_fp_register (regnum
); /* this should work also for pseudoregs */
4041 else if (regnum
>= tdep
->PC_C_REGNUM
4042 && regnum
<= tdep
->FPUL_C_REGNUM
)
4043 do_cr_c_register_info (regnum
);
4048 sh_do_register (int regnum
)
4050 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
4052 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
4053 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum
)), gdb_stdout
);
4055 /* Get the data in raw format. */
4056 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
4057 printf_filtered ("*value not available*\n");
4059 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
4060 gdb_stdout
, 'x', 1, 0, Val_pretty_default
);
4061 printf_filtered ("\t");
4062 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
4063 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
4064 printf_filtered ("\n");
4068 sh_print_register (int regnum
)
4070 if (regnum
< 0 || regnum
>= NUM_REGS
+ NUM_PSEUDO_REGS
)
4071 internal_error (__FILE__
, __LINE__
,
4072 "Invalid register number %d\n", regnum
);
4074 else if (regnum
>= 0 && regnum
< NUM_REGS
)
4076 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
4077 sh_do_fp_register (regnum
); /* FP regs */
4079 sh_do_register (regnum
); /* All other regs */
4082 else if (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4083 do_pseudo_register (regnum
);
4087 sh_do_registers_info (int regnum
, int fpregs
)
4089 if (regnum
!= -1) /* do one specified register */
4091 if (*(REGISTER_NAME (regnum
)) == '\0')
4092 error ("Not a valid register for the current processor type");
4094 sh_print_register (regnum
);
4097 /* do all (or most) registers */
4100 while (regnum
< NUM_REGS
)
4102 /* If the register name is empty, it is undefined for this
4103 processor, so don't display anything. */
4104 if (REGISTER_NAME (regnum
) == NULL
4105 || *(REGISTER_NAME (regnum
)) == '\0')
4111 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
4115 /* true for "INFO ALL-REGISTERS" command */
4116 sh_do_fp_register (regnum
); /* FP regs */
4120 regnum
+= (gdbarch_tdep (current_gdbarch
)->FP_LAST_REGNUM
- FP0_REGNUM
); /* skip FP regs */
4124 sh_do_register (regnum
); /* All other regs */
4130 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4132 do_pseudo_register (regnum
);
4139 sh_compact_do_registers_info (int regnum
, int fpregs
)
4141 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4142 if (regnum
!= -1) /* do one specified register */
4144 if (*(REGISTER_NAME (regnum
)) == '\0')
4145 error ("Not a valid register for the current processor type");
4147 if (regnum
>= 0 && regnum
< tdep
->R0_C_REGNUM
)
4148 error ("Not a valid register for the current processor mode.");
4150 sh_print_register (regnum
);
4153 /* do all compact registers */
4155 regnum
= tdep
->R0_C_REGNUM
;
4156 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4158 do_pseudo_register (regnum
);
4165 sh64_do_registers_info (int regnum
, int fpregs
)
4167 if (pc_is_isa32 (selected_frame
->pc
))
4168 sh_do_registers_info (regnum
, fpregs
);
4170 sh_compact_do_registers_info (regnum
, fpregs
);
4173 #ifdef SVR4_SHARED_LIBS
4175 /* Fetch (and possibly build) an appropriate link_map_offsets structure
4176 for native i386 linux targets using the struct offsets defined in
4177 link.h (but without actual reference to that file).
4179 This makes it possible to access i386-linux shared libraries from
4180 a gdb that was not built on an i386-linux host (for cross debugging).
4183 struct link_map_offsets
*
4184 sh_linux_svr4_fetch_link_map_offsets (void)
4186 static struct link_map_offsets lmo
;
4187 static struct link_map_offsets
*lmp
= 0;
4193 lmo
.r_debug_size
= 8; /* 20 not actual size but all we need */
4195 lmo
.r_map_offset
= 4;
4198 lmo
.link_map_size
= 20; /* 552 not actual size but all we need */
4200 lmo
.l_addr_offset
= 0;
4201 lmo
.l_addr_size
= 4;
4203 lmo
.l_name_offset
= 4;
4204 lmo
.l_name_size
= 4;
4206 lmo
.l_next_offset
= 12;
4207 lmo
.l_next_size
= 4;
4209 lmo
.l_prev_offset
= 16;
4210 lmo
.l_prev_size
= 4;
4215 #endif /* SVR4_SHARED_LIBS */
4218 /* This table matches the indices assigned to enum sh_osabi. Keep
4220 static const char * const sh_osabi_names
[] =
4229 process_note_abi_tag_sections (bfd
*abfd
, asection
*sect
, void *obj
)
4231 enum sh_osabi
*os_ident_ptr
= obj
;
4233 unsigned int sectsize
;
4235 name
= bfd_get_section_name (abfd
, sect
);
4236 sectsize
= bfd_section_size (abfd
, sect
);
4238 if (strcmp (name
, ".note.ABI-tag") == 0 && sectsize
> 0)
4240 unsigned int name_length
, data_length
, note_type
;
4243 /* If the section is larger than this, it's probably not what we are
4248 note
= alloca (sectsize
);
4250 bfd_get_section_contents (abfd
, sect
, note
,
4251 (file_ptr
) 0, (bfd_size_type
) sectsize
);
4253 name_length
= bfd_h_get_32 (abfd
, note
);
4254 data_length
= bfd_h_get_32 (abfd
, note
+ 4);
4255 note_type
= bfd_h_get_32 (abfd
, note
+ 8);
4257 if (name_length
== 4 && data_length
== 16 && note_type
== NT_GNU_ABI_TAG
4258 && strcmp (note
+ 12, "GNU") == 0)
4260 int os_number
= bfd_h_get_32 (abfd
, note
+ 16);
4262 /* The case numbers are from abi-tags in glibc. */
4265 case GNU_ABI_TAG_LINUX
:
4266 *os_ident_ptr
= SH_OSABI_LINUX
;
4269 case GNU_ABI_TAG_HURD
:
4271 (__FILE__
, __LINE__
,
4272 "process_note_abi_sections: Hurd objects not supported");
4275 case GNU_ABI_TAG_SOLARIS
:
4277 (__FILE__
, __LINE__
,
4278 "process_note_abi_sections: Solaris objects not supported");
4283 (__FILE__
, __LINE__
,
4284 "process_note_abi_sections: unknown OS number %d",
4289 /* NetBSD uses a similar trick. */
4290 else if (strcmp (name
, ".note.netbsd.ident") == 0 && sectsize
> 0)
4292 unsigned int name_length
, desc_length
, note_type
;
4295 /* If the section is larger than this, it's probably not what we are
4300 note
= alloca (sectsize
);
4302 bfd_get_section_contents (abfd
, sect
, note
,
4303 (file_ptr
) 0, (bfd_size_type
) sectsize
);
4305 name_length
= bfd_h_get_32 (abfd
, note
);
4306 desc_length
= bfd_h_get_32 (abfd
, note
+ 4);
4307 note_type
= bfd_h_get_32 (abfd
, note
+ 8);
4309 if (name_length
== 7 && desc_length
== 4 && note_type
== NT_NETBSD_IDENT
4310 && strcmp (note
+ 12, "NetBSD") == 0)
4311 /* XXX Should we check the version here?
4312 Probably not necessary yet. */
4313 *os_ident_ptr
= SH_OSABI_NETBSD_ELF
;
4318 get_elfosabi (bfd
*abfd
)
4321 enum sh_osabi sh_osabi
= SH_OSABI_UNKNOWN
;
4323 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
4328 /* When elfosabi is 0 (ELFOSABI_NONE), this is supposed to indicate
4329 that we're on a SYSV system. However, some systems use note sections
4330 to record OS/ABI info, but leave e_ident[EI_OSABI] zero. So we
4331 have to check the note sections too. */
4332 bfd_map_over_sections (abfd
,
4333 process_note_abi_tag_sections
,
4337 case ELFOSABI_NETBSD
:
4338 sh_osabi
= SH_OSABI_NETBSD_ELF
;
4341 case ELFOSABI_LINUX
:
4342 sh_osabi
= SH_OSABI_LINUX
;
4349 struct sh_osabi_handler
4351 struct sh_osabi_handler
*next
;
4353 void (*init_osabi
)(struct gdbarch_info
, struct gdbarch
*);
4356 struct sh_osabi_handler
*sh_osabi_handler_list
= NULL
;
4359 sh_gdbarch_register_os_abi (enum sh_osabi abi
,
4360 void (*init_osabi
)(struct gdbarch_info
,
4363 struct sh_osabi_handler
**handler_p
;
4365 for (handler_p
= &sh_osabi_handler_list
; *handler_p
!= NULL
;
4366 handler_p
= &(*handler_p
)->next
)
4368 if ((*handler_p
)->abi
== abi
)
4371 (__FILE__
, __LINE__
,
4372 "sh_gdbarch_register_os_abi: A handler for this ABI variant "
4373 "(%d) has already been registered", (int) abi
);
4374 /* If user wants to continue, override previous definition. */
4375 (*handler_p
)->init_osabi
= init_osabi
;
4381 = (struct sh_osabi_handler
*) xmalloc (sizeof (struct sh_osabi_handler
));
4382 (*handler_p
)->next
= NULL
;
4383 (*handler_p
)->abi
= abi
;
4384 (*handler_p
)->init_osabi
= init_osabi
;
4387 static gdbarch_init_ftype sh_gdbarch_init
;
4389 static struct gdbarch
*
4390 sh_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
4392 static LONGEST sh_call_dummy_words
[] = {0};
4393 struct gdbarch
*gdbarch
;
4394 struct gdbarch_tdep
*tdep
;
4395 gdbarch_register_name_ftype
*sh_register_name
;
4396 gdbarch_store_return_value_ftype
*sh_store_return_value
;
4397 gdbarch_register_virtual_type_ftype
*sh_register_virtual_type
;
4398 enum sh_osabi sh_osabi
= SH_OSABI_UNKNOWN
;
4399 struct sh_osabi_handler
*osabi_handler
;
4401 /* Try to determine the ABI of the object we are loading. */
4403 if (info
.abfd
!= NULL
)
4405 switch (bfd_get_flavour (info
.abfd
))
4407 case bfd_target_elf_flavour
:
4408 sh_osabi
= get_elfosabi (info
.abfd
);
4412 /* Just leave it as "unkown". */
4417 /* Find a candidate among the list of pre-declared architectures. */
4418 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4420 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4422 /* Make sure the ABI selection matches. */
4423 tdep
= gdbarch_tdep (arches
->gdbarch
);
4424 if (tdep
&& tdep
->sh_osabi
== sh_osabi
)
4425 return arches
->gdbarch
;
4428 /* None found, create a new architecture from the information
4430 tdep
= XMALLOC (struct gdbarch_tdep
);
4431 gdbarch
= gdbarch_alloc (&info
, tdep
);
4433 tdep
->sh_osabi
= sh_osabi
;
4434 if (sh_osabi
< SH_OSABI_INVALID
)
4435 tdep
->osabi_name
= sh_osabi_names
[sh_osabi
];
4438 internal_error (__FILE__
, __LINE__
, "Invalid setting of sh_osabi %d",
4440 tdep
->osabi_name
= "<invalid>";
4443 /* Initialize the register numbers that are not common to all the
4444 variants to -1, if necessary thse will be overwritten in the case
4446 tdep
->FPUL_REGNUM
= -1;
4447 tdep
->FPSCR_REGNUM
= -1;
4448 tdep
->PR_REGNUM
= 17;
4449 tdep
->SR_REGNUM
= 22;
4450 tdep
->DSR_REGNUM
= -1;
4451 tdep
->FP_LAST_REGNUM
= -1;
4452 tdep
->A0G_REGNUM
= -1;
4453 tdep
->A0_REGNUM
= -1;
4454 tdep
->A1G_REGNUM
= -1;
4455 tdep
->A1_REGNUM
= -1;
4456 tdep
->M0_REGNUM
= -1;
4457 tdep
->M1_REGNUM
= -1;
4458 tdep
->X0_REGNUM
= -1;
4459 tdep
->X1_REGNUM
= -1;
4460 tdep
->Y0_REGNUM
= -1;
4461 tdep
->Y1_REGNUM
= -1;
4462 tdep
->MOD_REGNUM
= -1;
4463 tdep
->RS_REGNUM
= -1;
4464 tdep
->RE_REGNUM
= -1;
4465 tdep
->SSR_REGNUM
= -1;
4466 tdep
->SPC_REGNUM
= -1;
4467 tdep
->DR0_REGNUM
= -1;
4468 tdep
->DR_LAST_REGNUM
= -1;
4469 tdep
->FV0_REGNUM
= -1;
4470 tdep
->FV_LAST_REGNUM
= -1;
4471 tdep
->ARG0_REGNUM
= 4;
4472 tdep
->ARGLAST_REGNUM
= 7;
4473 tdep
->RETURN_REGNUM
= 0;
4474 tdep
->FLOAT_ARGLAST_REGNUM
= -1;
4476 tdep
->sh_abi
= SH_ABI_UNKNOWN
;
4478 set_gdbarch_fp0_regnum (gdbarch
, -1);
4479 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
4480 set_gdbarch_max_register_raw_size (gdbarch
, 4);
4481 set_gdbarch_max_register_virtual_size (gdbarch
, 4);
4482 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4483 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4484 set_gdbarch_num_regs (gdbarch
, SH_DEFAULT_NUM_REGS
);
4485 set_gdbarch_sp_regnum (gdbarch
, 15);
4486 set_gdbarch_fp_regnum (gdbarch
, 14);
4487 set_gdbarch_pc_regnum (gdbarch
, 16);
4488 set_gdbarch_register_size (gdbarch
, 4);
4489 set_gdbarch_register_bytes (gdbarch
, SH_DEFAULT_NUM_REGS
* 4);
4490 set_gdbarch_do_registers_info (gdbarch
, sh_do_registers_info
);
4491 set_gdbarch_breakpoint_from_pc (gdbarch
, sh_breakpoint_from_pc
);
4492 set_gdbarch_frame_chain (gdbarch
, sh_frame_chain
);
4493 set_gdbarch_get_saved_register (gdbarch
, generic_get_saved_register
);
4494 set_gdbarch_init_extra_frame_info (gdbarch
, sh_init_extra_frame_info
);
4495 set_gdbarch_extract_return_value (gdbarch
, sh_extract_return_value
);
4496 set_gdbarch_push_arguments (gdbarch
, sh_push_arguments
);
4497 set_gdbarch_store_struct_return (gdbarch
, sh_store_struct_return
);
4498 set_gdbarch_use_struct_convention (gdbarch
, sh_use_struct_convention
);
4499 set_gdbarch_extract_struct_value_address (gdbarch
, sh_extract_struct_value_address
);
4500 set_gdbarch_pop_frame (gdbarch
, sh_pop_frame
);
4501 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_sh
);
4502 skip_prologue_hard_way
= sh_skip_prologue_hard_way
;
4503 do_pseudo_register
= sh_do_pseudo_register
;
4505 switch (info
.bfd_arch_info
->mach
)
4508 sh_register_name
= sh_sh_register_name
;
4509 sh_show_regs
= sh_generic_show_regs
;
4510 sh_store_return_value
= sh_default_store_return_value
;
4511 sh_register_virtual_type
= sh_default_register_virtual_type
;
4512 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4513 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4514 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4515 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4518 sh_register_name
= sh_sh_register_name
;
4519 sh_show_regs
= sh_generic_show_regs
;
4520 sh_store_return_value
= sh_default_store_return_value
;
4521 sh_register_virtual_type
= sh_default_register_virtual_type
;
4522 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4523 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4524 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4525 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4527 case bfd_mach_sh_dsp
:
4528 sh_register_name
= sh_sh_dsp_register_name
;
4529 sh_show_regs
= sh_dsp_show_regs
;
4530 sh_store_return_value
= sh_default_store_return_value
;
4531 sh_register_virtual_type
= sh_default_register_virtual_type
;
4532 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4533 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4534 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4535 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4536 tdep
->DSR_REGNUM
= 24;
4537 tdep
->A0G_REGNUM
= 25;
4538 tdep
->A0_REGNUM
= 26;
4539 tdep
->A1G_REGNUM
= 27;
4540 tdep
->A1_REGNUM
= 28;
4541 tdep
->M0_REGNUM
= 29;
4542 tdep
->M1_REGNUM
= 30;
4543 tdep
->X0_REGNUM
= 31;
4544 tdep
->X1_REGNUM
= 32;
4545 tdep
->Y0_REGNUM
= 33;
4546 tdep
->Y1_REGNUM
= 34;
4547 tdep
->MOD_REGNUM
= 40;
4548 tdep
->RS_REGNUM
= 43;
4549 tdep
->RE_REGNUM
= 44;
4552 sh_register_name
= sh_sh3_register_name
;
4553 sh_show_regs
= sh3_show_regs
;
4554 sh_store_return_value
= sh_default_store_return_value
;
4555 sh_register_virtual_type
= sh_default_register_virtual_type
;
4556 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4557 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4558 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4559 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4560 tdep
->SSR_REGNUM
= 41;
4561 tdep
->SPC_REGNUM
= 42;
4564 sh_register_name
= sh_sh3e_register_name
;
4565 sh_show_regs
= sh3e_show_regs
;
4566 sh_store_return_value
= sh3e_sh4_store_return_value
;
4567 sh_register_virtual_type
= sh_sh3e_register_virtual_type
;
4568 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_fp_frame_init_saved_regs
);
4569 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4570 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4571 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4572 set_gdbarch_extract_return_value (gdbarch
, sh3e_sh4_extract_return_value
);
4573 set_gdbarch_fp0_regnum (gdbarch
, 25);
4574 tdep
->FPUL_REGNUM
= 23;
4575 tdep
->FPSCR_REGNUM
= 24;
4576 tdep
->FP_LAST_REGNUM
= 40;
4577 tdep
->SSR_REGNUM
= 41;
4578 tdep
->SPC_REGNUM
= 42;
4580 case bfd_mach_sh3_dsp
:
4581 sh_register_name
= sh_sh3_dsp_register_name
;
4582 sh_show_regs
= sh3_dsp_show_regs
;
4583 sh_store_return_value
= sh_default_store_return_value
;
4584 sh_register_virtual_type
= sh_default_register_virtual_type
;
4585 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4586 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4587 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4588 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4589 tdep
->DSR_REGNUM
= 24;
4590 tdep
->A0G_REGNUM
= 25;
4591 tdep
->A0_REGNUM
= 26;
4592 tdep
->A1G_REGNUM
= 27;
4593 tdep
->A1_REGNUM
= 28;
4594 tdep
->M0_REGNUM
= 29;
4595 tdep
->M1_REGNUM
= 30;
4596 tdep
->X0_REGNUM
= 31;
4597 tdep
->X1_REGNUM
= 32;
4598 tdep
->Y0_REGNUM
= 33;
4599 tdep
->Y1_REGNUM
= 34;
4600 tdep
->MOD_REGNUM
= 40;
4601 tdep
->RS_REGNUM
= 43;
4602 tdep
->RE_REGNUM
= 44;
4603 tdep
->SSR_REGNUM
= 41;
4604 tdep
->SPC_REGNUM
= 42;
4607 sh_register_name
= sh_sh4_register_name
;
4608 sh_show_regs
= sh4_show_regs
;
4609 sh_store_return_value
= sh3e_sh4_store_return_value
;
4610 sh_register_virtual_type
= sh_sh4_register_virtual_type
;
4611 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_fp_frame_init_saved_regs
);
4612 set_gdbarch_extract_return_value (gdbarch
, sh3e_sh4_extract_return_value
);
4613 set_gdbarch_fp0_regnum (gdbarch
, 25);
4614 set_gdbarch_register_raw_size (gdbarch
, sh_sh4_register_raw_size
);
4615 set_gdbarch_register_virtual_size (gdbarch
, sh_sh4_register_raw_size
);
4616 set_gdbarch_register_byte (gdbarch
, sh_sh4_register_byte
);
4617 set_gdbarch_num_pseudo_regs (gdbarch
, 12);
4618 set_gdbarch_max_register_raw_size (gdbarch
, 4 * 4);
4619 set_gdbarch_max_register_virtual_size (gdbarch
, 4 * 4);
4620 set_gdbarch_register_read (gdbarch
, sh4_register_read
);
4621 set_gdbarch_register_write (gdbarch
, sh4_register_write
);
4622 tdep
->FPUL_REGNUM
= 23;
4623 tdep
->FPSCR_REGNUM
= 24;
4624 tdep
->FP_LAST_REGNUM
= 40;
4625 tdep
->SSR_REGNUM
= 41;
4626 tdep
->SPC_REGNUM
= 42;
4627 tdep
->DR0_REGNUM
= 59;
4628 tdep
->DR_LAST_REGNUM
= 66;
4629 tdep
->FV0_REGNUM
= 67;
4630 tdep
->FV_LAST_REGNUM
= 70;
4633 tdep
->PR_REGNUM
= 18;
4634 tdep
->SR_REGNUM
= 65;
4635 tdep
->FPSCR_REGNUM
= SIM_SH64_FPCSR_REGNUM
;
4636 tdep
->FP_LAST_REGNUM
= SIM_SH64_FR0_REGNUM
+ SIM_SH64_NR_FP_REGS
- 1;
4637 tdep
->SSR_REGNUM
= SIM_SH64_SSR_REGNUM
;
4638 tdep
->SPC_REGNUM
= SIM_SH64_SPC_REGNUM
;
4639 tdep
->TR7_REGNUM
= SIM_SH64_TR0_REGNUM
+ 7;
4640 tdep
->FPP0_REGNUM
= 173;
4641 tdep
->FPP_LAST_REGNUM
= 204;
4642 tdep
->DR0_REGNUM
= 141;
4643 tdep
->DR_LAST_REGNUM
= 172;
4644 tdep
->FV0_REGNUM
= 205;
4645 tdep
->FV_LAST_REGNUM
= 220;
4646 tdep
->R0_C_REGNUM
= 221;
4647 tdep
->R_LAST_C_REGNUM
= 236;
4648 tdep
->PC_C_REGNUM
= 237;
4649 tdep
->GBR_C_REGNUM
= 238;
4650 tdep
->MACH_C_REGNUM
= 239;
4651 tdep
->MACL_C_REGNUM
= 240;
4652 tdep
->PR_C_REGNUM
= 241;
4653 tdep
->T_C_REGNUM
= 242;
4654 tdep
->FPSCR_C_REGNUM
= 243;
4655 tdep
->FPUL_C_REGNUM
= 244;
4656 tdep
->FP0_C_REGNUM
= 245;
4657 tdep
->FP_LAST_C_REGNUM
= 260;
4658 tdep
->DR0_C_REGNUM
= 261;
4659 tdep
->DR_LAST_C_REGNUM
= 268;
4660 tdep
->FV0_C_REGNUM
= 269;
4661 tdep
->FV_LAST_C_REGNUM
= 272;
4662 tdep
->ARG0_REGNUM
= 2;
4663 tdep
->ARGLAST_REGNUM
= 9;
4664 tdep
->RETURN_REGNUM
= 2;
4665 tdep
->FLOAT_ARGLAST_REGNUM
= 11;
4667 set_gdbarch_num_pseudo_regs (gdbarch
, NUM_PSEUDO_REGS_SH_MEDIA
+ NUM_PSEUDO_REGS_SH_COMPACT
);
4668 set_gdbarch_fp0_regnum (gdbarch
, SIM_SH64_FR0_REGNUM
);
4669 set_gdbarch_pc_regnum (gdbarch
, 64);
4671 /* Determine the ABI */
4672 if (bfd_get_arch_size (info
.abfd
) == 64)
4674 /* If the ABI is the 64-bit one, it can only be sh-media. */
4675 tdep
->sh_abi
= SH_ABI_64
;
4676 set_gdbarch_ptr_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4677 set_gdbarch_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4681 /* If the ABI is the 32-bit one it could be either media or
4683 tdep
->sh_abi
= SH_ABI_32
;
4684 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4685 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4688 /* the number of real registers is the same whether we are in
4689 ISA16(compact) or ISA32(media). */
4690 set_gdbarch_num_regs (gdbarch
, SIM_SH64_NR_REGS
);
4691 set_gdbarch_register_size (gdbarch
, 8); /*????*/
4692 set_gdbarch_register_bytes (gdbarch
,
4693 ((SIM_SH64_NR_FP_REGS
+ 1) * 4)
4694 + (SIM_SH64_NR_REGS
- SIM_SH64_NR_FP_REGS
-1) * 8);
4696 sh_register_name
= sh_sh64_register_name
;
4697 sh_show_regs
= sh64_show_regs
;
4698 sh_register_virtual_type
= sh_sh64_register_virtual_type
;
4699 sh_store_return_value
= sh64_store_return_value
;
4700 skip_prologue_hard_way
= sh64_skip_prologue_hard_way
;
4701 do_pseudo_register
= sh64_do_pseudo_register
;
4702 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_sh64
);
4703 set_gdbarch_register_raw_size (gdbarch
, sh_sh64_register_raw_size
);
4704 set_gdbarch_register_virtual_size (gdbarch
, sh_sh64_register_raw_size
);
4705 set_gdbarch_register_byte (gdbarch
, sh_sh64_register_byte
);
4706 /* This seems awfully wrong!*/
4707 /*set_gdbarch_max_register_raw_size (gdbarch, 8);*/
4708 /* should include the size of the pseudo regs. */
4709 set_gdbarch_max_register_raw_size (gdbarch
, 4 * 4);
4710 /* Or should that go in the virtual_size? */
4711 /*set_gdbarch_max_register_virtual_size (gdbarch, 8);*/
4712 set_gdbarch_max_register_virtual_size (gdbarch
, 4 * 4);
4713 set_gdbarch_register_read (gdbarch
, sh64_register_read
);
4714 set_gdbarch_register_write (gdbarch
, sh64_register_write
);
4716 set_gdbarch_do_registers_info (gdbarch
, sh64_do_registers_info
);
4717 set_gdbarch_frame_init_saved_regs (gdbarch
, sh64_nofp_frame_init_saved_regs
);
4718 set_gdbarch_breakpoint_from_pc (gdbarch
, sh_sh64_breakpoint_from_pc
);
4719 set_gdbarch_init_extra_frame_info (gdbarch
, sh64_init_extra_frame_info
);
4720 set_gdbarch_frame_chain (gdbarch
, sh64_frame_chain
);
4721 set_gdbarch_get_saved_register (gdbarch
, sh64_get_saved_register
);
4722 set_gdbarch_extract_return_value (gdbarch
, sh64_extract_return_value
);
4723 set_gdbarch_push_arguments (gdbarch
, sh64_push_arguments
);
4724 /*set_gdbarch_store_struct_return (gdbarch, sh64_store_struct_return);*/
4725 set_gdbarch_extract_struct_value_address (gdbarch
, sh64_extract_struct_value_address
);
4726 set_gdbarch_use_struct_convention (gdbarch
, sh64_use_struct_convention
);
4727 set_gdbarch_pop_frame (gdbarch
, sh64_pop_frame
);
4728 set_gdbarch_elf_make_msymbol_special (gdbarch
,
4729 sh64_elf_make_msymbol_special
);
4732 sh_register_name
= sh_generic_register_name
;
4733 sh_show_regs
= sh_generic_show_regs
;
4734 sh_store_return_value
= sh_default_store_return_value
;
4735 sh_register_virtual_type
= sh_default_register_virtual_type
;
4736 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4737 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4738 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4739 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4743 set_gdbarch_read_pc (gdbarch
, generic_target_read_pc
);
4744 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
4745 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
4746 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
4747 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
4749 set_gdbarch_register_name (gdbarch
, sh_register_name
);
4750 set_gdbarch_register_virtual_type (gdbarch
, sh_register_virtual_type
);
4752 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
4753 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4754 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4755 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4756 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4757 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);/*??should be 8?*/
4759 set_gdbarch_use_generic_dummy_frames (gdbarch
, 1);
4760 set_gdbarch_call_dummy_length (gdbarch
, 0);
4761 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
4762 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
4763 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1); /*???*/
4764 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
4765 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
4766 set_gdbarch_pc_in_call_dummy (gdbarch
, generic_pc_in_call_dummy
);
4767 set_gdbarch_call_dummy_words (gdbarch
, sh_call_dummy_words
);
4768 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (sh_call_dummy_words
));
4769 set_gdbarch_call_dummy_p (gdbarch
, 1);
4770 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
4771 set_gdbarch_fix_call_dummy (gdbarch
, generic_fix_call_dummy
);
4772 set_gdbarch_coerce_float_to_double (gdbarch
,
4773 sh_coerce_float_to_double
);
4775 set_gdbarch_push_dummy_frame (gdbarch
, generic_push_dummy_frame
);
4776 set_gdbarch_push_return_address (gdbarch
, sh_push_return_address
);
4778 set_gdbarch_store_return_value (gdbarch
, sh_store_return_value
);
4779 set_gdbarch_skip_prologue (gdbarch
, sh_skip_prologue
);
4780 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4781 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
4782 set_gdbarch_function_start_offset (gdbarch
, 0);
4784 set_gdbarch_frame_args_skip (gdbarch
, 0);
4785 set_gdbarch_frameless_function_invocation (gdbarch
, frameless_look_for_prologue
);
4786 set_gdbarch_frame_chain_valid (gdbarch
, generic_file_frame_chain_valid
);
4787 set_gdbarch_frame_saved_pc (gdbarch
, sh_frame_saved_pc
);
4788 set_gdbarch_frame_args_address (gdbarch
, default_frame_address
);
4789 set_gdbarch_frame_locals_address (gdbarch
, default_frame_address
);
4790 set_gdbarch_saved_pc_after_call (gdbarch
, sh_saved_pc_after_call
);
4791 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
4792 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
4794 /* Hook in ABI-specific overrides, if they have been registered. If
4795 the ABI is unknown, this is probably an embedded target, so we
4796 should not warn about this situation. */
4797 if (sh_osabi
!= SH_OSABI_UNKNOWN
)
4799 for (osabi_handler
= sh_osabi_handler_list
; osabi_handler
!= NULL
;
4800 osabi_handler
= osabi_handler
->next
)
4801 if (osabi_handler
->abi
== sh_osabi
)
4805 osabi_handler
->init_osabi (info
, gdbarch
);
4808 /* We assume that if GDB_MULTI_ARCH is less than
4809 GDB_MULTI_ARCH_TM that an ABI variant can be supported by
4810 overriding definitions in this file. */
4811 if (GDB_MULTI_ARCH
> GDB_MULTI_ARCH_PARTIAL
)
4814 "A handler for the ABI variant \"%s\" is not built into this "
4815 "configuration of GDB. "
4816 "Attempting to continue with the default SuperH settings",
4817 sh_osabi_names
[sh_osabi
]);
4825 sh_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
4827 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4832 if (tdep
->osabi_name
!= NULL
)
4833 fprintf_unfiltered (file
, "sh_dump_tdep: OS ABI = %s\n", tdep
->osabi_name
);
4835 internal_error (__FILE__
, __LINE__
,
4836 "sh_dump_tdep: illegal setting of tdep->sh_osabi (%d)",
4837 (int) tdep
->sh_osabi
);
4841 _initialize_sh_tdep (void)
4843 struct cmd_list_element
*c
;
4845 gdbarch_register (bfd_arch_sh
, sh_gdbarch_init
, sh_dump_tdep
);
4847 add_com ("regs", class_vars
, sh_show_regs_command
, "Print all registers");