gdb/sh-tdep.c

   1 /* Target-dependent code for Hitachi Super-H, for GDB.
   2    Copyright 1993, 1994, 1995, 1996, 1997, 1998 Free Software Foundation, Inc.
   3
   4 This file is part of GDB.
   5
   6 This program is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 2 of the License, or
   9 (at your option) any later version.
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with this program; if not, write to the Free Software
  18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  19
  20 /*
  21  Contributed by Steve Chamberlain
  22                 sac@cygnus.com
  23  */
  24
  25 #include "defs.h"
  26 #include "frame.h"
  27 #include "obstack.h"
  28 #include "symtab.h"
  29 #include "symfile.h"
  30 #include "gdbtypes.h"
  31 #include "gdbcmd.h"
  32 #include "gdbcore.h"
  33 #include "value.h"
  34 #include "dis-asm.h"
  35 #include "inferior.h"           /* for BEFORE_TEXT_END etc. */
  36 #include "gdb_string.h"
  37
  38 /* A set of original names, to be used when restoring back to generic
  39    registers from a specific set.  */
  40
  41 char *sh_generic_reg_names[] = REGISTER_NAMES;
  42
  43 char *sh_reg_names[] = {
  44   "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
  45   "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
  46   "pc",   "pr",   "gbr",  "vbr",  "mach", "macl", "sr",
  47   "",     "",
  48   "",     "",     "",     "",     "",     "",     "",     "",
  49   "",     "",     "",     "",     "",     "",     "",     "",
  50   "",     "",
  51   "",     "",     "",     "",     "",     "",     "",     "",
  52   "",     "",     "",     "",     "",     "",     "",     "",
  53 };
  54
  55 char *sh3_reg_names[] = {
  56   "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
  57   "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
  58   "pc",   "pr",   "gbr",  "vbr",  "mach", "macl", "sr",
  59   "",     "",
  60   "",     "",     "",     "",     "",     "",     "",     "",
  61   "",     "",     "",     "",     "",     "",     "",     "",
  62   "ssr",  "spc",
  63   "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
  64   "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
  65 };
  66
  67 char *sh3e_reg_names[] = {
  68   "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
  69   "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
  70   "pc",   "pr",   "gbr",  "vbr",  "mach", "macl", "sr",
  71   "fpul", "fpscr",
  72   "fr0",  "fr1",  "fr2",  "fr3",  "fr4",  "fr5",  "fr6",  "fr7",
  73   "fr8",  "fr9",  "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
  74   "ssr",  "spc",
  75   "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
  76   "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
  77 };
  78
  79 struct {
  80   char **regnames;
  81   int mach;
  82 } sh_processor_type_table[] = {
  83   { sh_reg_names, bfd_mach_sh },
  84   { sh3_reg_names, bfd_mach_sh3 },
  85   { sh3e_reg_names, bfd_mach_sh3e },
  86   { sh3e_reg_names, bfd_mach_sh4 },
  87   { NULL, 0 }
  88 };
  89
  90 /* Prologue looks like
  91    [mov.l       <regs>,@-r15]...
  92    [sts.l       pr,@-r15]
  93    [mov.l       r14,@-r15]
  94    [mov         r15,r14]
  95 */
  96
  97 #define IS_STS(x)               ((x) == 0x4f22)
  98 #define IS_PUSH(x)              (((x) & 0xff0f) == 0x2f06)
  99 #define GET_PUSHED_REG(x)       (((x) >> 4) & 0xf)
 100 #define IS_MOV_SP_FP(x)         ((x) == 0x6ef3)
 101 #define IS_ADD_SP(x)            (((x) & 0xff00) == 0x7f00)
 102 #define IS_MOV_R3(x)            (((x) & 0xff00) == 0x1a00)
 103 #define IS_SHLL_R3(x)           ((x) == 0x4300)
 104 #define IS_ADD_R3SP(x)          ((x) == 0x3f3c)
 105 #define IS_FMOV(x)              (((x) & 0xf00f) == 0xf00b)
 106 #define FPSCR_SZ                (1 << 20)
 107
 108 /* Skip any prologue before the guts of a function */
 109
 110 CORE_ADDR
 111 sh_skip_prologue (start_pc)
 112      CORE_ADDR start_pc;
 113 {
 114   int w;
 115
 116   w = read_memory_integer (start_pc, 2);
 117   while (IS_STS (w)
 118          || IS_FMOV (w)
 119          || IS_PUSH (w)
 120          || IS_MOV_SP_FP (w)
 121          || IS_MOV_R3 (w)
 122          || IS_ADD_R3SP (w)
 123          || IS_ADD_SP (w)
 124          || IS_SHLL_R3 (w))
 125     {
 126       start_pc += 2;
 127       w = read_memory_integer (start_pc, 2);
 128     }
 129
 130   return start_pc;
 131 }
 132
 133 /* Disassemble an instruction.  */
 134
 135 int
 136 gdb_print_insn_sh (memaddr, info)
 137      bfd_vma memaddr;
 138      disassemble_info *info;
 139 {
 140   if (TARGET_BYTE_ORDER == BIG_ENDIAN)
 141     return print_insn_sh (memaddr, info);
 142   else
 143     return print_insn_shl (memaddr, info);
 144 }
 145
 146 /* Given a GDB frame, determine the address of the calling function's frame.
 147    This will be used to create a new GDB frame struct, and then
 148    INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
 149
 150    For us, the frame address is its stack pointer value, so we look up
 151    the function prologue to determine the caller's sp value, and return it.  */
 152
 153 CORE_ADDR
 154 sh_frame_chain (frame)
 155      struct frame_info *frame;
 156 {
 157   if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
 158     return frame->frame;        /* dummy frame same as caller's frame */
 159   if (!inside_entry_file (frame->pc))
 160     return read_memory_integer (FRAME_FP (frame) + frame->f_offset, 4);
 161   else
 162     return 0;
 163 }
 164
 165 /* Find REGNUM on the stack.  Otherwise, it's in an active register.  One thing
 166    we might want to do here is to check REGNUM against the clobber mask, and
 167    somehow flag it as invalid if it isn't saved on the stack somewhere.  This
 168    would provide a graceful failure mode when trying to get the value of
 169    caller-saves registers for an inner frame.  */
 170
 171 CORE_ADDR
 172 sh_find_callers_reg (fi, regnum)
 173      struct frame_info *fi;
 174      int regnum;
 175 {
 176   struct frame_saved_regs fsr;
 177
 178   for (; fi; fi = fi->next)
 179     if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
 180       /* When the caller requests PR from the dummy frame, we return PC because
 181          that's where the previous routine appears to have done a call from. */
 182       return generic_read_register_dummy (fi->pc, fi->frame, regnum);
 183     else
 184       {
 185         FRAME_FIND_SAVED_REGS(fi, fsr);
 186         if (fsr.regs[regnum] != 0)
 187           return read_memory_integer (fsr.regs[regnum],
 188                                       REGISTER_RAW_SIZE(regnum));
 189       }
 190   return read_register (regnum);
 191 }
 192
 193 /* Put here the code to store, into a struct frame_saved_regs, the
 194    addresses of the saved registers of frame described by FRAME_INFO.
 195    This includes special registers such as pc and fp saved in special
 196    ways in the stack frame.  sp is even more special: the address we
 197    return for it IS the sp for the next frame. */
 198
 199 void
 200 sh_frame_find_saved_regs (fi, fsr)
 201      struct frame_info *fi;
 202      struct frame_saved_regs *fsr;
 203 {
 204   int where[NUM_REGS];
 205   int rn;
 206   int have_fp = 0;
 207   int depth;
 208   int pc;
 209   int opc;
 210   int insn;
 211   int r3_val = 0;
 212   char * dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame);
 213
 214   if (dummy_regs)
 215     {
 216       /* DANGER!  This is ONLY going to work if the char buffer format of
 217          the saved registers is byte-for-byte identical to the
 218          CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
 219       memcpy (&fsr->regs, dummy_regs, sizeof(fsr));
 220       return;
 221     }
 222
 223   opc = pc = get_pc_function_start (fi->pc);
 224
 225   insn = read_memory_integer (pc, 2);
 226
 227   fi->leaf_function = 1;
 228   fi->f_offset = 0;
 229
 230   for (rn = 0; rn < NUM_REGS; rn++)
 231     where[rn] = -1;
 232
 233   depth = 0;
 234
 235   /* Loop around examining the prologue insns until we find something
 236      that does not appear to be part of the prologue.  But give up
 237      after 20 of them, since we're getting silly then. */
 238
 239   while (pc < opc + 20 * 2)
 240     {
 241       /* See where the registers will be saved to */
 242       if (IS_PUSH (insn))
 243         {
 244           pc += 2;
 245           rn = GET_PUSHED_REG (insn);
 246           where[rn] = depth;
 247           insn = read_memory_integer (pc, 2);
 248           depth += 4;
 249         }
 250       else if (IS_STS (insn))
 251         {
 252           pc += 2;
 253           where[PR_REGNUM] = depth;
 254           insn = read_memory_integer (pc, 2);
 255           /* If we're storing the pr then this isn't a leaf */
 256           fi->leaf_function = 0;
 257           depth += 4;
 258         }
 259       else if (IS_MOV_R3 (insn))
 260         {
 261           r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
 262           pc += 2;
 263           insn = read_memory_integer (pc, 2);
 264         }
 265       else if (IS_SHLL_R3 (insn))
 266         {
 267           r3_val <<= 1;
 268           pc += 2;
 269           insn = read_memory_integer (pc, 2);
 270         }
 271       else if (IS_ADD_R3SP (insn))
 272         {
 273           depth += -r3_val;
 274           pc += 2;
 275           insn = read_memory_integer (pc, 2);
 276         }
 277       else if (IS_ADD_SP (insn))
 278         {
 279           pc += 2;
 280           depth -= ((insn & 0xff) ^ 0x80) - 0x80;
 281           insn = read_memory_integer (pc, 2);
 282         }
 283       else if (IS_FMOV (insn))
 284         {
 285           pc += 2;
 286           insn = read_memory_integer (pc, 2);
 287           if (read_register (FPSCR_REGNUM) & FPSCR_SZ)
 288             {
 289               depth += 8;
 290             }
 291           else
 292             {
 293               depth += 4;
 294             }
 295         }
 296       else
 297         break;
 298     }
 299
 300   /* Now we know how deep things are, we can work out their addresses */
 301
 302   for (rn = 0; rn < NUM_REGS; rn++)
 303     {
 304       if (where[rn] >= 0)
 305         {
 306           if (rn == FP_REGNUM)
 307             have_fp = 1;
 308
 309           fsr->regs[rn] = fi->frame - where[rn] + depth - 4;
 310         }
 311       else
 312         {
 313           fsr->regs[rn] = 0;
 314         }
 315     }
 316
 317   if (have_fp)
 318     {
 319       fsr->regs[SP_REGNUM] = read_memory_integer (fsr->regs[FP_REGNUM], 4);
 320     }
 321   else
 322     {
 323       fsr->regs[SP_REGNUM] = fi->frame - 4;
 324     }
 325
 326   fi->f_offset = depth - where[FP_REGNUM] - 4;
 327   /* Work out the return pc - either from the saved pr or the pr
 328      value */
 329 }
 330
 331 /* initialize the extra info saved in a FRAME */
 332
 333 void
 334 sh_init_extra_frame_info (fromleaf, fi)
 335      int fromleaf;
 336      struct frame_info *fi;
 337 {
 338   struct frame_saved_regs fsr;
 339
 340   if (fi->next)
 341     fi->pc = FRAME_SAVED_PC (fi->next);
 342
 343   if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
 344     {
 345       /* We need to setup fi->frame here because run_stack_dummy gets it wrong
 346          by assuming it's always FP.  */
 347       fi->frame     = generic_read_register_dummy (fi->pc, fi->frame,
 348                                                    SP_REGNUM);
 349       fi->return_pc = generic_read_register_dummy (fi->pc, fi->frame,
 350                                                    PC_REGNUM);
 351       fi->f_offset = -(CALL_DUMMY_LENGTH + 4);
 352       fi->leaf_function = 0;
 353       return;
 354     }
 355   else
 356     {
 357       FRAME_FIND_SAVED_REGS (fi, fsr);
 358       fi->return_pc = sh_find_callers_reg (fi, PR_REGNUM);
 359     }
 360 }
 361
 362 /* Discard from the stack the innermost frame,
 363    restoring all saved registers.  */
 364
 365 void
 366 sh_pop_frame ()
 367 {
 368   register struct frame_info *frame = get_current_frame ();
 369   register CORE_ADDR fp;
 370   register int regnum;
 371   struct frame_saved_regs fsr;
 372
 373   if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
 374     generic_pop_dummy_frame ();
 375   else
 376   {
 377     fp = FRAME_FP (frame);
 378     get_frame_saved_regs (frame, &fsr);
 379
 380     /* Copy regs from where they were saved in the frame */
 381     for (regnum = 0; regnum < NUM_REGS; regnum++)
 382       if (fsr.regs[regnum])
 383         write_register (regnum, read_memory_integer (fsr.regs[regnum], 4));
 384
 385     write_register (PC_REGNUM, frame->return_pc);
 386     write_register (SP_REGNUM, fp + 4);
 387   }
 388   flush_cached_frames ();
 389 }
 390
 391 /* Function: push_arguments
 392    Setup the function arguments for calling a function in the inferior.
 393
 394    On the Hitachi SH architecture, there are four registers (R4 to R7)
 395    which are dedicated for passing function arguments.  Up to the first
 396    four arguments (depending on size) may go into these registers.
 397    The rest go on the stack.
 398
 399    Arguments that are smaller than 4 bytes will still take up a whole
 400    register or a whole 32-bit word on the stack, and will be
 401    right-justified in the register or the stack word.  This includes
 402    chars, shorts, and small aggregate types.
 403
 404    Arguments that are larger than 4 bytes may be split between two or
 405    more registers.  If there are not enough registers free, an argument
 406    may be passed partly in a register (or registers), and partly on the
 407    stack.  This includes doubles, long longs, and larger aggregates.
 408    As far as I know, there is no upper limit to the size of aggregates
 409    that will be passed in this way; in other words, the convention of
 410    passing a pointer to a large aggregate instead of a copy is not used.
 411
 412    An exceptional case exists for struct arguments (and possibly other
 413    aggregates such as arrays) if the size is larger than 4 bytes but
 414    not a multiple of 4 bytes.  In this case the argument is never split
 415    between the registers and the stack, but instead is copied in its
 416    entirety onto the stack, AND also copied into as many registers as
 417    there is room for.  In other words, space in registers permitting,
 418    two copies of the same argument are passed in.  As far as I can tell,
 419    only the one on the stack is used, although that may be a function
 420    of the level of compiler optimization.  I suspect this is a compiler
 421    bug.  Arguments of these odd sizes are left-justified within the
 422    word (as opposed to arguments smaller than 4 bytes, which are
 423    right-justified).
 424
 425
 426    If the function is to return an aggregate type such as a struct, it
 427    is either returned in the normal return value register R0 (if its
 428    size is no greater than one byte), or else the caller must allocate
 429    space into which the callee will copy the return value (if the size
 430    is greater than one byte).  In this case, a pointer to the return
 431    value location is passed into the callee in register R2, which does
 432    not displace any of the other arguments passed in via registers R4
 433    to R7.   */
 434
 435 CORE_ADDR
 436 sh_push_arguments (nargs, args, sp, struct_return, struct_addr)
 437      int nargs;
 438      value_ptr *args;
 439      CORE_ADDR sp;
 440      unsigned char struct_return;
 441      CORE_ADDR struct_addr;
 442 {
 443   int stack_offset, stack_alloc;
 444   int argreg;
 445   int argnum;
 446   struct type *type;
 447   CORE_ADDR regval;
 448   char *val;
 449   char valbuf[4];
 450   int len;
 451   int odd_sized_struct;
 452
 453   /* first force sp to a 4-byte alignment */
 454   sp = sp & ~3;
 455
 456   /* The "struct return pointer" pseudo-argument has its own dedicated
 457      register */
 458   if (struct_return)
 459       write_register (STRUCT_RETURN_REGNUM, struct_addr);
 460
 461   /* Now make sure there's space on the stack */
 462   for (argnum = 0, stack_alloc = 0;
 463        argnum < nargs; argnum++)
 464     stack_alloc += ((TYPE_LENGTH(VALUE_TYPE(args[argnum])) + 3) & ~3);
 465   sp -= stack_alloc;    /* make room on stack for args */
 466
 467
 468   /* Now load as many as possible of the first arguments into
 469      registers, and push the rest onto the stack.  There are 16 bytes
 470      in four registers available.  Loop thru args from first to last.  */
 471
 472   argreg = ARG0_REGNUM;
 473   for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
 474     {
 475       type = VALUE_TYPE (args[argnum]);
 476       len  = TYPE_LENGTH (type);
 477       memset(valbuf, 0, sizeof(valbuf));
 478       if (len < 4)
 479         { /* value gets right-justified in the register or stack word */
 480           memcpy(valbuf + (4 - len),
 481                  (char *) VALUE_CONTENTS (args[argnum]), len);
 482           val = valbuf;
 483         }
 484       else
 485         val = (char *) VALUE_CONTENTS (args[argnum]);
 486
 487       if (len > 4 && (len & 3) != 0)
 488         odd_sized_struct = 1;           /* such structs go entirely on stack */
 489       else
 490         odd_sized_struct = 0;
 491       while (len > 0)
 492         {
 493           if (argreg > ARGLAST_REGNUM || odd_sized_struct)
 494             {                           /* must go on the stack */
 495               write_memory (sp + stack_offset, val, 4);
 496               stack_offset += 4;
 497             }
 498           /* NOTE WELL!!!!!  This is not an "else if" clause!!!
 499              That's because some *&^%$ things get passed on the stack
 500              AND in the registers!   */
 501           if (argreg <= ARGLAST_REGNUM)
 502             {                           /* there's room in a register */
 503               regval = extract_address (val, REGISTER_RAW_SIZE(argreg));
 504               write_register (argreg++, regval);
 505             }
 506           /* Store the value 4 bytes at a time.  This means that things
 507              larger than 4 bytes may go partly in registers and partly
 508              on the stack.  */
 509           len -= REGISTER_RAW_SIZE(argreg);
 510           val += REGISTER_RAW_SIZE(argreg);
 511         }
 512     }
 513   return sp;
 514 }
 515
 516 /* Function: push_return_address (pc)
 517    Set up the return address for the inferior function call.
 518    Needed for targets where we don't actually execute a JSR/BSR instruction */
 519
 520 CORE_ADDR
 521 sh_push_return_address (pc, sp)
 522      CORE_ADDR pc;
 523      CORE_ADDR sp;
 524 {
 525   write_register (PR_REGNUM, CALL_DUMMY_ADDRESS ());
 526   return sp;
 527 }
 528
 529 /* Function: fix_call_dummy
 530    Poke the callee function's address into the destination part of
 531    the CALL_DUMMY.  The address is actually stored in a data word
 532    following the actualy CALL_DUMMY instructions, which will load
 533    it into a register using PC-relative addressing.  This function
 534    expects the CALL_DUMMY to look like this:
 535
 536         mov.w @(2,PC), R8
 537         jsr   @R8
 538         nop
 539         trap
 540         <destination>
 541   */
 542
 543 #if 0
 544 void
 545 sh_fix_call_dummy (dummy, pc, fun, nargs, args, type, gcc_p)
 546      char *dummy;
 547      CORE_ADDR pc;
 548      CORE_ADDR fun;
 549      int nargs;
 550      value_ptr *args;
 551      struct type *type;
 552      int gcc_p;
 553 {
 554   *(unsigned long *) (dummy + 8) = fun;
 555 }
 556 #endif
 557
 558 /* Function: get_saved_register
 559    Just call the generic_get_saved_register function.  */
 560
 561 void
 562 get_saved_register (raw_buffer, optimized, addrp, frame, regnum, lval)
 563      char *raw_buffer;
 564      int *optimized;
 565      CORE_ADDR *addrp;
 566      struct frame_info *frame;
 567      int regnum;
 568      enum lval_type *lval;
 569 {
 570   generic_get_saved_register (raw_buffer, optimized, addrp,
 571                               frame, regnum, lval);
 572 }
 573
 574
 575 /* Modify the actual processor type. */
 576
 577 int
 578 sh_target_architecture_hook (ap)
 579      const bfd_arch_info_type *ap;
 580 {
 581   int i, j;
 582
 583   if (ap->arch != bfd_arch_sh)
 584     return 0;
 585
 586   for (i = 0; sh_processor_type_table[i].regnames != NULL; i++)
 587     {
 588       if (sh_processor_type_table[i].mach == ap->mach)
 589         {
 590           for (j = 0; j < NUM_REGS; ++j)
 591             reg_names[j] = sh_processor_type_table[i].regnames[j];
 592           return 1;
 593         }
 594     }
 595
 596   fatal ("Architecture `%s' unreconized", ap->printable_name);
 597 }
 598
 599 /* Print the registers in a form similar to the E7000 */
 600
 601 static void
 602 sh_show_regs (args, from_tty)
 603      char *args;
 604      int from_tty;
 605 {
 606   int cpu;
 607   if (target_architecture->arch == bfd_arch_sh)
 608     cpu = target_architecture->mach;
 609   else
 610     cpu = 0;
 611   /* FIXME: sh4 has more registers */
 612   if (cpu == bfd_mach_sh4)
 613     cpu = bfd_mach_sh3;
 614
 615   printf_filtered ("PC=%08x SR=%08x PR=%08x MACH=%08x MACHL=%08x\n",
 616                    read_register (PC_REGNUM),
 617                    read_register (SR_REGNUM),
 618                    read_register (PR_REGNUM),
 619                    read_register (MACH_REGNUM),
 620                    read_register (MACL_REGNUM));
 621
 622   printf_filtered ("GBR=%08x VBR=%08x",
 623                    read_register (GBR_REGNUM),
 624                    read_register (VBR_REGNUM));
 625   if (cpu == bfd_mach_sh3 || cpu == bfd_mach_sh3e)
 626     {
 627       printf_filtered (" SSR=%08x SPC=%08x",
 628                        read_register (SSR_REGNUM),
 629                        read_register (SPC_REGNUM));
 630       if (cpu == bfd_mach_sh3e)
 631         {
 632           printf_filtered (" FPUL=%08x FPSCR=%08x",
 633                            read_register (FPUL_REGNUM),
 634                            read_register (FPSCR_REGNUM));
 635         }
 636     }
 637
 638   printf_filtered ("\nR0-R7  %08x %08x %08x %08x %08x %08x %08x %08x\n",
 639                    read_register (0),
 640                    read_register (1),
 641                    read_register (2),
 642                    read_register (3),
 643                    read_register (4),
 644                    read_register (5),
 645                    read_register (6),
 646                    read_register (7));
 647   printf_filtered ("R8-R15 %08x %08x %08x %08x %08x %08x %08x %08x\n",
 648                    read_register (8),
 649                    read_register (9),
 650                    read_register (10),
 651                    read_register (11),
 652                    read_register (12),
 653                    read_register (13),
 654                    read_register (14),
 655                    read_register (15));
 656   if (cpu == bfd_mach_sh3e)
 657     {
 658       printf_filtered ("FP0-FP7  %08x %08x %08x %08x %08x %08x %08x %08x\n",
 659                        read_register (FP0_REGNUM + 0),
 660                        read_register (FP0_REGNUM + 1),
 661                        read_register (FP0_REGNUM + 2),
 662                        read_register (FP0_REGNUM + 3),
 663                        read_register (FP0_REGNUM + 4),
 664                        read_register (FP0_REGNUM + 5),
 665                        read_register (FP0_REGNUM + 6),
 666                        read_register (FP0_REGNUM + 7));
 667       printf_filtered ("FP8-FP15 %08x %08x %08x %08x %08x %08x %08x %08x\n",
 668                        read_register (FP0_REGNUM + 8),
 669                        read_register (FP0_REGNUM + 9),
 670                        read_register (FP0_REGNUM + 10),
 671                        read_register (FP0_REGNUM + 11),
 672                        read_register (FP0_REGNUM + 12),
 673                        read_register (FP0_REGNUM + 13),
 674                        read_register (FP0_REGNUM + 14),
 675                        read_register (FP0_REGNUM + 15));
 676     }
 677 }
 678
 679 /* Function: extract_return_value
 680    Find a function's return value in the appropriate registers (in regbuf),
 681    and copy it into valbuf.  */
 682
 683 void
 684 sh_extract_return_value (type, regbuf, valbuf)
 685      struct type *type;
 686      void *regbuf;
 687      void *valbuf;
 688 {
 689   int len = TYPE_LENGTH(type);
 690
 691   if (len <= 4)
 692     memcpy (valbuf, ((char *) regbuf) + 4 - len, len);
 693   else if (len <= 8)
 694     memcpy (valbuf, ((char *) regbuf) + 8 - len, len);
 695   else
 696     error ("bad size for return value");
 697 }
 698
 699 void
 700 _initialize_sh_tdep ()
 701 {
 702   struct cmd_list_element *c;
 703
 704   tm_print_insn = gdb_print_insn_sh;
 705
 706   target_architecture_hook = sh_target_architecture_hook;
 707
 708   add_com ("regs", class_vars, sh_show_regs, "Print all registers");
 709 }