gdb/
[deliverable/binutils-gdb.git] / gdb / sh-tdep.c
1 /* Target-dependent code for Renesas Super-H, for GDB.
2
3 Copyright (C) 1993-2005, 2007-2012 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20 /* Contributed by Steve Chamberlain
21 sac@cygnus.com. */
22
23 #include "defs.h"
24 #include "frame.h"
25 #include "frame-base.h"
26 #include "frame-unwind.h"
27 #include "dwarf2-frame.h"
28 #include "symtab.h"
29 #include "gdbtypes.h"
30 #include "gdbcmd.h"
31 #include "gdbcore.h"
32 #include "value.h"
33 #include "dis-asm.h"
34 #include "inferior.h"
35 #include "gdb_string.h"
36 #include "gdb_assert.h"
37 #include "arch-utils.h"
38 #include "floatformat.h"
39 #include "regcache.h"
40 #include "doublest.h"
41 #include "osabi.h"
42 #include "reggroups.h"
43 #include "regset.h"
44 #include "objfiles.h"
45
46 #include "sh-tdep.h"
47 #include "sh64-tdep.h"
48
49 #include "elf-bfd.h"
50 #include "solib-svr4.h"
51
52 /* sh flags */
53 #include "elf/sh.h"
54 #include "dwarf2.h"
55 /* registers numbers shared with the simulator. */
56 #include "gdb/sim-sh.h"
57
58 /* List of "set sh ..." and "show sh ..." commands. */
59 static struct cmd_list_element *setshcmdlist = NULL;
60 static struct cmd_list_element *showshcmdlist = NULL;
61
62 static const char sh_cc_gcc[] = "gcc";
63 static const char sh_cc_renesas[] = "renesas";
64 static const char *const sh_cc_enum[] = {
65 sh_cc_gcc,
66 sh_cc_renesas,
67 NULL
68 };
69
70 static const char *sh_active_calling_convention = sh_cc_gcc;
71
72 static void (*sh_show_regs) (struct frame_info *);
73
74 #define SH_NUM_REGS 67
75
76 struct sh_frame_cache
77 {
78 /* Base address. */
79 CORE_ADDR base;
80 LONGEST sp_offset;
81 CORE_ADDR pc;
82
83 /* Flag showing that a frame has been created in the prologue code. */
84 int uses_fp;
85
86 /* Saved registers. */
87 CORE_ADDR saved_regs[SH_NUM_REGS];
88 CORE_ADDR saved_sp;
89 };
90
91 static int
92 sh_is_renesas_calling_convention (struct type *func_type)
93 {
94 int val = 0;
95
96 if (func_type)
97 {
98 func_type = check_typedef (func_type);
99
100 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
101 func_type = check_typedef (TYPE_TARGET_TYPE (func_type));
102
103 if (TYPE_CODE (func_type) == TYPE_CODE_FUNC
104 && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GNU_renesas_sh)
105 val = 1;
106 }
107
108 if (sh_active_calling_convention == sh_cc_renesas)
109 val = 1;
110
111 return val;
112 }
113
114 static const char *
115 sh_sh_register_name (struct gdbarch *gdbarch, int reg_nr)
116 {
117 static char *register_names[] = {
118 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
119 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
120 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
121 "", "",
122 "", "", "", "", "", "", "", "",
123 "", "", "", "", "", "", "", "",
124 "", "",
125 "", "", "", "", "", "", "", "",
126 "", "", "", "", "", "", "", "",
127 "", "", "", "", "", "", "", "",
128 };
129 if (reg_nr < 0)
130 return NULL;
131 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
132 return NULL;
133 return register_names[reg_nr];
134 }
135
136 static const char *
137 sh_sh3_register_name (struct gdbarch *gdbarch, int reg_nr)
138 {
139 static char *register_names[] = {
140 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
141 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
142 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
143 "", "",
144 "", "", "", "", "", "", "", "",
145 "", "", "", "", "", "", "", "",
146 "ssr", "spc",
147 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
148 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
149 "", "", "", "", "", "", "", "",
150 };
151 if (reg_nr < 0)
152 return NULL;
153 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
154 return NULL;
155 return register_names[reg_nr];
156 }
157
158 static const char *
159 sh_sh3e_register_name (struct gdbarch *gdbarch, int reg_nr)
160 {
161 static char *register_names[] = {
162 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
163 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
164 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
165 "fpul", "fpscr",
166 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
167 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
168 "ssr", "spc",
169 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
170 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
171 "", "", "", "", "", "", "", "",
172 };
173 if (reg_nr < 0)
174 return NULL;
175 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
176 return NULL;
177 return register_names[reg_nr];
178 }
179
180 static const char *
181 sh_sh2e_register_name (struct gdbarch *gdbarch, int reg_nr)
182 {
183 static char *register_names[] = {
184 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
185 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
186 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
187 "fpul", "fpscr",
188 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
189 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
190 "", "",
191 "", "", "", "", "", "", "", "",
192 "", "", "", "", "", "", "", "",
193 "", "", "", "", "", "", "", "",
194 };
195 if (reg_nr < 0)
196 return NULL;
197 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
198 return NULL;
199 return register_names[reg_nr];
200 }
201
202 static const char *
203 sh_sh2a_register_name (struct gdbarch *gdbarch, int reg_nr)
204 {
205 static char *register_names[] = {
206 /* general registers 0-15 */
207 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
208 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
209 /* 16 - 22 */
210 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
211 /* 23, 24 */
212 "fpul", "fpscr",
213 /* floating point registers 25 - 40 */
214 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
215 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
216 /* 41, 42 */
217 "", "",
218 /* 43 - 62. Banked registers. The bank number used is determined by
219 the bank register (63). */
220 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
221 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
222 "machb", "ivnb", "prb", "gbrb", "maclb",
223 /* 63: register bank number, not a real register but used to
224 communicate the register bank currently get/set. This register
225 is hidden to the user, who manipulates it using the pseudo
226 register called "bank" (67). See below. */
227 "",
228 /* 64 - 66 */
229 "ibcr", "ibnr", "tbr",
230 /* 67: register bank number, the user visible pseudo register. */
231 "bank",
232 /* double precision (pseudo) 68 - 75 */
233 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
234 };
235 if (reg_nr < 0)
236 return NULL;
237 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
238 return NULL;
239 return register_names[reg_nr];
240 }
241
242 static const char *
243 sh_sh2a_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
244 {
245 static char *register_names[] = {
246 /* general registers 0-15 */
247 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
248 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
249 /* 16 - 22 */
250 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
251 /* 23, 24 */
252 "", "",
253 /* floating point registers 25 - 40 */
254 "", "", "", "", "", "", "", "",
255 "", "", "", "", "", "", "", "",
256 /* 41, 42 */
257 "", "",
258 /* 43 - 62. Banked registers. The bank number used is determined by
259 the bank register (63). */
260 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
261 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
262 "machb", "ivnb", "prb", "gbrb", "maclb",
263 /* 63: register bank number, not a real register but used to
264 communicate the register bank currently get/set. This register
265 is hidden to the user, who manipulates it using the pseudo
266 register called "bank" (67). See below. */
267 "",
268 /* 64 - 66 */
269 "ibcr", "ibnr", "tbr",
270 /* 67: register bank number, the user visible pseudo register. */
271 "bank",
272 /* double precision (pseudo) 68 - 75 */
273 "", "", "", "", "", "", "", "",
274 };
275 if (reg_nr < 0)
276 return NULL;
277 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
278 return NULL;
279 return register_names[reg_nr];
280 }
281
282 static const char *
283 sh_sh_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
284 {
285 static char *register_names[] = {
286 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
287 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
288 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
289 "", "dsr",
290 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
291 "y0", "y1", "", "", "", "", "", "mod",
292 "", "",
293 "rs", "re", "", "", "", "", "", "",
294 "", "", "", "", "", "", "", "",
295 "", "", "", "", "", "", "", "",
296 };
297 if (reg_nr < 0)
298 return NULL;
299 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
300 return NULL;
301 return register_names[reg_nr];
302 }
303
304 static const char *
305 sh_sh3_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
306 {
307 static char *register_names[] = {
308 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
309 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
310 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
311 "", "dsr",
312 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
313 "y0", "y1", "", "", "", "", "", "mod",
314 "ssr", "spc",
315 "rs", "re", "", "", "", "", "", "",
316 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
317 "", "", "", "", "", "", "", "",
318 "", "", "", "", "", "", "", "",
319 };
320 if (reg_nr < 0)
321 return NULL;
322 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
323 return NULL;
324 return register_names[reg_nr];
325 }
326
327 static const char *
328 sh_sh4_register_name (struct gdbarch *gdbarch, int reg_nr)
329 {
330 static char *register_names[] = {
331 /* general registers 0-15 */
332 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
333 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
334 /* 16 - 22 */
335 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
336 /* 23, 24 */
337 "fpul", "fpscr",
338 /* floating point registers 25 - 40 */
339 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
340 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
341 /* 41, 42 */
342 "ssr", "spc",
343 /* bank 0 43 - 50 */
344 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
345 /* bank 1 51 - 58 */
346 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
347 "", "", "", "", "", "", "", "",
348 /* pseudo bank register. */
349 "",
350 /* double precision (pseudo) 59 - 66 */
351 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
352 /* vectors (pseudo) 67 - 70 */
353 "fv0", "fv4", "fv8", "fv12",
354 /* FIXME: missing XF 71 - 86 */
355 /* FIXME: missing XD 87 - 94 */
356 };
357 if (reg_nr < 0)
358 return NULL;
359 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
360 return NULL;
361 return register_names[reg_nr];
362 }
363
364 static const char *
365 sh_sh4_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
366 {
367 static char *register_names[] = {
368 /* general registers 0-15 */
369 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
370 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
371 /* 16 - 22 */
372 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
373 /* 23, 24 */
374 "", "",
375 /* floating point registers 25 - 40 -- not for nofpu target */
376 "", "", "", "", "", "", "", "",
377 "", "", "", "", "", "", "", "",
378 /* 41, 42 */
379 "ssr", "spc",
380 /* bank 0 43 - 50 */
381 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
382 /* bank 1 51 - 58 */
383 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
384 "", "", "", "", "", "", "", "",
385 /* pseudo bank register. */
386 "",
387 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
388 "", "", "", "", "", "", "", "",
389 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
390 "", "", "", "",
391 };
392 if (reg_nr < 0)
393 return NULL;
394 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
395 return NULL;
396 return register_names[reg_nr];
397 }
398
399 static const char *
400 sh_sh4al_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
401 {
402 static char *register_names[] = {
403 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
404 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
405 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
406 "", "dsr",
407 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
408 "y0", "y1", "", "", "", "", "", "mod",
409 "ssr", "spc",
410 "rs", "re", "", "", "", "", "", "",
411 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
412 "", "", "", "", "", "", "", "",
413 "", "", "", "", "", "", "", "",
414 };
415 if (reg_nr < 0)
416 return NULL;
417 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
418 return NULL;
419 return register_names[reg_nr];
420 }
421
422 static const unsigned char *
423 sh_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
424 {
425 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes. */
426 static unsigned char breakpoint[] = { 0xc3, 0xc3 };
427
428 /* For remote stub targets, trapa #20 is used. */
429 if (strcmp (target_shortname, "remote") == 0)
430 {
431 static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 };
432 static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 };
433
434 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
435 {
436 *lenptr = sizeof (big_remote_breakpoint);
437 return big_remote_breakpoint;
438 }
439 else
440 {
441 *lenptr = sizeof (little_remote_breakpoint);
442 return little_remote_breakpoint;
443 }
444 }
445
446 *lenptr = sizeof (breakpoint);
447 return breakpoint;
448 }
449
450 /* Prologue looks like
451 mov.l r14,@-r15
452 sts.l pr,@-r15
453 mov.l <regs>,@-r15
454 sub <room_for_loca_vars>,r15
455 mov r15,r14
456
457 Actually it can be more complicated than this but that's it, basically. */
458
459 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
460 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
461
462 /* JSR @Rm 0100mmmm00001011 */
463 #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
464
465 /* STS.L PR,@-r15 0100111100100010
466 r15-4-->r15, PR-->(r15) */
467 #define IS_STS(x) ((x) == 0x4f22)
468
469 /* STS.L MACL,@-r15 0100111100010010
470 r15-4-->r15, MACL-->(r15) */
471 #define IS_MACL_STS(x) ((x) == 0x4f12)
472
473 /* MOV.L Rm,@-r15 00101111mmmm0110
474 r15-4-->r15, Rm-->(R15) */
475 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
476
477 /* MOV r15,r14 0110111011110011
478 r15-->r14 */
479 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
480
481 /* ADD #imm,r15 01111111iiiiiiii
482 r15+imm-->r15 */
483 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
484
485 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
486 #define IS_SHLL_R3(x) ((x) == 0x4300)
487
488 /* ADD r3,r15 0011111100111100
489 r15+r3-->r15 */
490 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
491
492 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
493 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
494 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
495 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
496 make this entirely clear. */
497 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
498 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
499
500 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
501 #define IS_MOV_ARG_TO_REG(x) \
502 (((x) & 0xf00f) == 0x6003 && \
503 ((x) & 0x00f0) >= 0x0040 && \
504 ((x) & 0x00f0) <= 0x0070)
505 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
506 #define IS_MOV_ARG_TO_IND_R14(x) \
507 (((x) & 0xff0f) == 0x2e02 && \
508 ((x) & 0x00f0) >= 0x0040 && \
509 ((x) & 0x00f0) <= 0x0070)
510 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
511 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
512 (((x) & 0xff00) == 0x1e00 && \
513 ((x) & 0x00f0) >= 0x0040 && \
514 ((x) & 0x00f0) <= 0x0070)
515
516 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
517 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
518 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
519 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
520 /* MOVI20 #imm20,Rn 0000nnnniiii0000 */
521 #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
522 /* SUB Rn,R15 00111111nnnn1000 */
523 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
524
525 #define FPSCR_SZ (1 << 20)
526
527 /* The following instructions are used for epilogue testing. */
528 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
529 #define IS_RTS(x) ((x) == 0x000b)
530 #define IS_LDS(x) ((x) == 0x4f26)
531 #define IS_MACL_LDS(x) ((x) == 0x4f16)
532 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
533 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
534 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
535
536 static CORE_ADDR
537 sh_analyze_prologue (struct gdbarch *gdbarch,
538 CORE_ADDR pc, CORE_ADDR limit_pc,
539 struct sh_frame_cache *cache, ULONGEST fpscr)
540 {
541 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
542 ULONGEST inst;
543 int offset;
544 int sav_offset = 0;
545 int r3_val = 0;
546 int reg, sav_reg = -1;
547
548 cache->uses_fp = 0;
549 for (; pc < limit_pc; pc += 2)
550 {
551 inst = read_memory_unsigned_integer (pc, 2, byte_order);
552 /* See where the registers will be saved to. */
553 if (IS_PUSH (inst))
554 {
555 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
556 cache->sp_offset += 4;
557 }
558 else if (IS_STS (inst))
559 {
560 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
561 cache->sp_offset += 4;
562 }
563 else if (IS_MACL_STS (inst))
564 {
565 cache->saved_regs[MACL_REGNUM] = cache->sp_offset;
566 cache->sp_offset += 4;
567 }
568 else if (IS_MOV_R3 (inst))
569 {
570 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
571 }
572 else if (IS_SHLL_R3 (inst))
573 {
574 r3_val <<= 1;
575 }
576 else if (IS_ADD_R3SP (inst))
577 {
578 cache->sp_offset += -r3_val;
579 }
580 else if (IS_ADD_IMM_SP (inst))
581 {
582 offset = ((inst & 0xff) ^ 0x80) - 0x80;
583 cache->sp_offset -= offset;
584 }
585 else if (IS_MOVW_PCREL_TO_REG (inst))
586 {
587 if (sav_reg < 0)
588 {
589 reg = GET_TARGET_REG (inst);
590 if (reg < 14)
591 {
592 sav_reg = reg;
593 offset = (inst & 0xff) << 1;
594 sav_offset =
595 read_memory_integer ((pc + 4) + offset, 2, byte_order);
596 }
597 }
598 }
599 else if (IS_MOVL_PCREL_TO_REG (inst))
600 {
601 if (sav_reg < 0)
602 {
603 reg = GET_TARGET_REG (inst);
604 if (reg < 14)
605 {
606 sav_reg = reg;
607 offset = (inst & 0xff) << 2;
608 sav_offset =
609 read_memory_integer (((pc & 0xfffffffc) + 4) + offset,
610 4, byte_order);
611 }
612 }
613 }
614 else if (IS_MOVI20 (inst)
615 && (pc + 2 < limit_pc))
616 {
617 if (sav_reg < 0)
618 {
619 reg = GET_TARGET_REG (inst);
620 if (reg < 14)
621 {
622 sav_reg = reg;
623 sav_offset = GET_SOURCE_REG (inst) << 16;
624 /* MOVI20 is a 32 bit instruction! */
625 pc += 2;
626 sav_offset
627 |= read_memory_unsigned_integer (pc, 2, byte_order);
628 /* Now sav_offset contains an unsigned 20 bit value.
629 It must still get sign extended. */
630 if (sav_offset & 0x00080000)
631 sav_offset |= 0xfff00000;
632 }
633 }
634 }
635 else if (IS_SUB_REG_FROM_SP (inst))
636 {
637 reg = GET_SOURCE_REG (inst);
638 if (sav_reg > 0 && reg == sav_reg)
639 {
640 sav_reg = -1;
641 }
642 cache->sp_offset += sav_offset;
643 }
644 else if (IS_FPUSH (inst))
645 {
646 if (fpscr & FPSCR_SZ)
647 {
648 cache->sp_offset += 8;
649 }
650 else
651 {
652 cache->sp_offset += 4;
653 }
654 }
655 else if (IS_MOV_SP_FP (inst))
656 {
657 pc += 2;
658 /* Don't go any further than six more instructions. */
659 limit_pc = min (limit_pc, pc + (2 * 6));
660
661 cache->uses_fp = 1;
662 /* At this point, only allow argument register moves to other
663 registers or argument register moves to @(X,fp) which are
664 moving the register arguments onto the stack area allocated
665 by a former add somenumber to SP call. Don't allow moving
666 to an fp indirect address above fp + cache->sp_offset. */
667 for (; pc < limit_pc; pc += 2)
668 {
669 inst = read_memory_integer (pc, 2, byte_order);
670 if (IS_MOV_ARG_TO_IND_R14 (inst))
671 {
672 reg = GET_SOURCE_REG (inst);
673 if (cache->sp_offset > 0)
674 cache->saved_regs[reg] = cache->sp_offset;
675 }
676 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
677 {
678 reg = GET_SOURCE_REG (inst);
679 offset = (inst & 0xf) * 4;
680 if (cache->sp_offset > offset)
681 cache->saved_regs[reg] = cache->sp_offset - offset;
682 }
683 else if (IS_MOV_ARG_TO_REG (inst))
684 continue;
685 else
686 break;
687 }
688 break;
689 }
690 else if (IS_JSR (inst))
691 {
692 /* We have found a jsr that has been scheduled into the prologue.
693 If we continue the scan and return a pc someplace after this,
694 then setting a breakpoint on this function will cause it to
695 appear to be called after the function it is calling via the
696 jsr, which will be very confusing. Most likely the next
697 instruction is going to be IS_MOV_SP_FP in the delay slot. If
698 so, note that before returning the current pc. */
699 if (pc + 2 < limit_pc)
700 {
701 inst = read_memory_integer (pc + 2, 2, byte_order);
702 if (IS_MOV_SP_FP (inst))
703 cache->uses_fp = 1;
704 }
705 break;
706 }
707 #if 0 /* This used to just stop when it found an instruction
708 that was not considered part of the prologue. Now,
709 we just keep going looking for likely
710 instructions. */
711 else
712 break;
713 #endif
714 }
715
716 return pc;
717 }
718
719 /* Skip any prologue before the guts of a function. */
720 static CORE_ADDR
721 sh_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
722 {
723 CORE_ADDR post_prologue_pc, func_addr, func_end_addr, limit_pc;
724 struct sh_frame_cache cache;
725
726 /* See if we can determine the end of the prologue via the symbol table.
727 If so, then return either PC, or the PC after the prologue, whichever
728 is greater. */
729 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr))
730 {
731 post_prologue_pc = skip_prologue_using_sal (gdbarch, func_addr);
732 if (post_prologue_pc != 0)
733 return max (pc, post_prologue_pc);
734 }
735
736 /* Can't determine prologue from the symbol table, need to examine
737 instructions. */
738
739 /* Find an upper limit on the function prologue using the debug
740 information. If the debug information could not be used to provide
741 that bound, then use an arbitrary large number as the upper bound. */
742 limit_pc = skip_prologue_using_sal (gdbarch, pc);
743 if (limit_pc == 0)
744 /* Don't go any further than 28 instructions. */
745 limit_pc = pc + (2 * 28);
746
747 /* Do not allow limit_pc to be past the function end, if we know
748 where that end is... */
749 if (func_end_addr != 0)
750 limit_pc = min (limit_pc, func_end_addr);
751
752 cache.sp_offset = -4;
753 post_prologue_pc = sh_analyze_prologue (gdbarch, pc, limit_pc, &cache, 0);
754 if (cache.uses_fp)
755 pc = post_prologue_pc;
756
757 return pc;
758 }
759
760 /* The ABI says:
761
762 Aggregate types not bigger than 8 bytes that have the same size and
763 alignment as one of the integer scalar types are returned in the
764 same registers as the integer type they match.
765
766 For example, a 2-byte aligned structure with size 2 bytes has the
767 same size and alignment as a short int, and will be returned in R0.
768 A 4-byte aligned structure with size 8 bytes has the same size and
769 alignment as a long long int, and will be returned in R0 and R1.
770
771 When an aggregate type is returned in R0 and R1, R0 contains the
772 first four bytes of the aggregate, and R1 contains the
773 remainder. If the size of the aggregate type is not a multiple of 4
774 bytes, the aggregate is tail-padded up to a multiple of 4
775 bytes. The value of the padding is undefined. For little-endian
776 targets the padding will appear at the most significant end of the
777 last element, for big-endian targets the padding appears at the
778 least significant end of the last element.
779
780 All other aggregate types are returned by address. The caller
781 function passes the address of an area large enough to hold the
782 aggregate value in R2. The called function stores the result in
783 this location.
784
785 To reiterate, structs smaller than 8 bytes could also be returned
786 in memory, if they don't pass the "same size and alignment as an
787 integer type" rule.
788
789 For example, in
790
791 struct s { char c[3]; } wibble;
792 struct s foo(void) { return wibble; }
793
794 the return value from foo() will be in memory, not
795 in R0, because there is no 3-byte integer type.
796
797 Similarly, in
798
799 struct s { char c[2]; } wibble;
800 struct s foo(void) { return wibble; }
801
802 because a struct containing two chars has alignment 1, that matches
803 type char, but size 2, that matches type short. There's no integer
804 type that has alignment 1 and size 2, so the struct is returned in
805 memory. */
806
807 static int
808 sh_use_struct_convention (int renesas_abi, struct type *type)
809 {
810 int len = TYPE_LENGTH (type);
811 int nelem = TYPE_NFIELDS (type);
812
813 /* The Renesas ABI returns aggregate types always on stack. */
814 if (renesas_abi && (TYPE_CODE (type) == TYPE_CODE_STRUCT
815 || TYPE_CODE (type) == TYPE_CODE_UNION))
816 return 1;
817
818 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
819 fit in two registers anyway) use struct convention. */
820 if (len != 1 && len != 2 && len != 4 && len != 8)
821 return 1;
822
823 /* Scalar types and aggregate types with exactly one field are aligned
824 by definition. They are returned in registers. */
825 if (nelem <= 1)
826 return 0;
827
828 /* If the first field in the aggregate has the same length as the entire
829 aggregate type, the type is returned in registers. */
830 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
831 return 0;
832
833 /* If the size of the aggregate is 8 bytes and the first field is
834 of size 4 bytes its alignment is equal to long long's alignment,
835 so it's returned in registers. */
836 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
837 return 0;
838
839 /* Otherwise use struct convention. */
840 return 1;
841 }
842
843 static int
844 sh_use_struct_convention_nofpu (int renesas_abi, struct type *type)
845 {
846 /* The Renesas ABI returns long longs/doubles etc. always on stack. */
847 if (renesas_abi && TYPE_NFIELDS (type) == 0 && TYPE_LENGTH (type) >= 8)
848 return 1;
849 return sh_use_struct_convention (renesas_abi, type);
850 }
851
852 static CORE_ADDR
853 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
854 {
855 return sp & ~3;
856 }
857
858 /* Function: push_dummy_call (formerly push_arguments)
859 Setup the function arguments for calling a function in the inferior.
860
861 On the Renesas SH architecture, there are four registers (R4 to R7)
862 which are dedicated for passing function arguments. Up to the first
863 four arguments (depending on size) may go into these registers.
864 The rest go on the stack.
865
866 MVS: Except on SH variants that have floating point registers.
867 In that case, float and double arguments are passed in the same
868 manner, but using FP registers instead of GP registers.
869
870 Arguments that are smaller than 4 bytes will still take up a whole
871 register or a whole 32-bit word on the stack, and will be
872 right-justified in the register or the stack word. This includes
873 chars, shorts, and small aggregate types.
874
875 Arguments that are larger than 4 bytes may be split between two or
876 more registers. If there are not enough registers free, an argument
877 may be passed partly in a register (or registers), and partly on the
878 stack. This includes doubles, long longs, and larger aggregates.
879 As far as I know, there is no upper limit to the size of aggregates
880 that will be passed in this way; in other words, the convention of
881 passing a pointer to a large aggregate instead of a copy is not used.
882
883 MVS: The above appears to be true for the SH variants that do not
884 have an FPU, however those that have an FPU appear to copy the
885 aggregate argument onto the stack (and not place it in registers)
886 if it is larger than 16 bytes (four GP registers).
887
888 An exceptional case exists for struct arguments (and possibly other
889 aggregates such as arrays) if the size is larger than 4 bytes but
890 not a multiple of 4 bytes. In this case the argument is never split
891 between the registers and the stack, but instead is copied in its
892 entirety onto the stack, AND also copied into as many registers as
893 there is room for. In other words, space in registers permitting,
894 two copies of the same argument are passed in. As far as I can tell,
895 only the one on the stack is used, although that may be a function
896 of the level of compiler optimization. I suspect this is a compiler
897 bug. Arguments of these odd sizes are left-justified within the
898 word (as opposed to arguments smaller than 4 bytes, which are
899 right-justified).
900
901 If the function is to return an aggregate type such as a struct, it
902 is either returned in the normal return value register R0 (if its
903 size is no greater than one byte), or else the caller must allocate
904 space into which the callee will copy the return value (if the size
905 is greater than one byte). In this case, a pointer to the return
906 value location is passed into the callee in register R2, which does
907 not displace any of the other arguments passed in via registers R4
908 to R7. */
909
910 /* Helper function to justify value in register according to endianess. */
911 static char *
912 sh_justify_value_in_reg (struct gdbarch *gdbarch, struct value *val, int len)
913 {
914 static char valbuf[4];
915
916 memset (valbuf, 0, sizeof (valbuf));
917 if (len < 4)
918 {
919 /* value gets right-justified in the register or stack word. */
920 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
921 memcpy (valbuf + (4 - len), (char *) value_contents (val), len);
922 else
923 memcpy (valbuf, (char *) value_contents (val), len);
924 return valbuf;
925 }
926 return (char *) value_contents (val);
927 }
928
929 /* Helper function to eval number of bytes to allocate on stack. */
930 static CORE_ADDR
931 sh_stack_allocsize (int nargs, struct value **args)
932 {
933 int stack_alloc = 0;
934 while (nargs-- > 0)
935 stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3);
936 return stack_alloc;
937 }
938
939 /* Helper functions for getting the float arguments right. Registers usage
940 depends on the ABI and the endianess. The comments should enlighten how
941 it's intended to work. */
942
943 /* This array stores which of the float arg registers are already in use. */
944 static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
945
946 /* This function just resets the above array to "no reg used so far". */
947 static void
948 sh_init_flt_argreg (void)
949 {
950 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
951 }
952
953 /* This function returns the next register to use for float arg passing.
954 It returns either a valid value between FLOAT_ARG0_REGNUM and
955 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
956 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
957
958 Note that register number 0 in flt_argreg_array corresponds with the
959 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
960 29) the parity of the register number is preserved, which is important
961 for the double register passing test (see the "argreg & 1" test below). */
962 static int
963 sh_next_flt_argreg (struct gdbarch *gdbarch, int len, struct type *func_type)
964 {
965 int argreg;
966
967 /* First search for the next free register. */
968 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
969 ++argreg)
970 if (!flt_argreg_array[argreg])
971 break;
972
973 /* No register left? */
974 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
975 return FLOAT_ARGLAST_REGNUM + 1;
976
977 if (len == 8)
978 {
979 /* Doubles are always starting in a even register number. */
980 if (argreg & 1)
981 {
982 /* In gcc ABI, the skipped register is lost for further argument
983 passing now. Not so in Renesas ABI. */
984 if (!sh_is_renesas_calling_convention (func_type))
985 flt_argreg_array[argreg] = 1;
986
987 ++argreg;
988
989 /* No register left? */
990 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
991 return FLOAT_ARGLAST_REGNUM + 1;
992 }
993 /* Also mark the next register as used. */
994 flt_argreg_array[argreg + 1] = 1;
995 }
996 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
997 && !sh_is_renesas_calling_convention (func_type))
998 {
999 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
1000 if (!flt_argreg_array[argreg + 1])
1001 ++argreg;
1002 }
1003 flt_argreg_array[argreg] = 1;
1004 return FLOAT_ARG0_REGNUM + argreg;
1005 }
1006
1007 /* Helper function which figures out, if a type is treated like a float type.
1008
1009 The FPU ABIs have a special way how to treat types as float types.
1010 Structures with exactly one member, which is of type float or double, are
1011 treated exactly as the base types float or double:
1012
1013 struct sf {
1014 float f;
1015 };
1016
1017 struct sd {
1018 double d;
1019 };
1020
1021 are handled the same way as just
1022
1023 float f;
1024
1025 double d;
1026
1027 As a result, arguments of these struct types are pushed into floating point
1028 registers exactly as floats or doubles, using the same decision algorithm.
1029
1030 The same is valid if these types are used as function return types. The
1031 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
1032 or even using struct convention as it is for other structs. */
1033
1034 static int
1035 sh_treat_as_flt_p (struct type *type)
1036 {
1037 int len = TYPE_LENGTH (type);
1038
1039 /* Ordinary float types are obviously treated as float. */
1040 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1041 return 1;
1042 /* Otherwise non-struct types are not treated as float. */
1043 if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
1044 return 0;
1045 /* Otherwise structs with more than one memeber are not treated as float. */
1046 if (TYPE_NFIELDS (type) != 1)
1047 return 0;
1048 /* Otherwise if the type of that member is float, the whole type is
1049 treated as float. */
1050 if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
1051 return 1;
1052 /* Otherwise it's not treated as float. */
1053 return 0;
1054 }
1055
1056 static CORE_ADDR
1057 sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
1058 struct value *function,
1059 struct regcache *regcache,
1060 CORE_ADDR bp_addr, int nargs,
1061 struct value **args,
1062 CORE_ADDR sp, int struct_return,
1063 CORE_ADDR struct_addr)
1064 {
1065 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1066 int stack_offset = 0;
1067 int argreg = ARG0_REGNUM;
1068 int flt_argreg = 0;
1069 int argnum;
1070 struct type *func_type = value_type (function);
1071 struct type *type;
1072 CORE_ADDR regval;
1073 char *val;
1074 int len, reg_size = 0;
1075 int pass_on_stack = 0;
1076 int treat_as_flt;
1077 int last_reg_arg = INT_MAX;
1078
1079 /* The Renesas ABI expects all varargs arguments, plus the last
1080 non-vararg argument to be on the stack, no matter how many
1081 registers have been used so far. */
1082 if (sh_is_renesas_calling_convention (func_type)
1083 && TYPE_VARARGS (func_type))
1084 last_reg_arg = TYPE_NFIELDS (func_type) - 2;
1085
1086 /* First force sp to a 4-byte alignment. */
1087 sp = sh_frame_align (gdbarch, sp);
1088
1089 /* Make room on stack for args. */
1090 sp -= sh_stack_allocsize (nargs, args);
1091
1092 /* Initialize float argument mechanism. */
1093 sh_init_flt_argreg ();
1094
1095 /* Now load as many as possible of the first arguments into
1096 registers, and push the rest onto the stack. There are 16 bytes
1097 in four registers available. Loop thru args from first to last. */
1098 for (argnum = 0; argnum < nargs; argnum++)
1099 {
1100 type = value_type (args[argnum]);
1101 len = TYPE_LENGTH (type);
1102 val = sh_justify_value_in_reg (gdbarch, args[argnum], len);
1103
1104 /* Some decisions have to be made how various types are handled.
1105 This also differs in different ABIs. */
1106 pass_on_stack = 0;
1107
1108 /* Find out the next register to use for a floating point value. */
1109 treat_as_flt = sh_treat_as_flt_p (type);
1110 if (treat_as_flt)
1111 flt_argreg = sh_next_flt_argreg (gdbarch, len, func_type);
1112 /* In Renesas ABI, long longs and aggregate types are always passed
1113 on stack. */
1114 else if (sh_is_renesas_calling_convention (func_type)
1115 && ((TYPE_CODE (type) == TYPE_CODE_INT && len == 8)
1116 || TYPE_CODE (type) == TYPE_CODE_STRUCT
1117 || TYPE_CODE (type) == TYPE_CODE_UNION))
1118 pass_on_stack = 1;
1119 /* In contrast to non-FPU CPUs, arguments are never split between
1120 registers and stack. If an argument doesn't fit in the remaining
1121 registers it's always pushed entirely on the stack. */
1122 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
1123 pass_on_stack = 1;
1124
1125 while (len > 0)
1126 {
1127 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
1128 || (!treat_as_flt && (argreg > ARGLAST_REGNUM
1129 || pass_on_stack))
1130 || argnum > last_reg_arg)
1131 {
1132 /* The data goes entirely on the stack, 4-byte aligned. */
1133 reg_size = (len + 3) & ~3;
1134 write_memory (sp + stack_offset, val, reg_size);
1135 stack_offset += reg_size;
1136 }
1137 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
1138 {
1139 /* Argument goes in a float argument register. */
1140 reg_size = register_size (gdbarch, flt_argreg);
1141 regval = extract_unsigned_integer (val, reg_size, byte_order);
1142 /* In little endian mode, float types taking two registers
1143 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1144 be stored swapped in the argument registers. The below
1145 code first writes the first 32 bits in the next but one
1146 register, increments the val and len values accordingly
1147 and then proceeds as normal by writing the second 32 bits
1148 into the next register. */
1149 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
1150 && TYPE_LENGTH (type) == 2 * reg_size)
1151 {
1152 regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
1153 regval);
1154 val += reg_size;
1155 len -= reg_size;
1156 regval = extract_unsigned_integer (val, reg_size,
1157 byte_order);
1158 }
1159 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
1160 }
1161 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
1162 {
1163 /* there's room in a register */
1164 reg_size = register_size (gdbarch, argreg);
1165 regval = extract_unsigned_integer (val, reg_size, byte_order);
1166 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1167 }
1168 /* Store the value one register at a time or in one step on
1169 stack. */
1170 len -= reg_size;
1171 val += reg_size;
1172 }
1173 }
1174
1175 if (struct_return)
1176 {
1177 if (sh_is_renesas_calling_convention (func_type))
1178 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1179 the stack and store the struct return address there. */
1180 write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
1181 else
1182 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1183 its own dedicated register. */
1184 regcache_cooked_write_unsigned (regcache,
1185 STRUCT_RETURN_REGNUM, struct_addr);
1186 }
1187
1188 /* Store return address. */
1189 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1190
1191 /* Update stack pointer. */
1192 regcache_cooked_write_unsigned (regcache,
1193 gdbarch_sp_regnum (gdbarch), sp);
1194
1195 return sp;
1196 }
1197
1198 static CORE_ADDR
1199 sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
1200 struct value *function,
1201 struct regcache *regcache,
1202 CORE_ADDR bp_addr,
1203 int nargs, struct value **args,
1204 CORE_ADDR sp, int struct_return,
1205 CORE_ADDR struct_addr)
1206 {
1207 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1208 int stack_offset = 0;
1209 int argreg = ARG0_REGNUM;
1210 int argnum;
1211 struct type *func_type = value_type (function);
1212 struct type *type;
1213 CORE_ADDR regval;
1214 char *val;
1215 int len, reg_size = 0;
1216 int pass_on_stack = 0;
1217 int last_reg_arg = INT_MAX;
1218
1219 /* The Renesas ABI expects all varargs arguments, plus the last
1220 non-vararg argument to be on the stack, no matter how many
1221 registers have been used so far. */
1222 if (sh_is_renesas_calling_convention (func_type)
1223 && TYPE_VARARGS (func_type))
1224 last_reg_arg = TYPE_NFIELDS (func_type) - 2;
1225
1226 /* First force sp to a 4-byte alignment. */
1227 sp = sh_frame_align (gdbarch, sp);
1228
1229 /* Make room on stack for args. */
1230 sp -= sh_stack_allocsize (nargs, args);
1231
1232 /* Now load as many as possible of the first arguments into
1233 registers, and push the rest onto the stack. There are 16 bytes
1234 in four registers available. Loop thru args from first to last. */
1235 for (argnum = 0; argnum < nargs; argnum++)
1236 {
1237 type = value_type (args[argnum]);
1238 len = TYPE_LENGTH (type);
1239 val = sh_justify_value_in_reg (gdbarch, args[argnum], len);
1240
1241 /* Some decisions have to be made how various types are handled.
1242 This also differs in different ABIs. */
1243 pass_on_stack = 0;
1244 /* Renesas ABI pushes doubles and long longs entirely on stack.
1245 Same goes for aggregate types. */
1246 if (sh_is_renesas_calling_convention (func_type)
1247 && ((TYPE_CODE (type) == TYPE_CODE_INT && len >= 8)
1248 || (TYPE_CODE (type) == TYPE_CODE_FLT && len >= 8)
1249 || TYPE_CODE (type) == TYPE_CODE_STRUCT
1250 || TYPE_CODE (type) == TYPE_CODE_UNION))
1251 pass_on_stack = 1;
1252 while (len > 0)
1253 {
1254 if (argreg > ARGLAST_REGNUM || pass_on_stack
1255 || argnum > last_reg_arg)
1256 {
1257 /* The remainder of the data goes entirely on the stack,
1258 4-byte aligned. */
1259 reg_size = (len + 3) & ~3;
1260 write_memory (sp + stack_offset, val, reg_size);
1261 stack_offset += reg_size;
1262 }
1263 else if (argreg <= ARGLAST_REGNUM)
1264 {
1265 /* There's room in a register. */
1266 reg_size = register_size (gdbarch, argreg);
1267 regval = extract_unsigned_integer (val, reg_size, byte_order);
1268 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1269 }
1270 /* Store the value reg_size bytes at a time. This means that things
1271 larger than reg_size bytes may go partly in registers and partly
1272 on the stack. */
1273 len -= reg_size;
1274 val += reg_size;
1275 }
1276 }
1277
1278 if (struct_return)
1279 {
1280 if (sh_is_renesas_calling_convention (func_type))
1281 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1282 the stack and store the struct return address there. */
1283 write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
1284 else
1285 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1286 its own dedicated register. */
1287 regcache_cooked_write_unsigned (regcache,
1288 STRUCT_RETURN_REGNUM, struct_addr);
1289 }
1290
1291 /* Store return address. */
1292 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1293
1294 /* Update stack pointer. */
1295 regcache_cooked_write_unsigned (regcache,
1296 gdbarch_sp_regnum (gdbarch), sp);
1297
1298 return sp;
1299 }
1300
1301 /* Find a function's return value in the appropriate registers (in
1302 regbuf), and copy it into valbuf. Extract from an array REGBUF
1303 containing the (raw) register state a function return value of type
1304 TYPE, and copy that, in virtual format, into VALBUF. */
1305 static void
1306 sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache,
1307 void *valbuf)
1308 {
1309 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1310 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1311 int len = TYPE_LENGTH (type);
1312 int return_register = R0_REGNUM;
1313 int offset;
1314
1315 if (len <= 4)
1316 {
1317 ULONGEST c;
1318
1319 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
1320 store_unsigned_integer (valbuf, len, byte_order, c);
1321 }
1322 else if (len == 8)
1323 {
1324 int i, regnum = R0_REGNUM;
1325 for (i = 0; i < len; i += 4)
1326 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1327 }
1328 else
1329 error (_("bad size for return value"));
1330 }
1331
1332 static void
1333 sh_extract_return_value_fpu (struct type *type, struct regcache *regcache,
1334 void *valbuf)
1335 {
1336 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1337 if (sh_treat_as_flt_p (type))
1338 {
1339 int len = TYPE_LENGTH (type);
1340 int i, regnum = gdbarch_fp0_regnum (gdbarch);
1341 for (i = 0; i < len; i += 4)
1342 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1343 regcache_raw_read (regcache, regnum++,
1344 (char *) valbuf + len - 4 - i);
1345 else
1346 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1347 }
1348 else
1349 sh_extract_return_value_nofpu (type, regcache, valbuf);
1350 }
1351
1352 /* Write into appropriate registers a function return value
1353 of type TYPE, given in virtual format.
1354 If the architecture is sh4 or sh3e, store a function's return value
1355 in the R0 general register or in the FP0 floating point register,
1356 depending on the type of the return value. In all the other cases
1357 the result is stored in r0, left-justified. */
1358 static void
1359 sh_store_return_value_nofpu (struct type *type, struct regcache *regcache,
1360 const void *valbuf)
1361 {
1362 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1363 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1364 ULONGEST val;
1365 int len = TYPE_LENGTH (type);
1366
1367 if (len <= 4)
1368 {
1369 val = extract_unsigned_integer (valbuf, len, byte_order);
1370 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
1371 }
1372 else
1373 {
1374 int i, regnum = R0_REGNUM;
1375 for (i = 0; i < len; i += 4)
1376 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1377 }
1378 }
1379
1380 static void
1381 sh_store_return_value_fpu (struct type *type, struct regcache *regcache,
1382 const void *valbuf)
1383 {
1384 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1385 if (sh_treat_as_flt_p (type))
1386 {
1387 int len = TYPE_LENGTH (type);
1388 int i, regnum = gdbarch_fp0_regnum (gdbarch);
1389 for (i = 0; i < len; i += 4)
1390 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1391 regcache_raw_write (regcache, regnum++,
1392 (char *) valbuf + len - 4 - i);
1393 else
1394 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1395 }
1396 else
1397 sh_store_return_value_nofpu (type, regcache, valbuf);
1398 }
1399
1400 static enum return_value_convention
1401 sh_return_value_nofpu (struct gdbarch *gdbarch, struct value *function,
1402 struct type *type, struct regcache *regcache,
1403 gdb_byte *readbuf, const gdb_byte *writebuf)
1404 {
1405 struct type *func_type = function ? value_type (function) : NULL;
1406
1407 if (sh_use_struct_convention_nofpu (
1408 sh_is_renesas_calling_convention (func_type), type))
1409 return RETURN_VALUE_STRUCT_CONVENTION;
1410 if (writebuf)
1411 sh_store_return_value_nofpu (type, regcache, writebuf);
1412 else if (readbuf)
1413 sh_extract_return_value_nofpu (type, regcache, readbuf);
1414 return RETURN_VALUE_REGISTER_CONVENTION;
1415 }
1416
1417 static enum return_value_convention
1418 sh_return_value_fpu (struct gdbarch *gdbarch, struct value *function,
1419 struct type *type, struct regcache *regcache,
1420 gdb_byte *readbuf, const gdb_byte *writebuf)
1421 {
1422 struct type *func_type = function ? value_type (function) : NULL;
1423
1424 if (sh_use_struct_convention (
1425 sh_is_renesas_calling_convention (func_type), type))
1426 return RETURN_VALUE_STRUCT_CONVENTION;
1427 if (writebuf)
1428 sh_store_return_value_fpu (type, regcache, writebuf);
1429 else if (readbuf)
1430 sh_extract_return_value_fpu (type, regcache, readbuf);
1431 return RETURN_VALUE_REGISTER_CONVENTION;
1432 }
1433
1434 /* Print the registers in a form similar to the E7000. */
1435
1436 static void
1437 sh_generic_show_regs (struct frame_info *frame)
1438 {
1439 printf_filtered
1440 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1441 phex (get_frame_register_unsigned (frame,
1442 gdbarch_pc_regnum
1443 (get_frame_arch (frame))), 4),
1444 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1445 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1446 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1447
1448 printf_filtered
1449 (" GBR %08lx VBR %08lx MACL %08lx\n",
1450 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1451 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1452 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1453
1454 printf_filtered
1455 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1456 (long) get_frame_register_unsigned (frame, 0),
1457 (long) get_frame_register_unsigned (frame, 1),
1458 (long) get_frame_register_unsigned (frame, 2),
1459 (long) get_frame_register_unsigned (frame, 3),
1460 (long) get_frame_register_unsigned (frame, 4),
1461 (long) get_frame_register_unsigned (frame, 5),
1462 (long) get_frame_register_unsigned (frame, 6),
1463 (long) get_frame_register_unsigned (frame, 7));
1464 printf_filtered
1465 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1466 (long) get_frame_register_unsigned (frame, 8),
1467 (long) get_frame_register_unsigned (frame, 9),
1468 (long) get_frame_register_unsigned (frame, 10),
1469 (long) get_frame_register_unsigned (frame, 11),
1470 (long) get_frame_register_unsigned (frame, 12),
1471 (long) get_frame_register_unsigned (frame, 13),
1472 (long) get_frame_register_unsigned (frame, 14),
1473 (long) get_frame_register_unsigned (frame, 15));
1474 }
1475
1476 static void
1477 sh3_show_regs (struct frame_info *frame)
1478 {
1479 printf_filtered
1480 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1481 phex (get_frame_register_unsigned (frame,
1482 gdbarch_pc_regnum
1483 (get_frame_arch (frame))), 4),
1484 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1485 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1486 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1487
1488 printf_filtered
1489 (" GBR %08lx VBR %08lx MACL %08lx\n",
1490 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1491 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1492 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1493 printf_filtered
1494 (" SSR %08lx SPC %08lx\n",
1495 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1496 (long) get_frame_register_unsigned (frame, SPC_REGNUM));
1497
1498 printf_filtered
1499 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1500 (long) get_frame_register_unsigned (frame, 0),
1501 (long) get_frame_register_unsigned (frame, 1),
1502 (long) get_frame_register_unsigned (frame, 2),
1503 (long) get_frame_register_unsigned (frame, 3),
1504 (long) get_frame_register_unsigned (frame, 4),
1505 (long) get_frame_register_unsigned (frame, 5),
1506 (long) get_frame_register_unsigned (frame, 6),
1507 (long) get_frame_register_unsigned (frame, 7));
1508 printf_filtered
1509 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1510 (long) get_frame_register_unsigned (frame, 8),
1511 (long) get_frame_register_unsigned (frame, 9),
1512 (long) get_frame_register_unsigned (frame, 10),
1513 (long) get_frame_register_unsigned (frame, 11),
1514 (long) get_frame_register_unsigned (frame, 12),
1515 (long) get_frame_register_unsigned (frame, 13),
1516 (long) get_frame_register_unsigned (frame, 14),
1517 (long) get_frame_register_unsigned (frame, 15));
1518 }
1519
1520 static void
1521 sh2e_show_regs (struct frame_info *frame)
1522 {
1523 struct gdbarch *gdbarch = get_frame_arch (frame);
1524 printf_filtered
1525 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1526 phex (get_frame_register_unsigned (frame,
1527 gdbarch_pc_regnum (gdbarch)), 4),
1528 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1529 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1530 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1531
1532 printf_filtered
1533 (" GBR %08lx VBR %08lx MACL %08lx\n",
1534 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1535 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1536 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1537 printf_filtered
1538 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1539 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1540 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1541 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1542 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1543
1544 printf_filtered
1545 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1546 (long) get_frame_register_unsigned (frame, 0),
1547 (long) get_frame_register_unsigned (frame, 1),
1548 (long) get_frame_register_unsigned (frame, 2),
1549 (long) get_frame_register_unsigned (frame, 3),
1550 (long) get_frame_register_unsigned (frame, 4),
1551 (long) get_frame_register_unsigned (frame, 5),
1552 (long) get_frame_register_unsigned (frame, 6),
1553 (long) get_frame_register_unsigned (frame, 7));
1554 printf_filtered
1555 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1556 (long) get_frame_register_unsigned (frame, 8),
1557 (long) get_frame_register_unsigned (frame, 9),
1558 (long) get_frame_register_unsigned (frame, 10),
1559 (long) get_frame_register_unsigned (frame, 11),
1560 (long) get_frame_register_unsigned (frame, 12),
1561 (long) get_frame_register_unsigned (frame, 13),
1562 (long) get_frame_register_unsigned (frame, 14),
1563 (long) get_frame_register_unsigned (frame, 15));
1564
1565 printf_filtered
1566 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1567 (long) get_frame_register_unsigned
1568 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
1569 (long) get_frame_register_unsigned
1570 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
1571 (long) get_frame_register_unsigned
1572 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
1573 (long) get_frame_register_unsigned
1574 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
1575 (long) get_frame_register_unsigned
1576 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
1577 (long) get_frame_register_unsigned
1578 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
1579 (long) get_frame_register_unsigned
1580 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
1581 (long) get_frame_register_unsigned
1582 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
1583 printf_filtered
1584 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1585 (long) get_frame_register_unsigned
1586 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
1587 (long) get_frame_register_unsigned
1588 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
1589 (long) get_frame_register_unsigned
1590 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
1591 (long) get_frame_register_unsigned
1592 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
1593 (long) get_frame_register_unsigned
1594 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
1595 (long) get_frame_register_unsigned
1596 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
1597 (long) get_frame_register_unsigned
1598 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
1599 (long) get_frame_register_unsigned
1600 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
1601 }
1602
1603 static void
1604 sh2a_show_regs (struct frame_info *frame)
1605 {
1606 struct gdbarch *gdbarch = get_frame_arch (frame);
1607 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1608
1609 printf_filtered
1610 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1611 phex (get_frame_register_unsigned (frame,
1612 gdbarch_pc_regnum (gdbarch)), 4),
1613 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1614 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1615 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1616
1617 printf_filtered
1618 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1619 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1620 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1621 (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1622 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1623 printf_filtered
1624 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1625 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1626 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1627 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1628 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1629
1630 printf_filtered
1631 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1632 (long) get_frame_register_unsigned (frame, 0),
1633 (long) get_frame_register_unsigned (frame, 1),
1634 (long) get_frame_register_unsigned (frame, 2),
1635 (long) get_frame_register_unsigned (frame, 3),
1636 (long) get_frame_register_unsigned (frame, 4),
1637 (long) get_frame_register_unsigned (frame, 5),
1638 (long) get_frame_register_unsigned (frame, 6),
1639 (long) get_frame_register_unsigned (frame, 7));
1640 printf_filtered
1641 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1642 (long) get_frame_register_unsigned (frame, 8),
1643 (long) get_frame_register_unsigned (frame, 9),
1644 (long) get_frame_register_unsigned (frame, 10),
1645 (long) get_frame_register_unsigned (frame, 11),
1646 (long) get_frame_register_unsigned (frame, 12),
1647 (long) get_frame_register_unsigned (frame, 13),
1648 (long) get_frame_register_unsigned (frame, 14),
1649 (long) get_frame_register_unsigned (frame, 15));
1650
1651 printf_filtered
1652 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1653 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1654 (long) get_frame_register_unsigned
1655 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
1656 (long) get_frame_register_unsigned
1657 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
1658 (long) get_frame_register_unsigned
1659 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
1660 (long) get_frame_register_unsigned
1661 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
1662 (long) get_frame_register_unsigned
1663 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
1664 (long) get_frame_register_unsigned
1665 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
1666 (long) get_frame_register_unsigned
1667 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
1668 (long) get_frame_register_unsigned
1669 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
1670 printf_filtered
1671 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1672 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1673 (long) get_frame_register_unsigned
1674 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
1675 (long) get_frame_register_unsigned
1676 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
1677 (long) get_frame_register_unsigned
1678 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
1679 (long) get_frame_register_unsigned
1680 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
1681 (long) get_frame_register_unsigned
1682 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
1683 (long) get_frame_register_unsigned
1684 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
1685 (long) get_frame_register_unsigned
1686 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
1687 (long) get_frame_register_unsigned
1688 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
1689 printf_filtered
1690 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1691 printf_filtered
1692 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1693 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1694 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1695 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1696 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1697 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1698 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1699 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1700 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1701 printf_filtered
1702 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1703 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1704 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1705 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1706 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1707 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1708 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1709 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1710 printf_filtered
1711 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1712 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1713 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1714 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1715 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1716 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
1717 }
1718
1719 static void
1720 sh2a_nofpu_show_regs (struct frame_info *frame)
1721 {
1722 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1723
1724 printf_filtered
1725 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1726 phex (get_frame_register_unsigned (frame,
1727 gdbarch_pc_regnum
1728 (get_frame_arch (frame))), 4),
1729 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1730 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1731 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1732
1733 printf_filtered
1734 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1735 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1736 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1737 (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1738 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1739 printf_filtered
1740 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1741 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1742 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1743 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1744 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1745
1746 printf_filtered
1747 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1748 (long) get_frame_register_unsigned (frame, 0),
1749 (long) get_frame_register_unsigned (frame, 1),
1750 (long) get_frame_register_unsigned (frame, 2),
1751 (long) get_frame_register_unsigned (frame, 3),
1752 (long) get_frame_register_unsigned (frame, 4),
1753 (long) get_frame_register_unsigned (frame, 5),
1754 (long) get_frame_register_unsigned (frame, 6),
1755 (long) get_frame_register_unsigned (frame, 7));
1756 printf_filtered
1757 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1758 (long) get_frame_register_unsigned (frame, 8),
1759 (long) get_frame_register_unsigned (frame, 9),
1760 (long) get_frame_register_unsigned (frame, 10),
1761 (long) get_frame_register_unsigned (frame, 11),
1762 (long) get_frame_register_unsigned (frame, 12),
1763 (long) get_frame_register_unsigned (frame, 13),
1764 (long) get_frame_register_unsigned (frame, 14),
1765 (long) get_frame_register_unsigned (frame, 15));
1766
1767 printf_filtered
1768 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1769 printf_filtered
1770 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1771 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1772 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1773 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1774 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1775 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1776 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1777 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1778 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1779 printf_filtered
1780 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1781 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1782 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1783 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1784 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1785 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1786 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1787 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1788 printf_filtered
1789 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1790 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1791 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1792 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1793 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1794 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
1795 }
1796
1797 static void
1798 sh3e_show_regs (struct frame_info *frame)
1799 {
1800 struct gdbarch *gdbarch = get_frame_arch (frame);
1801 printf_filtered
1802 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1803 phex (get_frame_register_unsigned (frame,
1804 gdbarch_pc_regnum (gdbarch)), 4),
1805 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1806 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1807 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1808
1809 printf_filtered
1810 (" GBR %08lx VBR %08lx MACL %08lx\n",
1811 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1812 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1813 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1814 printf_filtered
1815 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1816 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1817 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1818 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1819 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1820
1821 printf_filtered
1822 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1823 (long) get_frame_register_unsigned (frame, 0),
1824 (long) get_frame_register_unsigned (frame, 1),
1825 (long) get_frame_register_unsigned (frame, 2),
1826 (long) get_frame_register_unsigned (frame, 3),
1827 (long) get_frame_register_unsigned (frame, 4),
1828 (long) get_frame_register_unsigned (frame, 5),
1829 (long) get_frame_register_unsigned (frame, 6),
1830 (long) get_frame_register_unsigned (frame, 7));
1831 printf_filtered
1832 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1833 (long) get_frame_register_unsigned (frame, 8),
1834 (long) get_frame_register_unsigned (frame, 9),
1835 (long) get_frame_register_unsigned (frame, 10),
1836 (long) get_frame_register_unsigned (frame, 11),
1837 (long) get_frame_register_unsigned (frame, 12),
1838 (long) get_frame_register_unsigned (frame, 13),
1839 (long) get_frame_register_unsigned (frame, 14),
1840 (long) get_frame_register_unsigned (frame, 15));
1841
1842 printf_filtered
1843 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1844 (long) get_frame_register_unsigned
1845 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
1846 (long) get_frame_register_unsigned
1847 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
1848 (long) get_frame_register_unsigned
1849 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
1850 (long) get_frame_register_unsigned
1851 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
1852 (long) get_frame_register_unsigned
1853 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
1854 (long) get_frame_register_unsigned
1855 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
1856 (long) get_frame_register_unsigned
1857 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
1858 (long) get_frame_register_unsigned
1859 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
1860 printf_filtered
1861 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1862 (long) get_frame_register_unsigned
1863 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
1864 (long) get_frame_register_unsigned
1865 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
1866 (long) get_frame_register_unsigned
1867 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
1868 (long) get_frame_register_unsigned
1869 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
1870 (long) get_frame_register_unsigned
1871 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
1872 (long) get_frame_register_unsigned
1873 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
1874 (long) get_frame_register_unsigned
1875 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
1876 (long) get_frame_register_unsigned
1877 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
1878 }
1879
1880 static void
1881 sh3_dsp_show_regs (struct frame_info *frame)
1882 {
1883 printf_filtered
1884 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1885 phex (get_frame_register_unsigned (frame,
1886 gdbarch_pc_regnum
1887 (get_frame_arch (frame))), 4),
1888 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1889 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1890 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1891
1892 printf_filtered
1893 (" GBR %08lx VBR %08lx MACL %08lx\n",
1894 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1895 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1896 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1897
1898 printf_filtered
1899 (" SSR %08lx SPC %08lx DSR %08lx\n",
1900 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1901 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1902 (long) get_frame_register_unsigned (frame, DSR_REGNUM));
1903
1904 printf_filtered
1905 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1906 (long) get_frame_register_unsigned (frame, 0),
1907 (long) get_frame_register_unsigned (frame, 1),
1908 (long) get_frame_register_unsigned (frame, 2),
1909 (long) get_frame_register_unsigned (frame, 3),
1910 (long) get_frame_register_unsigned (frame, 4),
1911 (long) get_frame_register_unsigned (frame, 5),
1912 (long) get_frame_register_unsigned (frame, 6),
1913 (long) get_frame_register_unsigned (frame, 7));
1914 printf_filtered
1915 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1916 (long) get_frame_register_unsigned (frame, 8),
1917 (long) get_frame_register_unsigned (frame, 9),
1918 (long) get_frame_register_unsigned (frame, 10),
1919 (long) get_frame_register_unsigned (frame, 11),
1920 (long) get_frame_register_unsigned (frame, 12),
1921 (long) get_frame_register_unsigned (frame, 13),
1922 (long) get_frame_register_unsigned (frame, 14),
1923 (long) get_frame_register_unsigned (frame, 15));
1924
1925 printf_filtered
1926 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1927 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
1928 (long) get_frame_register_unsigned (frame, A0_REGNUM),
1929 (long) get_frame_register_unsigned (frame, M0_REGNUM),
1930 (long) get_frame_register_unsigned (frame, X0_REGNUM),
1931 (long) get_frame_register_unsigned (frame, Y0_REGNUM),
1932 (long) get_frame_register_unsigned (frame, RS_REGNUM),
1933 (long) get_frame_register_unsigned (frame, MOD_REGNUM));
1934 printf_filtered
1935 ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1936 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
1937 (long) get_frame_register_unsigned (frame, A1_REGNUM),
1938 (long) get_frame_register_unsigned (frame, M1_REGNUM),
1939 (long) get_frame_register_unsigned (frame, X1_REGNUM),
1940 (long) get_frame_register_unsigned (frame, Y1_REGNUM),
1941 (long) get_frame_register_unsigned (frame, RE_REGNUM));
1942 }
1943
1944 static void
1945 sh4_show_regs (struct frame_info *frame)
1946 {
1947 struct gdbarch *gdbarch = get_frame_arch (frame);
1948 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1949
1950 printf_filtered
1951 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1952 phex (get_frame_register_unsigned (frame,
1953 gdbarch_pc_regnum (gdbarch)), 4),
1954 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1955 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1956 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1957
1958 printf_filtered
1959 (" GBR %08lx VBR %08lx MACL %08lx\n",
1960 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1961 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1962 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1963 printf_filtered
1964 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1965 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1966 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1967 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1968 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1969
1970 printf_filtered
1971 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1972 (long) get_frame_register_unsigned (frame, 0),
1973 (long) get_frame_register_unsigned (frame, 1),
1974 (long) get_frame_register_unsigned (frame, 2),
1975 (long) get_frame_register_unsigned (frame, 3),
1976 (long) get_frame_register_unsigned (frame, 4),
1977 (long) get_frame_register_unsigned (frame, 5),
1978 (long) get_frame_register_unsigned (frame, 6),
1979 (long) get_frame_register_unsigned (frame, 7));
1980 printf_filtered
1981 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1982 (long) get_frame_register_unsigned (frame, 8),
1983 (long) get_frame_register_unsigned (frame, 9),
1984 (long) get_frame_register_unsigned (frame, 10),
1985 (long) get_frame_register_unsigned (frame, 11),
1986 (long) get_frame_register_unsigned (frame, 12),
1987 (long) get_frame_register_unsigned (frame, 13),
1988 (long) get_frame_register_unsigned (frame, 14),
1989 (long) get_frame_register_unsigned (frame, 15));
1990
1991 printf_filtered
1992 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1993 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1994 (long) get_frame_register_unsigned
1995 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
1996 (long) get_frame_register_unsigned
1997 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
1998 (long) get_frame_register_unsigned
1999 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
2000 (long) get_frame_register_unsigned
2001 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
2002 (long) get_frame_register_unsigned
2003 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
2004 (long) get_frame_register_unsigned
2005 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
2006 (long) get_frame_register_unsigned
2007 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
2008 (long) get_frame_register_unsigned
2009 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
2010 printf_filtered
2011 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2012 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2013 (long) get_frame_register_unsigned
2014 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
2015 (long) get_frame_register_unsigned
2016 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
2017 (long) get_frame_register_unsigned
2018 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
2019 (long) get_frame_register_unsigned
2020 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
2021 (long) get_frame_register_unsigned
2022 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
2023 (long) get_frame_register_unsigned
2024 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
2025 (long) get_frame_register_unsigned
2026 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
2027 (long) get_frame_register_unsigned
2028 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
2029 }
2030
2031 static void
2032 sh4_nofpu_show_regs (struct frame_info *frame)
2033 {
2034 printf_filtered
2035 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
2036 phex (get_frame_register_unsigned (frame,
2037 gdbarch_pc_regnum
2038 (get_frame_arch (frame))), 4),
2039 (long) get_frame_register_unsigned (frame, SR_REGNUM),
2040 (long) get_frame_register_unsigned (frame, PR_REGNUM),
2041 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
2042
2043 printf_filtered
2044 (" GBR %08lx VBR %08lx MACL %08lx\n",
2045 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
2046 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
2047 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
2048 printf_filtered
2049 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
2050 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
2051 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
2052 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
2053 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
2054
2055 printf_filtered
2056 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2057 (long) get_frame_register_unsigned (frame, 0),
2058 (long) get_frame_register_unsigned (frame, 1),
2059 (long) get_frame_register_unsigned (frame, 2),
2060 (long) get_frame_register_unsigned (frame, 3),
2061 (long) get_frame_register_unsigned (frame, 4),
2062 (long) get_frame_register_unsigned (frame, 5),
2063 (long) get_frame_register_unsigned (frame, 6),
2064 (long) get_frame_register_unsigned (frame, 7));
2065 printf_filtered
2066 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2067 (long) get_frame_register_unsigned (frame, 8),
2068 (long) get_frame_register_unsigned (frame, 9),
2069 (long) get_frame_register_unsigned (frame, 10),
2070 (long) get_frame_register_unsigned (frame, 11),
2071 (long) get_frame_register_unsigned (frame, 12),
2072 (long) get_frame_register_unsigned (frame, 13),
2073 (long) get_frame_register_unsigned (frame, 14),
2074 (long) get_frame_register_unsigned (frame, 15));
2075 }
2076
2077 static void
2078 sh_dsp_show_regs (struct frame_info *frame)
2079 {
2080 printf_filtered
2081 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
2082 phex (get_frame_register_unsigned (frame,
2083 gdbarch_pc_regnum
2084 (get_frame_arch (frame))), 4),
2085 (long) get_frame_register_unsigned (frame, SR_REGNUM),
2086 (long) get_frame_register_unsigned (frame, PR_REGNUM),
2087 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
2088
2089 printf_filtered
2090 (" GBR %08lx VBR %08lx DSR %08lx MACL %08lx\n",
2091 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
2092 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
2093 (long) get_frame_register_unsigned (frame, DSR_REGNUM),
2094 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
2095
2096 printf_filtered
2097 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2098 (long) get_frame_register_unsigned (frame, 0),
2099 (long) get_frame_register_unsigned (frame, 1),
2100 (long) get_frame_register_unsigned (frame, 2),
2101 (long) get_frame_register_unsigned (frame, 3),
2102 (long) get_frame_register_unsigned (frame, 4),
2103 (long) get_frame_register_unsigned (frame, 5),
2104 (long) get_frame_register_unsigned (frame, 6),
2105 (long) get_frame_register_unsigned (frame, 7));
2106 printf_filtered
2107 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2108 (long) get_frame_register_unsigned (frame, 8),
2109 (long) get_frame_register_unsigned (frame, 9),
2110 (long) get_frame_register_unsigned (frame, 10),
2111 (long) get_frame_register_unsigned (frame, 11),
2112 (long) get_frame_register_unsigned (frame, 12),
2113 (long) get_frame_register_unsigned (frame, 13),
2114 (long) get_frame_register_unsigned (frame, 14),
2115 (long) get_frame_register_unsigned (frame, 15));
2116
2117 printf_filtered
2118 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2119 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
2120 (long) get_frame_register_unsigned (frame, A0_REGNUM),
2121 (long) get_frame_register_unsigned (frame, M0_REGNUM),
2122 (long) get_frame_register_unsigned (frame, X0_REGNUM),
2123 (long) get_frame_register_unsigned (frame, Y0_REGNUM),
2124 (long) get_frame_register_unsigned (frame, RS_REGNUM),
2125 (long) get_frame_register_unsigned (frame, MOD_REGNUM));
2126 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2127 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
2128 (long) get_frame_register_unsigned (frame, A1_REGNUM),
2129 (long) get_frame_register_unsigned (frame, M1_REGNUM),
2130 (long) get_frame_register_unsigned (frame, X1_REGNUM),
2131 (long) get_frame_register_unsigned (frame, Y1_REGNUM),
2132 (long) get_frame_register_unsigned (frame, RE_REGNUM));
2133 }
2134
2135 static void
2136 sh_show_regs_command (char *args, int from_tty)
2137 {
2138 if (sh_show_regs)
2139 (*sh_show_regs) (get_current_frame ());
2140 }
2141
2142 static struct type *
2143 sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr)
2144 {
2145 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
2146 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2147 return builtin_type (gdbarch)->builtin_float;
2148 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2149 return builtin_type (gdbarch)->builtin_double;
2150 else
2151 return builtin_type (gdbarch)->builtin_int;
2152 }
2153
2154 /* Return the GDB type object for the "standard" data type
2155 of data in register N. */
2156 static struct type *
2157 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
2158 {
2159 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
2160 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2161 return builtin_type (gdbarch)->builtin_float;
2162 else
2163 return builtin_type (gdbarch)->builtin_int;
2164 }
2165
2166 static struct type *
2167 sh_sh4_build_float_register_type (struct gdbarch *gdbarch, int high)
2168 {
2169 return lookup_array_range_type (builtin_type (gdbarch)->builtin_float,
2170 0, high);
2171 }
2172
2173 static struct type *
2174 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
2175 {
2176 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
2177 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2178 return builtin_type (gdbarch)->builtin_float;
2179 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2180 return builtin_type (gdbarch)->builtin_double;
2181 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2182 return sh_sh4_build_float_register_type (gdbarch, 3);
2183 else
2184 return builtin_type (gdbarch)->builtin_int;
2185 }
2186
2187 static struct type *
2188 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
2189 {
2190 return builtin_type (gdbarch)->builtin_int;
2191 }
2192
2193 /* Is a register in a reggroup?
2194 The default code in reggroup.c doesn't identify system registers, some
2195 float registers or any of the vector registers.
2196 TODO: sh2a and dsp registers. */
2197 static int
2198 sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2199 struct reggroup *reggroup)
2200 {
2201 if (gdbarch_register_name (gdbarch, regnum) == NULL
2202 || *gdbarch_register_name (gdbarch, regnum) == '\0')
2203 return 0;
2204
2205 if (reggroup == float_reggroup
2206 && (regnum == FPUL_REGNUM
2207 || regnum == FPSCR_REGNUM))
2208 return 1;
2209
2210 if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
2211 {
2212 if (reggroup == vector_reggroup || reggroup == float_reggroup)
2213 return 1;
2214 if (reggroup == general_reggroup)
2215 return 0;
2216 }
2217
2218 if (regnum == VBR_REGNUM
2219 || regnum == SR_REGNUM
2220 || regnum == FPSCR_REGNUM
2221 || regnum == SSR_REGNUM
2222 || regnum == SPC_REGNUM)
2223 {
2224 if (reggroup == system_reggroup)
2225 return 1;
2226 if (reggroup == general_reggroup)
2227 return 0;
2228 }
2229
2230 /* The default code can cope with any other registers. */
2231 return default_register_reggroup_p (gdbarch, regnum, reggroup);
2232 }
2233
2234 /* On the sh4, the DRi pseudo registers are problematic if the target
2235 is little endian. When the user writes one of those registers, for
2236 instance with 'ser var $dr0=1', we want the double to be stored
2237 like this:
2238 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2239 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2240
2241 This corresponds to little endian byte order & big endian word
2242 order. However if we let gdb write the register w/o conversion, it
2243 will write fr0 and fr1 this way:
2244 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2245 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2246 because it will consider fr0 and fr1 as a single LE stretch of memory.
2247
2248 To achieve what we want we must force gdb to store things in
2249 floatformat_ieee_double_littlebyte_bigword (which is defined in
2250 include/floatformat.h and libiberty/floatformat.c.
2251
2252 In case the target is big endian, there is no problem, the
2253 raw bytes will look like:
2254 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
2255 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2256
2257 The other pseudo registers (the FVs) also don't pose a problem
2258 because they are stored as 4 individual FP elements. */
2259
2260 static void
2261 sh_register_convert_to_virtual (int regnum, struct type *type,
2262 char *from, char *to)
2263 {
2264 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
2265 {
2266 DOUBLEST val;
2267 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2268 from, &val);
2269 store_typed_floating (to, type, val);
2270 }
2271 else
2272 error
2273 ("sh_register_convert_to_virtual called with non DR register number");
2274 }
2275
2276 static void
2277 sh_register_convert_to_raw (struct type *type, int regnum,
2278 const void *from, void *to)
2279 {
2280 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
2281 {
2282 DOUBLEST val = extract_typed_floating (from, type);
2283 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
2284 &val, to);
2285 }
2286 else
2287 error (_("sh_register_convert_to_raw called with non DR register number"));
2288 }
2289
2290 /* For vectors of 4 floating point registers. */
2291 static int
2292 fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum)
2293 {
2294 int fp_regnum;
2295
2296 fp_regnum = gdbarch_fp0_regnum (gdbarch)
2297 + (fv_regnum - FV0_REGNUM) * 4;
2298 return fp_regnum;
2299 }
2300
2301 /* For double precision floating point registers, i.e 2 fp regs. */
2302 static int
2303 dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum)
2304 {
2305 int fp_regnum;
2306
2307 fp_regnum = gdbarch_fp0_regnum (gdbarch)
2308 + (dr_regnum - DR0_REGNUM) * 2;
2309 return fp_regnum;
2310 }
2311
2312 /* Concatenate PORTIONS contiguous raw registers starting at
2313 BASE_REGNUM into BUFFER. */
2314
2315 static enum register_status
2316 pseudo_register_read_portions (struct gdbarch *gdbarch,
2317 struct regcache *regcache,
2318 int portions,
2319 int base_regnum, gdb_byte *buffer)
2320 {
2321 int portion;
2322
2323 for (portion = 0; portion < portions; portion++)
2324 {
2325 enum register_status status;
2326 gdb_byte *b;
2327
2328 b = buffer + register_size (gdbarch, base_regnum) * portion;
2329 status = regcache_raw_read (regcache, base_regnum + portion, b);
2330 if (status != REG_VALID)
2331 return status;
2332 }
2333
2334 return REG_VALID;
2335 }
2336
2337 static enum register_status
2338 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2339 int reg_nr, gdb_byte *buffer)
2340 {
2341 int base_regnum;
2342 char temp_buffer[MAX_REGISTER_SIZE];
2343 enum register_status status;
2344
2345 if (reg_nr == PSEUDO_BANK_REGNUM)
2346 return regcache_raw_read (regcache, BANK_REGNUM, buffer);
2347 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2348 {
2349 base_regnum = dr_reg_base_num (gdbarch, reg_nr);
2350
2351 /* Build the value in the provided buffer. */
2352 /* Read the real regs for which this one is an alias. */
2353 status = pseudo_register_read_portions (gdbarch, regcache,
2354 2, base_regnum, temp_buffer);
2355 if (status == REG_VALID)
2356 {
2357 /* We must pay attention to the endiannes. */
2358 sh_register_convert_to_virtual (reg_nr,
2359 register_type (gdbarch, reg_nr),
2360 temp_buffer, buffer);
2361 }
2362 return status;
2363 }
2364 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2365 {
2366 base_regnum = fv_reg_base_num (gdbarch, reg_nr);
2367
2368 /* Read the real regs for which this one is an alias. */
2369 return pseudo_register_read_portions (gdbarch, regcache,
2370 4, base_regnum, buffer);
2371 }
2372 else
2373 gdb_assert_not_reached ("invalid pseudo register number");
2374 }
2375
2376 static void
2377 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2378 int reg_nr, const gdb_byte *buffer)
2379 {
2380 int base_regnum, portion;
2381 char temp_buffer[MAX_REGISTER_SIZE];
2382
2383 if (reg_nr == PSEUDO_BANK_REGNUM)
2384 {
2385 /* When the bank register is written to, the whole register bank
2386 is switched and all values in the bank registers must be read
2387 from the target/sim again. We're just invalidating the regcache
2388 so that a re-read happens next time it's necessary. */
2389 int bregnum;
2390
2391 regcache_raw_write (regcache, BANK_REGNUM, buffer);
2392 for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum)
2393 regcache_invalidate (regcache, bregnum);
2394 }
2395 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2396 {
2397 base_regnum = dr_reg_base_num (gdbarch, reg_nr);
2398
2399 /* We must pay attention to the endiannes. */
2400 sh_register_convert_to_raw (register_type (gdbarch, reg_nr),
2401 reg_nr, buffer, temp_buffer);
2402
2403 /* Write the real regs for which this one is an alias. */
2404 for (portion = 0; portion < 2; portion++)
2405 regcache_raw_write (regcache, base_regnum + portion,
2406 (temp_buffer
2407 + register_size (gdbarch,
2408 base_regnum) * portion));
2409 }
2410 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2411 {
2412 base_regnum = fv_reg_base_num (gdbarch, reg_nr);
2413
2414 /* Write the real regs for which this one is an alias. */
2415 for (portion = 0; portion < 4; portion++)
2416 regcache_raw_write (regcache, base_regnum + portion,
2417 ((char *) buffer
2418 + register_size (gdbarch,
2419 base_regnum) * portion));
2420 }
2421 }
2422
2423 static int
2424 sh_dsp_register_sim_regno (struct gdbarch *gdbarch, int nr)
2425 {
2426 if (legacy_register_sim_regno (gdbarch, nr) < 0)
2427 return legacy_register_sim_regno (gdbarch, nr);
2428 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
2429 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
2430 if (nr == MOD_REGNUM)
2431 return SIM_SH_MOD_REGNUM;
2432 if (nr == RS_REGNUM)
2433 return SIM_SH_RS_REGNUM;
2434 if (nr == RE_REGNUM)
2435 return SIM_SH_RE_REGNUM;
2436 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
2437 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
2438 return nr;
2439 }
2440
2441 static int
2442 sh_sh2a_register_sim_regno (struct gdbarch *gdbarch, int nr)
2443 {
2444 switch (nr)
2445 {
2446 case TBR_REGNUM:
2447 return SIM_SH_TBR_REGNUM;
2448 case IBNR_REGNUM:
2449 return SIM_SH_IBNR_REGNUM;
2450 case IBCR_REGNUM:
2451 return SIM_SH_IBCR_REGNUM;
2452 case BANK_REGNUM:
2453 return SIM_SH_BANK_REGNUM;
2454 case MACLB_REGNUM:
2455 return SIM_SH_BANK_MACL_REGNUM;
2456 case GBRB_REGNUM:
2457 return SIM_SH_BANK_GBR_REGNUM;
2458 case PRB_REGNUM:
2459 return SIM_SH_BANK_PR_REGNUM;
2460 case IVNB_REGNUM:
2461 return SIM_SH_BANK_IVN_REGNUM;
2462 case MACHB_REGNUM:
2463 return SIM_SH_BANK_MACH_REGNUM;
2464 default:
2465 break;
2466 }
2467 return legacy_register_sim_regno (gdbarch, nr);
2468 }
2469
2470 /* Set up the register unwinding such that call-clobbered registers are
2471 not displayed in frames >0 because the true value is not certain.
2472 The 'undefined' registers will show up as 'not available' unless the
2473 CFI says otherwise.
2474
2475 This function is currently set up for SH4 and compatible only. */
2476
2477 static void
2478 sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
2479 struct dwarf2_frame_state_reg *reg,
2480 struct frame_info *this_frame)
2481 {
2482 /* Mark the PC as the destination for the return address. */
2483 if (regnum == gdbarch_pc_regnum (gdbarch))
2484 reg->how = DWARF2_FRAME_REG_RA;
2485
2486 /* Mark the stack pointer as the call frame address. */
2487 else if (regnum == gdbarch_sp_regnum (gdbarch))
2488 reg->how = DWARF2_FRAME_REG_CFA;
2489
2490 /* The above was taken from the default init_reg in dwarf2-frame.c
2491 while the below is SH specific. */
2492
2493 /* Caller save registers. */
2494 else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7)
2495 || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11)
2496 || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5)
2497 || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2)
2498 || (regnum == MACH_REGNUM)
2499 || (regnum == MACL_REGNUM)
2500 || (regnum == FPUL_REGNUM)
2501 || (regnum == SR_REGNUM))
2502 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2503
2504 /* Callee save registers. */
2505 else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15)
2506 || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15)
2507 || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8)
2508 || (regnum == FV0_REGNUM+3))
2509 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
2510
2511 /* Other registers. These are not in the ABI and may or may not
2512 mean anything in frames >0 so don't show them. */
2513 else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15)
2514 || (regnum == GBR_REGNUM)
2515 || (regnum == VBR_REGNUM)
2516 || (regnum == FPSCR_REGNUM)
2517 || (regnum == SSR_REGNUM)
2518 || (regnum == SPC_REGNUM))
2519 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2520 }
2521
2522 static struct sh_frame_cache *
2523 sh_alloc_frame_cache (void)
2524 {
2525 struct sh_frame_cache *cache;
2526 int i;
2527
2528 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
2529
2530 /* Base address. */
2531 cache->base = 0;
2532 cache->saved_sp = 0;
2533 cache->sp_offset = 0;
2534 cache->pc = 0;
2535
2536 /* Frameless until proven otherwise. */
2537 cache->uses_fp = 0;
2538
2539 /* Saved registers. We initialize these to -1 since zero is a valid
2540 offset (that's where fp is supposed to be stored). */
2541 for (i = 0; i < SH_NUM_REGS; i++)
2542 {
2543 cache->saved_regs[i] = -1;
2544 }
2545
2546 return cache;
2547 }
2548
2549 static struct sh_frame_cache *
2550 sh_frame_cache (struct frame_info *this_frame, void **this_cache)
2551 {
2552 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2553 struct sh_frame_cache *cache;
2554 CORE_ADDR current_pc;
2555 int i;
2556
2557 if (*this_cache)
2558 return *this_cache;
2559
2560 cache = sh_alloc_frame_cache ();
2561 *this_cache = cache;
2562
2563 /* In principle, for normal frames, fp holds the frame pointer,
2564 which holds the base address for the current stack frame.
2565 However, for functions that don't need it, the frame pointer is
2566 optional. For these "frameless" functions the frame pointer is
2567 actually the frame pointer of the calling frame. */
2568 cache->base = get_frame_register_unsigned (this_frame, FP_REGNUM);
2569 if (cache->base == 0)
2570 return cache;
2571
2572 cache->pc = get_frame_func (this_frame);
2573 current_pc = get_frame_pc (this_frame);
2574 if (cache->pc != 0)
2575 {
2576 ULONGEST fpscr;
2577
2578 /* Check for the existence of the FPSCR register. If it exists,
2579 fetch its value for use in prologue analysis. Passing a zero
2580 value is the best choice for architecture variants upon which
2581 there's no FPSCR register. */
2582 if (gdbarch_register_reggroup_p (gdbarch, FPSCR_REGNUM, all_reggroup))
2583 fpscr = get_frame_register_unsigned (this_frame, FPSCR_REGNUM);
2584 else
2585 fpscr = 0;
2586
2587 sh_analyze_prologue (gdbarch, cache->pc, current_pc, cache, fpscr);
2588 }
2589
2590 if (!cache->uses_fp)
2591 {
2592 /* We didn't find a valid frame, which means that CACHE->base
2593 currently holds the frame pointer for our calling frame. If
2594 we're at the start of a function, or somewhere half-way its
2595 prologue, the function's frame probably hasn't been fully
2596 setup yet. Try to reconstruct the base address for the stack
2597 frame by looking at the stack pointer. For truly "frameless"
2598 functions this might work too. */
2599 cache->base = get_frame_register_unsigned
2600 (this_frame, gdbarch_sp_regnum (gdbarch));
2601 }
2602
2603 /* Now that we have the base address for the stack frame we can
2604 calculate the value of sp in the calling frame. */
2605 cache->saved_sp = cache->base + cache->sp_offset;
2606
2607 /* Adjust all the saved registers such that they contain addresses
2608 instead of offsets. */
2609 for (i = 0; i < SH_NUM_REGS; i++)
2610 if (cache->saved_regs[i] != -1)
2611 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
2612
2613 return cache;
2614 }
2615
2616 static struct value *
2617 sh_frame_prev_register (struct frame_info *this_frame,
2618 void **this_cache, int regnum)
2619 {
2620 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2621 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
2622
2623 gdb_assert (regnum >= 0);
2624
2625 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
2626 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
2627
2628 /* The PC of the previous frame is stored in the PR register of
2629 the current frame. Frob regnum so that we pull the value from
2630 the correct place. */
2631 if (regnum == gdbarch_pc_regnum (gdbarch))
2632 regnum = PR_REGNUM;
2633
2634 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
2635 return frame_unwind_got_memory (this_frame, regnum,
2636 cache->saved_regs[regnum]);
2637
2638 return frame_unwind_got_register (this_frame, regnum, regnum);
2639 }
2640
2641 static void
2642 sh_frame_this_id (struct frame_info *this_frame, void **this_cache,
2643 struct frame_id *this_id)
2644 {
2645 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
2646
2647 /* This marks the outermost frame. */
2648 if (cache->base == 0)
2649 return;
2650
2651 *this_id = frame_id_build (cache->saved_sp, cache->pc);
2652 }
2653
2654 static const struct frame_unwind sh_frame_unwind = {
2655 NORMAL_FRAME,
2656 default_frame_unwind_stop_reason,
2657 sh_frame_this_id,
2658 sh_frame_prev_register,
2659 NULL,
2660 default_frame_sniffer
2661 };
2662
2663 static CORE_ADDR
2664 sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2665 {
2666 return frame_unwind_register_unsigned (next_frame,
2667 gdbarch_sp_regnum (gdbarch));
2668 }
2669
2670 static CORE_ADDR
2671 sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2672 {
2673 return frame_unwind_register_unsigned (next_frame,
2674 gdbarch_pc_regnum (gdbarch));
2675 }
2676
2677 static struct frame_id
2678 sh_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2679 {
2680 CORE_ADDR sp = get_frame_register_unsigned (this_frame,
2681 gdbarch_sp_regnum (gdbarch));
2682 return frame_id_build (sp, get_frame_pc (this_frame));
2683 }
2684
2685 static CORE_ADDR
2686 sh_frame_base_address (struct frame_info *this_frame, void **this_cache)
2687 {
2688 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
2689
2690 return cache->base;
2691 }
2692
2693 static const struct frame_base sh_frame_base = {
2694 &sh_frame_unwind,
2695 sh_frame_base_address,
2696 sh_frame_base_address,
2697 sh_frame_base_address
2698 };
2699
2700 static struct sh_frame_cache *
2701 sh_make_stub_cache (struct frame_info *this_frame)
2702 {
2703 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2704 struct sh_frame_cache *cache;
2705
2706 cache = sh_alloc_frame_cache ();
2707
2708 cache->saved_sp
2709 = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
2710
2711 return cache;
2712 }
2713
2714 static void
2715 sh_stub_this_id (struct frame_info *this_frame, void **this_cache,
2716 struct frame_id *this_id)
2717 {
2718 struct sh_frame_cache *cache;
2719
2720 if (*this_cache == NULL)
2721 *this_cache = sh_make_stub_cache (this_frame);
2722 cache = *this_cache;
2723
2724 *this_id = frame_id_build (cache->saved_sp, get_frame_pc (this_frame));
2725 }
2726
2727 static int
2728 sh_stub_unwind_sniffer (const struct frame_unwind *self,
2729 struct frame_info *this_frame,
2730 void **this_prologue_cache)
2731 {
2732 CORE_ADDR addr_in_block;
2733
2734 addr_in_block = get_frame_address_in_block (this_frame);
2735 if (in_plt_section (addr_in_block, NULL))
2736 return 1;
2737
2738 return 0;
2739 }
2740
2741 static const struct frame_unwind sh_stub_unwind =
2742 {
2743 NORMAL_FRAME,
2744 default_frame_unwind_stop_reason,
2745 sh_stub_this_id,
2746 sh_frame_prev_register,
2747 NULL,
2748 sh_stub_unwind_sniffer
2749 };
2750
2751 /* The epilogue is defined here as the area at the end of a function,
2752 either on the `ret' instruction itself or after an instruction which
2753 destroys the function's stack frame. */
2754 static int
2755 sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2756 {
2757 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2758 CORE_ADDR func_addr = 0, func_end = 0;
2759
2760 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2761 {
2762 ULONGEST inst;
2763 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2764 for a nop and some fixed data (e.g. big offsets) which are
2765 unfortunately also treated as part of the function (which
2766 means, they are below func_end. */
2767 CORE_ADDR addr = func_end - 28;
2768 if (addr < func_addr + 4)
2769 addr = func_addr + 4;
2770 if (pc < addr)
2771 return 0;
2772
2773 /* First search forward until hitting an rts. */
2774 while (addr < func_end
2775 && !IS_RTS (read_memory_unsigned_integer (addr, 2, byte_order)))
2776 addr += 2;
2777 if (addr >= func_end)
2778 return 0;
2779
2780 /* At this point we should find a mov.l @r15+,r14 instruction,
2781 either before or after the rts. If not, then the function has
2782 probably no "normal" epilogue and we bail out here. */
2783 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2784 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2,
2785 byte_order)))
2786 addr -= 2;
2787 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2,
2788 byte_order)))
2789 return 0;
2790
2791 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2792
2793 /* Step over possible lds.l @r15+,macl. */
2794 if (IS_MACL_LDS (inst))
2795 {
2796 addr -= 2;
2797 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2798 }
2799
2800 /* Step over possible lds.l @r15+,pr. */
2801 if (IS_LDS (inst))
2802 {
2803 addr -= 2;
2804 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2805 }
2806
2807 /* Step over possible mov r14,r15. */
2808 if (IS_MOV_FP_SP (inst))
2809 {
2810 addr -= 2;
2811 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2812 }
2813
2814 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2815 instructions. */
2816 while (addr > func_addr + 4
2817 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
2818 {
2819 addr -= 2;
2820 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2821 }
2822
2823 /* On SH2a check if the previous instruction was perhaps a MOVI20.
2824 That's allowed for the epilogue. */
2825 if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a
2826 || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu)
2827 && addr > func_addr + 6
2828 && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2,
2829 byte_order)))
2830 addr -= 4;
2831
2832 if (pc >= addr)
2833 return 1;
2834 }
2835 return 0;
2836 }
2837
2838
2839 /* Supply register REGNUM from the buffer specified by REGS and LEN
2840 in the register set REGSET to register cache REGCACHE.
2841 REGTABLE specifies where each register can be found in REGS.
2842 If REGNUM is -1, do this for all registers in REGSET. */
2843
2844 void
2845 sh_corefile_supply_regset (const struct regset *regset,
2846 struct regcache *regcache,
2847 int regnum, const void *regs, size_t len)
2848 {
2849 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2850 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2851 const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset
2852 ? tdep->core_gregmap
2853 : tdep->core_fpregmap);
2854 int i;
2855
2856 for (i = 0; regmap[i].regnum != -1; i++)
2857 {
2858 if ((regnum == -1 || regnum == regmap[i].regnum)
2859 && regmap[i].offset + 4 <= len)
2860 regcache_raw_supply (regcache, regmap[i].regnum,
2861 (char *)regs + regmap[i].offset);
2862 }
2863 }
2864
2865 /* Collect register REGNUM in the register set REGSET from register cache
2866 REGCACHE into the buffer specified by REGS and LEN.
2867 REGTABLE specifies where each register can be found in REGS.
2868 If REGNUM is -1, do this for all registers in REGSET. */
2869
2870 void
2871 sh_corefile_collect_regset (const struct regset *regset,
2872 const struct regcache *regcache,
2873 int regnum, void *regs, size_t len)
2874 {
2875 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2876 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2877 const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset
2878 ? tdep->core_gregmap
2879 : tdep->core_fpregmap);
2880 int i;
2881
2882 for (i = 0; regmap[i].regnum != -1; i++)
2883 {
2884 if ((regnum == -1 || regnum == regmap[i].regnum)
2885 && regmap[i].offset + 4 <= len)
2886 regcache_raw_collect (regcache, regmap[i].regnum,
2887 (char *)regs + regmap[i].offset);
2888 }
2889 }
2890
2891 /* The following two regsets have the same contents, so it is tempting to
2892 unify them, but they are distiguished by their address, so don't. */
2893
2894 struct regset sh_corefile_gregset =
2895 {
2896 NULL,
2897 sh_corefile_supply_regset,
2898 sh_corefile_collect_regset
2899 };
2900
2901 static struct regset sh_corefile_fpregset =
2902 {
2903 NULL,
2904 sh_corefile_supply_regset,
2905 sh_corefile_collect_regset
2906 };
2907
2908 static const struct regset *
2909 sh_regset_from_core_section (struct gdbarch *gdbarch, const char *sect_name,
2910 size_t sect_size)
2911 {
2912 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2913
2914 if (tdep->core_gregmap && strcmp (sect_name, ".reg") == 0)
2915 return &sh_corefile_gregset;
2916
2917 if (tdep->core_fpregmap && strcmp (sect_name, ".reg2") == 0)
2918 return &sh_corefile_fpregset;
2919
2920 return NULL;
2921 }
2922 \f
2923
2924 static struct gdbarch *
2925 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2926 {
2927 struct gdbarch *gdbarch;
2928 struct gdbarch_tdep *tdep;
2929
2930 sh_show_regs = sh_generic_show_regs;
2931 switch (info.bfd_arch_info->mach)
2932 {
2933 case bfd_mach_sh2e:
2934 sh_show_regs = sh2e_show_regs;
2935 break;
2936 case bfd_mach_sh2a:
2937 sh_show_regs = sh2a_show_regs;
2938 break;
2939 case bfd_mach_sh2a_nofpu:
2940 sh_show_regs = sh2a_nofpu_show_regs;
2941 break;
2942 case bfd_mach_sh_dsp:
2943 sh_show_regs = sh_dsp_show_regs;
2944 break;
2945
2946 case bfd_mach_sh3:
2947 case bfd_mach_sh3_nommu:
2948 case bfd_mach_sh2a_nofpu_or_sh3_nommu:
2949 sh_show_regs = sh3_show_regs;
2950 break;
2951
2952 case bfd_mach_sh3e:
2953 case bfd_mach_sh2a_or_sh3e:
2954 sh_show_regs = sh3e_show_regs;
2955 break;
2956
2957 case bfd_mach_sh3_dsp:
2958 case bfd_mach_sh4al_dsp:
2959 sh_show_regs = sh3_dsp_show_regs;
2960 break;
2961
2962 case bfd_mach_sh4:
2963 case bfd_mach_sh4a:
2964 case bfd_mach_sh2a_or_sh4:
2965 sh_show_regs = sh4_show_regs;
2966 break;
2967
2968 case bfd_mach_sh4_nofpu:
2969 case bfd_mach_sh4_nommu_nofpu:
2970 case bfd_mach_sh4a_nofpu:
2971 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
2972 sh_show_regs = sh4_nofpu_show_regs;
2973 break;
2974
2975 case bfd_mach_sh5:
2976 sh_show_regs = sh64_show_regs;
2977 /* SH5 is handled entirely in sh64-tdep.c. */
2978 return sh64_gdbarch_init (info, arches);
2979 }
2980
2981 /* If there is already a candidate, use it. */
2982 arches = gdbarch_list_lookup_by_info (arches, &info);
2983 if (arches != NULL)
2984 return arches->gdbarch;
2985
2986 /* None found, create a new architecture from the information
2987 provided. */
2988 tdep = XZALLOC (struct gdbarch_tdep);
2989 gdbarch = gdbarch_alloc (&info, tdep);
2990
2991 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2992 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2993 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2994 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2995 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2996 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2997 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2998 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2999
3000 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
3001 set_gdbarch_sp_regnum (gdbarch, 15);
3002 set_gdbarch_pc_regnum (gdbarch, 16);
3003 set_gdbarch_fp0_regnum (gdbarch, -1);
3004 set_gdbarch_num_pseudo_regs (gdbarch, 0);
3005
3006 set_gdbarch_register_type (gdbarch, sh_default_register_type);
3007 set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p);
3008
3009 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
3010
3011 set_gdbarch_print_insn (gdbarch, print_insn_sh);
3012 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
3013
3014 set_gdbarch_return_value (gdbarch, sh_return_value_nofpu);
3015
3016 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
3017 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3018
3019 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
3020
3021 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
3022
3023 set_gdbarch_frame_align (gdbarch, sh_frame_align);
3024 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
3025 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
3026 set_gdbarch_dummy_id (gdbarch, sh_dummy_id);
3027 frame_base_set_default (gdbarch, &sh_frame_base);
3028
3029 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
3030
3031 dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg);
3032
3033 set_gdbarch_regset_from_core_section (gdbarch, sh_regset_from_core_section);
3034
3035 switch (info.bfd_arch_info->mach)
3036 {
3037 case bfd_mach_sh:
3038 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
3039 break;
3040
3041 case bfd_mach_sh2:
3042 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
3043 break;
3044
3045 case bfd_mach_sh2e:
3046 /* doubles on sh2e and sh3e are actually 4 byte. */
3047 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3048
3049 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
3050 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
3051 set_gdbarch_fp0_regnum (gdbarch, 25);
3052 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
3053 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
3054 break;
3055
3056 case bfd_mach_sh2a:
3057 set_gdbarch_register_name (gdbarch, sh_sh2a_register_name);
3058 set_gdbarch_register_type (gdbarch, sh_sh2a_register_type);
3059 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
3060
3061 set_gdbarch_fp0_regnum (gdbarch, 25);
3062 set_gdbarch_num_pseudo_regs (gdbarch, 9);
3063 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
3064 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
3065 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
3066 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
3067 break;
3068
3069 case bfd_mach_sh2a_nofpu:
3070 set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name);
3071 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
3072
3073 set_gdbarch_num_pseudo_regs (gdbarch, 1);
3074 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
3075 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
3076 break;
3077
3078 case bfd_mach_sh_dsp:
3079 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
3080 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
3081 break;
3082
3083 case bfd_mach_sh3:
3084 case bfd_mach_sh3_nommu:
3085 case bfd_mach_sh2a_nofpu_or_sh3_nommu:
3086 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
3087 break;
3088
3089 case bfd_mach_sh3e:
3090 case bfd_mach_sh2a_or_sh3e:
3091 /* doubles on sh2e and sh3e are actually 4 byte. */
3092 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3093
3094 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
3095 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
3096 set_gdbarch_fp0_regnum (gdbarch, 25);
3097 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
3098 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
3099 break;
3100
3101 case bfd_mach_sh3_dsp:
3102 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
3103 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
3104 break;
3105
3106 case bfd_mach_sh4:
3107 case bfd_mach_sh4a:
3108 case bfd_mach_sh2a_or_sh4:
3109 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
3110 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
3111 set_gdbarch_fp0_regnum (gdbarch, 25);
3112 set_gdbarch_num_pseudo_regs (gdbarch, 13);
3113 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
3114 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
3115 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
3116 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
3117 break;
3118
3119 case bfd_mach_sh4_nofpu:
3120 case bfd_mach_sh4a_nofpu:
3121 case bfd_mach_sh4_nommu_nofpu:
3122 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
3123 set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
3124 break;
3125
3126 case bfd_mach_sh4al_dsp:
3127 set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
3128 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
3129 break;
3130
3131 default:
3132 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
3133 break;
3134 }
3135
3136 /* Hook in ABI-specific overrides, if they have been registered. */
3137 gdbarch_init_osabi (info, gdbarch);
3138
3139 dwarf2_append_unwinders (gdbarch);
3140 frame_unwind_append_unwinder (gdbarch, &sh_stub_unwind);
3141 frame_unwind_append_unwinder (gdbarch, &sh_frame_unwind);
3142
3143 return gdbarch;
3144 }
3145
3146 static void
3147 show_sh_command (char *args, int from_tty)
3148 {
3149 help_list (showshcmdlist, "show sh ", all_commands, gdb_stdout);
3150 }
3151
3152 static void
3153 set_sh_command (char *args, int from_tty)
3154 {
3155 printf_unfiltered
3156 ("\"set sh\" must be followed by an appropriate subcommand.\n");
3157 help_list (setshcmdlist, "set sh ", all_commands, gdb_stdout);
3158 }
3159
3160 extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
3161
3162 void
3163 _initialize_sh_tdep (void)
3164 {
3165 struct cmd_list_element *c;
3166
3167 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
3168
3169 add_com ("regs", class_vars, sh_show_regs_command, _("Print all registers"));
3170
3171 add_prefix_cmd ("sh", no_class, set_sh_command, "SH specific commands.",
3172 &setshcmdlist, "set sh ", 0, &setlist);
3173 add_prefix_cmd ("sh", no_class, show_sh_command, "SH specific commands.",
3174 &showshcmdlist, "show sh ", 0, &showlist);
3175
3176 add_setshow_enum_cmd ("calling-convention", class_vars, sh_cc_enum,
3177 &sh_active_calling_convention,
3178 _("Set calling convention used when calling target "
3179 "functions from GDB."),
3180 _("Show calling convention used when calling target "
3181 "functions from GDB."),
3182 _("gcc - Use GCC calling convention (default).\n"
3183 "renesas - Enforce Renesas calling convention."),
3184 NULL, NULL,
3185 &setshcmdlist, &showshcmdlist);
3186 }
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