1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993-2005, 2007-2012 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* Contributed by Steve Chamberlain
25 #include "frame-base.h"
26 #include "frame-unwind.h"
27 #include "dwarf2-frame.h"
35 #include "gdb_string.h"
36 #include "gdb_assert.h"
37 #include "arch-utils.h"
38 #include "floatformat.h"
42 #include "reggroups.h"
47 #include "sh64-tdep.h"
50 #include "solib-svr4.h"
55 /* registers numbers shared with the simulator. */
56 #include "gdb/sim-sh.h"
58 /* List of "set sh ..." and "show sh ..." commands. */
59 static struct cmd_list_element
*setshcmdlist
= NULL
;
60 static struct cmd_list_element
*showshcmdlist
= NULL
;
62 static const char sh_cc_gcc
[] = "gcc";
63 static const char sh_cc_renesas
[] = "renesas";
64 static const char *const sh_cc_enum
[] = {
70 static const char *sh_active_calling_convention
= sh_cc_gcc
;
72 static void (*sh_show_regs
) (struct frame_info
*);
74 #define SH_NUM_REGS 67
83 /* Flag showing that a frame has been created in the prologue code. */
86 /* Saved registers. */
87 CORE_ADDR saved_regs
[SH_NUM_REGS
];
92 sh_is_renesas_calling_convention (struct type
*func_type
)
98 func_type
= check_typedef (func_type
);
100 if (TYPE_CODE (func_type
) == TYPE_CODE_PTR
)
101 func_type
= check_typedef (TYPE_TARGET_TYPE (func_type
));
103 if (TYPE_CODE (func_type
) == TYPE_CODE_FUNC
104 && TYPE_CALLING_CONVENTION (func_type
) == DW_CC_GNU_renesas_sh
)
108 if (sh_active_calling_convention
== sh_cc_renesas
)
115 sh_sh_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
117 static char *register_names
[] = {
118 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
119 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
120 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
122 "", "", "", "", "", "", "", "",
123 "", "", "", "", "", "", "", "",
125 "", "", "", "", "", "", "", "",
126 "", "", "", "", "", "", "", "",
127 "", "", "", "", "", "", "", "",
131 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
133 return register_names
[reg_nr
];
137 sh_sh3_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
139 static char *register_names
[] = {
140 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
141 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
142 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
144 "", "", "", "", "", "", "", "",
145 "", "", "", "", "", "", "", "",
147 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
148 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
149 "", "", "", "", "", "", "", "",
153 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
155 return register_names
[reg_nr
];
159 sh_sh3e_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
161 static char *register_names
[] = {
162 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
163 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
164 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
166 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
167 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
169 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
170 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
171 "", "", "", "", "", "", "", "",
175 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
177 return register_names
[reg_nr
];
181 sh_sh2e_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
183 static char *register_names
[] = {
184 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
185 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
186 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
188 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
189 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
191 "", "", "", "", "", "", "", "",
192 "", "", "", "", "", "", "", "",
193 "", "", "", "", "", "", "", "",
197 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
199 return register_names
[reg_nr
];
203 sh_sh2a_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
205 static char *register_names
[] = {
206 /* general registers 0-15 */
207 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
208 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
210 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
213 /* floating point registers 25 - 40 */
214 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
215 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
218 /* 43 - 62. Banked registers. The bank number used is determined by
219 the bank register (63). */
220 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
221 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
222 "machb", "ivnb", "prb", "gbrb", "maclb",
223 /* 63: register bank number, not a real register but used to
224 communicate the register bank currently get/set. This register
225 is hidden to the user, who manipulates it using the pseudo
226 register called "bank" (67). See below. */
229 "ibcr", "ibnr", "tbr",
230 /* 67: register bank number, the user visible pseudo register. */
232 /* double precision (pseudo) 68 - 75 */
233 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
237 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
239 return register_names
[reg_nr
];
243 sh_sh2a_nofpu_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
245 static char *register_names
[] = {
246 /* general registers 0-15 */
247 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
248 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
250 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
253 /* floating point registers 25 - 40 */
254 "", "", "", "", "", "", "", "",
255 "", "", "", "", "", "", "", "",
258 /* 43 - 62. Banked registers. The bank number used is determined by
259 the bank register (63). */
260 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
261 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
262 "machb", "ivnb", "prb", "gbrb", "maclb",
263 /* 63: register bank number, not a real register but used to
264 communicate the register bank currently get/set. This register
265 is hidden to the user, who manipulates it using the pseudo
266 register called "bank" (67). See below. */
269 "ibcr", "ibnr", "tbr",
270 /* 67: register bank number, the user visible pseudo register. */
272 /* double precision (pseudo) 68 - 75 */
273 "", "", "", "", "", "", "", "",
277 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
279 return register_names
[reg_nr
];
283 sh_sh_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
285 static char *register_names
[] = {
286 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
287 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
288 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
290 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
291 "y0", "y1", "", "", "", "", "", "mod",
293 "rs", "re", "", "", "", "", "", "",
294 "", "", "", "", "", "", "", "",
295 "", "", "", "", "", "", "", "",
299 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
301 return register_names
[reg_nr
];
305 sh_sh3_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
307 static char *register_names
[] = {
308 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
309 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
310 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
312 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
313 "y0", "y1", "", "", "", "", "", "mod",
315 "rs", "re", "", "", "", "", "", "",
316 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
317 "", "", "", "", "", "", "", "",
318 "", "", "", "", "", "", "", "",
322 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
324 return register_names
[reg_nr
];
328 sh_sh4_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
330 static char *register_names
[] = {
331 /* general registers 0-15 */
332 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
333 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
335 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
338 /* floating point registers 25 - 40 */
339 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
340 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
344 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
346 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
347 "", "", "", "", "", "", "", "",
348 /* pseudo bank register. */
350 /* double precision (pseudo) 59 - 66 */
351 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
352 /* vectors (pseudo) 67 - 70 */
353 "fv0", "fv4", "fv8", "fv12",
354 /* FIXME: missing XF 71 - 86 */
355 /* FIXME: missing XD 87 - 94 */
359 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
361 return register_names
[reg_nr
];
365 sh_sh4_nofpu_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
367 static char *register_names
[] = {
368 /* general registers 0-15 */
369 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
370 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
372 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
375 /* floating point registers 25 - 40 -- not for nofpu target */
376 "", "", "", "", "", "", "", "",
377 "", "", "", "", "", "", "", "",
381 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
383 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
384 "", "", "", "", "", "", "", "",
385 /* pseudo bank register. */
387 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
388 "", "", "", "", "", "", "", "",
389 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
394 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
396 return register_names
[reg_nr
];
400 sh_sh4al_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
402 static char *register_names
[] = {
403 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
404 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
405 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
407 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
408 "y0", "y1", "", "", "", "", "", "mod",
410 "rs", "re", "", "", "", "", "", "",
411 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
412 "", "", "", "", "", "", "", "",
413 "", "", "", "", "", "", "", "",
417 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
419 return register_names
[reg_nr
];
422 static const unsigned char *
423 sh_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
425 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes. */
426 static unsigned char breakpoint
[] = { 0xc3, 0xc3 };
428 /* For remote stub targets, trapa #20 is used. */
429 if (strcmp (target_shortname
, "remote") == 0)
431 static unsigned char big_remote_breakpoint
[] = { 0xc3, 0x20 };
432 static unsigned char little_remote_breakpoint
[] = { 0x20, 0xc3 };
434 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
436 *lenptr
= sizeof (big_remote_breakpoint
);
437 return big_remote_breakpoint
;
441 *lenptr
= sizeof (little_remote_breakpoint
);
442 return little_remote_breakpoint
;
446 *lenptr
= sizeof (breakpoint
);
450 /* Prologue looks like
454 sub <room_for_loca_vars>,r15
457 Actually it can be more complicated than this but that's it, basically. */
459 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
460 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
462 /* JSR @Rm 0100mmmm00001011 */
463 #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
465 /* STS.L PR,@-r15 0100111100100010
466 r15-4-->r15, PR-->(r15) */
467 #define IS_STS(x) ((x) == 0x4f22)
469 /* STS.L MACL,@-r15 0100111100010010
470 r15-4-->r15, MACL-->(r15) */
471 #define IS_MACL_STS(x) ((x) == 0x4f12)
473 /* MOV.L Rm,@-r15 00101111mmmm0110
474 r15-4-->r15, Rm-->(R15) */
475 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
477 /* MOV r15,r14 0110111011110011
479 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
481 /* ADD #imm,r15 01111111iiiiiiii
483 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
485 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
486 #define IS_SHLL_R3(x) ((x) == 0x4300)
488 /* ADD r3,r15 0011111100111100
490 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
492 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
493 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
494 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
495 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
496 make this entirely clear. */
497 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
498 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
500 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
501 #define IS_MOV_ARG_TO_REG(x) \
502 (((x) & 0xf00f) == 0x6003 && \
503 ((x) & 0x00f0) >= 0x0040 && \
504 ((x) & 0x00f0) <= 0x0070)
505 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
506 #define IS_MOV_ARG_TO_IND_R14(x) \
507 (((x) & 0xff0f) == 0x2e02 && \
508 ((x) & 0x00f0) >= 0x0040 && \
509 ((x) & 0x00f0) <= 0x0070)
510 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
511 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
512 (((x) & 0xff00) == 0x1e00 && \
513 ((x) & 0x00f0) >= 0x0040 && \
514 ((x) & 0x00f0) <= 0x0070)
516 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
517 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
518 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
519 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
520 /* MOVI20 #imm20,Rn 0000nnnniiii0000 */
521 #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
522 /* SUB Rn,R15 00111111nnnn1000 */
523 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
525 #define FPSCR_SZ (1 << 20)
527 /* The following instructions are used for epilogue testing. */
528 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
529 #define IS_RTS(x) ((x) == 0x000b)
530 #define IS_LDS(x) ((x) == 0x4f26)
531 #define IS_MACL_LDS(x) ((x) == 0x4f16)
532 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
533 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
534 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
537 sh_analyze_prologue (struct gdbarch
*gdbarch
,
538 CORE_ADDR pc
, CORE_ADDR current_pc
,
539 struct sh_frame_cache
*cache
, ULONGEST fpscr
)
541 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
547 int reg
, sav_reg
= -1;
549 if (pc
>= current_pc
)
553 for (opc
= pc
+ (2 * 28); pc
< opc
; pc
+= 2)
555 inst
= read_memory_unsigned_integer (pc
, 2, byte_order
);
556 /* See where the registers will be saved to. */
559 cache
->saved_regs
[GET_SOURCE_REG (inst
)] = cache
->sp_offset
;
560 cache
->sp_offset
+= 4;
562 else if (IS_STS (inst
))
564 cache
->saved_regs
[PR_REGNUM
] = cache
->sp_offset
;
565 cache
->sp_offset
+= 4;
567 else if (IS_MACL_STS (inst
))
569 cache
->saved_regs
[MACL_REGNUM
] = cache
->sp_offset
;
570 cache
->sp_offset
+= 4;
572 else if (IS_MOV_R3 (inst
))
574 r3_val
= ((inst
& 0xff) ^ 0x80) - 0x80;
576 else if (IS_SHLL_R3 (inst
))
580 else if (IS_ADD_R3SP (inst
))
582 cache
->sp_offset
+= -r3_val
;
584 else if (IS_ADD_IMM_SP (inst
))
586 offset
= ((inst
& 0xff) ^ 0x80) - 0x80;
587 cache
->sp_offset
-= offset
;
589 else if (IS_MOVW_PCREL_TO_REG (inst
))
593 reg
= GET_TARGET_REG (inst
);
597 offset
= (inst
& 0xff) << 1;
599 read_memory_integer ((pc
+ 4) + offset
, 2, byte_order
);
603 else if (IS_MOVL_PCREL_TO_REG (inst
))
607 reg
= GET_TARGET_REG (inst
);
611 offset
= (inst
& 0xff) << 2;
613 read_memory_integer (((pc
& 0xfffffffc) + 4) + offset
,
618 else if (IS_MOVI20 (inst
))
622 reg
= GET_TARGET_REG (inst
);
626 sav_offset
= GET_SOURCE_REG (inst
) << 16;
627 /* MOVI20 is a 32 bit instruction! */
630 |= read_memory_unsigned_integer (pc
, 2, byte_order
);
631 /* Now sav_offset contains an unsigned 20 bit value.
632 It must still get sign extended. */
633 if (sav_offset
& 0x00080000)
634 sav_offset
|= 0xfff00000;
638 else if (IS_SUB_REG_FROM_SP (inst
))
640 reg
= GET_SOURCE_REG (inst
);
641 if (sav_reg
> 0 && reg
== sav_reg
)
645 cache
->sp_offset
+= sav_offset
;
647 else if (IS_FPUSH (inst
))
649 if (fpscr
& FPSCR_SZ
)
651 cache
->sp_offset
+= 8;
655 cache
->sp_offset
+= 4;
658 else if (IS_MOV_SP_FP (inst
))
661 /* At this point, only allow argument register moves to other
662 registers or argument register moves to @(X,fp) which are
663 moving the register arguments onto the stack area allocated
664 by a former add somenumber to SP call. Don't allow moving
665 to an fp indirect address above fp + cache->sp_offset. */
667 for (opc
= pc
+ 12; pc
< opc
; pc
+= 2)
669 inst
= read_memory_integer (pc
, 2, byte_order
);
670 if (IS_MOV_ARG_TO_IND_R14 (inst
))
672 reg
= GET_SOURCE_REG (inst
);
673 if (cache
->sp_offset
> 0)
674 cache
->saved_regs
[reg
] = cache
->sp_offset
;
676 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst
))
678 reg
= GET_SOURCE_REG (inst
);
679 offset
= (inst
& 0xf) * 4;
680 if (cache
->sp_offset
> offset
)
681 cache
->saved_regs
[reg
] = cache
->sp_offset
- offset
;
683 else if (IS_MOV_ARG_TO_REG (inst
))
690 else if (IS_JSR (inst
))
692 /* We have found a jsr that has been scheduled into the prologue.
693 If we continue the scan and return a pc someplace after this,
694 then setting a breakpoint on this function will cause it to
695 appear to be called after the function it is calling via the
696 jsr, which will be very confusing. Most likely the next
697 instruction is going to be IS_MOV_SP_FP in the delay slot. If
698 so, note that before returning the current pc. */
699 inst
= read_memory_integer (pc
+ 2, 2, byte_order
);
700 if (IS_MOV_SP_FP (inst
))
704 #if 0 /* This used to just stop when it found an instruction
705 that was not considered part of the prologue. Now,
706 we just keep going looking for likely
716 /* Skip any prologue before the guts of a function. */
718 sh_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
720 CORE_ADDR post_prologue_pc
, func_addr
;
721 struct sh_frame_cache cache
;
723 /* See if we can determine the end of the prologue via the symbol table.
724 If so, then return either PC, or the PC after the prologue, whichever
726 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
728 post_prologue_pc
= skip_prologue_using_sal (gdbarch
, func_addr
);
729 if (post_prologue_pc
!= 0)
730 return max (pc
, post_prologue_pc
);
733 /* Can't determine prologue from the symbol table, need to examine
736 cache
.sp_offset
= -4;
737 post_prologue_pc
= sh_analyze_prologue (gdbarch
, pc
, (CORE_ADDR
) -1, &cache
, 0);
739 pc
= post_prologue_pc
;
746 Aggregate types not bigger than 8 bytes that have the same size and
747 alignment as one of the integer scalar types are returned in the
748 same registers as the integer type they match.
750 For example, a 2-byte aligned structure with size 2 bytes has the
751 same size and alignment as a short int, and will be returned in R0.
752 A 4-byte aligned structure with size 8 bytes has the same size and
753 alignment as a long long int, and will be returned in R0 and R1.
755 When an aggregate type is returned in R0 and R1, R0 contains the
756 first four bytes of the aggregate, and R1 contains the
757 remainder. If the size of the aggregate type is not a multiple of 4
758 bytes, the aggregate is tail-padded up to a multiple of 4
759 bytes. The value of the padding is undefined. For little-endian
760 targets the padding will appear at the most significant end of the
761 last element, for big-endian targets the padding appears at the
762 least significant end of the last element.
764 All other aggregate types are returned by address. The caller
765 function passes the address of an area large enough to hold the
766 aggregate value in R2. The called function stores the result in
769 To reiterate, structs smaller than 8 bytes could also be returned
770 in memory, if they don't pass the "same size and alignment as an
775 struct s { char c[3]; } wibble;
776 struct s foo(void) { return wibble; }
778 the return value from foo() will be in memory, not
779 in R0, because there is no 3-byte integer type.
783 struct s { char c[2]; } wibble;
784 struct s foo(void) { return wibble; }
786 because a struct containing two chars has alignment 1, that matches
787 type char, but size 2, that matches type short. There's no integer
788 type that has alignment 1 and size 2, so the struct is returned in
792 sh_use_struct_convention (int renesas_abi
, struct type
*type
)
794 int len
= TYPE_LENGTH (type
);
795 int nelem
= TYPE_NFIELDS (type
);
797 /* The Renesas ABI returns aggregate types always on stack. */
798 if (renesas_abi
&& (TYPE_CODE (type
) == TYPE_CODE_STRUCT
799 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
802 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
803 fit in two registers anyway) use struct convention. */
804 if (len
!= 1 && len
!= 2 && len
!= 4 && len
!= 8)
807 /* Scalar types and aggregate types with exactly one field are aligned
808 by definition. They are returned in registers. */
812 /* If the first field in the aggregate has the same length as the entire
813 aggregate type, the type is returned in registers. */
814 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0)) == len
)
817 /* If the size of the aggregate is 8 bytes and the first field is
818 of size 4 bytes its alignment is equal to long long's alignment,
819 so it's returned in registers. */
820 if (len
== 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0)) == 4)
823 /* Otherwise use struct convention. */
828 sh_use_struct_convention_nofpu (int renesas_abi
, struct type
*type
)
830 /* The Renesas ABI returns long longs/doubles etc. always on stack. */
831 if (renesas_abi
&& TYPE_NFIELDS (type
) == 0 && TYPE_LENGTH (type
) >= 8)
833 return sh_use_struct_convention (renesas_abi
, type
);
837 sh_frame_align (struct gdbarch
*ignore
, CORE_ADDR sp
)
842 /* Function: push_dummy_call (formerly push_arguments)
843 Setup the function arguments for calling a function in the inferior.
845 On the Renesas SH architecture, there are four registers (R4 to R7)
846 which are dedicated for passing function arguments. Up to the first
847 four arguments (depending on size) may go into these registers.
848 The rest go on the stack.
850 MVS: Except on SH variants that have floating point registers.
851 In that case, float and double arguments are passed in the same
852 manner, but using FP registers instead of GP registers.
854 Arguments that are smaller than 4 bytes will still take up a whole
855 register or a whole 32-bit word on the stack, and will be
856 right-justified in the register or the stack word. This includes
857 chars, shorts, and small aggregate types.
859 Arguments that are larger than 4 bytes may be split between two or
860 more registers. If there are not enough registers free, an argument
861 may be passed partly in a register (or registers), and partly on the
862 stack. This includes doubles, long longs, and larger aggregates.
863 As far as I know, there is no upper limit to the size of aggregates
864 that will be passed in this way; in other words, the convention of
865 passing a pointer to a large aggregate instead of a copy is not used.
867 MVS: The above appears to be true for the SH variants that do not
868 have an FPU, however those that have an FPU appear to copy the
869 aggregate argument onto the stack (and not place it in registers)
870 if it is larger than 16 bytes (four GP registers).
872 An exceptional case exists for struct arguments (and possibly other
873 aggregates such as arrays) if the size is larger than 4 bytes but
874 not a multiple of 4 bytes. In this case the argument is never split
875 between the registers and the stack, but instead is copied in its
876 entirety onto the stack, AND also copied into as many registers as
877 there is room for. In other words, space in registers permitting,
878 two copies of the same argument are passed in. As far as I can tell,
879 only the one on the stack is used, although that may be a function
880 of the level of compiler optimization. I suspect this is a compiler
881 bug. Arguments of these odd sizes are left-justified within the
882 word (as opposed to arguments smaller than 4 bytes, which are
885 If the function is to return an aggregate type such as a struct, it
886 is either returned in the normal return value register R0 (if its
887 size is no greater than one byte), or else the caller must allocate
888 space into which the callee will copy the return value (if the size
889 is greater than one byte). In this case, a pointer to the return
890 value location is passed into the callee in register R2, which does
891 not displace any of the other arguments passed in via registers R4
894 /* Helper function to justify value in register according to endianess. */
896 sh_justify_value_in_reg (struct gdbarch
*gdbarch
, struct value
*val
, int len
)
898 static char valbuf
[4];
900 memset (valbuf
, 0, sizeof (valbuf
));
903 /* value gets right-justified in the register or stack word. */
904 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
905 memcpy (valbuf
+ (4 - len
), (char *) value_contents (val
), len
);
907 memcpy (valbuf
, (char *) value_contents (val
), len
);
910 return (char *) value_contents (val
);
913 /* Helper function to eval number of bytes to allocate on stack. */
915 sh_stack_allocsize (int nargs
, struct value
**args
)
919 stack_alloc
+= ((TYPE_LENGTH (value_type (args
[nargs
])) + 3) & ~3);
923 /* Helper functions for getting the float arguments right. Registers usage
924 depends on the ABI and the endianess. The comments should enlighten how
925 it's intended to work. */
927 /* This array stores which of the float arg registers are already in use. */
928 static int flt_argreg_array
[FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
+ 1];
930 /* This function just resets the above array to "no reg used so far". */
932 sh_init_flt_argreg (void)
934 memset (flt_argreg_array
, 0, sizeof flt_argreg_array
);
937 /* This function returns the next register to use for float arg passing.
938 It returns either a valid value between FLOAT_ARG0_REGNUM and
939 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
940 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
942 Note that register number 0 in flt_argreg_array corresponds with the
943 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
944 29) the parity of the register number is preserved, which is important
945 for the double register passing test (see the "argreg & 1" test below). */
947 sh_next_flt_argreg (struct gdbarch
*gdbarch
, int len
, struct type
*func_type
)
951 /* First search for the next free register. */
952 for (argreg
= 0; argreg
<= FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
;
954 if (!flt_argreg_array
[argreg
])
957 /* No register left? */
958 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
959 return FLOAT_ARGLAST_REGNUM
+ 1;
963 /* Doubles are always starting in a even register number. */
966 /* In gcc ABI, the skipped register is lost for further argument
967 passing now. Not so in Renesas ABI. */
968 if (!sh_is_renesas_calling_convention (func_type
))
969 flt_argreg_array
[argreg
] = 1;
973 /* No register left? */
974 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
975 return FLOAT_ARGLAST_REGNUM
+ 1;
977 /* Also mark the next register as used. */
978 flt_argreg_array
[argreg
+ 1] = 1;
980 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
981 && !sh_is_renesas_calling_convention (func_type
))
983 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
984 if (!flt_argreg_array
[argreg
+ 1])
987 flt_argreg_array
[argreg
] = 1;
988 return FLOAT_ARG0_REGNUM
+ argreg
;
991 /* Helper function which figures out, if a type is treated like a float type.
993 The FPU ABIs have a special way how to treat types as float types.
994 Structures with exactly one member, which is of type float or double, are
995 treated exactly as the base types float or double:
1005 are handled the same way as just
1011 As a result, arguments of these struct types are pushed into floating point
1012 registers exactly as floats or doubles, using the same decision algorithm.
1014 The same is valid if these types are used as function return types. The
1015 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
1016 or even using struct convention as it is for other structs. */
1019 sh_treat_as_flt_p (struct type
*type
)
1021 int len
= TYPE_LENGTH (type
);
1023 /* Ordinary float types are obviously treated as float. */
1024 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1026 /* Otherwise non-struct types are not treated as float. */
1027 if (TYPE_CODE (type
) != TYPE_CODE_STRUCT
)
1029 /* Otherwise structs with more than one memeber are not treated as float. */
1030 if (TYPE_NFIELDS (type
) != 1)
1032 /* Otherwise if the type of that member is float, the whole type is
1033 treated as float. */
1034 if (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0)) == TYPE_CODE_FLT
)
1036 /* Otherwise it's not treated as float. */
1041 sh_push_dummy_call_fpu (struct gdbarch
*gdbarch
,
1042 struct value
*function
,
1043 struct regcache
*regcache
,
1044 CORE_ADDR bp_addr
, int nargs
,
1045 struct value
**args
,
1046 CORE_ADDR sp
, int struct_return
,
1047 CORE_ADDR struct_addr
)
1049 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1050 int stack_offset
= 0;
1051 int argreg
= ARG0_REGNUM
;
1054 struct type
*func_type
= value_type (function
);
1058 int len
, reg_size
= 0;
1059 int pass_on_stack
= 0;
1061 int last_reg_arg
= INT_MAX
;
1063 /* The Renesas ABI expects all varargs arguments, plus the last
1064 non-vararg argument to be on the stack, no matter how many
1065 registers have been used so far. */
1066 if (sh_is_renesas_calling_convention (func_type
)
1067 && TYPE_VARARGS (func_type
))
1068 last_reg_arg
= TYPE_NFIELDS (func_type
) - 2;
1070 /* First force sp to a 4-byte alignment. */
1071 sp
= sh_frame_align (gdbarch
, sp
);
1073 /* Make room on stack for args. */
1074 sp
-= sh_stack_allocsize (nargs
, args
);
1076 /* Initialize float argument mechanism. */
1077 sh_init_flt_argreg ();
1079 /* Now load as many as possible of the first arguments into
1080 registers, and push the rest onto the stack. There are 16 bytes
1081 in four registers available. Loop thru args from first to last. */
1082 for (argnum
= 0; argnum
< nargs
; argnum
++)
1084 type
= value_type (args
[argnum
]);
1085 len
= TYPE_LENGTH (type
);
1086 val
= sh_justify_value_in_reg (gdbarch
, args
[argnum
], len
);
1088 /* Some decisions have to be made how various types are handled.
1089 This also differs in different ABIs. */
1092 /* Find out the next register to use for a floating point value. */
1093 treat_as_flt
= sh_treat_as_flt_p (type
);
1095 flt_argreg
= sh_next_flt_argreg (gdbarch
, len
, func_type
);
1096 /* In Renesas ABI, long longs and aggregate types are always passed
1098 else if (sh_is_renesas_calling_convention (func_type
)
1099 && ((TYPE_CODE (type
) == TYPE_CODE_INT
&& len
== 8)
1100 || TYPE_CODE (type
) == TYPE_CODE_STRUCT
1101 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
1103 /* In contrast to non-FPU CPUs, arguments are never split between
1104 registers and stack. If an argument doesn't fit in the remaining
1105 registers it's always pushed entirely on the stack. */
1106 else if (len
> ((ARGLAST_REGNUM
- argreg
+ 1) * 4))
1111 if ((treat_as_flt
&& flt_argreg
> FLOAT_ARGLAST_REGNUM
)
1112 || (!treat_as_flt
&& (argreg
> ARGLAST_REGNUM
1114 || argnum
> last_reg_arg
)
1116 /* The data goes entirely on the stack, 4-byte aligned. */
1117 reg_size
= (len
+ 3) & ~3;
1118 write_memory (sp
+ stack_offset
, val
, reg_size
);
1119 stack_offset
+= reg_size
;
1121 else if (treat_as_flt
&& flt_argreg
<= FLOAT_ARGLAST_REGNUM
)
1123 /* Argument goes in a float argument register. */
1124 reg_size
= register_size (gdbarch
, flt_argreg
);
1125 regval
= extract_unsigned_integer (val
, reg_size
, byte_order
);
1126 /* In little endian mode, float types taking two registers
1127 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1128 be stored swapped in the argument registers. The below
1129 code first writes the first 32 bits in the next but one
1130 register, increments the val and len values accordingly
1131 and then proceeds as normal by writing the second 32 bits
1132 into the next register. */
1133 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
1134 && TYPE_LENGTH (type
) == 2 * reg_size
)
1136 regcache_cooked_write_unsigned (regcache
, flt_argreg
+ 1,
1140 regval
= extract_unsigned_integer (val
, reg_size
,
1143 regcache_cooked_write_unsigned (regcache
, flt_argreg
++, regval
);
1145 else if (!treat_as_flt
&& argreg
<= ARGLAST_REGNUM
)
1147 /* there's room in a register */
1148 reg_size
= register_size (gdbarch
, argreg
);
1149 regval
= extract_unsigned_integer (val
, reg_size
, byte_order
);
1150 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
1152 /* Store the value one register at a time or in one step on
1161 if (sh_is_renesas_calling_convention (func_type
))
1162 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1163 the stack and store the struct return address there. */
1164 write_memory_unsigned_integer (sp
-= 4, 4, byte_order
, struct_addr
);
1166 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1167 its own dedicated register. */
1168 regcache_cooked_write_unsigned (regcache
,
1169 STRUCT_RETURN_REGNUM
, struct_addr
);
1172 /* Store return address. */
1173 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1175 /* Update stack pointer. */
1176 regcache_cooked_write_unsigned (regcache
,
1177 gdbarch_sp_regnum (gdbarch
), sp
);
1183 sh_push_dummy_call_nofpu (struct gdbarch
*gdbarch
,
1184 struct value
*function
,
1185 struct regcache
*regcache
,
1187 int nargs
, struct value
**args
,
1188 CORE_ADDR sp
, int struct_return
,
1189 CORE_ADDR struct_addr
)
1191 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1192 int stack_offset
= 0;
1193 int argreg
= ARG0_REGNUM
;
1195 struct type
*func_type
= value_type (function
);
1199 int len
, reg_size
= 0;
1200 int pass_on_stack
= 0;
1201 int last_reg_arg
= INT_MAX
;
1203 /* The Renesas ABI expects all varargs arguments, plus the last
1204 non-vararg argument to be on the stack, no matter how many
1205 registers have been used so far. */
1206 if (sh_is_renesas_calling_convention (func_type
)
1207 && TYPE_VARARGS (func_type
))
1208 last_reg_arg
= TYPE_NFIELDS (func_type
) - 2;
1210 /* First force sp to a 4-byte alignment. */
1211 sp
= sh_frame_align (gdbarch
, sp
);
1213 /* Make room on stack for args. */
1214 sp
-= sh_stack_allocsize (nargs
, args
);
1216 /* Now load as many as possible of the first arguments into
1217 registers, and push the rest onto the stack. There are 16 bytes
1218 in four registers available. Loop thru args from first to last. */
1219 for (argnum
= 0; argnum
< nargs
; argnum
++)
1221 type
= value_type (args
[argnum
]);
1222 len
= TYPE_LENGTH (type
);
1223 val
= sh_justify_value_in_reg (gdbarch
, args
[argnum
], len
);
1225 /* Some decisions have to be made how various types are handled.
1226 This also differs in different ABIs. */
1228 /* Renesas ABI pushes doubles and long longs entirely on stack.
1229 Same goes for aggregate types. */
1230 if (sh_is_renesas_calling_convention (func_type
)
1231 && ((TYPE_CODE (type
) == TYPE_CODE_INT
&& len
>= 8)
1232 || (TYPE_CODE (type
) == TYPE_CODE_FLT
&& len
>= 8)
1233 || TYPE_CODE (type
) == TYPE_CODE_STRUCT
1234 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
1238 if (argreg
> ARGLAST_REGNUM
|| pass_on_stack
1239 || argnum
> last_reg_arg
)
1241 /* The remainder of the data goes entirely on the stack,
1243 reg_size
= (len
+ 3) & ~3;
1244 write_memory (sp
+ stack_offset
, val
, reg_size
);
1245 stack_offset
+= reg_size
;
1247 else if (argreg
<= ARGLAST_REGNUM
)
1249 /* There's room in a register. */
1250 reg_size
= register_size (gdbarch
, argreg
);
1251 regval
= extract_unsigned_integer (val
, reg_size
, byte_order
);
1252 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
1254 /* Store the value reg_size bytes at a time. This means that things
1255 larger than reg_size bytes may go partly in registers and partly
1264 if (sh_is_renesas_calling_convention (func_type
))
1265 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1266 the stack and store the struct return address there. */
1267 write_memory_unsigned_integer (sp
-= 4, 4, byte_order
, struct_addr
);
1269 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1270 its own dedicated register. */
1271 regcache_cooked_write_unsigned (regcache
,
1272 STRUCT_RETURN_REGNUM
, struct_addr
);
1275 /* Store return address. */
1276 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1278 /* Update stack pointer. */
1279 regcache_cooked_write_unsigned (regcache
,
1280 gdbarch_sp_regnum (gdbarch
), sp
);
1285 /* Find a function's return value in the appropriate registers (in
1286 regbuf), and copy it into valbuf. Extract from an array REGBUF
1287 containing the (raw) register state a function return value of type
1288 TYPE, and copy that, in virtual format, into VALBUF. */
1290 sh_extract_return_value_nofpu (struct type
*type
, struct regcache
*regcache
,
1293 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1294 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1295 int len
= TYPE_LENGTH (type
);
1296 int return_register
= R0_REGNUM
;
1303 regcache_cooked_read_unsigned (regcache
, R0_REGNUM
, &c
);
1304 store_unsigned_integer (valbuf
, len
, byte_order
, c
);
1308 int i
, regnum
= R0_REGNUM
;
1309 for (i
= 0; i
< len
; i
+= 4)
1310 regcache_raw_read (regcache
, regnum
++, (char *) valbuf
+ i
);
1313 error (_("bad size for return value"));
1317 sh_extract_return_value_fpu (struct type
*type
, struct regcache
*regcache
,
1320 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1321 if (sh_treat_as_flt_p (type
))
1323 int len
= TYPE_LENGTH (type
);
1324 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1325 for (i
= 0; i
< len
; i
+= 4)
1326 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1327 regcache_raw_read (regcache
, regnum
++,
1328 (char *) valbuf
+ len
- 4 - i
);
1330 regcache_raw_read (regcache
, regnum
++, (char *) valbuf
+ i
);
1333 sh_extract_return_value_nofpu (type
, regcache
, valbuf
);
1336 /* Write into appropriate registers a function return value
1337 of type TYPE, given in virtual format.
1338 If the architecture is sh4 or sh3e, store a function's return value
1339 in the R0 general register or in the FP0 floating point register,
1340 depending on the type of the return value. In all the other cases
1341 the result is stored in r0, left-justified. */
1343 sh_store_return_value_nofpu (struct type
*type
, struct regcache
*regcache
,
1346 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1347 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1349 int len
= TYPE_LENGTH (type
);
1353 val
= extract_unsigned_integer (valbuf
, len
, byte_order
);
1354 regcache_cooked_write_unsigned (regcache
, R0_REGNUM
, val
);
1358 int i
, regnum
= R0_REGNUM
;
1359 for (i
= 0; i
< len
; i
+= 4)
1360 regcache_raw_write (regcache
, regnum
++, (char *) valbuf
+ i
);
1365 sh_store_return_value_fpu (struct type
*type
, struct regcache
*regcache
,
1368 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1369 if (sh_treat_as_flt_p (type
))
1371 int len
= TYPE_LENGTH (type
);
1372 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1373 for (i
= 0; i
< len
; i
+= 4)
1374 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1375 regcache_raw_write (regcache
, regnum
++,
1376 (char *) valbuf
+ len
- 4 - i
);
1378 regcache_raw_write (regcache
, regnum
++, (char *) valbuf
+ i
);
1381 sh_store_return_value_nofpu (type
, regcache
, valbuf
);
1384 static enum return_value_convention
1385 sh_return_value_nofpu (struct gdbarch
*gdbarch
, struct type
*func_type
,
1386 struct type
*type
, struct regcache
*regcache
,
1387 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1389 if (sh_use_struct_convention_nofpu (
1390 sh_is_renesas_calling_convention (func_type
), type
))
1391 return RETURN_VALUE_STRUCT_CONVENTION
;
1393 sh_store_return_value_nofpu (type
, regcache
, writebuf
);
1395 sh_extract_return_value_nofpu (type
, regcache
, readbuf
);
1396 return RETURN_VALUE_REGISTER_CONVENTION
;
1399 static enum return_value_convention
1400 sh_return_value_fpu (struct gdbarch
*gdbarch
, struct type
*func_type
,
1401 struct type
*type
, struct regcache
*regcache
,
1402 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1404 if (sh_use_struct_convention (
1405 sh_is_renesas_calling_convention (func_type
), type
))
1406 return RETURN_VALUE_STRUCT_CONVENTION
;
1408 sh_store_return_value_fpu (type
, regcache
, writebuf
);
1410 sh_extract_return_value_fpu (type
, regcache
, readbuf
);
1411 return RETURN_VALUE_REGISTER_CONVENTION
;
1414 /* Print the registers in a form similar to the E7000. */
1417 sh_generic_show_regs (struct frame_info
*frame
)
1420 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1421 phex (get_frame_register_unsigned (frame
,
1423 (get_frame_arch (frame
))), 4),
1424 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1425 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1426 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1429 (" GBR %08lx VBR %08lx MACL %08lx\n",
1430 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1431 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1432 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1435 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1436 (long) get_frame_register_unsigned (frame
, 0),
1437 (long) get_frame_register_unsigned (frame
, 1),
1438 (long) get_frame_register_unsigned (frame
, 2),
1439 (long) get_frame_register_unsigned (frame
, 3),
1440 (long) get_frame_register_unsigned (frame
, 4),
1441 (long) get_frame_register_unsigned (frame
, 5),
1442 (long) get_frame_register_unsigned (frame
, 6),
1443 (long) get_frame_register_unsigned (frame
, 7));
1445 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1446 (long) get_frame_register_unsigned (frame
, 8),
1447 (long) get_frame_register_unsigned (frame
, 9),
1448 (long) get_frame_register_unsigned (frame
, 10),
1449 (long) get_frame_register_unsigned (frame
, 11),
1450 (long) get_frame_register_unsigned (frame
, 12),
1451 (long) get_frame_register_unsigned (frame
, 13),
1452 (long) get_frame_register_unsigned (frame
, 14),
1453 (long) get_frame_register_unsigned (frame
, 15));
1457 sh3_show_regs (struct frame_info
*frame
)
1460 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1461 phex (get_frame_register_unsigned (frame
,
1463 (get_frame_arch (frame
))), 4),
1464 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1465 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1466 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1469 (" GBR %08lx VBR %08lx MACL %08lx\n",
1470 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1471 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1472 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1474 (" SSR %08lx SPC %08lx\n",
1475 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1476 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
));
1479 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1480 (long) get_frame_register_unsigned (frame
, 0),
1481 (long) get_frame_register_unsigned (frame
, 1),
1482 (long) get_frame_register_unsigned (frame
, 2),
1483 (long) get_frame_register_unsigned (frame
, 3),
1484 (long) get_frame_register_unsigned (frame
, 4),
1485 (long) get_frame_register_unsigned (frame
, 5),
1486 (long) get_frame_register_unsigned (frame
, 6),
1487 (long) get_frame_register_unsigned (frame
, 7));
1489 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1490 (long) get_frame_register_unsigned (frame
, 8),
1491 (long) get_frame_register_unsigned (frame
, 9),
1492 (long) get_frame_register_unsigned (frame
, 10),
1493 (long) get_frame_register_unsigned (frame
, 11),
1494 (long) get_frame_register_unsigned (frame
, 12),
1495 (long) get_frame_register_unsigned (frame
, 13),
1496 (long) get_frame_register_unsigned (frame
, 14),
1497 (long) get_frame_register_unsigned (frame
, 15));
1501 sh2e_show_regs (struct frame_info
*frame
)
1503 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1505 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1506 phex (get_frame_register_unsigned (frame
,
1507 gdbarch_pc_regnum (gdbarch
)), 4),
1508 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1509 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1510 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1513 (" GBR %08lx VBR %08lx MACL %08lx\n",
1514 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1515 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1516 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1518 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1519 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1520 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1521 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
1522 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1525 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1526 (long) get_frame_register_unsigned (frame
, 0),
1527 (long) get_frame_register_unsigned (frame
, 1),
1528 (long) get_frame_register_unsigned (frame
, 2),
1529 (long) get_frame_register_unsigned (frame
, 3),
1530 (long) get_frame_register_unsigned (frame
, 4),
1531 (long) get_frame_register_unsigned (frame
, 5),
1532 (long) get_frame_register_unsigned (frame
, 6),
1533 (long) get_frame_register_unsigned (frame
, 7));
1535 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1536 (long) get_frame_register_unsigned (frame
, 8),
1537 (long) get_frame_register_unsigned (frame
, 9),
1538 (long) get_frame_register_unsigned (frame
, 10),
1539 (long) get_frame_register_unsigned (frame
, 11),
1540 (long) get_frame_register_unsigned (frame
, 12),
1541 (long) get_frame_register_unsigned (frame
, 13),
1542 (long) get_frame_register_unsigned (frame
, 14),
1543 (long) get_frame_register_unsigned (frame
, 15));
1546 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1547 (long) get_frame_register_unsigned
1548 (frame
, gdbarch_fp0_regnum (gdbarch
) + 0),
1549 (long) get_frame_register_unsigned
1550 (frame
, gdbarch_fp0_regnum (gdbarch
) + 1),
1551 (long) get_frame_register_unsigned
1552 (frame
, gdbarch_fp0_regnum (gdbarch
) + 2),
1553 (long) get_frame_register_unsigned
1554 (frame
, gdbarch_fp0_regnum (gdbarch
) + 3),
1555 (long) get_frame_register_unsigned
1556 (frame
, gdbarch_fp0_regnum (gdbarch
) + 4),
1557 (long) get_frame_register_unsigned
1558 (frame
, gdbarch_fp0_regnum (gdbarch
) + 5),
1559 (long) get_frame_register_unsigned
1560 (frame
, gdbarch_fp0_regnum (gdbarch
) + 6),
1561 (long) get_frame_register_unsigned
1562 (frame
, gdbarch_fp0_regnum (gdbarch
) + 7));
1564 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1565 (long) get_frame_register_unsigned
1566 (frame
, gdbarch_fp0_regnum (gdbarch
) + 8),
1567 (long) get_frame_register_unsigned
1568 (frame
, gdbarch_fp0_regnum (gdbarch
) + 9),
1569 (long) get_frame_register_unsigned
1570 (frame
, gdbarch_fp0_regnum (gdbarch
) + 10),
1571 (long) get_frame_register_unsigned
1572 (frame
, gdbarch_fp0_regnum (gdbarch
) + 11),
1573 (long) get_frame_register_unsigned
1574 (frame
, gdbarch_fp0_regnum (gdbarch
) + 12),
1575 (long) get_frame_register_unsigned
1576 (frame
, gdbarch_fp0_regnum (gdbarch
) + 13),
1577 (long) get_frame_register_unsigned
1578 (frame
, gdbarch_fp0_regnum (gdbarch
) + 14),
1579 (long) get_frame_register_unsigned
1580 (frame
, gdbarch_fp0_regnum (gdbarch
) + 15));
1584 sh2a_show_regs (struct frame_info
*frame
)
1586 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1587 int pr
= get_frame_register_unsigned (frame
, FPSCR_REGNUM
) & 0x80000;
1590 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1591 phex (get_frame_register_unsigned (frame
,
1592 gdbarch_pc_regnum (gdbarch
)), 4),
1593 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1594 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1595 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1598 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1599 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1600 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1601 (long) get_frame_register_unsigned (frame
, TBR_REGNUM
),
1602 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1604 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1605 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1606 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1607 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
1608 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1611 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1612 (long) get_frame_register_unsigned (frame
, 0),
1613 (long) get_frame_register_unsigned (frame
, 1),
1614 (long) get_frame_register_unsigned (frame
, 2),
1615 (long) get_frame_register_unsigned (frame
, 3),
1616 (long) get_frame_register_unsigned (frame
, 4),
1617 (long) get_frame_register_unsigned (frame
, 5),
1618 (long) get_frame_register_unsigned (frame
, 6),
1619 (long) get_frame_register_unsigned (frame
, 7));
1621 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1622 (long) get_frame_register_unsigned (frame
, 8),
1623 (long) get_frame_register_unsigned (frame
, 9),
1624 (long) get_frame_register_unsigned (frame
, 10),
1625 (long) get_frame_register_unsigned (frame
, 11),
1626 (long) get_frame_register_unsigned (frame
, 12),
1627 (long) get_frame_register_unsigned (frame
, 13),
1628 (long) get_frame_register_unsigned (frame
, 14),
1629 (long) get_frame_register_unsigned (frame
, 15));
1632 (pr
? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1633 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1634 (long) get_frame_register_unsigned
1635 (frame
, gdbarch_fp0_regnum (gdbarch
) + 0),
1636 (long) get_frame_register_unsigned
1637 (frame
, gdbarch_fp0_regnum (gdbarch
) + 1),
1638 (long) get_frame_register_unsigned
1639 (frame
, gdbarch_fp0_regnum (gdbarch
) + 2),
1640 (long) get_frame_register_unsigned
1641 (frame
, gdbarch_fp0_regnum (gdbarch
) + 3),
1642 (long) get_frame_register_unsigned
1643 (frame
, gdbarch_fp0_regnum (gdbarch
) + 4),
1644 (long) get_frame_register_unsigned
1645 (frame
, gdbarch_fp0_regnum (gdbarch
) + 5),
1646 (long) get_frame_register_unsigned
1647 (frame
, gdbarch_fp0_regnum (gdbarch
) + 6),
1648 (long) get_frame_register_unsigned
1649 (frame
, gdbarch_fp0_regnum (gdbarch
) + 7));
1651 (pr
? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1652 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1653 (long) get_frame_register_unsigned
1654 (frame
, gdbarch_fp0_regnum (gdbarch
) + 8),
1655 (long) get_frame_register_unsigned
1656 (frame
, gdbarch_fp0_regnum (gdbarch
) + 9),
1657 (long) get_frame_register_unsigned
1658 (frame
, gdbarch_fp0_regnum (gdbarch
) + 10),
1659 (long) get_frame_register_unsigned
1660 (frame
, gdbarch_fp0_regnum (gdbarch
) + 11),
1661 (long) get_frame_register_unsigned
1662 (frame
, gdbarch_fp0_regnum (gdbarch
) + 12),
1663 (long) get_frame_register_unsigned
1664 (frame
, gdbarch_fp0_regnum (gdbarch
) + 13),
1665 (long) get_frame_register_unsigned
1666 (frame
, gdbarch_fp0_regnum (gdbarch
) + 14),
1667 (long) get_frame_register_unsigned
1668 (frame
, gdbarch_fp0_regnum (gdbarch
) + 15));
1670 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame
, BANK_REGNUM
));
1672 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1673 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 0),
1674 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 1),
1675 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 2),
1676 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 3),
1677 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 4),
1678 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 5),
1679 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 6),
1680 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 7));
1682 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1683 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 8),
1684 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 9),
1685 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 10),
1686 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 11),
1687 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 12),
1688 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 13),
1689 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 14));
1691 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1692 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 15),
1693 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 16),
1694 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 17),
1695 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 18),
1696 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 19));
1700 sh2a_nofpu_show_regs (struct frame_info
*frame
)
1702 int pr
= get_frame_register_unsigned (frame
, FPSCR_REGNUM
) & 0x80000;
1705 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1706 phex (get_frame_register_unsigned (frame
,
1708 (get_frame_arch (frame
))), 4),
1709 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1710 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1711 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1714 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1715 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1716 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1717 (long) get_frame_register_unsigned (frame
, TBR_REGNUM
),
1718 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1720 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1721 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1722 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1723 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
1724 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1727 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1728 (long) get_frame_register_unsigned (frame
, 0),
1729 (long) get_frame_register_unsigned (frame
, 1),
1730 (long) get_frame_register_unsigned (frame
, 2),
1731 (long) get_frame_register_unsigned (frame
, 3),
1732 (long) get_frame_register_unsigned (frame
, 4),
1733 (long) get_frame_register_unsigned (frame
, 5),
1734 (long) get_frame_register_unsigned (frame
, 6),
1735 (long) get_frame_register_unsigned (frame
, 7));
1737 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1738 (long) get_frame_register_unsigned (frame
, 8),
1739 (long) get_frame_register_unsigned (frame
, 9),
1740 (long) get_frame_register_unsigned (frame
, 10),
1741 (long) get_frame_register_unsigned (frame
, 11),
1742 (long) get_frame_register_unsigned (frame
, 12),
1743 (long) get_frame_register_unsigned (frame
, 13),
1744 (long) get_frame_register_unsigned (frame
, 14),
1745 (long) get_frame_register_unsigned (frame
, 15));
1748 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame
, BANK_REGNUM
));
1750 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1751 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 0),
1752 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 1),
1753 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 2),
1754 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 3),
1755 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 4),
1756 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 5),
1757 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 6),
1758 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 7));
1760 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1761 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 8),
1762 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 9),
1763 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 10),
1764 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 11),
1765 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 12),
1766 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 13),
1767 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 14));
1769 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1770 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 15),
1771 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 16),
1772 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 17),
1773 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 18),
1774 (long) get_frame_register_unsigned (frame
, R0_BANK0_REGNUM
+ 19));
1778 sh3e_show_regs (struct frame_info
*frame
)
1780 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1782 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1783 phex (get_frame_register_unsigned (frame
,
1784 gdbarch_pc_regnum (gdbarch
)), 4),
1785 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1786 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1787 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1790 (" GBR %08lx VBR %08lx MACL %08lx\n",
1791 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1792 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1793 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1795 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1796 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1797 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1798 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
1799 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1802 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1803 (long) get_frame_register_unsigned (frame
, 0),
1804 (long) get_frame_register_unsigned (frame
, 1),
1805 (long) get_frame_register_unsigned (frame
, 2),
1806 (long) get_frame_register_unsigned (frame
, 3),
1807 (long) get_frame_register_unsigned (frame
, 4),
1808 (long) get_frame_register_unsigned (frame
, 5),
1809 (long) get_frame_register_unsigned (frame
, 6),
1810 (long) get_frame_register_unsigned (frame
, 7));
1812 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1813 (long) get_frame_register_unsigned (frame
, 8),
1814 (long) get_frame_register_unsigned (frame
, 9),
1815 (long) get_frame_register_unsigned (frame
, 10),
1816 (long) get_frame_register_unsigned (frame
, 11),
1817 (long) get_frame_register_unsigned (frame
, 12),
1818 (long) get_frame_register_unsigned (frame
, 13),
1819 (long) get_frame_register_unsigned (frame
, 14),
1820 (long) get_frame_register_unsigned (frame
, 15));
1823 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1824 (long) get_frame_register_unsigned
1825 (frame
, gdbarch_fp0_regnum (gdbarch
) + 0),
1826 (long) get_frame_register_unsigned
1827 (frame
, gdbarch_fp0_regnum (gdbarch
) + 1),
1828 (long) get_frame_register_unsigned
1829 (frame
, gdbarch_fp0_regnum (gdbarch
) + 2),
1830 (long) get_frame_register_unsigned
1831 (frame
, gdbarch_fp0_regnum (gdbarch
) + 3),
1832 (long) get_frame_register_unsigned
1833 (frame
, gdbarch_fp0_regnum (gdbarch
) + 4),
1834 (long) get_frame_register_unsigned
1835 (frame
, gdbarch_fp0_regnum (gdbarch
) + 5),
1836 (long) get_frame_register_unsigned
1837 (frame
, gdbarch_fp0_regnum (gdbarch
) + 6),
1838 (long) get_frame_register_unsigned
1839 (frame
, gdbarch_fp0_regnum (gdbarch
) + 7));
1841 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1842 (long) get_frame_register_unsigned
1843 (frame
, gdbarch_fp0_regnum (gdbarch
) + 8),
1844 (long) get_frame_register_unsigned
1845 (frame
, gdbarch_fp0_regnum (gdbarch
) + 9),
1846 (long) get_frame_register_unsigned
1847 (frame
, gdbarch_fp0_regnum (gdbarch
) + 10),
1848 (long) get_frame_register_unsigned
1849 (frame
, gdbarch_fp0_regnum (gdbarch
) + 11),
1850 (long) get_frame_register_unsigned
1851 (frame
, gdbarch_fp0_regnum (gdbarch
) + 12),
1852 (long) get_frame_register_unsigned
1853 (frame
, gdbarch_fp0_regnum (gdbarch
) + 13),
1854 (long) get_frame_register_unsigned
1855 (frame
, gdbarch_fp0_regnum (gdbarch
) + 14),
1856 (long) get_frame_register_unsigned
1857 (frame
, gdbarch_fp0_regnum (gdbarch
) + 15));
1861 sh3_dsp_show_regs (struct frame_info
*frame
)
1864 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1865 phex (get_frame_register_unsigned (frame
,
1867 (get_frame_arch (frame
))), 4),
1868 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1869 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1870 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1873 (" GBR %08lx VBR %08lx MACL %08lx\n",
1874 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1875 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1876 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1879 (" SSR %08lx SPC %08lx DSR %08lx\n",
1880 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1881 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1882 (long) get_frame_register_unsigned (frame
, DSR_REGNUM
));
1885 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1886 (long) get_frame_register_unsigned (frame
, 0),
1887 (long) get_frame_register_unsigned (frame
, 1),
1888 (long) get_frame_register_unsigned (frame
, 2),
1889 (long) get_frame_register_unsigned (frame
, 3),
1890 (long) get_frame_register_unsigned (frame
, 4),
1891 (long) get_frame_register_unsigned (frame
, 5),
1892 (long) get_frame_register_unsigned (frame
, 6),
1893 (long) get_frame_register_unsigned (frame
, 7));
1895 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1896 (long) get_frame_register_unsigned (frame
, 8),
1897 (long) get_frame_register_unsigned (frame
, 9),
1898 (long) get_frame_register_unsigned (frame
, 10),
1899 (long) get_frame_register_unsigned (frame
, 11),
1900 (long) get_frame_register_unsigned (frame
, 12),
1901 (long) get_frame_register_unsigned (frame
, 13),
1902 (long) get_frame_register_unsigned (frame
, 14),
1903 (long) get_frame_register_unsigned (frame
, 15));
1906 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1907 (long) get_frame_register_unsigned (frame
, A0G_REGNUM
) & 0xff,
1908 (long) get_frame_register_unsigned (frame
, A0_REGNUM
),
1909 (long) get_frame_register_unsigned (frame
, M0_REGNUM
),
1910 (long) get_frame_register_unsigned (frame
, X0_REGNUM
),
1911 (long) get_frame_register_unsigned (frame
, Y0_REGNUM
),
1912 (long) get_frame_register_unsigned (frame
, RS_REGNUM
),
1913 (long) get_frame_register_unsigned (frame
, MOD_REGNUM
));
1915 ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1916 (long) get_frame_register_unsigned (frame
, A1G_REGNUM
) & 0xff,
1917 (long) get_frame_register_unsigned (frame
, A1_REGNUM
),
1918 (long) get_frame_register_unsigned (frame
, M1_REGNUM
),
1919 (long) get_frame_register_unsigned (frame
, X1_REGNUM
),
1920 (long) get_frame_register_unsigned (frame
, Y1_REGNUM
),
1921 (long) get_frame_register_unsigned (frame
, RE_REGNUM
));
1925 sh4_show_regs (struct frame_info
*frame
)
1927 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1928 int pr
= get_frame_register_unsigned (frame
, FPSCR_REGNUM
) & 0x80000;
1931 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1932 phex (get_frame_register_unsigned (frame
,
1933 gdbarch_pc_regnum (gdbarch
)), 4),
1934 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
1935 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
1936 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
1939 (" GBR %08lx VBR %08lx MACL %08lx\n",
1940 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
1941 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
1942 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
1944 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1945 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
1946 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
1947 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
1948 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
1951 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1952 (long) get_frame_register_unsigned (frame
, 0),
1953 (long) get_frame_register_unsigned (frame
, 1),
1954 (long) get_frame_register_unsigned (frame
, 2),
1955 (long) get_frame_register_unsigned (frame
, 3),
1956 (long) get_frame_register_unsigned (frame
, 4),
1957 (long) get_frame_register_unsigned (frame
, 5),
1958 (long) get_frame_register_unsigned (frame
, 6),
1959 (long) get_frame_register_unsigned (frame
, 7));
1961 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1962 (long) get_frame_register_unsigned (frame
, 8),
1963 (long) get_frame_register_unsigned (frame
, 9),
1964 (long) get_frame_register_unsigned (frame
, 10),
1965 (long) get_frame_register_unsigned (frame
, 11),
1966 (long) get_frame_register_unsigned (frame
, 12),
1967 (long) get_frame_register_unsigned (frame
, 13),
1968 (long) get_frame_register_unsigned (frame
, 14),
1969 (long) get_frame_register_unsigned (frame
, 15));
1972 (pr
? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1973 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1974 (long) get_frame_register_unsigned
1975 (frame
, gdbarch_fp0_regnum (gdbarch
) + 0),
1976 (long) get_frame_register_unsigned
1977 (frame
, gdbarch_fp0_regnum (gdbarch
) + 1),
1978 (long) get_frame_register_unsigned
1979 (frame
, gdbarch_fp0_regnum (gdbarch
) + 2),
1980 (long) get_frame_register_unsigned
1981 (frame
, gdbarch_fp0_regnum (gdbarch
) + 3),
1982 (long) get_frame_register_unsigned
1983 (frame
, gdbarch_fp0_regnum (gdbarch
) + 4),
1984 (long) get_frame_register_unsigned
1985 (frame
, gdbarch_fp0_regnum (gdbarch
) + 5),
1986 (long) get_frame_register_unsigned
1987 (frame
, gdbarch_fp0_regnum (gdbarch
) + 6),
1988 (long) get_frame_register_unsigned
1989 (frame
, gdbarch_fp0_regnum (gdbarch
) + 7));
1991 (pr
? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1992 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1993 (long) get_frame_register_unsigned
1994 (frame
, gdbarch_fp0_regnum (gdbarch
) + 8),
1995 (long) get_frame_register_unsigned
1996 (frame
, gdbarch_fp0_regnum (gdbarch
) + 9),
1997 (long) get_frame_register_unsigned
1998 (frame
, gdbarch_fp0_regnum (gdbarch
) + 10),
1999 (long) get_frame_register_unsigned
2000 (frame
, gdbarch_fp0_regnum (gdbarch
) + 11),
2001 (long) get_frame_register_unsigned
2002 (frame
, gdbarch_fp0_regnum (gdbarch
) + 12),
2003 (long) get_frame_register_unsigned
2004 (frame
, gdbarch_fp0_regnum (gdbarch
) + 13),
2005 (long) get_frame_register_unsigned
2006 (frame
, gdbarch_fp0_regnum (gdbarch
) + 14),
2007 (long) get_frame_register_unsigned
2008 (frame
, gdbarch_fp0_regnum (gdbarch
) + 15));
2012 sh4_nofpu_show_regs (struct frame_info
*frame
)
2015 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
2016 phex (get_frame_register_unsigned (frame
,
2018 (get_frame_arch (frame
))), 4),
2019 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
2020 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
2021 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
2024 (" GBR %08lx VBR %08lx MACL %08lx\n",
2025 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
2026 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
2027 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
2029 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
2030 (long) get_frame_register_unsigned (frame
, SSR_REGNUM
),
2031 (long) get_frame_register_unsigned (frame
, SPC_REGNUM
),
2032 (long) get_frame_register_unsigned (frame
, FPUL_REGNUM
),
2033 (long) get_frame_register_unsigned (frame
, FPSCR_REGNUM
));
2036 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2037 (long) get_frame_register_unsigned (frame
, 0),
2038 (long) get_frame_register_unsigned (frame
, 1),
2039 (long) get_frame_register_unsigned (frame
, 2),
2040 (long) get_frame_register_unsigned (frame
, 3),
2041 (long) get_frame_register_unsigned (frame
, 4),
2042 (long) get_frame_register_unsigned (frame
, 5),
2043 (long) get_frame_register_unsigned (frame
, 6),
2044 (long) get_frame_register_unsigned (frame
, 7));
2046 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2047 (long) get_frame_register_unsigned (frame
, 8),
2048 (long) get_frame_register_unsigned (frame
, 9),
2049 (long) get_frame_register_unsigned (frame
, 10),
2050 (long) get_frame_register_unsigned (frame
, 11),
2051 (long) get_frame_register_unsigned (frame
, 12),
2052 (long) get_frame_register_unsigned (frame
, 13),
2053 (long) get_frame_register_unsigned (frame
, 14),
2054 (long) get_frame_register_unsigned (frame
, 15));
2058 sh_dsp_show_regs (struct frame_info
*frame
)
2061 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
2062 phex (get_frame_register_unsigned (frame
,
2064 (get_frame_arch (frame
))), 4),
2065 (long) get_frame_register_unsigned (frame
, SR_REGNUM
),
2066 (long) get_frame_register_unsigned (frame
, PR_REGNUM
),
2067 (long) get_frame_register_unsigned (frame
, MACH_REGNUM
));
2070 (" GBR %08lx VBR %08lx DSR %08lx MACL %08lx\n",
2071 (long) get_frame_register_unsigned (frame
, GBR_REGNUM
),
2072 (long) get_frame_register_unsigned (frame
, VBR_REGNUM
),
2073 (long) get_frame_register_unsigned (frame
, DSR_REGNUM
),
2074 (long) get_frame_register_unsigned (frame
, MACL_REGNUM
));
2077 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2078 (long) get_frame_register_unsigned (frame
, 0),
2079 (long) get_frame_register_unsigned (frame
, 1),
2080 (long) get_frame_register_unsigned (frame
, 2),
2081 (long) get_frame_register_unsigned (frame
, 3),
2082 (long) get_frame_register_unsigned (frame
, 4),
2083 (long) get_frame_register_unsigned (frame
, 5),
2084 (long) get_frame_register_unsigned (frame
, 6),
2085 (long) get_frame_register_unsigned (frame
, 7));
2087 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2088 (long) get_frame_register_unsigned (frame
, 8),
2089 (long) get_frame_register_unsigned (frame
, 9),
2090 (long) get_frame_register_unsigned (frame
, 10),
2091 (long) get_frame_register_unsigned (frame
, 11),
2092 (long) get_frame_register_unsigned (frame
, 12),
2093 (long) get_frame_register_unsigned (frame
, 13),
2094 (long) get_frame_register_unsigned (frame
, 14),
2095 (long) get_frame_register_unsigned (frame
, 15));
2098 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2099 (long) get_frame_register_unsigned (frame
, A0G_REGNUM
) & 0xff,
2100 (long) get_frame_register_unsigned (frame
, A0_REGNUM
),
2101 (long) get_frame_register_unsigned (frame
, M0_REGNUM
),
2102 (long) get_frame_register_unsigned (frame
, X0_REGNUM
),
2103 (long) get_frame_register_unsigned (frame
, Y0_REGNUM
),
2104 (long) get_frame_register_unsigned (frame
, RS_REGNUM
),
2105 (long) get_frame_register_unsigned (frame
, MOD_REGNUM
));
2106 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2107 (long) get_frame_register_unsigned (frame
, A1G_REGNUM
) & 0xff,
2108 (long) get_frame_register_unsigned (frame
, A1_REGNUM
),
2109 (long) get_frame_register_unsigned (frame
, M1_REGNUM
),
2110 (long) get_frame_register_unsigned (frame
, X1_REGNUM
),
2111 (long) get_frame_register_unsigned (frame
, Y1_REGNUM
),
2112 (long) get_frame_register_unsigned (frame
, RE_REGNUM
));
2116 sh_show_regs_command (char *args
, int from_tty
)
2119 (*sh_show_regs
) (get_current_frame ());
2122 static struct type
*
2123 sh_sh2a_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
2125 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
2126 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
2127 return builtin_type (gdbarch
)->builtin_float
;
2128 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
2129 return builtin_type (gdbarch
)->builtin_double
;
2131 return builtin_type (gdbarch
)->builtin_int
;
2134 /* Return the GDB type object for the "standard" data type
2135 of data in register N. */
2136 static struct type
*
2137 sh_sh3e_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
2139 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
2140 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
2141 return builtin_type (gdbarch
)->builtin_float
;
2143 return builtin_type (gdbarch
)->builtin_int
;
2146 static struct type
*
2147 sh_sh4_build_float_register_type (struct gdbarch
*gdbarch
, int high
)
2149 return lookup_array_range_type (builtin_type (gdbarch
)->builtin_float
,
2153 static struct type
*
2154 sh_sh4_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
2156 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
2157 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
2158 return builtin_type (gdbarch
)->builtin_float
;
2159 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
2160 return builtin_type (gdbarch
)->builtin_double
;
2161 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
2162 return sh_sh4_build_float_register_type (gdbarch
, 3);
2164 return builtin_type (gdbarch
)->builtin_int
;
2167 static struct type
*
2168 sh_default_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
2170 return builtin_type (gdbarch
)->builtin_int
;
2173 /* Is a register in a reggroup?
2174 The default code in reggroup.c doesn't identify system registers, some
2175 float registers or any of the vector registers.
2176 TODO: sh2a and dsp registers. */
2178 sh_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2179 struct reggroup
*reggroup
)
2181 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
2182 || *gdbarch_register_name (gdbarch
, regnum
) == '\0')
2185 if (reggroup
== float_reggroup
2186 && (regnum
== FPUL_REGNUM
2187 || regnum
== FPSCR_REGNUM
))
2190 if (regnum
>= FV0_REGNUM
&& regnum
<= FV_LAST_REGNUM
)
2192 if (reggroup
== vector_reggroup
|| reggroup
== float_reggroup
)
2194 if (reggroup
== general_reggroup
)
2198 if (regnum
== VBR_REGNUM
2199 || regnum
== SR_REGNUM
2200 || regnum
== FPSCR_REGNUM
2201 || regnum
== SSR_REGNUM
2202 || regnum
== SPC_REGNUM
)
2204 if (reggroup
== system_reggroup
)
2206 if (reggroup
== general_reggroup
)
2210 /* The default code can cope with any other registers. */
2211 return default_register_reggroup_p (gdbarch
, regnum
, reggroup
);
2214 /* On the sh4, the DRi pseudo registers are problematic if the target
2215 is little endian. When the user writes one of those registers, for
2216 instance with 'ser var $dr0=1', we want the double to be stored
2218 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2219 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2221 This corresponds to little endian byte order & big endian word
2222 order. However if we let gdb write the register w/o conversion, it
2223 will write fr0 and fr1 this way:
2224 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2225 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2226 because it will consider fr0 and fr1 as a single LE stretch of memory.
2228 To achieve what we want we must force gdb to store things in
2229 floatformat_ieee_double_littlebyte_bigword (which is defined in
2230 include/floatformat.h and libiberty/floatformat.c.
2232 In case the target is big endian, there is no problem, the
2233 raw bytes will look like:
2234 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
2235 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2237 The other pseudo registers (the FVs) also don't pose a problem
2238 because they are stored as 4 individual FP elements. */
2241 sh_register_convert_to_virtual (int regnum
, struct type
*type
,
2242 char *from
, char *to
)
2244 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
2247 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
2249 store_typed_floating (to
, type
, val
);
2253 ("sh_register_convert_to_virtual called with non DR register number");
2257 sh_register_convert_to_raw (struct type
*type
, int regnum
,
2258 const void *from
, void *to
)
2260 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
2262 DOUBLEST val
= extract_typed_floating (from
, type
);
2263 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
,
2267 error (_("sh_register_convert_to_raw called with non DR register number"));
2270 /* For vectors of 4 floating point registers. */
2272 fv_reg_base_num (struct gdbarch
*gdbarch
, int fv_regnum
)
2276 fp_regnum
= gdbarch_fp0_regnum (gdbarch
)
2277 + (fv_regnum
- FV0_REGNUM
) * 4;
2281 /* For double precision floating point registers, i.e 2 fp regs. */
2283 dr_reg_base_num (struct gdbarch
*gdbarch
, int dr_regnum
)
2287 fp_regnum
= gdbarch_fp0_regnum (gdbarch
)
2288 + (dr_regnum
- DR0_REGNUM
) * 2;
2292 /* Concatenate PORTIONS contiguous raw registers starting at
2293 BASE_REGNUM into BUFFER. */
2295 static enum register_status
2296 pseudo_register_read_portions (struct gdbarch
*gdbarch
,
2297 struct regcache
*regcache
,
2299 int base_regnum
, gdb_byte
*buffer
)
2303 for (portion
= 0; portion
< portions
; portion
++)
2305 enum register_status status
;
2308 b
= buffer
+ register_size (gdbarch
, base_regnum
) * portion
;
2309 status
= regcache_raw_read (regcache
, base_regnum
+ portion
, b
);
2310 if (status
!= REG_VALID
)
2317 static enum register_status
2318 sh_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2319 int reg_nr
, gdb_byte
*buffer
)
2322 char temp_buffer
[MAX_REGISTER_SIZE
];
2323 enum register_status status
;
2325 if (reg_nr
== PSEUDO_BANK_REGNUM
)
2326 return regcache_raw_read (regcache
, BANK_REGNUM
, buffer
);
2327 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
2329 base_regnum
= dr_reg_base_num (gdbarch
, reg_nr
);
2331 /* Build the value in the provided buffer. */
2332 /* Read the real regs for which this one is an alias. */
2333 status
= pseudo_register_read_portions (gdbarch
, regcache
,
2334 2, base_regnum
, temp_buffer
);
2335 if (status
== REG_VALID
)
2337 /* We must pay attention to the endiannes. */
2338 sh_register_convert_to_virtual (reg_nr
,
2339 register_type (gdbarch
, reg_nr
),
2340 temp_buffer
, buffer
);
2344 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
2346 base_regnum
= fv_reg_base_num (gdbarch
, reg_nr
);
2348 /* Read the real regs for which this one is an alias. */
2349 return pseudo_register_read_portions (gdbarch
, regcache
,
2350 4, base_regnum
, buffer
);
2353 gdb_assert_not_reached ("invalid pseudo register number");
2357 sh_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2358 int reg_nr
, const gdb_byte
*buffer
)
2360 int base_regnum
, portion
;
2361 char temp_buffer
[MAX_REGISTER_SIZE
];
2363 if (reg_nr
== PSEUDO_BANK_REGNUM
)
2365 /* When the bank register is written to, the whole register bank
2366 is switched and all values in the bank registers must be read
2367 from the target/sim again. We're just invalidating the regcache
2368 so that a re-read happens next time it's necessary. */
2371 regcache_raw_write (regcache
, BANK_REGNUM
, buffer
);
2372 for (bregnum
= R0_BANK0_REGNUM
; bregnum
< MACLB_REGNUM
; ++bregnum
)
2373 regcache_invalidate (regcache
, bregnum
);
2375 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
2377 base_regnum
= dr_reg_base_num (gdbarch
, reg_nr
);
2379 /* We must pay attention to the endiannes. */
2380 sh_register_convert_to_raw (register_type (gdbarch
, reg_nr
),
2381 reg_nr
, buffer
, temp_buffer
);
2383 /* Write the real regs for which this one is an alias. */
2384 for (portion
= 0; portion
< 2; portion
++)
2385 regcache_raw_write (regcache
, base_regnum
+ portion
,
2387 + register_size (gdbarch
,
2388 base_regnum
) * portion
));
2390 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
2392 base_regnum
= fv_reg_base_num (gdbarch
, reg_nr
);
2394 /* Write the real regs for which this one is an alias. */
2395 for (portion
= 0; portion
< 4; portion
++)
2396 regcache_raw_write (regcache
, base_regnum
+ portion
,
2398 + register_size (gdbarch
,
2399 base_regnum
) * portion
));
2404 sh_dsp_register_sim_regno (struct gdbarch
*gdbarch
, int nr
)
2406 if (legacy_register_sim_regno (gdbarch
, nr
) < 0)
2407 return legacy_register_sim_regno (gdbarch
, nr
);
2408 if (nr
>= DSR_REGNUM
&& nr
<= Y1_REGNUM
)
2409 return nr
- DSR_REGNUM
+ SIM_SH_DSR_REGNUM
;
2410 if (nr
== MOD_REGNUM
)
2411 return SIM_SH_MOD_REGNUM
;
2412 if (nr
== RS_REGNUM
)
2413 return SIM_SH_RS_REGNUM
;
2414 if (nr
== RE_REGNUM
)
2415 return SIM_SH_RE_REGNUM
;
2416 if (nr
>= DSP_R0_BANK_REGNUM
&& nr
<= DSP_R7_BANK_REGNUM
)
2417 return nr
- DSP_R0_BANK_REGNUM
+ SIM_SH_R0_BANK_REGNUM
;
2422 sh_sh2a_register_sim_regno (struct gdbarch
*gdbarch
, int nr
)
2427 return SIM_SH_TBR_REGNUM
;
2429 return SIM_SH_IBNR_REGNUM
;
2431 return SIM_SH_IBCR_REGNUM
;
2433 return SIM_SH_BANK_REGNUM
;
2435 return SIM_SH_BANK_MACL_REGNUM
;
2437 return SIM_SH_BANK_GBR_REGNUM
;
2439 return SIM_SH_BANK_PR_REGNUM
;
2441 return SIM_SH_BANK_IVN_REGNUM
;
2443 return SIM_SH_BANK_MACH_REGNUM
;
2447 return legacy_register_sim_regno (gdbarch
, nr
);
2450 /* Set up the register unwinding such that call-clobbered registers are
2451 not displayed in frames >0 because the true value is not certain.
2452 The 'undefined' registers will show up as 'not available' unless the
2455 This function is currently set up for SH4 and compatible only. */
2458 sh_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
2459 struct dwarf2_frame_state_reg
*reg
,
2460 struct frame_info
*this_frame
)
2462 /* Mark the PC as the destination for the return address. */
2463 if (regnum
== gdbarch_pc_regnum (gdbarch
))
2464 reg
->how
= DWARF2_FRAME_REG_RA
;
2466 /* Mark the stack pointer as the call frame address. */
2467 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
2468 reg
->how
= DWARF2_FRAME_REG_CFA
;
2470 /* The above was taken from the default init_reg in dwarf2-frame.c
2471 while the below is SH specific. */
2473 /* Caller save registers. */
2474 else if ((regnum
>= R0_REGNUM
&& regnum
<= R0_REGNUM
+7)
2475 || (regnum
>= FR0_REGNUM
&& regnum
<= FR0_REGNUM
+11)
2476 || (regnum
>= DR0_REGNUM
&& regnum
<= DR0_REGNUM
+5)
2477 || (regnum
>= FV0_REGNUM
&& regnum
<= FV0_REGNUM
+2)
2478 || (regnum
== MACH_REGNUM
)
2479 || (regnum
== MACL_REGNUM
)
2480 || (regnum
== FPUL_REGNUM
)
2481 || (regnum
== SR_REGNUM
))
2482 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
2484 /* Callee save registers. */
2485 else if ((regnum
>= R0_REGNUM
+8 && regnum
<= R0_REGNUM
+15)
2486 || (regnum
>= FR0_REGNUM
+12 && regnum
<= FR0_REGNUM
+15)
2487 || (regnum
>= DR0_REGNUM
+6 && regnum
<= DR0_REGNUM
+8)
2488 || (regnum
== FV0_REGNUM
+3))
2489 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
2491 /* Other registers. These are not in the ABI and may or may not
2492 mean anything in frames >0 so don't show them. */
2493 else if ((regnum
>= R0_BANK0_REGNUM
&& regnum
<= R0_BANK0_REGNUM
+15)
2494 || (regnum
== GBR_REGNUM
)
2495 || (regnum
== VBR_REGNUM
)
2496 || (regnum
== FPSCR_REGNUM
)
2497 || (regnum
== SSR_REGNUM
)
2498 || (regnum
== SPC_REGNUM
))
2499 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
2502 static struct sh_frame_cache
*
2503 sh_alloc_frame_cache (void)
2505 struct sh_frame_cache
*cache
;
2508 cache
= FRAME_OBSTACK_ZALLOC (struct sh_frame_cache
);
2512 cache
->saved_sp
= 0;
2513 cache
->sp_offset
= 0;
2516 /* Frameless until proven otherwise. */
2519 /* Saved registers. We initialize these to -1 since zero is a valid
2520 offset (that's where fp is supposed to be stored). */
2521 for (i
= 0; i
< SH_NUM_REGS
; i
++)
2523 cache
->saved_regs
[i
] = -1;
2529 static struct sh_frame_cache
*
2530 sh_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2532 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2533 struct sh_frame_cache
*cache
;
2534 CORE_ADDR current_pc
;
2540 cache
= sh_alloc_frame_cache ();
2541 *this_cache
= cache
;
2543 /* In principle, for normal frames, fp holds the frame pointer,
2544 which holds the base address for the current stack frame.
2545 However, for functions that don't need it, the frame pointer is
2546 optional. For these "frameless" functions the frame pointer is
2547 actually the frame pointer of the calling frame. */
2548 cache
->base
= get_frame_register_unsigned (this_frame
, FP_REGNUM
);
2549 if (cache
->base
== 0)
2552 cache
->pc
= get_frame_func (this_frame
);
2553 current_pc
= get_frame_pc (this_frame
);
2557 fpscr
= get_frame_register_unsigned (this_frame
, FPSCR_REGNUM
);
2558 sh_analyze_prologue (gdbarch
, cache
->pc
, current_pc
, cache
, fpscr
);
2561 if (!cache
->uses_fp
)
2563 /* We didn't find a valid frame, which means that CACHE->base
2564 currently holds the frame pointer for our calling frame. If
2565 we're at the start of a function, or somewhere half-way its
2566 prologue, the function's frame probably hasn't been fully
2567 setup yet. Try to reconstruct the base address for the stack
2568 frame by looking at the stack pointer. For truly "frameless"
2569 functions this might work too. */
2570 cache
->base
= get_frame_register_unsigned
2571 (this_frame
, gdbarch_sp_regnum (gdbarch
));
2574 /* Now that we have the base address for the stack frame we can
2575 calculate the value of sp in the calling frame. */
2576 cache
->saved_sp
= cache
->base
+ cache
->sp_offset
;
2578 /* Adjust all the saved registers such that they contain addresses
2579 instead of offsets. */
2580 for (i
= 0; i
< SH_NUM_REGS
; i
++)
2581 if (cache
->saved_regs
[i
] != -1)
2582 cache
->saved_regs
[i
] = cache
->saved_sp
- cache
->saved_regs
[i
] - 4;
2587 static struct value
*
2588 sh_frame_prev_register (struct frame_info
*this_frame
,
2589 void **this_cache
, int regnum
)
2591 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2592 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
2594 gdb_assert (regnum
>= 0);
2596 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2597 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2599 /* The PC of the previous frame is stored in the PR register of
2600 the current frame. Frob regnum so that we pull the value from
2601 the correct place. */
2602 if (regnum
== gdbarch_pc_regnum (gdbarch
))
2605 if (regnum
< SH_NUM_REGS
&& cache
->saved_regs
[regnum
] != -1)
2606 return frame_unwind_got_memory (this_frame
, regnum
,
2607 cache
->saved_regs
[regnum
]);
2609 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2613 sh_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2614 struct frame_id
*this_id
)
2616 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
2618 /* This marks the outermost frame. */
2619 if (cache
->base
== 0)
2622 *this_id
= frame_id_build (cache
->saved_sp
, cache
->pc
);
2625 static const struct frame_unwind sh_frame_unwind
= {
2627 default_frame_unwind_stop_reason
,
2629 sh_frame_prev_register
,
2631 default_frame_sniffer
2635 sh_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2637 return frame_unwind_register_unsigned (next_frame
,
2638 gdbarch_sp_regnum (gdbarch
));
2642 sh_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2644 return frame_unwind_register_unsigned (next_frame
,
2645 gdbarch_pc_regnum (gdbarch
));
2648 static struct frame_id
2649 sh_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2651 CORE_ADDR sp
= get_frame_register_unsigned (this_frame
,
2652 gdbarch_sp_regnum (gdbarch
));
2653 return frame_id_build (sp
, get_frame_pc (this_frame
));
2657 sh_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2659 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
2664 static const struct frame_base sh_frame_base
= {
2666 sh_frame_base_address
,
2667 sh_frame_base_address
,
2668 sh_frame_base_address
2671 static struct sh_frame_cache
*
2672 sh_make_stub_cache (struct frame_info
*this_frame
)
2674 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2675 struct sh_frame_cache
*cache
;
2677 cache
= sh_alloc_frame_cache ();
2680 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
2686 sh_stub_this_id (struct frame_info
*this_frame
, void **this_cache
,
2687 struct frame_id
*this_id
)
2689 struct sh_frame_cache
*cache
;
2691 if (*this_cache
== NULL
)
2692 *this_cache
= sh_make_stub_cache (this_frame
);
2693 cache
= *this_cache
;
2695 *this_id
= frame_id_build (cache
->saved_sp
, get_frame_pc (this_frame
));
2699 sh_stub_unwind_sniffer (const struct frame_unwind
*self
,
2700 struct frame_info
*this_frame
,
2701 void **this_prologue_cache
)
2703 CORE_ADDR addr_in_block
;
2705 addr_in_block
= get_frame_address_in_block (this_frame
);
2706 if (in_plt_section (addr_in_block
, NULL
))
2712 static const struct frame_unwind sh_stub_unwind
=
2715 default_frame_unwind_stop_reason
,
2717 sh_frame_prev_register
,
2719 sh_stub_unwind_sniffer
2722 /* The epilogue is defined here as the area at the end of a function,
2723 either on the `ret' instruction itself or after an instruction which
2724 destroys the function's stack frame. */
2726 sh_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2728 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2729 CORE_ADDR func_addr
= 0, func_end
= 0;
2731 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
2734 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2735 for a nop and some fixed data (e.g. big offsets) which are
2736 unfortunately also treated as part of the function (which
2737 means, they are below func_end. */
2738 CORE_ADDR addr
= func_end
- 28;
2739 if (addr
< func_addr
+ 4)
2740 addr
= func_addr
+ 4;
2744 /* First search forward until hitting an rts. */
2745 while (addr
< func_end
2746 && !IS_RTS (read_memory_unsigned_integer (addr
, 2, byte_order
)))
2748 if (addr
>= func_end
)
2751 /* At this point we should find a mov.l @r15+,r14 instruction,
2752 either before or after the rts. If not, then the function has
2753 probably no "normal" epilogue and we bail out here. */
2754 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2755 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr
- 2, 2,
2758 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr
+ 2, 2,
2762 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2764 /* Step over possible lds.l @r15+,macl. */
2765 if (IS_MACL_LDS (inst
))
2768 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2771 /* Step over possible lds.l @r15+,pr. */
2775 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2778 /* Step over possible mov r14,r15. */
2779 if (IS_MOV_FP_SP (inst
))
2782 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2785 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2787 while (addr
> func_addr
+ 4
2788 && (IS_ADD_REG_TO_FP (inst
) || IS_ADD_IMM_FP (inst
)))
2791 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2794 /* On SH2a check if the previous instruction was perhaps a MOVI20.
2795 That's allowed for the epilogue. */
2796 if ((gdbarch_bfd_arch_info (gdbarch
)->mach
== bfd_mach_sh2a
2797 || gdbarch_bfd_arch_info (gdbarch
)->mach
== bfd_mach_sh2a_nofpu
)
2798 && addr
> func_addr
+ 6
2799 && IS_MOVI20 (read_memory_unsigned_integer (addr
- 4, 2,
2810 /* Supply register REGNUM from the buffer specified by REGS and LEN
2811 in the register set REGSET to register cache REGCACHE.
2812 REGTABLE specifies where each register can be found in REGS.
2813 If REGNUM is -1, do this for all registers in REGSET. */
2816 sh_corefile_supply_regset (const struct regset
*regset
,
2817 struct regcache
*regcache
,
2818 int regnum
, const void *regs
, size_t len
)
2820 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2821 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2822 const struct sh_corefile_regmap
*regmap
= (regset
== &sh_corefile_gregset
2823 ? tdep
->core_gregmap
2824 : tdep
->core_fpregmap
);
2827 for (i
= 0; regmap
[i
].regnum
!= -1; i
++)
2829 if ((regnum
== -1 || regnum
== regmap
[i
].regnum
)
2830 && regmap
[i
].offset
+ 4 <= len
)
2831 regcache_raw_supply (regcache
, regmap
[i
].regnum
,
2832 (char *)regs
+ regmap
[i
].offset
);
2836 /* Collect register REGNUM in the register set REGSET from register cache
2837 REGCACHE into the buffer specified by REGS and LEN.
2838 REGTABLE specifies where each register can be found in REGS.
2839 If REGNUM is -1, do this for all registers in REGSET. */
2842 sh_corefile_collect_regset (const struct regset
*regset
,
2843 const struct regcache
*regcache
,
2844 int regnum
, void *regs
, size_t len
)
2846 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2847 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2848 const struct sh_corefile_regmap
*regmap
= (regset
== &sh_corefile_gregset
2849 ? tdep
->core_gregmap
2850 : tdep
->core_fpregmap
);
2853 for (i
= 0; regmap
[i
].regnum
!= -1; i
++)
2855 if ((regnum
== -1 || regnum
== regmap
[i
].regnum
)
2856 && regmap
[i
].offset
+ 4 <= len
)
2857 regcache_raw_collect (regcache
, regmap
[i
].regnum
,
2858 (char *)regs
+ regmap
[i
].offset
);
2862 /* The following two regsets have the same contents, so it is tempting to
2863 unify them, but they are distiguished by their address, so don't. */
2865 struct regset sh_corefile_gregset
=
2868 sh_corefile_supply_regset
,
2869 sh_corefile_collect_regset
2872 static struct regset sh_corefile_fpregset
=
2875 sh_corefile_supply_regset
,
2876 sh_corefile_collect_regset
2879 static const struct regset
*
2880 sh_regset_from_core_section (struct gdbarch
*gdbarch
, const char *sect_name
,
2883 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2885 if (tdep
->core_gregmap
&& strcmp (sect_name
, ".reg") == 0)
2886 return &sh_corefile_gregset
;
2888 if (tdep
->core_fpregmap
&& strcmp (sect_name
, ".reg2") == 0)
2889 return &sh_corefile_fpregset
;
2895 static struct gdbarch
*
2896 sh_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2898 struct gdbarch
*gdbarch
;
2899 struct gdbarch_tdep
*tdep
;
2901 sh_show_regs
= sh_generic_show_regs
;
2902 switch (info
.bfd_arch_info
->mach
)
2905 sh_show_regs
= sh2e_show_regs
;
2908 sh_show_regs
= sh2a_show_regs
;
2910 case bfd_mach_sh2a_nofpu
:
2911 sh_show_regs
= sh2a_nofpu_show_regs
;
2913 case bfd_mach_sh_dsp
:
2914 sh_show_regs
= sh_dsp_show_regs
;
2918 case bfd_mach_sh3_nommu
:
2919 case bfd_mach_sh2a_nofpu_or_sh3_nommu
:
2920 sh_show_regs
= sh3_show_regs
;
2924 case bfd_mach_sh2a_or_sh3e
:
2925 sh_show_regs
= sh3e_show_regs
;
2928 case bfd_mach_sh3_dsp
:
2929 case bfd_mach_sh4al_dsp
:
2930 sh_show_regs
= sh3_dsp_show_regs
;
2935 case bfd_mach_sh2a_or_sh4
:
2936 sh_show_regs
= sh4_show_regs
;
2939 case bfd_mach_sh4_nofpu
:
2940 case bfd_mach_sh4_nommu_nofpu
:
2941 case bfd_mach_sh4a_nofpu
:
2942 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu
:
2943 sh_show_regs
= sh4_nofpu_show_regs
;
2947 sh_show_regs
= sh64_show_regs
;
2948 /* SH5 is handled entirely in sh64-tdep.c. */
2949 return sh64_gdbarch_init (info
, arches
);
2952 /* If there is already a candidate, use it. */
2953 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2955 return arches
->gdbarch
;
2957 /* None found, create a new architecture from the information
2959 tdep
= XZALLOC (struct gdbarch_tdep
);
2960 gdbarch
= gdbarch_alloc (&info
, tdep
);
2962 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2963 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2964 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2965 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2966 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2967 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2968 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2969 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2971 set_gdbarch_num_regs (gdbarch
, SH_NUM_REGS
);
2972 set_gdbarch_sp_regnum (gdbarch
, 15);
2973 set_gdbarch_pc_regnum (gdbarch
, 16);
2974 set_gdbarch_fp0_regnum (gdbarch
, -1);
2975 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
2977 set_gdbarch_register_type (gdbarch
, sh_default_register_type
);
2978 set_gdbarch_register_reggroup_p (gdbarch
, sh_register_reggroup_p
);
2980 set_gdbarch_breakpoint_from_pc (gdbarch
, sh_breakpoint_from_pc
);
2982 set_gdbarch_print_insn (gdbarch
, print_insn_sh
);
2983 set_gdbarch_register_sim_regno (gdbarch
, legacy_register_sim_regno
);
2985 set_gdbarch_return_value (gdbarch
, sh_return_value_nofpu
);
2987 set_gdbarch_skip_prologue (gdbarch
, sh_skip_prologue
);
2988 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2990 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_nofpu
);
2992 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2994 set_gdbarch_frame_align (gdbarch
, sh_frame_align
);
2995 set_gdbarch_unwind_sp (gdbarch
, sh_unwind_sp
);
2996 set_gdbarch_unwind_pc (gdbarch
, sh_unwind_pc
);
2997 set_gdbarch_dummy_id (gdbarch
, sh_dummy_id
);
2998 frame_base_set_default (gdbarch
, &sh_frame_base
);
3000 set_gdbarch_in_function_epilogue_p (gdbarch
, sh_in_function_epilogue_p
);
3002 dwarf2_frame_set_init_reg (gdbarch
, sh_dwarf2_frame_init_reg
);
3004 set_gdbarch_regset_from_core_section (gdbarch
, sh_regset_from_core_section
);
3006 switch (info
.bfd_arch_info
->mach
)
3009 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
3013 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
3017 /* doubles on sh2e and sh3e are actually 4 byte. */
3018 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3020 set_gdbarch_register_name (gdbarch
, sh_sh2e_register_name
);
3021 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
3022 set_gdbarch_fp0_regnum (gdbarch
, 25);
3023 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
3024 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
3028 set_gdbarch_register_name (gdbarch
, sh_sh2a_register_name
);
3029 set_gdbarch_register_type (gdbarch
, sh_sh2a_register_type
);
3030 set_gdbarch_register_sim_regno (gdbarch
, sh_sh2a_register_sim_regno
);
3032 set_gdbarch_fp0_regnum (gdbarch
, 25);
3033 set_gdbarch_num_pseudo_regs (gdbarch
, 9);
3034 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
3035 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
3036 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
3037 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
3040 case bfd_mach_sh2a_nofpu
:
3041 set_gdbarch_register_name (gdbarch
, sh_sh2a_nofpu_register_name
);
3042 set_gdbarch_register_sim_regno (gdbarch
, sh_sh2a_register_sim_regno
);
3044 set_gdbarch_num_pseudo_regs (gdbarch
, 1);
3045 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
3046 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
3049 case bfd_mach_sh_dsp
:
3050 set_gdbarch_register_name (gdbarch
, sh_sh_dsp_register_name
);
3051 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
3055 case bfd_mach_sh3_nommu
:
3056 case bfd_mach_sh2a_nofpu_or_sh3_nommu
:
3057 set_gdbarch_register_name (gdbarch
, sh_sh3_register_name
);
3061 case bfd_mach_sh2a_or_sh3e
:
3062 /* doubles on sh2e and sh3e are actually 4 byte. */
3063 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3065 set_gdbarch_register_name (gdbarch
, sh_sh3e_register_name
);
3066 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
3067 set_gdbarch_fp0_regnum (gdbarch
, 25);
3068 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
3069 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
3072 case bfd_mach_sh3_dsp
:
3073 set_gdbarch_register_name (gdbarch
, sh_sh3_dsp_register_name
);
3074 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
3079 case bfd_mach_sh2a_or_sh4
:
3080 set_gdbarch_register_name (gdbarch
, sh_sh4_register_name
);
3081 set_gdbarch_register_type (gdbarch
, sh_sh4_register_type
);
3082 set_gdbarch_fp0_regnum (gdbarch
, 25);
3083 set_gdbarch_num_pseudo_regs (gdbarch
, 13);
3084 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
3085 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
3086 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
3087 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
3090 case bfd_mach_sh4_nofpu
:
3091 case bfd_mach_sh4a_nofpu
:
3092 case bfd_mach_sh4_nommu_nofpu
:
3093 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu
:
3094 set_gdbarch_register_name (gdbarch
, sh_sh4_nofpu_register_name
);
3097 case bfd_mach_sh4al_dsp
:
3098 set_gdbarch_register_name (gdbarch
, sh_sh4al_dsp_register_name
);
3099 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
3103 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
3107 /* Hook in ABI-specific overrides, if they have been registered. */
3108 gdbarch_init_osabi (info
, gdbarch
);
3110 dwarf2_append_unwinders (gdbarch
);
3111 frame_unwind_append_unwinder (gdbarch
, &sh_stub_unwind
);
3112 frame_unwind_append_unwinder (gdbarch
, &sh_frame_unwind
);
3118 show_sh_command (char *args
, int from_tty
)
3120 help_list (showshcmdlist
, "show sh ", all_commands
, gdb_stdout
);
3124 set_sh_command (char *args
, int from_tty
)
3127 ("\"set sh\" must be followed by an appropriate subcommand.\n");
3128 help_list (setshcmdlist
, "set sh ", all_commands
, gdb_stdout
);
3131 extern initialize_file_ftype _initialize_sh_tdep
; /* -Wmissing-prototypes */
3134 _initialize_sh_tdep (void)
3136 struct cmd_list_element
*c
;
3138 gdbarch_register (bfd_arch_sh
, sh_gdbarch_init
, NULL
);
3140 add_com ("regs", class_vars
, sh_show_regs_command
, _("Print all registers"));
3142 add_prefix_cmd ("sh", no_class
, set_sh_command
, "SH specific commands.",
3143 &setshcmdlist
, "set sh ", 0, &setlist
);
3144 add_prefix_cmd ("sh", no_class
, show_sh_command
, "SH specific commands.",
3145 &showshcmdlist
, "show sh ", 0, &showlist
);
3147 add_setshow_enum_cmd ("calling-convention", class_vars
, sh_cc_enum
,
3148 &sh_active_calling_convention
,
3149 _("Set calling convention used when calling target "
3150 "functions from GDB."),
3151 _("Show calling convention used when calling target "
3152 "functions from GDB."),
3153 _("gcc - Use GCC calling convention (default).\n"
3154 "renesas - Enforce Renesas calling convention."),
3156 &setshcmdlist
, &showshcmdlist
);