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* config.if: Remove unused libc_interface determination.
[deliverable/binutils-gdb.git] / gdb / sh-tdep.c
1 /* Target-dependent code for Hitachi Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 /*
23 Contributed by Steve Chamberlain
24 sac@cygnus.com
25 */
26
27 #include "defs.h"
28 #include "frame.h"
29 #include "symtab.h"
30 #include "symfile.h"
31 #include "gdbtypes.h"
32 #include "gdbcmd.h"
33 #include "gdbcore.h"
34 #include "value.h"
35 #include "dis-asm.h"
36 #include "inferior.h"
37 #include "gdb_string.h"
38 #include "arch-utils.h"
39 #include "floatformat.h"
40 #include "regcache.h"
41 #include "doublest.h"
42 #include "osabi.h"
43
44 #include "sh-tdep.h"
45
46 #include "elf-bfd.h"
47 #include "solib-svr4.h"
48
49 /* sh64 flags */
50 #include "elf/sh.h"
51 /* registers numbers shared with the simulator */
52 #include "gdb/sim-sh.h"
53
54 void (*sh_show_regs) (void);
55 CORE_ADDR (*skip_prologue_hard_way) (CORE_ADDR);
56 void (*do_pseudo_register) (int);
57
58 #define SH_DEFAULT_NUM_REGS 59
59
60 /* Define other aspects of the stack frame.
61 we keep a copy of the worked out return pc lying around, since it
62 is a useful bit of info */
63
64 struct frame_extra_info
65 {
66 CORE_ADDR return_pc;
67 int leaf_function;
68 int f_offset;
69 };
70
71 static const char *
72 sh_generic_register_name (int reg_nr)
73 {
74 static char *register_names[] =
75 {
76 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
77 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
78 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
79 "fpul", "fpscr",
80 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
81 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
82 "ssr", "spc",
83 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
84 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
85 };
86 if (reg_nr < 0)
87 return NULL;
88 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
89 return NULL;
90 return register_names[reg_nr];
91 }
92
93 static const char *
94 sh_sh_register_name (int reg_nr)
95 {
96 static char *register_names[] =
97 {
98 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
99 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
100 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
101 "", "",
102 "", "", "", "", "", "", "", "",
103 "", "", "", "", "", "", "", "",
104 "", "",
105 "", "", "", "", "", "", "", "",
106 "", "", "", "", "", "", "", "",
107 };
108 if (reg_nr < 0)
109 return NULL;
110 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
111 return NULL;
112 return register_names[reg_nr];
113 }
114
115 static const char *
116 sh_sh3_register_name (int reg_nr)
117 {
118 static char *register_names[] =
119 {
120 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
121 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
122 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
123 "", "",
124 "", "", "", "", "", "", "", "",
125 "", "", "", "", "", "", "", "",
126 "ssr", "spc",
127 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
128 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
129 };
130 if (reg_nr < 0)
131 return NULL;
132 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
133 return NULL;
134 return register_names[reg_nr];
135 }
136
137 static const char *
138 sh_sh3e_register_name (int reg_nr)
139 {
140 static char *register_names[] =
141 {
142 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
143 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
144 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
145 "fpul", "fpscr",
146 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
147 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
148 "ssr", "spc",
149 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
150 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
151 };
152 if (reg_nr < 0)
153 return NULL;
154 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
155 return NULL;
156 return register_names[reg_nr];
157 }
158
159 static const char *
160 sh_sh2e_register_name (int reg_nr)
161 {
162 static char *register_names[] =
163 {
164 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
165 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
166 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
167 "fpul", "fpscr",
168 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
169 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
170 "", "",
171 "", "", "", "", "", "", "", "",
172 "", "", "", "", "", "", "", "",
173 };
174 if (reg_nr < 0)
175 return NULL;
176 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
177 return NULL;
178 return register_names[reg_nr];
179 }
180
181 static const char *
182 sh_sh_dsp_register_name (int reg_nr)
183 {
184 static char *register_names[] =
185 {
186 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
187 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
188 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
189 "", "dsr",
190 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
191 "y0", "y1", "", "", "", "", "", "mod",
192 "", "",
193 "rs", "re", "", "", "", "", "", "",
194 "", "", "", "", "", "", "", "",
195 };
196 if (reg_nr < 0)
197 return NULL;
198 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
199 return NULL;
200 return register_names[reg_nr];
201 }
202
203 static const char *
204 sh_sh3_dsp_register_name (int reg_nr)
205 {
206 static char *register_names[] =
207 {
208 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
209 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
210 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
211 "", "dsr",
212 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
213 "y0", "y1", "", "", "", "", "", "mod",
214 "ssr", "spc",
215 "rs", "re", "", "", "", "", "", "",
216 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
217 "", "", "", "", "", "", "", "",
218 };
219 if (reg_nr < 0)
220 return NULL;
221 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
222 return NULL;
223 return register_names[reg_nr];
224 }
225
226 static const char *
227 sh_sh4_register_name (int reg_nr)
228 {
229 static char *register_names[] =
230 {
231 /* general registers 0-15 */
232 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
233 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
234 /* 16 - 22 */
235 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
236 /* 23, 24 */
237 "fpul", "fpscr",
238 /* floating point registers 25 - 40 */
239 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
240 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
241 /* 41, 42 */
242 "ssr", "spc",
243 /* bank 0 43 - 50 */
244 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
245 /* bank 1 51 - 58 */
246 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
247 /* double precision (pseudo) 59 - 66 */
248 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
249 /* vectors (pseudo) 67 - 70 */
250 "fv0", "fv4", "fv8", "fv12",
251 /* FIXME: missing XF 71 - 86 */
252 /* FIXME: missing XD 87 - 94 */
253 };
254 if (reg_nr < 0)
255 return NULL;
256 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
257 return NULL;
258 return register_names[reg_nr];
259 }
260
261 static const char *
262 sh_sh64_register_name (int reg_nr)
263 {
264 static char *register_names[] =
265 {
266 /* SH MEDIA MODE (ISA 32) */
267 /* general registers (64-bit) 0-63 */
268 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
269 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
270 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
271 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
272 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
273 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
274 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
275 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
276
277 /* pc (64-bit) 64 */
278 "pc",
279
280 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
281 "sr", "ssr", "spc",
282
283 /* target registers (64-bit) 68-75*/
284 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
285
286 /* floating point state control register (32-bit) 76 */
287 "fpscr",
288
289 /* single precision floating point registers (32-bit) 77-140*/
290 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
291 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
292 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
293 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
294 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
295 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
296 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
297 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
298
299 /* double precision registers (pseudo) 141-172 */
300 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
301 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
302 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
303 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
304
305 /* floating point pairs (pseudo) 173-204*/
306 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
307 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
308 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
309 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
310
311 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
312 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
313 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
314
315 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
316 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
317 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
318 "pc_c",
319 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
320 "fpscr_c", "fpul_c",
321 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
322 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
323 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
324 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
325 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
326 };
327
328 if (reg_nr < 0)
329 return NULL;
330 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
331 return NULL;
332 return register_names[reg_nr];
333 }
334
335 #define NUM_PSEUDO_REGS_SH_MEDIA 80
336 #define NUM_PSEUDO_REGS_SH_COMPACT 51
337
338 static const unsigned char *
339 sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
340 {
341 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
342 static unsigned char breakpoint[] = {0xc3, 0xc3};
343
344 *lenptr = sizeof (breakpoint);
345 return breakpoint;
346 }
347
348 /* Macros and functions for setting and testing a bit in a minimal
349 symbol that marks it as 32-bit function. The MSB of the minimal
350 symbol's "info" field is used for this purpose. This field is
351 already being used to store the symbol size, so the assumption is
352 that the symbol size cannot exceed 2^31.
353
354 ELF_MAKE_MSYMBOL_SPECIAL
355 tests whether an ELF symbol is "special", i.e. refers
356 to a 32-bit function, and sets a "special" bit in a
357 minimal symbol to mark it as a 32-bit function
358 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol
359 MSYMBOL_SIZE returns the size of the minimal symbol, i.e.
360 the "info" field with the "special" bit masked out */
361
362 #define MSYMBOL_IS_SPECIAL(msym) \
363 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
364
365 static void
366 sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
367 {
368 if (msym == NULL)
369 return;
370
371 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32)
372 {
373 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000);
374 SYMBOL_VALUE_ADDRESS (msym) |= 1;
375 }
376 }
377
378 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
379 are some macros to test, set, or clear bit 0 of addresses. */
380 #define IS_ISA32_ADDR(addr) ((addr) & 1)
381 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
382 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
383
384 static int
385 pc_is_isa32 (bfd_vma memaddr)
386 {
387 struct minimal_symbol *sym;
388
389 /* If bit 0 of the address is set, assume this is a
390 ISA32 (shmedia) address. */
391 if (IS_ISA32_ADDR (memaddr))
392 return 1;
393
394 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
395 the high bit of the info field. Use this to decide if the function is
396 ISA16 or ISA32. */
397 sym = lookup_minimal_symbol_by_pc (memaddr);
398 if (sym)
399 return MSYMBOL_IS_SPECIAL (sym);
400 else
401 return 0;
402 }
403
404 static const unsigned char *
405 sh_sh64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
406 {
407 /* The BRK instruction for shmedia is
408 01101111 11110101 11111111 11110000
409 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
410 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
411
412 /* The BRK instruction for shcompact is
413 00000000 00111011
414 which translates in big endian mode to 0x0, 0x3b
415 and in little endian mode to 0x3b, 0x0*/
416
417 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
418 {
419 if (pc_is_isa32 (*pcptr))
420 {
421 static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0};
422 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
423 *lenptr = sizeof (big_breakpoint_media);
424 return big_breakpoint_media;
425 }
426 else
427 {
428 static unsigned char big_breakpoint_compact[] = {0x0, 0x3b};
429 *lenptr = sizeof (big_breakpoint_compact);
430 return big_breakpoint_compact;
431 }
432 }
433 else
434 {
435 if (pc_is_isa32 (*pcptr))
436 {
437 static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f};
438 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
439 *lenptr = sizeof (little_breakpoint_media);
440 return little_breakpoint_media;
441 }
442 else
443 {
444 static unsigned char little_breakpoint_compact[] = {0x3b, 0x0};
445 *lenptr = sizeof (little_breakpoint_compact);
446 return little_breakpoint_compact;
447 }
448 }
449 }
450
451 /* Prologue looks like
452 [mov.l <regs>,@-r15]...
453 [sts.l pr,@-r15]
454 [mov.l r14,@-r15]
455 [mov r15,r14]
456
457 Actually it can be more complicated than this. For instance, with
458 newer gcc's:
459
460 mov.l r14,@-r15
461 add #-12,r15
462 mov r15,r14
463 mov r4,r1
464 mov r5,r2
465 mov.l r6,@(4,r14)
466 mov.l r7,@(8,r14)
467 mov.b r1,@r14
468 mov r14,r1
469 mov r14,r1
470 add #2,r1
471 mov.w r2,@r1
472
473 */
474
475 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
476 with l=1 and n = 18 0110101111110001010010100aaa0000 */
477 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
478
479 /* STS.L PR,@-r0 0100000000100010
480 r0-4-->r0, PR-->(r0) */
481 #define IS_STS_R0(x) ((x) == 0x4022)
482
483 /* STS PR, Rm 0000mmmm00101010
484 PR-->Rm */
485 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
486
487 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
488 Rm-->(dispx4+r15) */
489 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
490
491 /* MOV.L R14,@(disp,r15) 000111111110dddd
492 R14-->(dispx4+r15) */
493 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
494
495 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
496 R18-->(dispx8+R14) */
497 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
498
499 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
500 R18-->(dispx8+R15) */
501 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
502
503 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
504 R18-->(dispx4+R15) */
505 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
506
507 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
508 R14-->(dispx8+R15) */
509 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
510
511 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
512 R14-->(dispx4+R15) */
513 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
514
515 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
516 R15 + imm --> R15 */
517 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
518
519 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
520 R15 + imm --> R15 */
521 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
522
523 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
524 R15 + R63 --> R14 */
525 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
526
527 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
528 R15 + R63 --> R14 */
529 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
530
531 #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
532
533 /* MOV #imm, R0 1110 0000 ssss ssss
534 #imm-->R0 */
535 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
536
537 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
538 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
539
540 /* ADD r15,r0 0011 0000 1111 1100
541 r15+r0-->r0 */
542 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
543
544 /* MOV.L R14 @-R0 0010 0000 1110 0110
545 R14-->(R0-4), R0-4-->R0 */
546 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
547
548 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
549 where Rm is one of r2-r9 which are the argument registers. */
550 /* FIXME: Recognize the float and double register moves too! */
551 #define IS_MEDIA_IND_ARG_MOV(x) \
552 ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
553
554 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
555 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
556 where Rm is one of r2-r9 which are the argument registers. */
557 #define IS_MEDIA_ARG_MOV(x) \
558 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
559 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
560
561 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
562 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
563 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
564 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
565 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
566 #define IS_MEDIA_MOV_TO_R14(x) \
567 ((((x) & 0xfffffc0f) == 0xa0e00000) \
568 || (((x) & 0xfffffc0f) == 0xa4e00000) \
569 || (((x) & 0xfffffc0f) == 0xa8e00000) \
570 || (((x) & 0xfffffc0f) == 0xb4e00000) \
571 || (((x) & 0xfffffc0f) == 0xbce00000))
572
573 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
574 where Rm is r2-r9 */
575 #define IS_COMPACT_IND_ARG_MOV(x) \
576 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
577
578 /* compact direct arg move!
579 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
580 #define IS_COMPACT_ARG_MOV(x) \
581 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
582
583 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
584 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
585 #define IS_COMPACT_MOV_TO_R14(x) \
586 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
587
588 #define IS_JSR_R0(x) ((x) == 0x400b)
589 #define IS_NOP(x) ((x) == 0x0009)
590
591
592 /* STS.L PR,@-r15 0100111100100010
593 r15-4-->r15, PR-->(r15) */
594 #define IS_STS(x) ((x) == 0x4f22)
595
596 /* MOV.L Rm,@-r15 00101111mmmm0110
597 r15-4-->r15, Rm-->(R15) */
598 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
599
600 #define GET_PUSHED_REG(x) (((x) >> 4) & 0xf)
601
602 /* MOV r15,r14 0110111011110011
603 r15-->r14 */
604 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
605
606 /* ADD #imm,r15 01111111iiiiiiii
607 r15+imm-->r15 */
608 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
609
610 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
611 #define IS_SHLL_R3(x) ((x) == 0x4300)
612
613 /* ADD r3,r15 0011111100111100
614 r15+r3-->r15 */
615 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
616
617 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
618 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
619 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
620 #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b)
621
622 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011
623 MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd
624 MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010
625 where Rm is one of r4,r5,r6,r7 which are the argument registers. */
626 #define IS_ARG_MOV(x) \
627 (((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
628 || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
629 || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)))
630
631 /* MOV.L Rm,@(disp,r14) 00011110mmmmdddd
632 Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */
633 #define IS_MOV_TO_R14(x) \
634 ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))
635
636 #define FPSCR_SZ (1 << 20)
637
638 /* Skip any prologue before the guts of a function */
639
640 /* Skip the prologue using the debug information. If this fails we'll
641 fall back on the 'guess' method below. */
642 static CORE_ADDR
643 after_prologue (CORE_ADDR pc)
644 {
645 struct symtab_and_line sal;
646 CORE_ADDR func_addr, func_end;
647
648 /* If we can not find the symbol in the partial symbol table, then
649 there is no hope we can determine the function's start address
650 with this code. */
651 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
652 return 0;
653
654 /* Get the line associated with FUNC_ADDR. */
655 sal = find_pc_line (func_addr, 0);
656
657 /* There are only two cases to consider. First, the end of the source line
658 is within the function bounds. In that case we return the end of the
659 source line. Second is the end of the source line extends beyond the
660 bounds of the current function. We need to use the slow code to
661 examine instructions in that case. */
662 if (sal.end < func_end)
663 return sal.end;
664 else
665 return 0;
666 }
667
668 /* Here we look at each instruction in the function, and try to guess
669 where the prologue ends. Unfortunately this is not always
670 accurate. */
671 static CORE_ADDR
672 sh_skip_prologue_hard_way (CORE_ADDR start_pc)
673 {
674 CORE_ADDR here, end;
675 int updated_fp = 0;
676
677 if (!start_pc)
678 return 0;
679
680 for (here = start_pc, end = start_pc + (2 * 28); here < end;)
681 {
682 int w = read_memory_integer (here, 2);
683 here += 2;
684 if (IS_FMOV (w) || IS_PUSH (w) || IS_STS (w) || IS_MOV_R3 (w)
685 || IS_ADD_R3SP (w) || IS_ADD_SP (w) || IS_SHLL_R3 (w)
686 || IS_ARG_MOV (w) || IS_MOV_TO_R14 (w))
687 {
688 start_pc = here;
689 }
690 else if (IS_MOV_SP_FP (w))
691 {
692 start_pc = here;
693 updated_fp = 1;
694 }
695 else
696 /* Don't bail out yet, if we are before the copy of sp. */
697 if (updated_fp)
698 break;
699 }
700
701 return start_pc;
702 }
703
704 static CORE_ADDR
705 look_for_args_moves (CORE_ADDR start_pc, int media_mode)
706 {
707 CORE_ADDR here, end;
708 int w;
709 int insn_size = (media_mode ? 4 : 2);
710
711 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
712 {
713 if (media_mode)
714 {
715 w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
716 here += insn_size;
717 if (IS_MEDIA_IND_ARG_MOV (w))
718 {
719 /* This must be followed by a store to r14, so the argument
720 is where the debug info says it is. This can happen after
721 the SP has been saved, unfortunately. */
722
723 int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here),
724 insn_size);
725 here += insn_size;
726 if (IS_MEDIA_MOV_TO_R14 (next_insn))
727 start_pc = here;
728 }
729 else if (IS_MEDIA_ARG_MOV (w))
730 {
731 /* These instructions store directly the argument in r14. */
732 start_pc = here;
733 }
734 else
735 break;
736 }
737 else
738 {
739 w = read_memory_integer (here, insn_size);
740 w = w & 0xffff;
741 here += insn_size;
742 if (IS_COMPACT_IND_ARG_MOV (w))
743 {
744 /* This must be followed by a store to r14, so the argument
745 is where the debug info says it is. This can happen after
746 the SP has been saved, unfortunately. */
747
748 int next_insn = 0xffff & read_memory_integer (here, insn_size);
749 here += insn_size;
750 if (IS_COMPACT_MOV_TO_R14 (next_insn))
751 start_pc = here;
752 }
753 else if (IS_COMPACT_ARG_MOV (w))
754 {
755 /* These instructions store directly the argument in r14. */
756 start_pc = here;
757 }
758 else if (IS_MOVL_R0 (w))
759 {
760 /* There is a function that gcc calls to get the arguments
761 passed correctly to the function. Only after this
762 function call the arguments will be found at the place
763 where they are supposed to be. This happens in case the
764 argument has to be stored into a 64-bit register (for
765 instance doubles, long longs). SHcompact doesn't have
766 access to the full 64-bits, so we store the register in
767 stack slot and store the address of the stack slot in
768 the register, then do a call through a wrapper that
769 loads the memory value into the register. A SHcompact
770 callee calls an argument decoder
771 (GCC_shcompact_incoming_args) that stores the 64-bit
772 value in a stack slot and stores the address of the
773 stack slot in the register. GCC thinks the argument is
774 just passed by transparent reference, but this is only
775 true after the argument decoder is called. Such a call
776 needs to be considered part of the prologue. */
777
778 /* This must be followed by a JSR @r0 instruction and by
779 a NOP instruction. After these, the prologue is over! */
780
781 int next_insn = 0xffff & read_memory_integer (here, insn_size);
782 here += insn_size;
783 if (IS_JSR_R0 (next_insn))
784 {
785 next_insn = 0xffff & read_memory_integer (here, insn_size);
786 here += insn_size;
787
788 if (IS_NOP (next_insn))
789 start_pc = here;
790 }
791 }
792 else
793 break;
794 }
795 }
796
797 return start_pc;
798 }
799
800 static CORE_ADDR
801 sh64_skip_prologue_hard_way (CORE_ADDR start_pc)
802 {
803 CORE_ADDR here, end;
804 int updated_fp = 0;
805 int insn_size = 4;
806 int media_mode = 1;
807
808 if (!start_pc)
809 return 0;
810
811 if (pc_is_isa32 (start_pc) == 0)
812 {
813 insn_size = 2;
814 media_mode = 0;
815 }
816
817 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
818 {
819
820 if (media_mode)
821 {
822 int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
823 here += insn_size;
824 if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w)
825 || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w)
826 || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w))
827 {
828 start_pc = here;
829 }
830 else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w))
831 {
832 start_pc = here;
833 updated_fp = 1;
834 }
835 else
836 if (updated_fp)
837 {
838 /* Don't bail out yet, we may have arguments stored in
839 registers here, according to the debug info, so that
840 gdb can print the frames correctly. */
841 start_pc = look_for_args_moves (here - insn_size, media_mode);
842 break;
843 }
844 }
845 else
846 {
847 int w = 0xffff & read_memory_integer (here, insn_size);
848 here += insn_size;
849
850 if (IS_STS_R0 (w) || IS_STS_PR (w)
851 || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w)
852 || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w))
853 {
854 start_pc = here;
855 }
856 else if (IS_MOV_SP_FP (w))
857 {
858 start_pc = here;
859 updated_fp = 1;
860 }
861 else
862 if (updated_fp)
863 {
864 /* Don't bail out yet, we may have arguments stored in
865 registers here, according to the debug info, so that
866 gdb can print the frames correctly. */
867 start_pc = look_for_args_moves (here - insn_size, media_mode);
868 break;
869 }
870 }
871 }
872
873 return start_pc;
874 }
875
876 static CORE_ADDR
877 sh_skip_prologue (CORE_ADDR pc)
878 {
879 CORE_ADDR post_prologue_pc;
880
881 /* See if we can determine the end of the prologue via the symbol table.
882 If so, then return either PC, or the PC after the prologue, whichever
883 is greater. */
884 post_prologue_pc = after_prologue (pc);
885
886 /* If after_prologue returned a useful address, then use it. Else
887 fall back on the instruction skipping code. */
888 if (post_prologue_pc != 0)
889 return max (pc, post_prologue_pc);
890 else
891 return (skip_prologue_hard_way (pc));
892 }
893
894 /* Immediately after a function call, return the saved pc.
895 Can't always go through the frames for this because on some machines
896 the new frame is not set up until the new function executes
897 some instructions.
898
899 The return address is the value saved in the PR register + 4 */
900 static CORE_ADDR
901 sh_saved_pc_after_call (struct frame_info *frame)
902 {
903 return (ADDR_BITS_REMOVE (read_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM)));
904 }
905
906 /* Should call_function allocate stack space for a struct return? */
907 static int
908 sh_use_struct_convention (int gcc_p, struct type *type)
909 {
910 #if 0
911 return (TYPE_LENGTH (type) > 1);
912 #else
913 int len = TYPE_LENGTH (type);
914 int nelem = TYPE_NFIELDS (type);
915 return ((len != 1 && len != 2 && len != 4 && len != 8) || nelem != 1) &&
916 (len != 8 || TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) != 4);
917 #endif
918 }
919
920 static int
921 sh64_use_struct_convention (int gcc_p, struct type *type)
922 {
923 return (TYPE_LENGTH (type) > 8);
924 }
925
926 /* Store the address of the place in which to copy the structure the
927 subroutine will return. This is called from call_function.
928
929 We store structs through a pointer passed in R2 */
930 static void
931 sh_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
932 {
933 write_register (STRUCT_RETURN_REGNUM, (addr));
934 }
935
936 /* Disassemble an instruction. */
937 static int
938 gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info)
939 {
940 info->endian = TARGET_BYTE_ORDER;
941 return print_insn_sh (memaddr, info);
942 }
943
944 /* Given a GDB frame, determine the address of the calling function's
945 frame. This will be used to create a new GDB frame struct, and
946 then DEPRECATED_INIT_EXTRA_FRAME_INFO and DEPRECATED_INIT_FRAME_PC
947 will be called for the new frame.
948
949 For us, the frame address is its stack pointer value, so we look up
950 the function prologue to determine the caller's sp value, and return it. */
951 static CORE_ADDR
952 sh_frame_chain (struct frame_info *frame)
953 {
954 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
955 get_frame_base (frame),
956 get_frame_base (frame)))
957 return get_frame_base (frame); /* dummy frame same as caller's frame */
958 if (get_frame_pc (frame) && !inside_entry_file (get_frame_pc (frame)))
959 return read_memory_integer (get_frame_base (frame)
960 + get_frame_extra_info (frame)->f_offset, 4);
961 else
962 return 0;
963 }
964
965 /* Given a register number RN as it appears in an assembly
966 instruction, find the corresponding register number in the GDB
967 scheme. */
968 static int
969 translate_insn_rn (int rn, int media_mode)
970 {
971 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
972
973 /* FIXME: this assumes that the number rn is for a not pseudo
974 register only. */
975 if (media_mode)
976 return rn;
977 else
978 {
979 /* These registers don't have a corresponding compact one. */
980 /* FIXME: This is probably not enough. */
981 #if 0
982 if ((rn >= 16 && rn <= 63) || (rn >= 93 && rn <= 140))
983 return rn;
984 #endif
985 if (rn >= 0 && rn <= tdep->R0_C_REGNUM)
986 return tdep->R0_C_REGNUM + rn;
987 else
988 return rn;
989 }
990 }
991
992 static CORE_ADDR
993 sh64_frame_chain (struct frame_info *frame)
994 {
995 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
996 get_frame_base (frame),
997 get_frame_base (frame)))
998 return get_frame_base (frame); /* dummy frame same as caller's frame */
999 if (get_frame_pc (frame) && !inside_entry_file (get_frame_pc (frame)))
1000 {
1001 int media_mode = pc_is_isa32 (get_frame_pc (frame));
1002 int size;
1003 if (gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
1004 size = 4;
1005 else
1006 size = REGISTER_RAW_SIZE (translate_insn_rn (DEPRECATED_FP_REGNUM, media_mode));
1007 return read_memory_integer (get_frame_base (frame)
1008 + get_frame_extra_info (frame)->f_offset,
1009 size);
1010 }
1011 else
1012 return 0;
1013 }
1014
1015 /* Find REGNUM on the stack. Otherwise, it's in an active register. One thing
1016 we might want to do here is to check REGNUM against the clobber mask, and
1017 somehow flag it as invalid if it isn't saved on the stack somewhere. This
1018 would provide a graceful failure mode when trying to get the value of
1019 caller-saves registers for an inner frame. */
1020 static CORE_ADDR
1021 sh_find_callers_reg (struct frame_info *fi, int regnum)
1022 {
1023 for (; fi; fi = get_next_frame (fi))
1024 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
1025 get_frame_base (fi)))
1026 /* When the caller requests PR from the dummy frame, we return PC because
1027 that's where the previous routine appears to have done a call from. */
1028 return deprecated_read_register_dummy (get_frame_pc (fi),
1029 get_frame_base (fi), regnum);
1030 else
1031 {
1032 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
1033 if (!get_frame_pc (fi))
1034 return 0;
1035 if (get_frame_saved_regs (fi)[regnum] != 0)
1036 return read_memory_integer (get_frame_saved_regs (fi)[regnum],
1037 REGISTER_RAW_SIZE (regnum));
1038 }
1039 return read_register (regnum);
1040 }
1041
1042 static CORE_ADDR
1043 sh64_get_saved_pr (struct frame_info *fi, int pr_regnum)
1044 {
1045 int media_mode = 0;
1046
1047 for (; fi; fi = get_next_frame (fi))
1048 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
1049 get_frame_base (fi)))
1050 /* When the caller requests PR from the dummy frame, we return PC because
1051 that's where the previous routine appears to have done a call from. */
1052 return deprecated_read_register_dummy (get_frame_pc (fi),
1053 get_frame_base (fi), pr_regnum);
1054 else
1055 {
1056 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
1057 if (!get_frame_pc (fi))
1058 return 0;
1059
1060 media_mode = pc_is_isa32 (get_frame_pc (fi));
1061
1062 if (get_frame_saved_regs (fi)[pr_regnum] != 0)
1063 {
1064 int gdb_reg_num = translate_insn_rn (pr_regnum, media_mode);
1065 int size = ((gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
1066 ? 4
1067 : REGISTER_RAW_SIZE (gdb_reg_num));
1068 return read_memory_integer (get_frame_saved_regs (fi)[pr_regnum], size);
1069 }
1070 }
1071 return read_register (pr_regnum);
1072 }
1073
1074 /* Put here the code to store, into a struct frame_saved_regs, the
1075 addresses of the saved registers of frame described by FRAME_INFO.
1076 This includes special registers such as pc and fp saved in special
1077 ways in the stack frame. sp is even more special: the address we
1078 return for it IS the sp for the next frame. */
1079 static void
1080 sh_nofp_frame_init_saved_regs (struct frame_info *fi)
1081 {
1082 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof(int));
1083 int rn;
1084 int have_fp = 0;
1085 int depth;
1086 int pc;
1087 int opc;
1088 int insn;
1089 int r3_val = 0;
1090 char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi),
1091 get_frame_base (fi));
1092
1093 if (get_frame_saved_regs (fi) == NULL)
1094 frame_saved_regs_zalloc (fi);
1095 else
1096 memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS);
1097
1098 if (dummy_regs)
1099 {
1100 /* DANGER! This is ONLY going to work if the char buffer format of
1101 the saved registers is byte-for-byte identical to the
1102 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1103 memcpy (get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS);
1104 return;
1105 }
1106
1107 get_frame_extra_info (fi)->leaf_function = 1;
1108 get_frame_extra_info (fi)->f_offset = 0;
1109
1110 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1111 where[rn] = -1;
1112
1113 depth = 0;
1114
1115 /* Loop around examining the prologue insns until we find something
1116 that does not appear to be part of the prologue. But give up
1117 after 20 of them, since we're getting silly then. */
1118
1119 pc = get_frame_func (fi);
1120 if (!pc)
1121 {
1122 deprecated_update_frame_pc_hack (fi, 0);
1123 return;
1124 }
1125
1126 for (opc = pc + (2 * 28); pc < opc; pc += 2)
1127 {
1128 insn = read_memory_integer (pc, 2);
1129 /* See where the registers will be saved to */
1130 if (IS_PUSH (insn))
1131 {
1132 rn = GET_PUSHED_REG (insn);
1133 where[rn] = depth;
1134 depth += 4;
1135 }
1136 else if (IS_STS (insn))
1137 {
1138 where[gdbarch_tdep (current_gdbarch)->PR_REGNUM] = depth;
1139 /* If we're storing the pr then this isn't a leaf */
1140 get_frame_extra_info (fi)->leaf_function = 0;
1141 depth += 4;
1142 }
1143 else if (IS_MOV_R3 (insn))
1144 {
1145 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
1146 }
1147 else if (IS_SHLL_R3 (insn))
1148 {
1149 r3_val <<= 1;
1150 }
1151 else if (IS_ADD_R3SP (insn))
1152 {
1153 depth += -r3_val;
1154 }
1155 else if (IS_ADD_SP (insn))
1156 {
1157 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1158 }
1159 else if (IS_MOV_SP_FP (insn))
1160 break;
1161 #if 0 /* This used to just stop when it found an instruction that
1162 was not considered part of the prologue. Now, we just
1163 keep going looking for likely instructions. */
1164 else
1165 break;
1166 #endif
1167 }
1168
1169 /* Now we know how deep things are, we can work out their addresses */
1170
1171 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1172 {
1173 if (where[rn] >= 0)
1174 {
1175 if (rn == DEPRECATED_FP_REGNUM)
1176 have_fp = 1;
1177
1178 get_frame_saved_regs (fi)[rn] = get_frame_base (fi) - where[rn] + depth - 4;
1179 }
1180 else
1181 {
1182 get_frame_saved_regs (fi)[rn] = 0;
1183 }
1184 }
1185
1186 if (have_fp)
1187 {
1188 get_frame_saved_regs (fi)[SP_REGNUM] = read_memory_integer (get_frame_saved_regs (fi)[DEPRECATED_FP_REGNUM], 4);
1189 }
1190 else
1191 {
1192 get_frame_saved_regs (fi)[SP_REGNUM] = get_frame_base (fi) - 4;
1193 }
1194
1195 get_frame_extra_info (fi)->f_offset = depth - where[DEPRECATED_FP_REGNUM] - 4;
1196 /* Work out the return pc - either from the saved pr or the pr
1197 value */
1198 }
1199
1200 /* For vectors of 4 floating point registers. */
1201 static int
1202 fv_reg_base_num (int fv_regnum)
1203 {
1204 int fp_regnum;
1205
1206 fp_regnum = FP0_REGNUM +
1207 (fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM) * 4;
1208 return fp_regnum;
1209 }
1210
1211 /* For double precision floating point registers, i.e 2 fp regs.*/
1212 static int
1213 dr_reg_base_num (int dr_regnum)
1214 {
1215 int fp_regnum;
1216
1217 fp_regnum = FP0_REGNUM +
1218 (dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM) * 2;
1219 return fp_regnum;
1220 }
1221
1222 /* For pairs of floating point registers */
1223 static int
1224 fpp_reg_base_num (int fpp_regnum)
1225 {
1226 int fp_regnum;
1227
1228 fp_regnum = FP0_REGNUM +
1229 (fpp_regnum - gdbarch_tdep (current_gdbarch)->FPP0_REGNUM) * 2;
1230 return fp_regnum;
1231 }
1232
1233 static int
1234 is_media_pseudo (int rn)
1235 {
1236 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1237
1238 return (rn >= tdep->DR0_REGNUM
1239 && rn <= tdep->FV_LAST_REGNUM);
1240 }
1241
1242 static int
1243 sh64_get_gdb_regnum (int gcc_regnum, CORE_ADDR pc)
1244 {
1245 return translate_insn_rn (gcc_regnum, pc_is_isa32 (pc));
1246 }
1247
1248 static int
1249 sh64_media_reg_base_num (int reg_nr)
1250 {
1251 int base_regnum = -1;
1252 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1253
1254 if (reg_nr >= tdep->DR0_REGNUM
1255 && reg_nr <= tdep->DR_LAST_REGNUM)
1256 base_regnum = dr_reg_base_num (reg_nr);
1257
1258 else if (reg_nr >= tdep->FPP0_REGNUM
1259 && reg_nr <= tdep->FPP_LAST_REGNUM)
1260 base_regnum = fpp_reg_base_num (reg_nr);
1261
1262 else if (reg_nr >= tdep->FV0_REGNUM
1263 && reg_nr <= tdep->FV_LAST_REGNUM)
1264 base_regnum = fv_reg_base_num (reg_nr);
1265
1266 return base_regnum;
1267 }
1268
1269 /* *INDENT-OFF* */
1270 /*
1271 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1272 GDB_REGNUM BASE_REGNUM
1273 r0_c 221 0
1274 r1_c 222 1
1275 r2_c 223 2
1276 r3_c 224 3
1277 r4_c 225 4
1278 r5_c 226 5
1279 r6_c 227 6
1280 r7_c 228 7
1281 r8_c 229 8
1282 r9_c 230 9
1283 r10_c 231 10
1284 r11_c 232 11
1285 r12_c 233 12
1286 r13_c 234 13
1287 r14_c 235 14
1288 r15_c 236 15
1289
1290 pc_c 237 64
1291 gbr_c 238 16
1292 mach_c 239 17
1293 macl_c 240 17
1294 pr_c 241 18
1295 t_c 242 19
1296 fpscr_c 243 76
1297 fpul_c 244 109
1298
1299 fr0_c 245 77
1300 fr1_c 246 78
1301 fr2_c 247 79
1302 fr3_c 248 80
1303 fr4_c 249 81
1304 fr5_c 250 82
1305 fr6_c 251 83
1306 fr7_c 252 84
1307 fr8_c 253 85
1308 fr9_c 254 86
1309 fr10_c 255 87
1310 fr11_c 256 88
1311 fr12_c 257 89
1312 fr13_c 258 90
1313 fr14_c 259 91
1314 fr15_c 260 92
1315
1316 dr0_c 261 77
1317 dr2_c 262 79
1318 dr4_c 263 81
1319 dr6_c 264 83
1320 dr8_c 265 85
1321 dr10_c 266 87
1322 dr12_c 267 89
1323 dr14_c 268 91
1324
1325 fv0_c 269 77
1326 fv4_c 270 81
1327 fv8_c 271 85
1328 fv12_c 272 91
1329 */
1330 /* *INDENT-ON* */
1331 static int
1332 sh64_compact_reg_base_num (int reg_nr)
1333 {
1334 int base_regnum = -1;
1335 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1336
1337 /* general register N maps to general register N */
1338 if (reg_nr >= tdep->R0_C_REGNUM
1339 && reg_nr <= tdep->R_LAST_C_REGNUM)
1340 base_regnum = reg_nr - tdep->R0_C_REGNUM;
1341
1342 /* floating point register N maps to floating point register N */
1343 else if (reg_nr >= tdep->FP0_C_REGNUM
1344 && reg_nr <= tdep->FP_LAST_C_REGNUM)
1345 base_regnum = reg_nr - tdep->FP0_C_REGNUM + FP0_REGNUM;
1346
1347 /* double prec register N maps to base regnum for double prec register N */
1348 else if (reg_nr >= tdep->DR0_C_REGNUM
1349 && reg_nr <= tdep->DR_LAST_C_REGNUM)
1350 base_regnum = dr_reg_base_num (tdep->DR0_REGNUM
1351 + reg_nr - tdep->DR0_C_REGNUM);
1352
1353 /* vector N maps to base regnum for vector register N */
1354 else if (reg_nr >= tdep->FV0_C_REGNUM
1355 && reg_nr <= tdep->FV_LAST_C_REGNUM)
1356 base_regnum = fv_reg_base_num (tdep->FV0_REGNUM
1357 + reg_nr - tdep->FV0_C_REGNUM);
1358
1359 else if (reg_nr == tdep->PC_C_REGNUM)
1360 base_regnum = PC_REGNUM;
1361
1362 else if (reg_nr == tdep->GBR_C_REGNUM)
1363 base_regnum = 16;
1364
1365 else if (reg_nr == tdep->MACH_C_REGNUM
1366 || reg_nr == tdep->MACL_C_REGNUM)
1367 base_regnum = 17;
1368
1369 else if (reg_nr == tdep->PR_C_REGNUM)
1370 base_regnum = 18;
1371
1372 else if (reg_nr == tdep->T_C_REGNUM)
1373 base_regnum = 19;
1374
1375 else if (reg_nr == tdep->FPSCR_C_REGNUM)
1376 base_regnum = tdep->FPSCR_REGNUM; /*???? this register is a mess. */
1377
1378 else if (reg_nr == tdep->FPUL_C_REGNUM)
1379 base_regnum = FP0_REGNUM + 32;
1380
1381 return base_regnum;
1382 }
1383
1384 /* Given a register number RN (according to the gdb scheme) , return
1385 its corresponding architectural register. In media mode, only a
1386 subset of the registers is pseudo registers. For compact mode, all
1387 the registers are pseudo. */
1388 static int
1389 translate_rn_to_arch_reg_num (int rn, int media_mode)
1390 {
1391
1392 if (media_mode)
1393 {
1394 if (!is_media_pseudo (rn))
1395 return rn;
1396 else
1397 return sh64_media_reg_base_num (rn);
1398 }
1399 else
1400 /* All compact registers are pseudo. */
1401 return sh64_compact_reg_base_num (rn);
1402 }
1403
1404 static int
1405 sign_extend (int value, int bits)
1406 {
1407 value = value & ((1 << bits) - 1);
1408 return (value & (1 << (bits - 1))
1409 ? value | (~((1 << bits) - 1))
1410 : value);
1411 }
1412
1413 static void
1414 sh64_nofp_frame_init_saved_regs (struct frame_info *fi)
1415 {
1416 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int));
1417 int rn;
1418 int have_fp = 0;
1419 int fp_regnum;
1420 int sp_regnum;
1421 int depth;
1422 int pc;
1423 int opc;
1424 int insn;
1425 int r0_val = 0;
1426 int media_mode = 0;
1427 int insn_size;
1428 int gdb_register_number;
1429 int register_number;
1430 char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi), get_frame_base (fi));
1431 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1432
1433 if (get_frame_saved_regs (fi) == NULL)
1434 frame_saved_regs_zalloc (fi);
1435 else
1436 memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS);
1437
1438 if (dummy_regs)
1439 {
1440 /* DANGER! This is ONLY going to work if the char buffer format of
1441 the saved registers is byte-for-byte identical to the
1442 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1443 memcpy (get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS);
1444 return;
1445 }
1446
1447 get_frame_extra_info (fi)->leaf_function = 1;
1448 get_frame_extra_info (fi)->f_offset = 0;
1449
1450 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1451 where[rn] = -1;
1452
1453 depth = 0;
1454
1455 /* Loop around examining the prologue insns until we find something
1456 that does not appear to be part of the prologue. But give up
1457 after 20 of them, since we're getting silly then. */
1458
1459 pc = get_frame_func (fi);
1460 if (!pc)
1461 {
1462 deprecated_update_frame_pc_hack (fi, 0);
1463 return;
1464 }
1465
1466 if (pc_is_isa32 (pc))
1467 {
1468 media_mode = 1;
1469 insn_size = 4;
1470 }
1471 else
1472 {
1473 media_mode = 0;
1474 insn_size = 2;
1475 }
1476
1477 /* The frame pointer register is general register 14 in shmedia and
1478 shcompact modes. In sh compact it is a pseudo register. Same goes
1479 for the stack pointer register, which is register 15. */
1480 fp_regnum = translate_insn_rn (DEPRECATED_FP_REGNUM, media_mode);
1481 sp_regnum = translate_insn_rn (SP_REGNUM, media_mode);
1482
1483 for (opc = pc + (insn_size * 28); pc < opc; pc += insn_size)
1484 {
1485 insn = read_memory_integer (media_mode ? UNMAKE_ISA32_ADDR (pc) : pc,
1486 insn_size);
1487
1488 if (media_mode == 0)
1489 {
1490 if (IS_STS_PR (insn))
1491 {
1492 int next_insn = read_memory_integer (pc + insn_size, insn_size);
1493 if (IS_MOV_TO_R15 (next_insn))
1494 {
1495 int reg_nr = tdep->PR_C_REGNUM;
1496
1497 where[reg_nr] = depth - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2);
1498 get_frame_extra_info (fi)->leaf_function = 0;
1499 pc += insn_size;
1500 }
1501 }
1502 else if (IS_MOV_R14 (insn))
1503 {
1504 where[fp_regnum] = depth - ((((insn & 0xf) ^ 0x8) - 0x8) << 2);
1505 }
1506
1507 else if (IS_MOV_R0 (insn))
1508 {
1509 /* Put in R0 the offset from SP at which to store some
1510 registers. We are interested in this value, because it
1511 will tell us where the given registers are stored within
1512 the frame. */
1513 r0_val = ((insn & 0xff) ^ 0x80) - 0x80;
1514 }
1515 else if (IS_ADD_SP_R0 (insn))
1516 {
1517 /* This instruction still prepares r0, but we don't care.
1518 We already have the offset in r0_val. */
1519 }
1520 else if (IS_STS_R0 (insn))
1521 {
1522 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
1523 int reg_nr = tdep->PR_C_REGNUM;
1524 where[reg_nr] = depth - (r0_val - 4);
1525 r0_val -= 4;
1526 get_frame_extra_info (fi)->leaf_function = 0;
1527 }
1528 else if (IS_MOV_R14_R0 (insn))
1529 {
1530 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
1531 where[fp_regnum] = depth - (r0_val - 4);
1532 r0_val -= 4;
1533 }
1534
1535 else if (IS_ADD_SP (insn))
1536 {
1537 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1538 }
1539 else if (IS_MOV_SP_FP (insn))
1540 break;
1541 }
1542 else
1543 {
1544 if (IS_ADDIL_SP_MEDIA (insn)
1545 || IS_ADDI_SP_MEDIA (insn))
1546 {
1547 depth -= sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
1548 }
1549
1550 else if (IS_STQ_R18_R15 (insn))
1551 {
1552 where[tdep->PR_REGNUM] =
1553 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1554 get_frame_extra_info (fi)->leaf_function = 0;
1555 }
1556
1557 else if (IS_STL_R18_R15 (insn))
1558 {
1559 where[tdep->PR_REGNUM] =
1560 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1561 get_frame_extra_info (fi)->leaf_function = 0;
1562 }
1563
1564 else if (IS_STQ_R14_R15 (insn))
1565 {
1566 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1567 }
1568
1569 else if (IS_STL_R14_R15 (insn))
1570 {
1571 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1572 }
1573
1574 else if (IS_MOV_SP_FP_MEDIA (insn))
1575 break;
1576 }
1577 }
1578
1579 /* Now we know how deep things are, we can work out their addresses. */
1580 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1581 {
1582 register_number = translate_rn_to_arch_reg_num (rn, media_mode);
1583
1584 if (where[rn] >= 0)
1585 {
1586 if (rn == fp_regnum)
1587 have_fp = 1;
1588
1589 /* Watch out! saved_regs is only for the real registers, and
1590 doesn't include space for the pseudo registers. */
1591 get_frame_saved_regs (fi)[register_number]= get_frame_base (fi) - where[rn] + depth;
1592
1593 }
1594 else
1595 get_frame_saved_regs (fi)[register_number] = 0;
1596 }
1597
1598 if (have_fp)
1599 {
1600 /* SP_REGNUM is 15. For shmedia 15 is the real register. For
1601 shcompact 15 is the arch register corresponding to the pseudo
1602 register r15 which still is the SP register. */
1603 /* The place on the stack where fp is stored contains the sp of
1604 the caller. */
1605 /* Again, saved_registers contains only space for the real
1606 registers, so we store in DEPRECATED_FP_REGNUM position. */
1607 int size;
1608 if (tdep->sh_abi == SH_ABI_32)
1609 size = 4;
1610 else
1611 size = REGISTER_RAW_SIZE (fp_regnum);
1612 get_frame_saved_regs (fi)[sp_regnum] = read_memory_integer (get_frame_saved_regs (fi)[fp_regnum], size);
1613 }
1614 else
1615 get_frame_saved_regs (fi)[sp_regnum] = get_frame_base (fi);
1616
1617 get_frame_extra_info (fi)->f_offset = depth - where[fp_regnum];
1618 }
1619
1620 static void
1621 sh_fp_frame_init_saved_regs (struct frame_info *fi)
1622 {
1623 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int));
1624 int rn;
1625 int have_fp = 0;
1626 int depth;
1627 int pc;
1628 int opc;
1629 int insn;
1630 int r3_val = 0;
1631 char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi), get_frame_base (fi));
1632 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1633
1634 if (get_frame_saved_regs (fi) == NULL)
1635 frame_saved_regs_zalloc (fi);
1636 else
1637 memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS);
1638
1639 if (dummy_regs)
1640 {
1641 /* DANGER! This is ONLY going to work if the char buffer format of
1642 the saved registers is byte-for-byte identical to the
1643 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1644 memcpy (get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS);
1645 return;
1646 }
1647
1648 get_frame_extra_info (fi)->leaf_function = 1;
1649 get_frame_extra_info (fi)->f_offset = 0;
1650
1651 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1652 where[rn] = -1;
1653
1654 depth = 0;
1655
1656 /* Loop around examining the prologue insns until we find something
1657 that does not appear to be part of the prologue. But give up
1658 after 20 of them, since we're getting silly then. */
1659
1660 pc = get_frame_func (fi);
1661 if (!pc)
1662 {
1663 deprecated_update_frame_pc_hack (fi, 0);
1664 return;
1665 }
1666
1667 for (opc = pc + (2 * 28); pc < opc; pc += 2)
1668 {
1669 insn = read_memory_integer (pc, 2);
1670 /* See where the registers will be saved to */
1671 if (IS_PUSH (insn))
1672 {
1673 rn = GET_PUSHED_REG (insn);
1674 where[rn] = depth;
1675 depth += 4;
1676 }
1677 else if (IS_STS (insn))
1678 {
1679 where[tdep->PR_REGNUM] = depth;
1680 /* If we're storing the pr then this isn't a leaf */
1681 get_frame_extra_info (fi)->leaf_function = 0;
1682 depth += 4;
1683 }
1684 else if (IS_MOV_R3 (insn))
1685 {
1686 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
1687 }
1688 else if (IS_SHLL_R3 (insn))
1689 {
1690 r3_val <<= 1;
1691 }
1692 else if (IS_ADD_R3SP (insn))
1693 {
1694 depth += -r3_val;
1695 }
1696 else if (IS_ADD_SP (insn))
1697 {
1698 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1699 }
1700 else if (IS_FMOV (insn))
1701 {
1702 if (read_register (tdep->FPSCR_REGNUM) & FPSCR_SZ)
1703 {
1704 depth += 8;
1705 }
1706 else
1707 {
1708 depth += 4;
1709 }
1710 }
1711 else if (IS_MOV_SP_FP (insn))
1712 break;
1713 #if 0 /* This used to just stop when it found an instruction that
1714 was not considered part of the prologue. Now, we just
1715 keep going looking for likely instructions. */
1716 else
1717 break;
1718 #endif
1719 }
1720
1721 /* Now we know how deep things are, we can work out their addresses */
1722
1723 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1724 {
1725 if (where[rn] >= 0)
1726 {
1727 if (rn == DEPRECATED_FP_REGNUM)
1728 have_fp = 1;
1729
1730 get_frame_saved_regs (fi)[rn] = get_frame_base (fi) - where[rn] + depth - 4;
1731 }
1732 else
1733 {
1734 get_frame_saved_regs (fi)[rn] = 0;
1735 }
1736 }
1737
1738 if (have_fp)
1739 {
1740 get_frame_saved_regs (fi)[SP_REGNUM] =
1741 read_memory_integer (get_frame_saved_regs (fi)[DEPRECATED_FP_REGNUM], 4);
1742 }
1743 else
1744 {
1745 get_frame_saved_regs (fi)[SP_REGNUM] = get_frame_base (fi) - 4;
1746 }
1747
1748 get_frame_extra_info (fi)->f_offset = depth - where[DEPRECATED_FP_REGNUM] - 4;
1749 /* Work out the return pc - either from the saved pr or the pr
1750 value */
1751 }
1752
1753 /* Initialize the extra info saved in a FRAME */
1754 static void
1755 sh_init_extra_frame_info (int fromleaf, struct frame_info *fi)
1756 {
1757
1758 frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info));
1759
1760 if (get_next_frame (fi))
1761 deprecated_update_frame_pc_hack (fi, DEPRECATED_FRAME_SAVED_PC (get_next_frame (fi)));
1762
1763 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
1764 get_frame_base (fi)))
1765 {
1766 /* We need to setup fi->frame here because call_function_by_hand
1767 gets it wrong by assuming it's always FP. */
1768 deprecated_update_frame_base_hack (fi, deprecated_read_register_dummy (get_frame_pc (fi), get_frame_base (fi),
1769 SP_REGNUM));
1770 get_frame_extra_info (fi)->return_pc = deprecated_read_register_dummy (get_frame_pc (fi),
1771 get_frame_base (fi),
1772 PC_REGNUM);
1773 get_frame_extra_info (fi)->f_offset = -(DEPRECATED_CALL_DUMMY_LENGTH + 4);
1774 get_frame_extra_info (fi)->leaf_function = 0;
1775 return;
1776 }
1777 else
1778 {
1779 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
1780 get_frame_extra_info (fi)->return_pc =
1781 sh_find_callers_reg (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM);
1782 }
1783 }
1784
1785 static void
1786 sh64_init_extra_frame_info (int fromleaf, struct frame_info *fi)
1787 {
1788 int media_mode = pc_is_isa32 (get_frame_pc (fi));
1789
1790 frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info));
1791
1792 if (get_next_frame (fi))
1793 deprecated_update_frame_pc_hack (fi, DEPRECATED_FRAME_SAVED_PC (get_next_frame (fi)));
1794
1795 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
1796 get_frame_base (fi)))
1797 {
1798 /* We need to setup fi->frame here because call_function_by_hand
1799 gets it wrong by assuming it's always FP. */
1800 deprecated_update_frame_base_hack (fi, deprecated_read_register_dummy (get_frame_pc (fi), get_frame_base (fi), SP_REGNUM));
1801 get_frame_extra_info (fi)->return_pc =
1802 deprecated_read_register_dummy (get_frame_pc (fi),
1803 get_frame_base (fi), PC_REGNUM);
1804 get_frame_extra_info (fi)->f_offset = -(DEPRECATED_CALL_DUMMY_LENGTH + 4);
1805 get_frame_extra_info (fi)->leaf_function = 0;
1806 return;
1807 }
1808 else
1809 {
1810 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
1811 get_frame_extra_info (fi)->return_pc =
1812 sh64_get_saved_pr (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM);
1813 }
1814 }
1815
1816 static void
1817 sh64_get_saved_register (char *raw_buffer, int *optimized, CORE_ADDR *addrp,
1818 struct frame_info *frame, int regnum,
1819 enum lval_type *lval)
1820 {
1821 int media_mode;
1822 int live_regnum = regnum;
1823 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1824
1825 if (!target_has_registers)
1826 error ("No registers.");
1827
1828 /* Normal systems don't optimize out things with register numbers. */
1829 if (optimized != NULL)
1830 *optimized = 0;
1831
1832 if (addrp) /* default assumption: not found in memory */
1833 *addrp = 0;
1834
1835 if (raw_buffer)
1836 memset (raw_buffer, 0, sizeof (raw_buffer));
1837
1838 /* We must do this here, before the following while loop changes
1839 frame, and makes it NULL. If this is a media register number,
1840 but we are in compact mode, it will become the corresponding
1841 compact pseudo register. If there is no corresponding compact
1842 pseudo-register what do we do?*/
1843 media_mode = pc_is_isa32 (get_frame_pc (frame));
1844 live_regnum = translate_insn_rn (regnum, media_mode);
1845
1846 /* Note: since the current frame's registers could only have been
1847 saved by frames INTERIOR TO the current frame, we skip examining
1848 the current frame itself: otherwise, we would be getting the
1849 previous frame's registers which were saved by the current frame. */
1850
1851 while (frame && ((frame = get_next_frame (frame)) != NULL))
1852 {
1853 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
1854 get_frame_base (frame),
1855 get_frame_base (frame)))
1856 {
1857 if (lval) /* found it in a CALL_DUMMY frame */
1858 *lval = not_lval;
1859 if (raw_buffer)
1860 memcpy (raw_buffer,
1861 (deprecated_generic_find_dummy_frame (get_frame_pc (frame), get_frame_base (frame))
1862 + REGISTER_BYTE (regnum)),
1863 REGISTER_RAW_SIZE (regnum));
1864 return;
1865 }
1866
1867 DEPRECATED_FRAME_INIT_SAVED_REGS (frame);
1868 if (get_frame_saved_regs (frame) != NULL
1869 && get_frame_saved_regs (frame)[regnum] != 0)
1870 {
1871 if (lval) /* found it saved on the stack */
1872 *lval = lval_memory;
1873 if (regnum == SP_REGNUM)
1874 {
1875 if (raw_buffer) /* SP register treated specially */
1876 store_unsigned_integer (raw_buffer, REGISTER_RAW_SIZE (regnum),
1877 get_frame_saved_regs (frame)[regnum]);
1878 }
1879 else
1880 { /* any other register */
1881
1882 if (addrp)
1883 *addrp = get_frame_saved_regs (frame)[regnum];
1884 if (raw_buffer)
1885 {
1886 int size;
1887 if (tdep->sh_abi == SH_ABI_32
1888 && (live_regnum == DEPRECATED_FP_REGNUM
1889 || live_regnum == tdep->PR_REGNUM))
1890 size = 4;
1891 else
1892 size = REGISTER_RAW_SIZE (live_regnum);
1893 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1894 read_memory (get_frame_saved_regs (frame)[regnum], raw_buffer, size);
1895 else
1896 read_memory (get_frame_saved_regs (frame)[regnum],
1897 raw_buffer
1898 + REGISTER_RAW_SIZE (live_regnum)
1899 - size,
1900 size);
1901 }
1902 }
1903 return;
1904 }
1905 }
1906
1907 /* If we get thru the loop to this point, it means the register was
1908 not saved in any frame. Return the actual live-register value. */
1909
1910 if (lval) /* found it in a live register */
1911 *lval = lval_register;
1912 if (addrp)
1913 *addrp = REGISTER_BYTE (live_regnum);
1914 if (raw_buffer)
1915 deprecated_read_register_gen (live_regnum, raw_buffer);
1916 }
1917
1918 /* Extract from an array REGBUF containing the (raw) register state
1919 the address in which a function should return its structure value,
1920 as a CORE_ADDR (or an expression that can be used as one). */
1921 static CORE_ADDR
1922 sh_extract_struct_value_address (char *regbuf)
1923 {
1924 return (extract_unsigned_integer ((regbuf), REGISTER_RAW_SIZE (0)));
1925 }
1926
1927 static CORE_ADDR
1928 sh64_extract_struct_value_address (char *regbuf)
1929 {
1930 return (extract_unsigned_integer ((regbuf + REGISTER_BYTE (STRUCT_RETURN_REGNUM)),
1931 REGISTER_RAW_SIZE (STRUCT_RETURN_REGNUM)));
1932 }
1933
1934 static CORE_ADDR
1935 sh_frame_saved_pc (struct frame_info *frame)
1936 {
1937 return (get_frame_extra_info (frame)->return_pc);
1938 }
1939
1940 /* Discard from the stack the innermost frame,
1941 restoring all saved registers. */
1942 static void
1943 sh_pop_frame (void)
1944 {
1945 register struct frame_info *frame = get_current_frame ();
1946 register CORE_ADDR fp;
1947 register int regnum;
1948
1949 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
1950 get_frame_base (frame),
1951 get_frame_base (frame)))
1952 generic_pop_dummy_frame ();
1953 else
1954 {
1955 fp = get_frame_base (frame);
1956 DEPRECATED_FRAME_INIT_SAVED_REGS (frame);
1957
1958 /* Copy regs from where they were saved in the frame */
1959 for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
1960 if (get_frame_saved_regs (frame)[regnum])
1961 write_register (regnum,
1962 read_memory_integer (get_frame_saved_regs (frame)[regnum], 4));
1963
1964 write_register (PC_REGNUM, get_frame_extra_info (frame)->return_pc);
1965 write_register (SP_REGNUM, fp + 4);
1966 }
1967 flush_cached_frames ();
1968 }
1969
1970 /* Used in the 'return' command. */
1971 static void
1972 sh64_pop_frame (void)
1973 {
1974 register struct frame_info *frame = get_current_frame ();
1975 register CORE_ADDR fp;
1976 register int regnum;
1977 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1978
1979 int media_mode = pc_is_isa32 (get_frame_pc (frame));
1980
1981 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
1982 get_frame_base (frame),
1983 get_frame_base (frame)))
1984 generic_pop_dummy_frame ();
1985 else
1986 {
1987 fp = get_frame_base (frame);
1988 DEPRECATED_FRAME_INIT_SAVED_REGS (frame);
1989
1990 /* Copy regs from where they were saved in the frame */
1991 for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
1992 if (get_frame_saved_regs (frame)[regnum])
1993 {
1994 int size;
1995 if (tdep->sh_abi == SH_ABI_32
1996 && (regnum == DEPRECATED_FP_REGNUM
1997 || regnum == tdep->PR_REGNUM))
1998 size = 4;
1999 else
2000 size = REGISTER_RAW_SIZE (translate_insn_rn (regnum,
2001 media_mode));
2002 write_register (regnum,
2003 read_memory_integer (get_frame_saved_regs (frame)[regnum],
2004 size));
2005 }
2006
2007 write_register (PC_REGNUM, get_frame_extra_info (frame)->return_pc);
2008 write_register (SP_REGNUM, fp + 8);
2009 }
2010 flush_cached_frames ();
2011 }
2012
2013 /* Function: push_arguments
2014 Setup the function arguments for calling a function in the inferior.
2015
2016 On the Hitachi SH architecture, there are four registers (R4 to R7)
2017 which are dedicated for passing function arguments. Up to the first
2018 four arguments (depending on size) may go into these registers.
2019 The rest go on the stack.
2020
2021 Arguments that are smaller than 4 bytes will still take up a whole
2022 register or a whole 32-bit word on the stack, and will be
2023 right-justified in the register or the stack word. This includes
2024 chars, shorts, and small aggregate types.
2025
2026 Arguments that are larger than 4 bytes may be split between two or
2027 more registers. If there are not enough registers free, an argument
2028 may be passed partly in a register (or registers), and partly on the
2029 stack. This includes doubles, long longs, and larger aggregates.
2030 As far as I know, there is no upper limit to the size of aggregates
2031 that will be passed in this way; in other words, the convention of
2032 passing a pointer to a large aggregate instead of a copy is not used.
2033
2034 An exceptional case exists for struct arguments (and possibly other
2035 aggregates such as arrays) if the size is larger than 4 bytes but
2036 not a multiple of 4 bytes. In this case the argument is never split
2037 between the registers and the stack, but instead is copied in its
2038 entirety onto the stack, AND also copied into as many registers as
2039 there is room for. In other words, space in registers permitting,
2040 two copies of the same argument are passed in. As far as I can tell,
2041 only the one on the stack is used, although that may be a function
2042 of the level of compiler optimization. I suspect this is a compiler
2043 bug. Arguments of these odd sizes are left-justified within the
2044 word (as opposed to arguments smaller than 4 bytes, which are
2045 right-justified).
2046
2047 If the function is to return an aggregate type such as a struct, it
2048 is either returned in the normal return value register R0 (if its
2049 size is no greater than one byte), or else the caller must allocate
2050 space into which the callee will copy the return value (if the size
2051 is greater than one byte). In this case, a pointer to the return
2052 value location is passed into the callee in register R2, which does
2053 not displace any of the other arguments passed in via registers R4
2054 to R7. */
2055
2056 static CORE_ADDR
2057 sh_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
2058 int struct_return, CORE_ADDR struct_addr)
2059 {
2060 int stack_offset, stack_alloc;
2061 int argreg;
2062 int argnum;
2063 struct type *type;
2064 CORE_ADDR regval;
2065 char *val;
2066 char valbuf[4];
2067 int len;
2068 int odd_sized_struct;
2069 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2070
2071 /* first force sp to a 4-byte alignment */
2072 sp = sp & ~3;
2073
2074 /* The "struct return pointer" pseudo-argument has its own dedicated
2075 register */
2076 if (struct_return)
2077 write_register (STRUCT_RETURN_REGNUM, struct_addr);
2078
2079 /* Now make sure there's space on the stack */
2080 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
2081 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
2082 sp -= stack_alloc; /* make room on stack for args */
2083
2084 /* Now load as many as possible of the first arguments into
2085 registers, and push the rest onto the stack. There are 16 bytes
2086 in four registers available. Loop thru args from first to last. */
2087
2088 argreg = tdep->ARG0_REGNUM;
2089 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
2090 {
2091 type = VALUE_TYPE (args[argnum]);
2092 len = TYPE_LENGTH (type);
2093 memset (valbuf, 0, sizeof (valbuf));
2094 if (len < 4)
2095 {
2096 /* value gets right-justified in the register or stack word */
2097 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2098 memcpy (valbuf + (4 - len),
2099 (char *) VALUE_CONTENTS (args[argnum]), len);
2100 else
2101 memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
2102 val = valbuf;
2103 }
2104 else
2105 val = (char *) VALUE_CONTENTS (args[argnum]);
2106
2107 if (len > 4 && (len & 3) != 0)
2108 odd_sized_struct = 1; /* such structs go entirely on stack */
2109 else
2110 odd_sized_struct = 0;
2111 while (len > 0)
2112 {
2113 if (argreg > tdep->ARGLAST_REGNUM
2114 || odd_sized_struct)
2115 {
2116 /* must go on the stack */
2117 write_memory (sp + stack_offset, val, 4);
2118 stack_offset += 4;
2119 }
2120 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2121 That's because some *&^%$ things get passed on the stack
2122 AND in the registers! */
2123 if (argreg <= tdep->ARGLAST_REGNUM)
2124 {
2125 /* there's room in a register */
2126 regval = extract_unsigned_integer (val, REGISTER_RAW_SIZE (argreg));
2127 write_register (argreg++, regval);
2128 }
2129 /* Store the value 4 bytes at a time. This means that things
2130 larger than 4 bytes may go partly in registers and partly
2131 on the stack. */
2132 len -= REGISTER_RAW_SIZE (argreg);
2133 val += REGISTER_RAW_SIZE (argreg);
2134 }
2135 }
2136 return sp;
2137 }
2138
2139 /* R2-R9 for integer types and integer equivalent (char, pointers) and
2140 non-scalar (struct, union) elements (even if the elements are
2141 floats).
2142 FR0-FR11 for single precision floating point (float)
2143 DR0-DR10 for double precision floating point (double)
2144
2145 If a float is argument number 3 (for instance) and arguments number
2146 1,2, and 4 are integer, the mapping will be:
2147 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
2148
2149 If a float is argument number 10 (for instance) and arguments number
2150 1 through 10 are integer, the mapping will be:
2151 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
2152 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
2153 I.e. there is hole in the stack.
2154
2155 Different rules apply for variable arguments functions, and for functions
2156 for which the prototype is not known. */
2157
2158 static CORE_ADDR
2159 sh64_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
2160 int struct_return, CORE_ADDR struct_addr)
2161 {
2162 int stack_offset, stack_alloc;
2163 int int_argreg;
2164 int float_argreg;
2165 int double_argreg;
2166 int float_arg_index = 0;
2167 int double_arg_index = 0;
2168 int argnum;
2169 struct type *type;
2170 CORE_ADDR regval;
2171 char *val;
2172 char valbuf[8];
2173 char valbuf_tmp[8];
2174 int len;
2175 int argreg_size;
2176 int fp_args[12];
2177 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2178
2179 memset (fp_args, 0, sizeof (fp_args));
2180
2181 /* first force sp to a 8-byte alignment */
2182 sp = sp & ~7;
2183
2184 /* The "struct return pointer" pseudo-argument has its own dedicated
2185 register */
2186
2187 if (struct_return)
2188 write_register (STRUCT_RETURN_REGNUM, struct_addr);
2189
2190 /* Now make sure there's space on the stack */
2191 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
2192 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 7) & ~7);
2193 sp -= stack_alloc; /* make room on stack for args */
2194
2195 /* Now load as many as possible of the first arguments into
2196 registers, and push the rest onto the stack. There are 64 bytes
2197 in eight registers available. Loop thru args from first to last. */
2198
2199 int_argreg = tdep->ARG0_REGNUM;
2200 float_argreg = FP0_REGNUM;
2201 double_argreg = tdep->DR0_REGNUM;
2202
2203 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
2204 {
2205 type = VALUE_TYPE (args[argnum]);
2206 len = TYPE_LENGTH (type);
2207 memset (valbuf, 0, sizeof (valbuf));
2208
2209 if (TYPE_CODE (type) != TYPE_CODE_FLT)
2210 {
2211 argreg_size = REGISTER_RAW_SIZE (int_argreg);
2212
2213 if (len < argreg_size)
2214 {
2215 /* value gets right-justified in the register or stack word */
2216 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2217 memcpy (valbuf + argreg_size - len,
2218 (char *) VALUE_CONTENTS (args[argnum]), len);
2219 else
2220 memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
2221
2222 val = valbuf;
2223 }
2224 else
2225 val = (char *) VALUE_CONTENTS (args[argnum]);
2226
2227 while (len > 0)
2228 {
2229 if (int_argreg > tdep->ARGLAST_REGNUM)
2230 {
2231 /* must go on the stack */
2232 write_memory (sp + stack_offset, val, argreg_size);
2233 stack_offset += 8;/*argreg_size;*/
2234 }
2235 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2236 That's because some *&^%$ things get passed on the stack
2237 AND in the registers! */
2238 if (int_argreg <= tdep->ARGLAST_REGNUM)
2239 {
2240 /* there's room in a register */
2241 regval = extract_unsigned_integer (val, argreg_size);
2242 write_register (int_argreg, regval);
2243 }
2244 /* Store the value 8 bytes at a time. This means that
2245 things larger than 8 bytes may go partly in registers
2246 and partly on the stack. FIXME: argreg is incremented
2247 before we use its size. */
2248 len -= argreg_size;
2249 val += argreg_size;
2250 int_argreg++;
2251 }
2252 }
2253 else
2254 {
2255 val = (char *) VALUE_CONTENTS (args[argnum]);
2256 if (len == 4)
2257 {
2258 /* Where is it going to be stored? */
2259 while (fp_args[float_arg_index])
2260 float_arg_index ++;
2261
2262 /* Now float_argreg points to the register where it
2263 should be stored. Are we still within the allowed
2264 register set? */
2265 if (float_arg_index <= tdep->FLOAT_ARGLAST_REGNUM)
2266 {
2267 /* Goes in FR0...FR11 */
2268 deprecated_write_register_gen (FP0_REGNUM + float_arg_index,
2269 val);
2270 fp_args[float_arg_index] = 1;
2271 /* Skip the corresponding general argument register. */
2272 int_argreg ++;
2273 }
2274 else
2275 ;
2276 /* Store it as the integers, 8 bytes at the time, if
2277 necessary spilling on the stack. */
2278
2279 }
2280 else if (len == 8)
2281 {
2282 /* Where is it going to be stored? */
2283 while (fp_args[double_arg_index])
2284 double_arg_index += 2;
2285 /* Now double_argreg points to the register
2286 where it should be stored.
2287 Are we still within the allowed register set? */
2288 if (double_arg_index < tdep->FLOAT_ARGLAST_REGNUM)
2289 {
2290 /* Goes in DR0...DR10 */
2291 /* The numbering of the DRi registers is consecutive,
2292 i.e. includes odd numbers. */
2293 int double_register_offset = double_arg_index / 2;
2294 int regnum = tdep->DR0_REGNUM +
2295 double_register_offset;
2296 #if 0
2297 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2298 {
2299 memset (valbuf_tmp, 0, sizeof (valbuf_tmp));
2300 DEPRECATED_REGISTER_CONVERT_TO_VIRTUAL (regnum,
2301 type, val,
2302 valbuf_tmp);
2303 val = valbuf_tmp;
2304 }
2305 #endif
2306 /* Note: must use write_register_gen here instead
2307 of regcache_raw_write, because
2308 regcache_raw_write works only for real
2309 registers, not pseudo. write_register_gen will
2310 call the gdbarch function to do register
2311 writes, and that will properly know how to deal
2312 with pseudoregs. */
2313 deprecated_write_register_gen (regnum, val);
2314 fp_args[double_arg_index] = 1;
2315 fp_args[double_arg_index + 1] = 1;
2316 /* Skip the corresponding general argument register. */
2317 int_argreg ++;
2318 }
2319 else
2320 ;
2321 /* Store it as the integers, 8 bytes at the time, if
2322 necessary spilling on the stack. */
2323 }
2324 }
2325 }
2326 return sp;
2327 }
2328
2329 /* Function: push_return_address (pc)
2330 Set up the return address for the inferior function call.
2331 Needed for targets where we don't actually execute a JSR/BSR instruction */
2332
2333 static CORE_ADDR
2334 sh_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
2335 {
2336 write_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM,
2337 CALL_DUMMY_ADDRESS ());
2338 return sp;
2339 }
2340
2341 /* Function: fix_call_dummy
2342 Poke the callee function's address into the destination part of
2343 the CALL_DUMMY. The address is actually stored in a data word
2344 following the actualy CALL_DUMMY instructions, which will load
2345 it into a register using PC-relative addressing. This function
2346 expects the CALL_DUMMY to look like this:
2347
2348 mov.w @(2,PC), R8
2349 jsr @R8
2350 nop
2351 trap
2352 <destination>
2353 */
2354
2355 #if 0
2356 void
2357 sh_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
2358 struct value **args, struct type *type, int gcc_p)
2359 {
2360 *(unsigned long *) (dummy + 8) = fun;
2361 }
2362 #endif
2363
2364 /* Find a function's return value in the appropriate registers (in
2365 regbuf), and copy it into valbuf. Extract from an array REGBUF
2366 containing the (raw) register state a function return value of type
2367 TYPE, and copy that, in virtual format, into VALBUF. */
2368 static void
2369 sh_extract_return_value (struct type *type, char *regbuf, char *valbuf)
2370 {
2371 int len = TYPE_LENGTH (type);
2372 int return_register = R0_REGNUM;
2373 int offset;
2374
2375 if (len <= 4)
2376 {
2377 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2378 offset = REGISTER_BYTE (return_register) + 4 - len;
2379 else
2380 offset = REGISTER_BYTE (return_register);
2381 memcpy (valbuf, regbuf + offset, len);
2382 }
2383 else if (len <= 8)
2384 {
2385 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2386 offset = REGISTER_BYTE (return_register) + 8 - len;
2387 else
2388 offset = REGISTER_BYTE (return_register);
2389 memcpy (valbuf, regbuf + offset, len);
2390 }
2391 else
2392 error ("bad size for return value");
2393 }
2394
2395 static void
2396 sh3e_sh4_extract_return_value (struct type *type, char *regbuf, char *valbuf)
2397 {
2398 int return_register;
2399 int offset;
2400 int len = TYPE_LENGTH (type);
2401
2402 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2403 return_register = FP0_REGNUM;
2404 else
2405 return_register = R0_REGNUM;
2406
2407 if (len == 8 && TYPE_CODE (type) == TYPE_CODE_FLT)
2408 {
2409 DOUBLEST val;
2410 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2411 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2412 (char *) regbuf + REGISTER_BYTE (return_register),
2413 &val);
2414 else
2415 floatformat_to_doublest (&floatformat_ieee_double_big,
2416 (char *) regbuf + REGISTER_BYTE (return_register),
2417 &val);
2418 deprecated_store_floating (valbuf, len, val);
2419 }
2420 else if (len <= 4)
2421 {
2422 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2423 offset = REGISTER_BYTE (return_register) + 4 - len;
2424 else
2425 offset = REGISTER_BYTE (return_register);
2426 memcpy (valbuf, regbuf + offset, len);
2427 }
2428 else if (len <= 8)
2429 {
2430 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2431 offset = REGISTER_BYTE (return_register) + 8 - len;
2432 else
2433 offset = REGISTER_BYTE (return_register);
2434 memcpy (valbuf, regbuf + offset, len);
2435 }
2436 else
2437 error ("bad size for return value");
2438 }
2439
2440 static void
2441 sh64_extract_return_value (struct type *type, char *regbuf, char *valbuf)
2442 {
2443 int offset;
2444 int return_register;
2445 int len = TYPE_LENGTH (type);
2446 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2447
2448 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2449 {
2450 if (len == 4)
2451 {
2452 /* Return value stored in FP0_REGNUM */
2453 return_register = FP0_REGNUM;
2454 offset = REGISTER_BYTE (return_register);
2455 memcpy (valbuf, (char *) regbuf + offset, len);
2456 }
2457 else if (len == 8)
2458 {
2459 /* return value stored in DR0_REGNUM */
2460 DOUBLEST val;
2461
2462 return_register = tdep->DR0_REGNUM;
2463 offset = REGISTER_BYTE (return_register);
2464
2465 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2466 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2467 (char *) regbuf + offset, &val);
2468 else
2469 floatformat_to_doublest (&floatformat_ieee_double_big,
2470 (char *) regbuf + offset, &val);
2471 deprecated_store_floating (valbuf, len, val);
2472 }
2473 }
2474 else
2475 {
2476 if (len <= 8)
2477 {
2478 /* Result is in register 2. If smaller than 8 bytes, it is padded
2479 at the most significant end. */
2480 return_register = tdep->RETURN_REGNUM;
2481 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2482 offset = REGISTER_BYTE (return_register) +
2483 REGISTER_RAW_SIZE (return_register) - len;
2484 else
2485 offset = REGISTER_BYTE (return_register);
2486 memcpy (valbuf, (char *) regbuf + offset, len);
2487 }
2488 else
2489 error ("bad size for return value");
2490 }
2491 }
2492
2493 /* Write into appropriate registers a function return value
2494 of type TYPE, given in virtual format.
2495 If the architecture is sh4 or sh3e, store a function's return value
2496 in the R0 general register or in the FP0 floating point register,
2497 depending on the type of the return value. In all the other cases
2498 the result is stored in r0, left-justified. */
2499 static void
2500 sh_default_store_return_value (struct type *type, char *valbuf)
2501 {
2502 char buf[32]; /* more than enough... */
2503
2504 if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (R0_REGNUM))
2505 {
2506 /* Add leading zeros to the value. */
2507 memset (buf, 0, REGISTER_RAW_SIZE (R0_REGNUM));
2508 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2509 memcpy (buf + REGISTER_RAW_SIZE (R0_REGNUM) - TYPE_LENGTH (type),
2510 valbuf, TYPE_LENGTH (type));
2511 else
2512 memcpy (buf, valbuf, TYPE_LENGTH (type));
2513 deprecated_write_register_bytes (REGISTER_BYTE (R0_REGNUM), buf,
2514 REGISTER_RAW_SIZE (R0_REGNUM));
2515 }
2516 else
2517 deprecated_write_register_bytes (REGISTER_BYTE (R0_REGNUM), valbuf,
2518 TYPE_LENGTH (type));
2519 }
2520
2521 static void
2522 sh3e_sh4_store_return_value (struct type *type, char *valbuf)
2523 {
2524 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2525 deprecated_write_register_bytes (REGISTER_BYTE (FP0_REGNUM),
2526 valbuf, TYPE_LENGTH (type));
2527 else
2528 sh_default_store_return_value (type, valbuf);
2529 }
2530
2531 static void
2532 sh64_store_return_value (struct type *type, char *valbuf)
2533 {
2534 char buf[64]; /* more than enough... */
2535 int len = TYPE_LENGTH (type);
2536
2537 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2538 {
2539 if (len == 4)
2540 {
2541 /* Return value stored in FP0_REGNUM */
2542 deprecated_write_register_gen (FP0_REGNUM, valbuf);
2543 }
2544 if (len == 8)
2545 {
2546 /* return value stored in DR0_REGNUM */
2547 /* FIXME: Implement */
2548 }
2549 }
2550 else
2551 {
2552 int return_register = gdbarch_tdep (current_gdbarch)->RETURN_REGNUM;
2553 int offset = 0;
2554
2555 if (len <= REGISTER_RAW_SIZE (return_register))
2556 {
2557 /* Pad with zeros. */
2558 memset (buf, 0, REGISTER_RAW_SIZE (return_register));
2559 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2560 offset = 0; /*REGISTER_RAW_SIZE (return_register) - len;*/
2561 else
2562 offset = REGISTER_RAW_SIZE (return_register) - len;
2563
2564 memcpy (buf + offset, valbuf, len);
2565 deprecated_write_register_gen (return_register, buf);
2566 }
2567 else
2568 deprecated_write_register_gen (return_register, valbuf);
2569 }
2570 }
2571
2572 /* Print the registers in a form similar to the E7000 */
2573
2574 static void
2575 sh_generic_show_regs (void)
2576 {
2577 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2578
2579 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2580 paddr (read_register (PC_REGNUM)),
2581 (long) read_register (tdep->SR_REGNUM),
2582 (long) read_register (tdep->PR_REGNUM),
2583 (long) read_register (MACH_REGNUM),
2584 (long) read_register (MACL_REGNUM));
2585
2586 printf_filtered ("GBR=%08lx VBR=%08lx",
2587 (long) read_register (GBR_REGNUM),
2588 (long) read_register (VBR_REGNUM));
2589
2590 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2591 (long) read_register (0),
2592 (long) read_register (1),
2593 (long) read_register (2),
2594 (long) read_register (3),
2595 (long) read_register (4),
2596 (long) read_register (5),
2597 (long) read_register (6),
2598 (long) read_register (7));
2599 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2600 (long) read_register (8),
2601 (long) read_register (9),
2602 (long) read_register (10),
2603 (long) read_register (11),
2604 (long) read_register (12),
2605 (long) read_register (13),
2606 (long) read_register (14),
2607 (long) read_register (15));
2608 }
2609
2610 static void
2611 sh3_show_regs (void)
2612 {
2613 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2614
2615 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2616 paddr (read_register (PC_REGNUM)),
2617 (long) read_register (tdep->SR_REGNUM),
2618 (long) read_register (tdep->PR_REGNUM),
2619 (long) read_register (MACH_REGNUM),
2620 (long) read_register (MACL_REGNUM));
2621
2622 printf_filtered ("GBR=%08lx VBR=%08lx",
2623 (long) read_register (GBR_REGNUM),
2624 (long) read_register (VBR_REGNUM));
2625 printf_filtered (" SSR=%08lx SPC=%08lx",
2626 (long) read_register (tdep->SSR_REGNUM),
2627 (long) read_register (tdep->SPC_REGNUM));
2628
2629 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2630 (long) read_register (0),
2631 (long) read_register (1),
2632 (long) read_register (2),
2633 (long) read_register (3),
2634 (long) read_register (4),
2635 (long) read_register (5),
2636 (long) read_register (6),
2637 (long) read_register (7));
2638 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2639 (long) read_register (8),
2640 (long) read_register (9),
2641 (long) read_register (10),
2642 (long) read_register (11),
2643 (long) read_register (12),
2644 (long) read_register (13),
2645 (long) read_register (14),
2646 (long) read_register (15));
2647 }
2648
2649
2650 static void
2651 sh2e_show_regs (void)
2652 {
2653 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2654 paddr (read_register (PC_REGNUM)),
2655 (long) read_register (SR_REGNUM),
2656 (long) read_register (PR_REGNUM),
2657 (long) read_register (MACH_REGNUM),
2658 (long) read_register (MACL_REGNUM));
2659
2660 printf_filtered ("GBR=%08lx VBR=%08lx",
2661 (long) read_register (GBR_REGNUM),
2662 (long) read_register (VBR_REGNUM));
2663 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
2664 (long) read_register (gdbarch_tdep (current_gdbarch)->FPUL_REGNUM),
2665 (long) read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM));
2666
2667 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2668 (long) read_register (0),
2669 (long) read_register (1),
2670 (long) read_register (2),
2671 (long) read_register (3),
2672 (long) read_register (4),
2673 (long) read_register (5),
2674 (long) read_register (6),
2675 (long) read_register (7));
2676 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2677 (long) read_register (8),
2678 (long) read_register (9),
2679 (long) read_register (10),
2680 (long) read_register (11),
2681 (long) read_register (12),
2682 (long) read_register (13),
2683 (long) read_register (14),
2684 (long) read_register (15));
2685
2686 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2687 (long) read_register (FP0_REGNUM + 0),
2688 (long) read_register (FP0_REGNUM + 1),
2689 (long) read_register (FP0_REGNUM + 2),
2690 (long) read_register (FP0_REGNUM + 3),
2691 (long) read_register (FP0_REGNUM + 4),
2692 (long) read_register (FP0_REGNUM + 5),
2693 (long) read_register (FP0_REGNUM + 6),
2694 (long) read_register (FP0_REGNUM + 7));
2695 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2696 (long) read_register (FP0_REGNUM + 8),
2697 (long) read_register (FP0_REGNUM + 9),
2698 (long) read_register (FP0_REGNUM + 10),
2699 (long) read_register (FP0_REGNUM + 11),
2700 (long) read_register (FP0_REGNUM + 12),
2701 (long) read_register (FP0_REGNUM + 13),
2702 (long) read_register (FP0_REGNUM + 14),
2703 (long) read_register (FP0_REGNUM + 15));
2704 }
2705
2706 static void
2707 sh3e_show_regs (void)
2708 {
2709 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2710
2711 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2712 paddr (read_register (PC_REGNUM)),
2713 (long) read_register (tdep->SR_REGNUM),
2714 (long) read_register (tdep->PR_REGNUM),
2715 (long) read_register (MACH_REGNUM),
2716 (long) read_register (MACL_REGNUM));
2717
2718 printf_filtered ("GBR=%08lx VBR=%08lx",
2719 (long) read_register (GBR_REGNUM),
2720 (long) read_register (VBR_REGNUM));
2721 printf_filtered (" SSR=%08lx SPC=%08lx",
2722 (long) read_register (tdep->SSR_REGNUM),
2723 (long) read_register (tdep->SPC_REGNUM));
2724 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
2725 (long) read_register (tdep->FPUL_REGNUM),
2726 (long) read_register (tdep->FPSCR_REGNUM));
2727
2728 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2729 (long) read_register (0),
2730 (long) read_register (1),
2731 (long) read_register (2),
2732 (long) read_register (3),
2733 (long) read_register (4),
2734 (long) read_register (5),
2735 (long) read_register (6),
2736 (long) read_register (7));
2737 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2738 (long) read_register (8),
2739 (long) read_register (9),
2740 (long) read_register (10),
2741 (long) read_register (11),
2742 (long) read_register (12),
2743 (long) read_register (13),
2744 (long) read_register (14),
2745 (long) read_register (15));
2746
2747 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2748 (long) read_register (FP0_REGNUM + 0),
2749 (long) read_register (FP0_REGNUM + 1),
2750 (long) read_register (FP0_REGNUM + 2),
2751 (long) read_register (FP0_REGNUM + 3),
2752 (long) read_register (FP0_REGNUM + 4),
2753 (long) read_register (FP0_REGNUM + 5),
2754 (long) read_register (FP0_REGNUM + 6),
2755 (long) read_register (FP0_REGNUM + 7));
2756 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2757 (long) read_register (FP0_REGNUM + 8),
2758 (long) read_register (FP0_REGNUM + 9),
2759 (long) read_register (FP0_REGNUM + 10),
2760 (long) read_register (FP0_REGNUM + 11),
2761 (long) read_register (FP0_REGNUM + 12),
2762 (long) read_register (FP0_REGNUM + 13),
2763 (long) read_register (FP0_REGNUM + 14),
2764 (long) read_register (FP0_REGNUM + 15));
2765 }
2766
2767 static void
2768 sh3_dsp_show_regs (void)
2769 {
2770 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2771
2772 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2773 paddr (read_register (PC_REGNUM)),
2774 (long) read_register (tdep->SR_REGNUM),
2775 (long) read_register (tdep->PR_REGNUM),
2776 (long) read_register (MACH_REGNUM),
2777 (long) read_register (MACL_REGNUM));
2778
2779 printf_filtered ("GBR=%08lx VBR=%08lx",
2780 (long) read_register (GBR_REGNUM),
2781 (long) read_register (VBR_REGNUM));
2782
2783 printf_filtered (" SSR=%08lx SPC=%08lx",
2784 (long) read_register (tdep->SSR_REGNUM),
2785 (long) read_register (tdep->SPC_REGNUM));
2786
2787 printf_filtered (" DSR=%08lx",
2788 (long) read_register (tdep->DSR_REGNUM));
2789
2790 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2791 (long) read_register (0),
2792 (long) read_register (1),
2793 (long) read_register (2),
2794 (long) read_register (3),
2795 (long) read_register (4),
2796 (long) read_register (5),
2797 (long) read_register (6),
2798 (long) read_register (7));
2799 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2800 (long) read_register (8),
2801 (long) read_register (9),
2802 (long) read_register (10),
2803 (long) read_register (11),
2804 (long) read_register (12),
2805 (long) read_register (13),
2806 (long) read_register (14),
2807 (long) read_register (15));
2808
2809 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2810 (long) read_register (tdep->A0G_REGNUM) & 0xff,
2811 (long) read_register (tdep->A0_REGNUM),
2812 (long) read_register (tdep->M0_REGNUM),
2813 (long) read_register (tdep->X0_REGNUM),
2814 (long) read_register (tdep->Y0_REGNUM),
2815 (long) read_register (tdep->RS_REGNUM),
2816 (long) read_register (tdep->MOD_REGNUM));
2817 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2818 (long) read_register (tdep->A1G_REGNUM) & 0xff,
2819 (long) read_register (tdep->A1_REGNUM),
2820 (long) read_register (tdep->M1_REGNUM),
2821 (long) read_register (tdep->X1_REGNUM),
2822 (long) read_register (tdep->Y1_REGNUM),
2823 (long) read_register (tdep->RE_REGNUM));
2824 }
2825
2826 static void
2827 sh4_show_regs (void)
2828 {
2829 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2830
2831 int pr = read_register (tdep->FPSCR_REGNUM) & 0x80000;
2832 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2833 paddr (read_register (PC_REGNUM)),
2834 (long) read_register (tdep->SR_REGNUM),
2835 (long) read_register (tdep->PR_REGNUM),
2836 (long) read_register (MACH_REGNUM),
2837 (long) read_register (MACL_REGNUM));
2838
2839 printf_filtered ("GBR=%08lx VBR=%08lx",
2840 (long) read_register (GBR_REGNUM),
2841 (long) read_register (VBR_REGNUM));
2842 printf_filtered (" SSR=%08lx SPC=%08lx",
2843 (long) read_register (tdep->SSR_REGNUM),
2844 (long) read_register (tdep->SPC_REGNUM));
2845 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
2846 (long) read_register (tdep->FPUL_REGNUM),
2847 (long) read_register (tdep->FPSCR_REGNUM));
2848
2849 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2850 (long) read_register (0),
2851 (long) read_register (1),
2852 (long) read_register (2),
2853 (long) read_register (3),
2854 (long) read_register (4),
2855 (long) read_register (5),
2856 (long) read_register (6),
2857 (long) read_register (7));
2858 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2859 (long) read_register (8),
2860 (long) read_register (9),
2861 (long) read_register (10),
2862 (long) read_register (11),
2863 (long) read_register (12),
2864 (long) read_register (13),
2865 (long) read_register (14),
2866 (long) read_register (15));
2867
2868 printf_filtered ((pr
2869 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2870 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2871 (long) read_register (FP0_REGNUM + 0),
2872 (long) read_register (FP0_REGNUM + 1),
2873 (long) read_register (FP0_REGNUM + 2),
2874 (long) read_register (FP0_REGNUM + 3),
2875 (long) read_register (FP0_REGNUM + 4),
2876 (long) read_register (FP0_REGNUM + 5),
2877 (long) read_register (FP0_REGNUM + 6),
2878 (long) read_register (FP0_REGNUM + 7));
2879 printf_filtered ((pr
2880 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2881 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2882 (long) read_register (FP0_REGNUM + 8),
2883 (long) read_register (FP0_REGNUM + 9),
2884 (long) read_register (FP0_REGNUM + 10),
2885 (long) read_register (FP0_REGNUM + 11),
2886 (long) read_register (FP0_REGNUM + 12),
2887 (long) read_register (FP0_REGNUM + 13),
2888 (long) read_register (FP0_REGNUM + 14),
2889 (long) read_register (FP0_REGNUM + 15));
2890 }
2891
2892 static void
2893 sh_dsp_show_regs (void)
2894 {
2895 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2896
2897 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2898 paddr (read_register (PC_REGNUM)),
2899 (long) read_register (tdep->SR_REGNUM),
2900 (long) read_register (tdep->PR_REGNUM),
2901 (long) read_register (MACH_REGNUM),
2902 (long) read_register (MACL_REGNUM));
2903
2904 printf_filtered ("GBR=%08lx VBR=%08lx",
2905 (long) read_register (GBR_REGNUM),
2906 (long) read_register (VBR_REGNUM));
2907
2908 printf_filtered (" DSR=%08lx",
2909 (long) read_register (tdep->DSR_REGNUM));
2910
2911 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2912 (long) read_register (0),
2913 (long) read_register (1),
2914 (long) read_register (2),
2915 (long) read_register (3),
2916 (long) read_register (4),
2917 (long) read_register (5),
2918 (long) read_register (6),
2919 (long) read_register (7));
2920 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2921 (long) read_register (8),
2922 (long) read_register (9),
2923 (long) read_register (10),
2924 (long) read_register (11),
2925 (long) read_register (12),
2926 (long) read_register (13),
2927 (long) read_register (14),
2928 (long) read_register (15));
2929
2930 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2931 (long) read_register (tdep->A0G_REGNUM) & 0xff,
2932 (long) read_register (tdep->A0_REGNUM),
2933 (long) read_register (tdep->M0_REGNUM),
2934 (long) read_register (tdep->X0_REGNUM),
2935 (long) read_register (tdep->Y0_REGNUM),
2936 (long) read_register (tdep->RS_REGNUM),
2937 (long) read_register (tdep->MOD_REGNUM));
2938 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2939 (long) read_register (tdep->A1G_REGNUM) & 0xff,
2940 (long) read_register (tdep->A1_REGNUM),
2941 (long) read_register (tdep->M1_REGNUM),
2942 (long) read_register (tdep->X1_REGNUM),
2943 (long) read_register (tdep->Y1_REGNUM),
2944 (long) read_register (tdep->RE_REGNUM));
2945 }
2946
2947 static void
2948 sh64_show_media_regs (void)
2949 {
2950 int i;
2951 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2952
2953 printf_filtered ("PC=%s SR=%016llx \n",
2954 paddr (read_register (PC_REGNUM)),
2955 (long long) read_register (tdep->SR_REGNUM));
2956
2957 printf_filtered ("SSR=%016llx SPC=%016llx \n",
2958 (long long) read_register (tdep->SSR_REGNUM),
2959 (long long) read_register (tdep->SPC_REGNUM));
2960 printf_filtered ("FPSCR=%016lx\n ",
2961 (long) read_register (tdep->FPSCR_REGNUM));
2962
2963 for (i = 0; i < 64; i = i + 4)
2964 printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
2965 i, i + 3,
2966 (long long) read_register (i + 0),
2967 (long long) read_register (i + 1),
2968 (long long) read_register (i + 2),
2969 (long long) read_register (i + 3));
2970
2971 printf_filtered ("\n");
2972
2973 for (i = 0; i < 64; i = i + 8)
2974 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2975 i, i + 7,
2976 (long) read_register (FP0_REGNUM + i + 0),
2977 (long) read_register (FP0_REGNUM + i + 1),
2978 (long) read_register (FP0_REGNUM + i + 2),
2979 (long) read_register (FP0_REGNUM + i + 3),
2980 (long) read_register (FP0_REGNUM + i + 4),
2981 (long) read_register (FP0_REGNUM + i + 5),
2982 (long) read_register (FP0_REGNUM + i + 6),
2983 (long) read_register (FP0_REGNUM + i + 7));
2984 }
2985
2986 static void
2987 sh64_show_compact_regs (void)
2988 {
2989 int i;
2990 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2991
2992 printf_filtered ("PC=%s \n",
2993 paddr (read_register (tdep->PC_C_REGNUM)));
2994
2995 printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
2996 (long) read_register (tdep->GBR_C_REGNUM),
2997 (long) read_register (tdep->MACH_C_REGNUM),
2998 (long) read_register (tdep->MACL_C_REGNUM),
2999 (long) read_register (tdep->PR_C_REGNUM),
3000 (long) read_register (tdep->T_C_REGNUM));
3001 printf_filtered ("FPSCR=%08lx FPUL=%08lx\n",
3002 (long) read_register (tdep->FPSCR_REGNUM),
3003 (long) read_register (tdep->FPUL_REGNUM));
3004
3005 for (i = 0; i < 16; i = i + 4)
3006 printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
3007 i, i + 3,
3008 (long) read_register (i + 0),
3009 (long) read_register (i + 1),
3010 (long) read_register (i + 2),
3011 (long) read_register (i + 3));
3012
3013 printf_filtered ("\n");
3014
3015 for (i = 0; i < 16; i = i + 8)
3016 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3017 i, i + 7,
3018 (long) read_register (FP0_REGNUM + i + 0),
3019 (long) read_register (FP0_REGNUM + i + 1),
3020 (long) read_register (FP0_REGNUM + i + 2),
3021 (long) read_register (FP0_REGNUM + i + 3),
3022 (long) read_register (FP0_REGNUM + i + 4),
3023 (long) read_register (FP0_REGNUM + i + 5),
3024 (long) read_register (FP0_REGNUM + i + 6),
3025 (long) read_register (FP0_REGNUM + i + 7));
3026 }
3027
3028 /*FIXME!!! This only shows the registers for shmedia, excluding the
3029 pseudo registers. */
3030 static void
3031 sh64_show_regs (void)
3032 {
3033 if (pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
3034 sh64_show_media_regs ();
3035 else
3036 sh64_show_compact_regs ();
3037 }
3038
3039 static void
3040 sh_show_regs_command (char *args, int from_tty)
3041 {
3042 if (sh_show_regs)
3043 (*sh_show_regs)();
3044 }
3045
3046 /* Index within `registers' of the first byte of the space for
3047 register N. */
3048 static int
3049 sh_default_register_byte (int reg_nr)
3050 {
3051 return (reg_nr * 4);
3052 }
3053
3054 static int
3055 sh_sh4_register_byte (int reg_nr)
3056 {
3057 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3058
3059 if (reg_nr >= tdep->DR0_REGNUM
3060 && reg_nr <= tdep->DR_LAST_REGNUM)
3061 return (dr_reg_base_num (reg_nr) * 4);
3062 else if (reg_nr >= tdep->FV0_REGNUM
3063 && reg_nr <= tdep->FV_LAST_REGNUM)
3064 return (fv_reg_base_num (reg_nr) * 4);
3065 else
3066 return (reg_nr * 4);
3067 }
3068
3069 /* *INDENT-OFF* */
3070 /*
3071 SH MEDIA MODE (ISA 32)
3072 general registers (64-bit) 0-63
3073 0 r0, r1, r2, r3, r4, r5, r6, r7,
3074 64 r8, r9, r10, r11, r12, r13, r14, r15,
3075 128 r16, r17, r18, r19, r20, r21, r22, r23,
3076 192 r24, r25, r26, r27, r28, r29, r30, r31,
3077 256 r32, r33, r34, r35, r36, r37, r38, r39,
3078 320 r40, r41, r42, r43, r44, r45, r46, r47,
3079 384 r48, r49, r50, r51, r52, r53, r54, r55,
3080 448 r56, r57, r58, r59, r60, r61, r62, r63,
3081
3082 pc (64-bit) 64
3083 512 pc,
3084
3085 status reg., saved status reg., saved pc reg. (64-bit) 65-67
3086 520 sr, ssr, spc,
3087
3088 target registers (64-bit) 68-75
3089 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
3090
3091 floating point state control register (32-bit) 76
3092 608 fpscr,
3093
3094 single precision floating point registers (32-bit) 77-140
3095 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
3096 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
3097 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
3098 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
3099 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
3100 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
3101 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
3102 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
3103
3104 TOTAL SPACE FOR REGISTERS: 868 bytes
3105
3106 From here on they are all pseudo registers: no memory allocated.
3107 REGISTER_BYTE returns the register byte for the base register.
3108
3109 double precision registers (pseudo) 141-172
3110 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
3111 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
3112 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
3113 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
3114
3115 floating point pairs (pseudo) 173-204
3116 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
3117 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
3118 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
3119 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
3120
3121 floating point vectors (4 floating point regs) (pseudo) 205-220
3122 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
3123 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
3124
3125 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
3126 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
3127 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
3128 pc_c,
3129 gbr_c, mach_c, macl_c, pr_c, t_c,
3130 fpscr_c, fpul_c,
3131 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
3132 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
3133 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
3134 fv0_c, fv4_c, fv8_c, fv12_c
3135 */
3136 /* *INDENT-ON* */
3137 static int
3138 sh_sh64_register_byte (int reg_nr)
3139 {
3140 int base_regnum = -1;
3141 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3142
3143 /* If it is a pseudo register, get the number of the first floating
3144 point register that is part of it. */
3145 if (reg_nr >= tdep->DR0_REGNUM
3146 && reg_nr <= tdep->DR_LAST_REGNUM)
3147 base_regnum = dr_reg_base_num (reg_nr);
3148
3149 else if (reg_nr >= tdep->FPP0_REGNUM
3150 && reg_nr <= tdep->FPP_LAST_REGNUM)
3151 base_regnum = fpp_reg_base_num (reg_nr);
3152
3153 else if (reg_nr >= tdep->FV0_REGNUM
3154 && reg_nr <= tdep->FV_LAST_REGNUM)
3155 base_regnum = fv_reg_base_num (reg_nr);
3156
3157 /* sh compact pseudo register. FPSCR is a pathological case, need to
3158 treat it as special. */
3159 else if ((reg_nr >= tdep->R0_C_REGNUM
3160 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3161 && reg_nr != tdep->FPSCR_C_REGNUM)
3162 base_regnum = sh64_compact_reg_base_num (reg_nr);
3163
3164 /* Now return the offset in bytes within the register cache. */
3165 /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */
3166 if (reg_nr >= tdep->DR0_REGNUM
3167 && reg_nr <= tdep->FV_LAST_REGNUM)
3168 return (base_regnum - FP0_REGNUM + 1) * 4
3169 + (tdep->TR7_REGNUM + 1) * 8;
3170
3171 /* sh compact pseudo register: general register */
3172 if ((reg_nr >= tdep->R0_C_REGNUM
3173 && reg_nr <= tdep->R_LAST_C_REGNUM))
3174 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3175 ? base_regnum * 8 + 4
3176 : base_regnum * 8);
3177
3178 /* sh compact pseudo register: */
3179 if (reg_nr == tdep->PC_C_REGNUM
3180 || reg_nr == tdep->GBR_C_REGNUM
3181 || reg_nr == tdep->MACL_C_REGNUM
3182 || reg_nr == tdep->PR_C_REGNUM)
3183 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3184 ? base_regnum * 8 + 4
3185 : base_regnum * 8);
3186
3187 if (reg_nr == tdep->MACH_C_REGNUM)
3188 return base_regnum * 8;
3189
3190 if (reg_nr == tdep->T_C_REGNUM)
3191 return base_regnum * 8; /* FIXME??? how do we get bit 0? Do we have to? */
3192
3193 /* sh compact pseudo register: floating point register */
3194 else if (reg_nr >=tdep->FP0_C_REGNUM
3195 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3196 return (base_regnum - FP0_REGNUM) * 4
3197 + (tdep->TR7_REGNUM + 1) * 8 + 4;
3198
3199 else if (reg_nr == tdep->FPSCR_C_REGNUM)
3200 /* This is complicated, for now return the beginning of the
3201 architectural FPSCR register. */
3202 return (tdep->TR7_REGNUM + 1) * 8;
3203
3204 else if (reg_nr == tdep->FPUL_C_REGNUM)
3205 return ((base_regnum - FP0_REGNUM) * 4 +
3206 (tdep->TR7_REGNUM + 1) * 8 + 4);
3207
3208 /* It is not a pseudo register. */
3209 /* It is a 64 bit register. */
3210 else if (reg_nr <= tdep->TR7_REGNUM)
3211 return reg_nr * 8;
3212
3213 /* It is a 32 bit register. */
3214 else
3215 if (reg_nr == tdep->FPSCR_REGNUM)
3216 return (tdep->FPSCR_REGNUM * 8);
3217
3218 /* It is floating point 32-bit register */
3219 else
3220 return ((tdep->TR7_REGNUM + 1) * 8
3221 + (reg_nr - FP0_REGNUM + 1) * 4);
3222 }
3223
3224 /* Number of bytes of storage in the actual machine representation for
3225 register REG_NR. */
3226 static int
3227 sh_default_register_raw_size (int reg_nr)
3228 {
3229 return 4;
3230 }
3231
3232 static int
3233 sh_sh4_register_raw_size (int reg_nr)
3234 {
3235 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3236
3237 if (reg_nr >= tdep->DR0_REGNUM
3238 && reg_nr <= tdep->DR_LAST_REGNUM)
3239 return 8;
3240 else if (reg_nr >= tdep->FV0_REGNUM
3241 && reg_nr <= tdep->FV_LAST_REGNUM)
3242 return 16;
3243 else
3244 return 4;
3245 }
3246
3247 static int
3248 sh_sh64_register_raw_size (int reg_nr)
3249 {
3250 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3251
3252 if ((reg_nr >= tdep->DR0_REGNUM
3253 && reg_nr <= tdep->DR_LAST_REGNUM)
3254 || (reg_nr >= tdep->FPP0_REGNUM
3255 && reg_nr <= tdep->FPP_LAST_REGNUM)
3256 || (reg_nr >= tdep->DR0_C_REGNUM
3257 && reg_nr <= tdep->DR_LAST_C_REGNUM)
3258 || (reg_nr <= tdep->TR7_REGNUM))
3259 return 8;
3260
3261 else if ((reg_nr >= tdep->FV0_REGNUM
3262 && reg_nr <= tdep->FV_LAST_REGNUM)
3263 || (reg_nr >= tdep->FV0_C_REGNUM
3264 && reg_nr <= tdep->FV_LAST_C_REGNUM))
3265 return 16;
3266
3267 else /* this covers also the 32-bit SH compact registers. */
3268 return 4;
3269 }
3270
3271 /* Number of bytes of storage in the program's representation
3272 for register N. */
3273 static int
3274 sh_register_virtual_size (int reg_nr)
3275 {
3276 return 4;
3277 }
3278
3279 /* ??????? FIXME */
3280 static int
3281 sh_sh64_register_virtual_size (int reg_nr)
3282 {
3283 if (reg_nr >= FP0_REGNUM
3284 && reg_nr <= gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM)
3285 return 4;
3286 else
3287 return 8;
3288 }
3289
3290 /* Return the GDB type object for the "standard" data type
3291 of data in register N. */
3292 static struct type *
3293 sh_sh3e_register_virtual_type (int reg_nr)
3294 {
3295 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3296
3297 if ((reg_nr >= FP0_REGNUM
3298 && (reg_nr <= tdep->FP_LAST_REGNUM))
3299 || (reg_nr == tdep->FPUL_REGNUM))
3300 return builtin_type_float;
3301 else
3302 return builtin_type_int;
3303 }
3304
3305 static struct type *
3306 sh_sh4_build_float_register_type (int high)
3307 {
3308 struct type *temp;
3309
3310 temp = create_range_type (NULL, builtin_type_int, 0, high);
3311 return create_array_type (NULL, builtin_type_float, temp);
3312 }
3313
3314 static struct type *
3315 sh_sh4_register_virtual_type (int reg_nr)
3316 {
3317 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3318
3319 if ((reg_nr >= FP0_REGNUM
3320 && (reg_nr <= tdep->FP_LAST_REGNUM))
3321 || (reg_nr == tdep->FPUL_REGNUM))
3322 return builtin_type_float;
3323 else if (reg_nr >= tdep->DR0_REGNUM
3324 && reg_nr <= tdep->DR_LAST_REGNUM)
3325 return builtin_type_double;
3326 else if (reg_nr >= tdep->FV0_REGNUM
3327 && reg_nr <= tdep->FV_LAST_REGNUM)
3328 return sh_sh4_build_float_register_type (3);
3329 else
3330 return builtin_type_int;
3331 }
3332
3333 static struct type *
3334 sh_sh64_register_virtual_type (int reg_nr)
3335 {
3336 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3337
3338 if ((reg_nr >= FP0_REGNUM
3339 && reg_nr <= tdep->FP_LAST_REGNUM)
3340 || (reg_nr >= tdep->FP0_C_REGNUM
3341 && reg_nr <= tdep->FP_LAST_C_REGNUM))
3342 return builtin_type_float;
3343 else if ((reg_nr >= tdep->DR0_REGNUM
3344 && reg_nr <= tdep->DR_LAST_REGNUM)
3345 || (reg_nr >= tdep->DR0_C_REGNUM
3346 && reg_nr <= tdep->DR_LAST_C_REGNUM))
3347 return builtin_type_double;
3348 else if (reg_nr >= tdep->FPP0_REGNUM
3349 && reg_nr <= tdep->FPP_LAST_REGNUM)
3350 return sh_sh4_build_float_register_type (1);
3351 else if ((reg_nr >= tdep->FV0_REGNUM
3352 && reg_nr <= tdep->FV_LAST_REGNUM)
3353 ||(reg_nr >= tdep->FV0_C_REGNUM
3354 && reg_nr <= tdep->FV_LAST_C_REGNUM))
3355 return sh_sh4_build_float_register_type (3);
3356 else if (reg_nr == tdep->FPSCR_REGNUM)
3357 return builtin_type_int;
3358 else if (reg_nr >= tdep->R0_C_REGNUM
3359 && reg_nr < tdep->FP0_C_REGNUM)
3360 return builtin_type_int;
3361 else
3362 return builtin_type_long_long;
3363 }
3364
3365 static struct type *
3366 sh_default_register_virtual_type (int reg_nr)
3367 {
3368 return builtin_type_int;
3369 }
3370
3371 /* On the sh4, the DRi pseudo registers are problematic if the target
3372 is little endian. When the user writes one of those registers, for
3373 instance with 'ser var $dr0=1', we want the double to be stored
3374 like this:
3375 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3376 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3377
3378 This corresponds to little endian byte order & big endian word
3379 order. However if we let gdb write the register w/o conversion, it
3380 will write fr0 and fr1 this way:
3381 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3382 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3383 because it will consider fr0 and fr1 as a single LE stretch of memory.
3384
3385 To achieve what we want we must force gdb to store things in
3386 floatformat_ieee_double_littlebyte_bigword (which is defined in
3387 include/floatformat.h and libiberty/floatformat.c.
3388
3389 In case the target is big endian, there is no problem, the
3390 raw bytes will look like:
3391 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
3392 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3393
3394 The other pseudo registers (the FVs) also don't pose a problem
3395 because they are stored as 4 individual FP elements. */
3396
3397 static void
3398 sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
3399 char *from, char *to)
3400 {
3401 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3402
3403 if (regnum >= tdep->DR0_REGNUM
3404 && regnum <= tdep->DR_LAST_REGNUM)
3405 {
3406 DOUBLEST val;
3407 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
3408 deprecated_store_floating (to, TYPE_LENGTH (type), val);
3409 }
3410 else
3411 error ("sh_register_convert_to_virtual called with non DR register number");
3412 }
3413
3414 static void
3415 sh_sh64_register_convert_to_virtual (int regnum, struct type *type,
3416 char *from, char *to)
3417 {
3418 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3419
3420 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
3421 {
3422 /* It is a no-op. */
3423 memcpy (to, from, REGISTER_RAW_SIZE (regnum));
3424 return;
3425 }
3426
3427 if ((regnum >= tdep->DR0_REGNUM
3428 && regnum <= tdep->DR_LAST_REGNUM)
3429 || (regnum >= tdep->DR0_C_REGNUM
3430 && regnum <= tdep->DR_LAST_C_REGNUM))
3431 {
3432 DOUBLEST val;
3433 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
3434 deprecated_store_floating(to, TYPE_LENGTH(type), val);
3435 }
3436 else
3437 error("sh_register_convert_to_virtual called with non DR register number");
3438 }
3439
3440 static void
3441 sh_sh4_register_convert_to_raw (struct type *type, int regnum,
3442 const void *from, void *to)
3443 {
3444 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3445
3446 if (regnum >= tdep->DR0_REGNUM
3447 && regnum <= tdep->DR_LAST_REGNUM)
3448 {
3449 DOUBLEST val = deprecated_extract_floating (from, TYPE_LENGTH(type));
3450 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
3451 }
3452 else
3453 error("sh_register_convert_to_raw called with non DR register number");
3454 }
3455
3456 static void
3457 sh_sh64_register_convert_to_raw (struct type *type, int regnum,
3458 const void *from, void *to)
3459 {
3460 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3461
3462 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
3463 {
3464 /* It is a no-op. */
3465 memcpy (to, from, REGISTER_RAW_SIZE (regnum));
3466 return;
3467 }
3468
3469 if ((regnum >= tdep->DR0_REGNUM
3470 && regnum <= tdep->DR_LAST_REGNUM)
3471 || (regnum >= tdep->DR0_C_REGNUM
3472 && regnum <= tdep->DR_LAST_C_REGNUM))
3473 {
3474 DOUBLEST val = deprecated_extract_floating (from, TYPE_LENGTH(type));
3475 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
3476 }
3477 else
3478 error("sh_register_convert_to_raw called with non DR register number");
3479 }
3480
3481 static void
3482 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
3483 int reg_nr, void *buffer)
3484 {
3485 int base_regnum, portion;
3486 char temp_buffer[MAX_REGISTER_SIZE];
3487 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3488
3489 if (reg_nr >= tdep->DR0_REGNUM
3490 && reg_nr <= tdep->DR_LAST_REGNUM)
3491 {
3492 base_regnum = dr_reg_base_num (reg_nr);
3493
3494 /* Build the value in the provided buffer. */
3495 /* Read the real regs for which this one is an alias. */
3496 for (portion = 0; portion < 2; portion++)
3497 regcache_raw_read (regcache, base_regnum + portion,
3498 (temp_buffer
3499 + REGISTER_RAW_SIZE (base_regnum) * portion));
3500 /* We must pay attention to the endiannes. */
3501 sh_sh4_register_convert_to_virtual (reg_nr,
3502 REGISTER_VIRTUAL_TYPE (reg_nr),
3503 temp_buffer, buffer);
3504 }
3505 else if (reg_nr >= tdep->FV0_REGNUM
3506 && reg_nr <= tdep->FV_LAST_REGNUM)
3507 {
3508 base_regnum = fv_reg_base_num (reg_nr);
3509
3510 /* Read the real regs for which this one is an alias. */
3511 for (portion = 0; portion < 4; portion++)
3512 regcache_raw_read (regcache, base_regnum + portion,
3513 ((char *) buffer
3514 + REGISTER_RAW_SIZE (base_regnum) * portion));
3515 }
3516 }
3517
3518 static void
3519 sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
3520 int reg_nr, void *buffer)
3521 {
3522 int base_regnum;
3523 int portion;
3524 int offset = 0;
3525 char temp_buffer[MAX_REGISTER_SIZE];
3526 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3527
3528 if (reg_nr >= tdep->DR0_REGNUM
3529 && reg_nr <= tdep->DR_LAST_REGNUM)
3530 {
3531 base_regnum = dr_reg_base_num (reg_nr);
3532
3533 /* Build the value in the provided buffer. */
3534 /* DR regs are double precision registers obtained by
3535 concatenating 2 single precision floating point registers. */
3536 for (portion = 0; portion < 2; portion++)
3537 regcache_raw_read (regcache, base_regnum + portion,
3538 (temp_buffer
3539 + REGISTER_RAW_SIZE (base_regnum) * portion));
3540
3541 /* We must pay attention to the endiannes. */
3542 sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr),
3543 temp_buffer, buffer);
3544
3545 }
3546
3547 else if (reg_nr >= tdep->FPP0_REGNUM
3548 && reg_nr <= tdep->FPP_LAST_REGNUM)
3549 {
3550 base_regnum = fpp_reg_base_num (reg_nr);
3551
3552 /* Build the value in the provided buffer. */
3553 /* FPP regs are pairs of single precision registers obtained by
3554 concatenating 2 single precision floating point registers. */
3555 for (portion = 0; portion < 2; portion++)
3556 regcache_raw_read (regcache, base_regnum + portion,
3557 ((char *) buffer
3558 + REGISTER_RAW_SIZE (base_regnum) * portion));
3559 }
3560
3561 else if (reg_nr >= tdep->FV0_REGNUM
3562 && reg_nr <= tdep->FV_LAST_REGNUM)
3563 {
3564 base_regnum = fv_reg_base_num (reg_nr);
3565
3566 /* Build the value in the provided buffer. */
3567 /* FV regs are vectors of single precision registers obtained by
3568 concatenating 4 single precision floating point registers. */
3569 for (portion = 0; portion < 4; portion++)
3570 regcache_raw_read (regcache, base_regnum + portion,
3571 ((char *) buffer
3572 + REGISTER_RAW_SIZE (base_regnum) * portion));
3573 }
3574
3575 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
3576 else if (reg_nr >= tdep->R0_C_REGNUM
3577 && reg_nr <= tdep->T_C_REGNUM)
3578 {
3579 base_regnum = sh64_compact_reg_base_num (reg_nr);
3580
3581 /* Build the value in the provided buffer. */
3582 regcache_raw_read (regcache, base_regnum, temp_buffer);
3583 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3584 offset = 4;
3585 memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/
3586 }
3587
3588 else if (reg_nr >= tdep->FP0_C_REGNUM
3589 && reg_nr <= tdep->FP_LAST_C_REGNUM)
3590 {
3591 base_regnum = sh64_compact_reg_base_num (reg_nr);
3592
3593 /* Build the value in the provided buffer. */
3594 /* Floating point registers map 1-1 to the media fp regs,
3595 they have the same size and endienness. */
3596 regcache_raw_read (regcache, base_regnum, buffer);
3597 }
3598
3599 else if (reg_nr >= tdep->DR0_C_REGNUM
3600 && reg_nr <= tdep->DR_LAST_C_REGNUM)
3601 {
3602 base_regnum = sh64_compact_reg_base_num (reg_nr);
3603
3604 /* DR_C regs are double precision registers obtained by
3605 concatenating 2 single precision floating point registers. */
3606 for (portion = 0; portion < 2; portion++)
3607 regcache_raw_read (regcache, base_regnum + portion,
3608 (temp_buffer
3609 + REGISTER_RAW_SIZE (base_regnum) * portion));
3610
3611 /* We must pay attention to the endiannes. */
3612 sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr),
3613 temp_buffer, buffer);
3614 }
3615
3616 else if (reg_nr >= tdep->FV0_C_REGNUM
3617 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3618 {
3619 base_regnum = sh64_compact_reg_base_num (reg_nr);
3620
3621 /* Build the value in the provided buffer. */
3622 /* FV_C regs are vectors of single precision registers obtained by
3623 concatenating 4 single precision floating point registers. */
3624 for (portion = 0; portion < 4; portion++)
3625 regcache_raw_read (regcache, base_regnum + portion,
3626 ((char *) buffer
3627 + REGISTER_RAW_SIZE (base_regnum) * portion));
3628 }
3629
3630 else if (reg_nr == tdep->FPSCR_C_REGNUM)
3631 {
3632 int fpscr_base_regnum;
3633 int sr_base_regnum;
3634 unsigned int fpscr_value;
3635 unsigned int sr_value;
3636 unsigned int fpscr_c_value;
3637 unsigned int fpscr_c_part1_value;
3638 unsigned int fpscr_c_part2_value;
3639
3640 fpscr_base_regnum = tdep->FPSCR_REGNUM;
3641 sr_base_regnum = tdep->SR_REGNUM;
3642
3643 /* Build the value in the provided buffer. */
3644 /* FPSCR_C is a very weird register that contains sparse bits
3645 from the FPSCR and the SR architectural registers.
3646 Specifically: */
3647 /* *INDENT-OFF* */
3648 /*
3649 FPSRC_C bit
3650 0 Bit 0 of FPSCR
3651 1 reserved
3652 2-17 Bit 2-18 of FPSCR
3653 18-20 Bits 12,13,14 of SR
3654 21-31 reserved
3655 */
3656 /* *INDENT-ON* */
3657 /* Get FPSCR into a local buffer */
3658 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
3659 /* Get value as an int. */
3660 fpscr_value = extract_unsigned_integer (temp_buffer, 4);
3661 /* Get SR into a local buffer */
3662 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
3663 /* Get value as an int. */
3664 sr_value = extract_unsigned_integer (temp_buffer, 4);
3665 /* Build the new value. */
3666 fpscr_c_part1_value = fpscr_value & 0x3fffd;
3667 fpscr_c_part2_value = (sr_value & 0x7000) << 6;
3668 fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value;
3669 /* Store that in out buffer!!! */
3670 store_unsigned_integer (buffer, 4, fpscr_c_value);
3671 /* FIXME There is surely an endianness gotcha here. */
3672 }
3673
3674 else if (reg_nr == tdep->FPUL_C_REGNUM)
3675 {
3676 base_regnum = sh64_compact_reg_base_num (reg_nr);
3677
3678 /* FPUL_C register is floating point register 32,
3679 same size, same endianness. */
3680 regcache_raw_read (regcache, base_regnum, buffer);
3681 }
3682 }
3683
3684 static void
3685 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3686 int reg_nr, const void *buffer)
3687 {
3688 int base_regnum, portion;
3689 char temp_buffer[MAX_REGISTER_SIZE];
3690 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3691
3692 if (reg_nr >= tdep->DR0_REGNUM
3693 && reg_nr <= tdep->DR_LAST_REGNUM)
3694 {
3695 base_regnum = dr_reg_base_num (reg_nr);
3696
3697 /* We must pay attention to the endiannes. */
3698 sh_sh4_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
3699 buffer, temp_buffer);
3700
3701 /* Write the real regs for which this one is an alias. */
3702 for (portion = 0; portion < 2; portion++)
3703 regcache_raw_write (regcache, base_regnum + portion,
3704 (temp_buffer
3705 + REGISTER_RAW_SIZE (base_regnum) * portion));
3706 }
3707 else if (reg_nr >= tdep->FV0_REGNUM
3708 && reg_nr <= tdep->FV_LAST_REGNUM)
3709 {
3710 base_regnum = fv_reg_base_num (reg_nr);
3711
3712 /* Write the real regs for which this one is an alias. */
3713 for (portion = 0; portion < 4; portion++)
3714 regcache_raw_write (regcache, base_regnum + portion,
3715 ((char *) buffer
3716 + REGISTER_RAW_SIZE (base_regnum) * portion));
3717 }
3718 }
3719
3720 static void
3721 sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3722 int reg_nr, const void *buffer)
3723 {
3724 int base_regnum, portion;
3725 int offset;
3726 char temp_buffer[MAX_REGISTER_SIZE];
3727 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3728
3729 if (reg_nr >= tdep->DR0_REGNUM
3730 && reg_nr <= tdep->DR_LAST_REGNUM)
3731 {
3732 base_regnum = dr_reg_base_num (reg_nr);
3733 /* We must pay attention to the endiannes. */
3734 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
3735 buffer, temp_buffer);
3736
3737
3738 /* Write the real regs for which this one is an alias. */
3739 for (portion = 0; portion < 2; portion++)
3740 regcache_raw_write (regcache, base_regnum + portion,
3741 (temp_buffer
3742 + REGISTER_RAW_SIZE (base_regnum) * portion));
3743 }
3744
3745 else if (reg_nr >= tdep->FPP0_REGNUM
3746 && reg_nr <= tdep->FPP_LAST_REGNUM)
3747 {
3748 base_regnum = fpp_reg_base_num (reg_nr);
3749
3750 /* Write the real regs for which this one is an alias. */
3751 for (portion = 0; portion < 2; portion++)
3752 regcache_raw_write (regcache, base_regnum + portion,
3753 ((char *) buffer
3754 + REGISTER_RAW_SIZE (base_regnum) * portion));
3755 }
3756
3757 else if (reg_nr >= tdep->FV0_REGNUM
3758 && reg_nr <= tdep->FV_LAST_REGNUM)
3759 {
3760 base_regnum = fv_reg_base_num (reg_nr);
3761
3762 /* Write the real regs for which this one is an alias. */
3763 for (portion = 0; portion < 4; portion++)
3764 regcache_raw_write (regcache, base_regnum + portion,
3765 ((char *) buffer
3766 + REGISTER_RAW_SIZE (base_regnum) * portion));
3767 }
3768
3769 /* sh compact general pseudo registers. 1-to-1 with a shmedia
3770 register but only 4 bytes of it. */
3771 else if (reg_nr >= tdep->R0_C_REGNUM
3772 && reg_nr <= tdep->T_C_REGNUM)
3773 {
3774 base_regnum = sh64_compact_reg_base_num (reg_nr);
3775 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
3776 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3777 offset = 4;
3778 else
3779 offset = 0;
3780 /* Let's read the value of the base register into a temporary
3781 buffer, so that overwriting the last four bytes with the new
3782 value of the pseudo will leave the upper 4 bytes unchanged. */
3783 regcache_raw_read (regcache, base_regnum, temp_buffer);
3784 /* Write as an 8 byte quantity */
3785 memcpy (temp_buffer + offset, buffer, 4);
3786 regcache_raw_write (regcache, base_regnum, temp_buffer);
3787 }
3788
3789 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
3790 registers. Both are 4 bytes. */
3791 else if (reg_nr >= tdep->FP0_C_REGNUM
3792 && reg_nr <= tdep->FP_LAST_C_REGNUM)
3793 {
3794 base_regnum = sh64_compact_reg_base_num (reg_nr);
3795 regcache_raw_write (regcache, base_regnum, buffer);
3796 }
3797
3798 else if (reg_nr >= tdep->DR0_C_REGNUM
3799 && reg_nr <= tdep->DR_LAST_C_REGNUM)
3800 {
3801 base_regnum = sh64_compact_reg_base_num (reg_nr);
3802 for (portion = 0; portion < 2; portion++)
3803 {
3804 /* We must pay attention to the endiannes. */
3805 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
3806 buffer, temp_buffer);
3807
3808 regcache_raw_write (regcache, base_regnum + portion,
3809 (temp_buffer
3810 + REGISTER_RAW_SIZE (base_regnum) * portion));
3811 }
3812 }
3813
3814 else if (reg_nr >= tdep->FV0_C_REGNUM
3815 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3816 {
3817 base_regnum = sh64_compact_reg_base_num (reg_nr);
3818
3819 for (portion = 0; portion < 4; portion++)
3820 {
3821 regcache_raw_write (regcache, base_regnum + portion,
3822 ((char *) buffer
3823 + REGISTER_RAW_SIZE (base_regnum) * portion));
3824 }
3825 }
3826
3827 else if (reg_nr == tdep->FPSCR_C_REGNUM)
3828 {
3829 int fpscr_base_regnum;
3830 int sr_base_regnum;
3831 unsigned int fpscr_value;
3832 unsigned int sr_value;
3833 unsigned int old_fpscr_value;
3834 unsigned int old_sr_value;
3835 unsigned int fpscr_c_value;
3836 unsigned int fpscr_mask;
3837 unsigned int sr_mask;
3838
3839 fpscr_base_regnum = tdep->FPSCR_REGNUM;
3840 sr_base_regnum = tdep->SR_REGNUM;
3841
3842 /* FPSCR_C is a very weird register that contains sparse bits
3843 from the FPSCR and the SR architectural registers.
3844 Specifically: */
3845 /* *INDENT-OFF* */
3846 /*
3847 FPSRC_C bit
3848 0 Bit 0 of FPSCR
3849 1 reserved
3850 2-17 Bit 2-18 of FPSCR
3851 18-20 Bits 12,13,14 of SR
3852 21-31 reserved
3853 */
3854 /* *INDENT-ON* */
3855 /* Get value as an int. */
3856 fpscr_c_value = extract_unsigned_integer (buffer, 4);
3857
3858 /* Build the new values. */
3859 fpscr_mask = 0x0003fffd;
3860 sr_mask = 0x001c0000;
3861
3862 fpscr_value = fpscr_c_value & fpscr_mask;
3863 sr_value = (fpscr_value & sr_mask) >> 6;
3864
3865 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
3866 old_fpscr_value = extract_unsigned_integer (temp_buffer, 4);
3867 old_fpscr_value &= 0xfffc0002;
3868 fpscr_value |= old_fpscr_value;
3869 store_unsigned_integer (temp_buffer, 4, fpscr_value);
3870 regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer);
3871
3872 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
3873 old_sr_value = extract_unsigned_integer (temp_buffer, 4);
3874 old_sr_value &= 0xffff8fff;
3875 sr_value |= old_sr_value;
3876 store_unsigned_integer (temp_buffer, 4, sr_value);
3877 regcache_raw_write (regcache, sr_base_regnum, temp_buffer);
3878 }
3879
3880 else if (reg_nr == tdep->FPUL_C_REGNUM)
3881 {
3882 base_regnum = sh64_compact_reg_base_num (reg_nr);
3883 regcache_raw_write (regcache, base_regnum, buffer);
3884 }
3885 }
3886
3887 /* Floating point vector of 4 float registers. */
3888 static void
3889 do_fv_register_info (int fv_regnum)
3890 {
3891 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
3892 printf_filtered ("fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3893 fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM,
3894 (int) read_register (first_fp_reg_num),
3895 (int) read_register (first_fp_reg_num + 1),
3896 (int) read_register (first_fp_reg_num + 2),
3897 (int) read_register (first_fp_reg_num + 3));
3898 }
3899
3900 /* Floating point vector of 4 float registers, compact mode. */
3901 static void
3902 do_fv_c_register_info (int fv_regnum)
3903 {
3904 int first_fp_reg_num = sh64_compact_reg_base_num (fv_regnum);
3905 printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3906 fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_C_REGNUM,
3907 (int) read_register (first_fp_reg_num),
3908 (int) read_register (first_fp_reg_num + 1),
3909 (int) read_register (first_fp_reg_num + 2),
3910 (int) read_register (first_fp_reg_num + 3));
3911 }
3912
3913 /* Pairs of single regs. The DR are instead double precision
3914 registers. */
3915 static void
3916 do_fpp_register_info (int fpp_regnum)
3917 {
3918 int first_fp_reg_num = fpp_reg_base_num (fpp_regnum);
3919
3920 printf_filtered ("fpp%d\t0x%08x\t0x%08x\n",
3921 fpp_regnum - gdbarch_tdep (current_gdbarch)->FPP0_REGNUM,
3922 (int) read_register (first_fp_reg_num),
3923 (int) read_register (first_fp_reg_num + 1));
3924 }
3925
3926 /* Double precision registers. */
3927 static void
3928 do_dr_register_info (int dr_regnum)
3929 {
3930 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
3931
3932 printf_filtered ("dr%d\t0x%08x%08x\n",
3933 dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM,
3934 (int) read_register (first_fp_reg_num),
3935 (int) read_register (first_fp_reg_num + 1));
3936 }
3937
3938 /* Double precision registers, compact mode. */
3939 static void
3940 do_dr_c_register_info (int dr_regnum)
3941 {
3942 int first_fp_reg_num = sh64_compact_reg_base_num (dr_regnum);
3943
3944 printf_filtered ("dr%d_c\t0x%08x%08x\n",
3945 dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_C_REGNUM,
3946 (int) read_register (first_fp_reg_num),
3947 (int) read_register (first_fp_reg_num +1));
3948 }
3949
3950 /* General register in compact mode. */
3951 static void
3952 do_r_c_register_info (int r_c_regnum)
3953 {
3954 int regnum = sh64_compact_reg_base_num (r_c_regnum);
3955
3956 printf_filtered ("r%d_c\t0x%08x\n",
3957 r_c_regnum - gdbarch_tdep (current_gdbarch)->R0_C_REGNUM,
3958 /*FIXME!!!*/ (int) read_register (regnum));
3959 }
3960
3961 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
3962 shmedia REGISTERS. */
3963 /* Control registers, compact mode. */
3964 static void
3965 do_cr_c_register_info (int cr_c_regnum)
3966 {
3967 switch (cr_c_regnum)
3968 {
3969 case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3970 break;
3971 case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3972 break;
3973 case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3974 break;
3975 case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3976 break;
3977 case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3978 break;
3979 case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3980 break;
3981 case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3982 break;
3983 case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum));
3984 break;
3985 }
3986 }
3987
3988 static void
3989 sh_do_pseudo_register (int regnum)
3990 {
3991 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3992
3993 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
3994 internal_error (__FILE__, __LINE__,
3995 "Invalid pseudo register number %d\n", regnum);
3996 else if (regnum >= tdep->DR0_REGNUM
3997 && regnum < tdep->DR_LAST_REGNUM)
3998 do_dr_register_info (regnum);
3999 else if (regnum >= tdep->FV0_REGNUM
4000 && regnum <= tdep->FV_LAST_REGNUM)
4001 do_fv_register_info (regnum);
4002 }
4003
4004 static void
4005 sh_do_fp_register (int regnum)
4006 { /* do values for FP (float) regs */
4007 char *raw_buffer;
4008 double flt; /* double extracted from raw hex data */
4009 int inv;
4010 int j;
4011
4012 /* Allocate space for the float. */
4013 raw_buffer = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM));
4014
4015 /* Get the data in raw format. */
4016 if (!frame_register_read (deprecated_selected_frame, regnum, raw_buffer))
4017 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
4018
4019 /* Get the register as a number */
4020 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
4021
4022 /* Print the name and some spaces. */
4023 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
4024 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
4025
4026 /* Print the value. */
4027 if (inv)
4028 printf_filtered ("<invalid float>");
4029 else
4030 printf_filtered ("%-10.9g", flt);
4031
4032 /* Print the fp register as hex. */
4033 printf_filtered ("\t(raw 0x");
4034 for (j = 0; j < REGISTER_RAW_SIZE (regnum); j++)
4035 {
4036 register int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j
4037 : REGISTER_RAW_SIZE (regnum) - 1 - j;
4038 printf_filtered ("%02x", (unsigned char) raw_buffer[idx]);
4039 }
4040 printf_filtered (")");
4041 printf_filtered ("\n");
4042 }
4043
4044 static void
4045 sh64_do_pseudo_register (int regnum)
4046 {
4047 /* All the sh64-compact mode registers are pseudo registers. */
4048 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4049
4050 if (regnum < NUM_REGS
4051 || regnum >= NUM_REGS + NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT)
4052 internal_error (__FILE__, __LINE__,
4053 "Invalid pseudo register number %d\n", regnum);
4054
4055 else if ((regnum >= tdep->DR0_REGNUM
4056 && regnum <= tdep->DR_LAST_REGNUM))
4057 do_dr_register_info (regnum);
4058
4059 else if ((regnum >= tdep->DR0_C_REGNUM
4060 && regnum <= tdep->DR_LAST_C_REGNUM))
4061 do_dr_c_register_info (regnum);
4062
4063 else if ((regnum >= tdep->FV0_REGNUM
4064 && regnum <= tdep->FV_LAST_REGNUM))
4065 do_fv_register_info (regnum);
4066
4067 else if ((regnum >= tdep->FV0_C_REGNUM
4068 && regnum <= tdep->FV_LAST_C_REGNUM))
4069 do_fv_c_register_info (regnum);
4070
4071 else if (regnum >= tdep->FPP0_REGNUM
4072 && regnum <= tdep->FPP_LAST_REGNUM)
4073 do_fpp_register_info (regnum);
4074
4075 else if (regnum >= tdep->R0_C_REGNUM
4076 && regnum <= tdep->R_LAST_C_REGNUM)
4077 do_r_c_register_info (regnum); /* FIXME, this function will not print the right format */
4078
4079 else if (regnum >= tdep->FP0_C_REGNUM
4080 && regnum <= tdep->FP_LAST_C_REGNUM)
4081 sh_do_fp_register (regnum); /* this should work also for pseudoregs */
4082
4083 else if (regnum >= tdep->PC_C_REGNUM
4084 && regnum <= tdep->FPUL_C_REGNUM)
4085 do_cr_c_register_info (regnum);
4086
4087 }
4088
4089 static void
4090 sh_do_register (int regnum)
4091 {
4092 char raw_buffer[MAX_REGISTER_SIZE];
4093
4094 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
4095 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
4096
4097 /* Get the data in raw format. */
4098 if (!frame_register_read (deprecated_selected_frame, regnum, raw_buffer))
4099 printf_filtered ("*value not available*\n");
4100
4101 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
4102 gdb_stdout, 'x', 1, 0, Val_pretty_default);
4103 printf_filtered ("\t");
4104 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
4105 gdb_stdout, 0, 1, 0, Val_pretty_default);
4106 printf_filtered ("\n");
4107 }
4108
4109 static void
4110 sh_print_register (int regnum)
4111 {
4112 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
4113 internal_error (__FILE__, __LINE__,
4114 "Invalid register number %d\n", regnum);
4115
4116 else if (regnum >= 0 && regnum < NUM_REGS)
4117 {
4118 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4119 sh_do_fp_register (regnum); /* FP regs */
4120 else
4121 sh_do_register (regnum); /* All other regs */
4122 }
4123
4124 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4125 do_pseudo_register (regnum);
4126 }
4127
4128 static void
4129 sh_do_registers_info (int regnum, int fpregs)
4130 {
4131 if (regnum != -1) /* do one specified register */
4132 {
4133 if (*(REGISTER_NAME (regnum)) == '\0')
4134 error ("Not a valid register for the current processor type");
4135
4136 sh_print_register (regnum);
4137 }
4138 else
4139 /* do all (or most) registers */
4140 {
4141 regnum = 0;
4142 while (regnum < NUM_REGS)
4143 {
4144 /* If the register name is empty, it is undefined for this
4145 processor, so don't display anything. */
4146 if (REGISTER_NAME (regnum) == NULL
4147 || *(REGISTER_NAME (regnum)) == '\0')
4148 {
4149 regnum++;
4150 continue;
4151 }
4152
4153 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4154 {
4155 if (fpregs)
4156 {
4157 /* true for "INFO ALL-REGISTERS" command */
4158 sh_do_fp_register (regnum); /* FP regs */
4159 regnum ++;
4160 }
4161 else
4162 regnum += (gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
4163 }
4164 else
4165 {
4166 sh_do_register (regnum); /* All other regs */
4167 regnum++;
4168 }
4169 }
4170
4171 if (fpregs)
4172 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4173 {
4174 do_pseudo_register (regnum);
4175 regnum++;
4176 }
4177 }
4178 }
4179
4180 static void
4181 sh_compact_do_registers_info (int regnum, int fpregs)
4182 {
4183 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4184 if (regnum != -1) /* do one specified register */
4185 {
4186 if (*(REGISTER_NAME (regnum)) == '\0')
4187 error ("Not a valid register for the current processor type");
4188
4189 if (regnum >= 0 && regnum < tdep->R0_C_REGNUM)
4190 error ("Not a valid register for the current processor mode.");
4191
4192 sh_print_register (regnum);
4193 }
4194 else
4195 /* do all compact registers */
4196 {
4197 regnum = tdep->R0_C_REGNUM;
4198 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4199 {
4200 do_pseudo_register (regnum);
4201 regnum++;
4202 }
4203 }
4204 }
4205
4206 static void
4207 sh64_do_registers_info (int regnum, int fpregs)
4208 {
4209 if (pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
4210 sh_do_registers_info (regnum, fpregs);
4211 else
4212 sh_compact_do_registers_info (regnum, fpregs);
4213 }
4214
4215 #ifdef SVR4_SHARED_LIBS
4216
4217 /* Fetch (and possibly build) an appropriate link_map_offsets structure
4218 for native i386 linux targets using the struct offsets defined in
4219 link.h (but without actual reference to that file).
4220
4221 This makes it possible to access i386-linux shared libraries from
4222 a gdb that was not built on an i386-linux host (for cross debugging).
4223 */
4224
4225 struct link_map_offsets *
4226 sh_linux_svr4_fetch_link_map_offsets (void)
4227 {
4228 static struct link_map_offsets lmo;
4229 static struct link_map_offsets *lmp = 0;
4230
4231 if (lmp == 0)
4232 {
4233 lmp = &lmo;
4234
4235 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
4236
4237 lmo.r_map_offset = 4;
4238 lmo.r_map_size = 4;
4239
4240 lmo.link_map_size = 20; /* 552 not actual size but all we need */
4241
4242 lmo.l_addr_offset = 0;
4243 lmo.l_addr_size = 4;
4244
4245 lmo.l_name_offset = 4;
4246 lmo.l_name_size = 4;
4247
4248 lmo.l_next_offset = 12;
4249 lmo.l_next_size = 4;
4250
4251 lmo.l_prev_offset = 16;
4252 lmo.l_prev_size = 4;
4253 }
4254
4255 return lmp;
4256 }
4257 #endif /* SVR4_SHARED_LIBS */
4258
4259 \f
4260 enum
4261 {
4262 DSP_DSR_REGNUM = 24,
4263 DSP_A0G_REGNUM,
4264 DSP_A0_REGNUM,
4265 DSP_A1G_REGNUM,
4266 DSP_A1_REGNUM,
4267 DSP_M0_REGNUM,
4268 DSP_M1_REGNUM,
4269 DSP_X0_REGNUM,
4270 DSP_X1_REGNUM,
4271 DSP_Y0_REGNUM,
4272 DSP_Y1_REGNUM,
4273
4274 DSP_MOD_REGNUM = 40,
4275
4276 DSP_RS_REGNUM = 43,
4277 DSP_RE_REGNUM,
4278
4279 DSP_R0_BANK_REGNUM = 51,
4280 DSP_R7_BANK_REGNUM = DSP_R0_BANK_REGNUM + 7
4281 };
4282
4283 static int
4284 sh_dsp_register_sim_regno (int nr)
4285 {
4286 if (legacy_register_sim_regno (nr) < 0)
4287 return legacy_register_sim_regno (nr);
4288 if (nr >= DSP_DSR_REGNUM && nr <= DSP_Y1_REGNUM)
4289 return nr - DSP_DSR_REGNUM + SIM_SH_DSR_REGNUM;
4290 if (nr == DSP_MOD_REGNUM)
4291 return SIM_SH_MOD_REGNUM;
4292 if (nr == DSP_RS_REGNUM)
4293 return SIM_SH_RS_REGNUM;
4294 if (nr == DSP_RE_REGNUM)
4295 return SIM_SH_RE_REGNUM;
4296 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
4297 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
4298 return nr;
4299 }
4300 \f
4301 static gdbarch_init_ftype sh_gdbarch_init;
4302
4303 static struct gdbarch *
4304 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
4305 {
4306 static LONGEST sh_call_dummy_words[] = {0};
4307 struct gdbarch *gdbarch;
4308 struct gdbarch_tdep *tdep;
4309 gdbarch_register_name_ftype *sh_register_name;
4310 gdbarch_deprecated_store_return_value_ftype *sh_store_return_value;
4311 gdbarch_deprecated_register_virtual_type_ftype *sh_register_virtual_type;
4312
4313 /* If there is already a candidate, use it. */
4314 arches = gdbarch_list_lookup_by_info (arches, &info);
4315 if (arches != NULL)
4316 return arches->gdbarch;
4317
4318 /* None found, create a new architecture from the information
4319 provided. */
4320 tdep = XMALLOC (struct gdbarch_tdep);
4321 gdbarch = gdbarch_alloc (&info, tdep);
4322
4323 /* NOTE: cagney/2002-12-06: This can be deleted when this arch is
4324 ready to unwind the PC first (see frame.c:get_prev_frame()). */
4325 set_gdbarch_deprecated_init_frame_pc (gdbarch, init_frame_pc_default);
4326
4327 /* Initialize the register numbers that are not common to all the
4328 variants to -1, if necessary thse will be overwritten in the case
4329 statement below. */
4330 tdep->FPUL_REGNUM = -1;
4331 tdep->FPSCR_REGNUM = -1;
4332 tdep->PR_REGNUM = 17;
4333 tdep->SR_REGNUM = 22;
4334 tdep->DSR_REGNUM = -1;
4335 tdep->FP_LAST_REGNUM = -1;
4336 tdep->A0G_REGNUM = -1;
4337 tdep->A0_REGNUM = -1;
4338 tdep->A1G_REGNUM = -1;
4339 tdep->A1_REGNUM = -1;
4340 tdep->M0_REGNUM = -1;
4341 tdep->M1_REGNUM = -1;
4342 tdep->X0_REGNUM = -1;
4343 tdep->X1_REGNUM = -1;
4344 tdep->Y0_REGNUM = -1;
4345 tdep->Y1_REGNUM = -1;
4346 tdep->MOD_REGNUM = -1;
4347 tdep->RS_REGNUM = -1;
4348 tdep->RE_REGNUM = -1;
4349 tdep->SSR_REGNUM = -1;
4350 tdep->SPC_REGNUM = -1;
4351 tdep->DR0_REGNUM = -1;
4352 tdep->DR_LAST_REGNUM = -1;
4353 tdep->FV0_REGNUM = -1;
4354 tdep->FV_LAST_REGNUM = -1;
4355 tdep->ARG0_REGNUM = 4;
4356 tdep->ARGLAST_REGNUM = 7;
4357 tdep->RETURN_REGNUM = 0;
4358 tdep->FLOAT_ARGLAST_REGNUM = -1;
4359
4360 tdep->sh_abi = SH_ABI_UNKNOWN;
4361
4362 set_gdbarch_fp0_regnum (gdbarch, -1);
4363 set_gdbarch_num_pseudo_regs (gdbarch, 0);
4364 set_gdbarch_deprecated_max_register_raw_size (gdbarch, 4);
4365 set_gdbarch_deprecated_max_register_virtual_size (gdbarch, 4);
4366 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4367 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4368 set_gdbarch_num_regs (gdbarch, SH_DEFAULT_NUM_REGS);
4369 set_gdbarch_sp_regnum (gdbarch, 15);
4370 set_gdbarch_deprecated_fp_regnum (gdbarch, 14);
4371 set_gdbarch_pc_regnum (gdbarch, 16);
4372 set_gdbarch_deprecated_register_size (gdbarch, 4);
4373 set_gdbarch_deprecated_register_bytes (gdbarch, SH_DEFAULT_NUM_REGS * 4);
4374 set_gdbarch_deprecated_do_registers_info (gdbarch, sh_do_registers_info);
4375 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
4376 set_gdbarch_deprecated_frame_chain (gdbarch, sh_frame_chain);
4377 set_gdbarch_deprecated_get_saved_register (gdbarch, deprecated_generic_get_saved_register);
4378 set_gdbarch_deprecated_init_extra_frame_info (gdbarch, sh_init_extra_frame_info);
4379 set_gdbarch_deprecated_extract_return_value (gdbarch, sh_extract_return_value);
4380 set_gdbarch_deprecated_push_arguments (gdbarch, sh_push_arguments);
4381 set_gdbarch_deprecated_store_struct_return (gdbarch, sh_store_struct_return);
4382 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
4383 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
4384 set_gdbarch_deprecated_pop_frame (gdbarch, sh_pop_frame);
4385 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
4386 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
4387 skip_prologue_hard_way = sh_skip_prologue_hard_way;
4388 do_pseudo_register = sh_do_pseudo_register;
4389
4390 switch (info.bfd_arch_info->mach)
4391 {
4392 case bfd_mach_sh:
4393 sh_register_name = sh_sh_register_name;
4394 sh_show_regs = sh_generic_show_regs;
4395 sh_store_return_value = sh_default_store_return_value;
4396 sh_register_virtual_type = sh_default_register_virtual_type;
4397 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4398 set_gdbarch_deprecated_register_raw_size (gdbarch, sh_default_register_raw_size);
4399 set_gdbarch_deprecated_register_virtual_size (gdbarch, sh_default_register_raw_size);
4400 set_gdbarch_deprecated_register_byte (gdbarch, sh_default_register_byte);
4401 break;
4402 case bfd_mach_sh2:
4403 sh_register_name = sh_sh_register_name;
4404 sh_show_regs = sh_generic_show_regs;
4405 sh_store_return_value = sh_default_store_return_value;
4406 sh_register_virtual_type = sh_default_register_virtual_type;
4407 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4408 set_gdbarch_deprecated_register_raw_size (gdbarch, sh_default_register_raw_size);
4409 set_gdbarch_deprecated_register_virtual_size (gdbarch, sh_default_register_raw_size);
4410 set_gdbarch_deprecated_register_byte (gdbarch, sh_default_register_byte);
4411 break;
4412 case bfd_mach_sh2e:
4413 sh_register_name = sh_sh2e_register_name;
4414 sh_show_regs = sh2e_show_regs;
4415 sh_store_return_value = sh3e_sh4_store_return_value;
4416 sh_register_virtual_type = sh_sh3e_register_virtual_type;
4417 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4418 set_gdbarch_deprecated_register_raw_size (gdbarch, sh_default_register_raw_size);
4419 set_gdbarch_deprecated_register_virtual_size (gdbarch, sh_default_register_raw_size);
4420 set_gdbarch_deprecated_register_byte (gdbarch, sh_default_register_byte);
4421 set_gdbarch_fp0_regnum (gdbarch, 25);
4422 tdep->FPUL_REGNUM = 23;
4423 tdep->FPSCR_REGNUM = 24;
4424 tdep->FP_LAST_REGNUM = 40;
4425 break;
4426 case bfd_mach_sh_dsp:
4427 sh_register_name = sh_sh_dsp_register_name;
4428 sh_show_regs = sh_dsp_show_regs;
4429 sh_store_return_value = sh_default_store_return_value;
4430 sh_register_virtual_type = sh_default_register_virtual_type;
4431 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4432 set_gdbarch_deprecated_register_raw_size (gdbarch, sh_default_register_raw_size);
4433 set_gdbarch_deprecated_register_virtual_size (gdbarch, sh_default_register_raw_size);
4434 set_gdbarch_deprecated_register_byte (gdbarch, sh_default_register_byte);
4435 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
4436 tdep->DSR_REGNUM = 24;
4437 tdep->A0G_REGNUM = 25;
4438 tdep->A0_REGNUM = 26;
4439 tdep->A1G_REGNUM = 27;
4440 tdep->A1_REGNUM = 28;
4441 tdep->M0_REGNUM = 29;
4442 tdep->M1_REGNUM = 30;
4443 tdep->X0_REGNUM = 31;
4444 tdep->X1_REGNUM = 32;
4445 tdep->Y0_REGNUM = 33;
4446 tdep->Y1_REGNUM = 34;
4447 tdep->MOD_REGNUM = 40;
4448 tdep->RS_REGNUM = 43;
4449 tdep->RE_REGNUM = 44;
4450 break;
4451 case bfd_mach_sh3:
4452 sh_register_name = sh_sh3_register_name;
4453 sh_show_regs = sh3_show_regs;
4454 sh_store_return_value = sh_default_store_return_value;
4455 sh_register_virtual_type = sh_default_register_virtual_type;
4456 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4457 set_gdbarch_deprecated_register_raw_size (gdbarch, sh_default_register_raw_size);
4458 set_gdbarch_deprecated_register_virtual_size (gdbarch, sh_default_register_raw_size);
4459 set_gdbarch_deprecated_register_byte (gdbarch, sh_default_register_byte);
4460 tdep->SSR_REGNUM = 41;
4461 tdep->SPC_REGNUM = 42;
4462 break;
4463 case bfd_mach_sh3e:
4464 sh_register_name = sh_sh3e_register_name;
4465 sh_show_regs = sh3e_show_regs;
4466 sh_store_return_value = sh3e_sh4_store_return_value;
4467 sh_register_virtual_type = sh_sh3e_register_virtual_type;
4468 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
4469 set_gdbarch_deprecated_register_raw_size (gdbarch, sh_default_register_raw_size);
4470 set_gdbarch_deprecated_register_virtual_size (gdbarch, sh_default_register_raw_size);
4471 set_gdbarch_deprecated_register_byte (gdbarch, sh_default_register_byte);
4472 set_gdbarch_deprecated_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
4473 set_gdbarch_fp0_regnum (gdbarch, 25);
4474 tdep->FPUL_REGNUM = 23;
4475 tdep->FPSCR_REGNUM = 24;
4476 tdep->FP_LAST_REGNUM = 40;
4477 tdep->SSR_REGNUM = 41;
4478 tdep->SPC_REGNUM = 42;
4479 break;
4480 case bfd_mach_sh3_dsp:
4481 sh_register_name = sh_sh3_dsp_register_name;
4482 sh_show_regs = sh3_dsp_show_regs;
4483 sh_store_return_value = sh_default_store_return_value;
4484 sh_register_virtual_type = sh_default_register_virtual_type;
4485 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4486 set_gdbarch_deprecated_register_raw_size (gdbarch, sh_default_register_raw_size);
4487 set_gdbarch_deprecated_register_virtual_size (gdbarch, sh_default_register_raw_size);
4488 set_gdbarch_deprecated_register_byte (gdbarch, sh_default_register_byte);
4489 tdep->DSR_REGNUM = 24;
4490 tdep->A0G_REGNUM = 25;
4491 tdep->A0_REGNUM = 26;
4492 tdep->A1G_REGNUM = 27;
4493 tdep->A1_REGNUM = 28;
4494 tdep->M0_REGNUM = 29;
4495 tdep->M1_REGNUM = 30;
4496 tdep->X0_REGNUM = 31;
4497 tdep->X1_REGNUM = 32;
4498 tdep->Y0_REGNUM = 33;
4499 tdep->Y1_REGNUM = 34;
4500 tdep->MOD_REGNUM = 40;
4501 tdep->RS_REGNUM = 43;
4502 tdep->RE_REGNUM = 44;
4503 tdep->SSR_REGNUM = 41;
4504 tdep->SPC_REGNUM = 42;
4505 break;
4506 case bfd_mach_sh4:
4507 sh_register_name = sh_sh4_register_name;
4508 sh_show_regs = sh4_show_regs;
4509 sh_store_return_value = sh3e_sh4_store_return_value;
4510 sh_register_virtual_type = sh_sh4_register_virtual_type;
4511 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
4512 set_gdbarch_deprecated_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
4513 set_gdbarch_fp0_regnum (gdbarch, 25);
4514 set_gdbarch_deprecated_register_raw_size (gdbarch, sh_sh4_register_raw_size);
4515 set_gdbarch_deprecated_register_virtual_size (gdbarch, sh_sh4_register_raw_size);
4516 set_gdbarch_deprecated_register_byte (gdbarch, sh_sh4_register_byte);
4517 set_gdbarch_num_pseudo_regs (gdbarch, 12);
4518 set_gdbarch_deprecated_max_register_raw_size (gdbarch, 4 * 4);
4519 set_gdbarch_deprecated_max_register_virtual_size (gdbarch, 4 * 4);
4520 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
4521 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
4522 tdep->FPUL_REGNUM = 23;
4523 tdep->FPSCR_REGNUM = 24;
4524 tdep->FP_LAST_REGNUM = 40;
4525 tdep->SSR_REGNUM = 41;
4526 tdep->SPC_REGNUM = 42;
4527 tdep->DR0_REGNUM = 59;
4528 tdep->DR_LAST_REGNUM = 66;
4529 tdep->FV0_REGNUM = 67;
4530 tdep->FV_LAST_REGNUM = 70;
4531 break;
4532 case bfd_mach_sh5:
4533 tdep->PR_REGNUM = 18;
4534 tdep->SR_REGNUM = 65;
4535 tdep->FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM;
4536 tdep->FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1;
4537 tdep->SSR_REGNUM = SIM_SH64_SSR_REGNUM;
4538 tdep->SPC_REGNUM = SIM_SH64_SPC_REGNUM;
4539 tdep->TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7;
4540 tdep->FPP0_REGNUM = 173;
4541 tdep->FPP_LAST_REGNUM = 204;
4542 tdep->DR0_REGNUM = 141;
4543 tdep->DR_LAST_REGNUM = 172;
4544 tdep->FV0_REGNUM = 205;
4545 tdep->FV_LAST_REGNUM = 220;
4546 tdep->R0_C_REGNUM = 221;
4547 tdep->R_LAST_C_REGNUM = 236;
4548 tdep->PC_C_REGNUM = 237;
4549 tdep->GBR_C_REGNUM = 238;
4550 tdep->MACH_C_REGNUM = 239;
4551 tdep->MACL_C_REGNUM = 240;
4552 tdep->PR_C_REGNUM = 241;
4553 tdep->T_C_REGNUM = 242;
4554 tdep->FPSCR_C_REGNUM = 243;
4555 tdep->FPUL_C_REGNUM = 244;
4556 tdep->FP0_C_REGNUM = 245;
4557 tdep->FP_LAST_C_REGNUM = 260;
4558 tdep->DR0_C_REGNUM = 261;
4559 tdep->DR_LAST_C_REGNUM = 268;
4560 tdep->FV0_C_REGNUM = 269;
4561 tdep->FV_LAST_C_REGNUM = 272;
4562 tdep->ARG0_REGNUM = 2;
4563 tdep->ARGLAST_REGNUM = 9;
4564 tdep->RETURN_REGNUM = 2;
4565 tdep->FLOAT_ARGLAST_REGNUM = 11;
4566
4567 set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT);
4568 set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM);
4569 set_gdbarch_pc_regnum (gdbarch, 64);
4570
4571 /* Determine the ABI */
4572 if (bfd_get_arch_size (info.abfd) == 64)
4573 {
4574 /* If the ABI is the 64-bit one, it can only be sh-media. */
4575 tdep->sh_abi = SH_ABI_64;
4576 set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4577 set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4578 }
4579 else
4580 {
4581 /* If the ABI is the 32-bit one it could be either media or
4582 compact. */
4583 tdep->sh_abi = SH_ABI_32;
4584 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4585 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4586 }
4587
4588 /* the number of real registers is the same whether we are in
4589 ISA16(compact) or ISA32(media). */
4590 set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS);
4591 set_gdbarch_deprecated_register_size (gdbarch, 8); /*????*/
4592 set_gdbarch_deprecated_register_bytes (gdbarch,
4593 ((SIM_SH64_NR_FP_REGS + 1) * 4)
4594 + (SIM_SH64_NR_REGS - SIM_SH64_NR_FP_REGS -1) * 8);
4595
4596 sh_register_name = sh_sh64_register_name;
4597 sh_show_regs = sh64_show_regs;
4598 sh_register_virtual_type = sh_sh64_register_virtual_type;
4599 sh_store_return_value = sh64_store_return_value;
4600 skip_prologue_hard_way = sh64_skip_prologue_hard_way;
4601 do_pseudo_register = sh64_do_pseudo_register;
4602 set_gdbarch_deprecated_register_raw_size (gdbarch, sh_sh64_register_raw_size);
4603 set_gdbarch_deprecated_register_virtual_size (gdbarch, sh_sh64_register_raw_size);
4604 set_gdbarch_deprecated_register_byte (gdbarch, sh_sh64_register_byte);
4605 /* This seems awfully wrong!*/
4606 /*set_gdbarch_deprecated_max_register_raw_size (gdbarch, 8);*/
4607 /* should include the size of the pseudo regs. */
4608 set_gdbarch_deprecated_max_register_raw_size (gdbarch, 4 * 4);
4609 /* Or should that go in the virtual_size? */
4610 /*set_gdbarch_deprecated_max_register_virtual_size (gdbarch, 8);*/
4611 set_gdbarch_deprecated_max_register_virtual_size (gdbarch, 4 * 4);
4612 set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read);
4613 set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write);
4614
4615 set_gdbarch_deprecated_do_registers_info (gdbarch, sh64_do_registers_info);
4616 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh64_nofp_frame_init_saved_regs);
4617 set_gdbarch_breakpoint_from_pc (gdbarch, sh_sh64_breakpoint_from_pc);
4618 set_gdbarch_deprecated_init_extra_frame_info (gdbarch, sh64_init_extra_frame_info);
4619 set_gdbarch_deprecated_frame_chain (gdbarch, sh64_frame_chain);
4620 set_gdbarch_deprecated_get_saved_register (gdbarch, sh64_get_saved_register);
4621 set_gdbarch_deprecated_extract_return_value (gdbarch, sh64_extract_return_value);
4622 set_gdbarch_deprecated_push_arguments (gdbarch, sh64_push_arguments);
4623 /*set_gdbarch_deprecated_store_struct_return (gdbarch, sh64_store_struct_return);*/
4624 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh64_extract_struct_value_address);
4625 set_gdbarch_use_struct_convention (gdbarch, sh64_use_struct_convention);
4626 set_gdbarch_deprecated_pop_frame (gdbarch, sh64_pop_frame);
4627 set_gdbarch_elf_make_msymbol_special (gdbarch,
4628 sh64_elf_make_msymbol_special);
4629 break;
4630 default:
4631 sh_register_name = sh_generic_register_name;
4632 sh_show_regs = sh_generic_show_regs;
4633 sh_store_return_value = sh_default_store_return_value;
4634 sh_register_virtual_type = sh_default_register_virtual_type;
4635 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4636 set_gdbarch_deprecated_register_raw_size (gdbarch, sh_default_register_raw_size);
4637 set_gdbarch_deprecated_register_virtual_size (gdbarch, sh_default_register_raw_size);
4638 set_gdbarch_deprecated_register_byte (gdbarch, sh_default_register_byte);
4639 break;
4640 }
4641
4642 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
4643 set_gdbarch_deprecated_dummy_write_sp (gdbarch, deprecated_write_sp);
4644
4645 set_gdbarch_register_name (gdbarch, sh_register_name);
4646 set_gdbarch_deprecated_register_virtual_type (gdbarch, sh_register_virtual_type);
4647
4648 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
4649 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4650 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4651 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4652 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4653 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4654
4655 set_gdbarch_deprecated_call_dummy_words (gdbarch, sh_call_dummy_words);
4656 set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, sizeof (sh_call_dummy_words));
4657
4658 set_gdbarch_deprecated_push_return_address (gdbarch, sh_push_return_address);
4659
4660 set_gdbarch_deprecated_store_return_value (gdbarch, sh_store_return_value);
4661 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
4662 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4663 set_gdbarch_decr_pc_after_break (gdbarch, 0);
4664 set_gdbarch_function_start_offset (gdbarch, 0);
4665
4666 set_gdbarch_frame_args_skip (gdbarch, 0);
4667 set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
4668 set_gdbarch_deprecated_frame_saved_pc (gdbarch, sh_frame_saved_pc);
4669 set_gdbarch_deprecated_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
4670 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
4671
4672 /* Hook in ABI-specific overrides, if they have been registered. */
4673 gdbarch_init_osabi (info, gdbarch);
4674
4675 return gdbarch;
4676 }
4677
4678 static void
4679 sh_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
4680 {
4681 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4682
4683 if (tdep == NULL)
4684 return;
4685
4686 /* FIXME: dump the rest of gdbarch_tdep. */
4687 }
4688
4689 extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
4690
4691 void
4692 _initialize_sh_tdep (void)
4693 {
4694 struct cmd_list_element *c;
4695
4696 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, sh_dump_tdep);
4697
4698 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");
4699 }
GDB Binutils - Deliverables
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