1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993-2016 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* Contributed by Steve Chamberlain
25 #include "frame-base.h"
26 #include "frame-unwind.h"
27 #include "dwarf2-frame.h"
35 #include "arch-utils.h"
44 /* Register numbers shared with the simulator. */
45 #include "gdb/sim-sh.h"
47 #include "sh64-tdep.h"
50 /* Information that is dependent on the processor variant. */
63 struct sh64_frame_cache
70 /* Flag showing that a frame has been created in the prologue code. */
75 /* Saved registers. */
76 CORE_ADDR saved_regs
[SIM_SH64_NR_REGS
];
80 /* Registers of SH5 */
84 DEFAULT_RETURN_REGNUM
= 2,
85 STRUCT_RETURN_REGNUM
= 2,
88 FLOAT_ARGLAST_REGNUM
= 11,
94 /* FPP stands for Floating Point Pair, to avoid confusion with
95 GDB's gdbarch_fp0_regnum, which is the number of the first Floating
96 point register. Unfortunately on the sh5, the floating point
97 registers are called FR, and the floating point pairs are called FP. */
99 FPP_LAST_REGNUM
= 204,
101 FV_LAST_REGNUM
= 220,
103 R_LAST_C_REGNUM
= 236,
110 FPSCR_C_REGNUM
= 243,
113 FP_LAST_C_REGNUM
= 260,
115 DR_LAST_C_REGNUM
= 268,
117 FV_LAST_C_REGNUM
= 272,
118 FPSCR_REGNUM
= SIM_SH64_FPCSR_REGNUM
,
119 SSR_REGNUM
= SIM_SH64_SSR_REGNUM
,
120 SPC_REGNUM
= SIM_SH64_SPC_REGNUM
,
121 TR7_REGNUM
= SIM_SH64_TR0_REGNUM
+ 7,
122 FP_LAST_REGNUM
= SIM_SH64_FR0_REGNUM
+ SIM_SH64_NR_FP_REGS
- 1
126 sh64_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
128 static char *register_names
[] =
130 /* SH MEDIA MODE (ISA 32) */
131 /* general registers (64-bit) 0-63 */
132 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
133 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
134 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
135 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
136 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
137 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
138 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
139 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
144 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
147 /* target registers (64-bit) 68-75 */
148 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
150 /* floating point state control register (32-bit) 76 */
153 /* single precision floating point registers (32-bit) 77-140 */
154 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
155 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
156 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
157 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
158 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
159 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
160 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
161 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
163 /* double precision registers (pseudo) 141-172 */
164 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
165 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
166 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
167 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
169 /* floating point pairs (pseudo) 173-204 */
170 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
171 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
172 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
173 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
175 /* floating point vectors (4 floating point regs) (pseudo) 205-220 */
176 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
177 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
179 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272 */
180 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
181 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
183 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
185 "fr0_c", "fr1_c", "fr2_c", "fr3_c",
186 "fr4_c", "fr5_c", "fr6_c", "fr7_c",
187 "fr8_c", "fr9_c", "fr10_c", "fr11_c",
188 "fr12_c", "fr13_c", "fr14_c", "fr15_c",
189 "dr0_c", "dr2_c", "dr4_c", "dr6_c",
190 "dr8_c", "dr10_c", "dr12_c", "dr14_c",
191 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
192 /* FIXME!!!! XF0 XF15, XD0 XD14 ????? */
197 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
199 return register_names
[reg_nr
];
202 #define NUM_PSEUDO_REGS_SH_MEDIA 80
203 #define NUM_PSEUDO_REGS_SH_COMPACT 51
205 /* Macros and functions for setting and testing a bit in a minimal
206 symbol that marks it as 32-bit function. The MSB of the minimal
207 symbol's "info" field is used for this purpose.
209 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
210 i.e. refers to a 32-bit function, and sets a "special" bit in a
211 minimal symbol to mark it as a 32-bit function
212 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
214 #define MSYMBOL_IS_SPECIAL(msym) \
215 MSYMBOL_TARGET_FLAG_1 (msym)
218 sh64_elf_make_msymbol_special (asymbol
*sym
, struct minimal_symbol
*msym
)
223 if (((elf_symbol_type
*)(sym
))->internal_elf_sym
.st_other
== STO_SH5_ISA32
)
225 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
226 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
230 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
231 are some macros to test, set, or clear bit 0 of addresses. */
232 #define IS_ISA32_ADDR(addr) ((addr) & 1)
233 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
234 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
237 pc_is_isa32 (bfd_vma memaddr
)
239 struct bound_minimal_symbol sym
;
241 /* If bit 0 of the address is set, assume this is a
242 ISA32 (shmedia) address. */
243 if (IS_ISA32_ADDR (memaddr
))
246 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
247 the high bit of the info field. Use this to decide if the function is
249 sym
= lookup_minimal_symbol_by_pc (memaddr
);
251 return MSYMBOL_IS_SPECIAL (sym
.minsym
);
257 sh64_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
259 if (pc_is_isa32 (*pcptr
))
261 *pcptr
= UNMAKE_ISA32_ADDR (*pcptr
);
268 static const gdb_byte
*
269 sh64_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
273 /* The BRK instruction for shmedia is
274 01101111 11110101 11111111 11110000
275 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
276 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
278 /* The BRK instruction for shcompact is
280 which translates in big endian mode to 0x0, 0x3b
281 and in little endian mode to 0x3b, 0x0 */
285 static unsigned char big_breakpoint_media
[] = {
286 0x6f, 0xf5, 0xff, 0xf0
288 static unsigned char little_breakpoint_media
[] = {
289 0xf0, 0xff, 0xf5, 0x6f
292 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
293 return big_breakpoint_media
;
295 return little_breakpoint_media
;
299 static unsigned char big_breakpoint_compact
[] = {0x0, 0x3b};
300 static unsigned char little_breakpoint_compact
[] = {0x3b, 0x0};
302 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
303 return big_breakpoint_compact
;
305 return little_breakpoint_compact
;
309 GDBARCH_BREAKPOINT_FROM_PC (sh64
)
311 /* Prologue looks like
312 [mov.l <regs>,@-r15]...
317 Actually it can be more complicated than this. For instance, with
335 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
336 with l=1 and n = 18 0110101111110001010010100aaa0000 */
337 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
339 /* STS.L PR,@-r0 0100000000100010
340 r0-4-->r0, PR-->(r0) */
341 #define IS_STS_R0(x) ((x) == 0x4022)
343 /* STS PR, Rm 0000mmmm00101010
345 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
347 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
349 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
351 /* MOV.L R14,@(disp,r15) 000111111110dddd
352 R14-->(dispx4+r15) */
353 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
355 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
356 R18-->(dispx8+R14) */
357 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
359 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
360 R18-->(dispx8+R15) */
361 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
363 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
364 R18-->(dispx4+R15) */
365 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
367 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
368 R14-->(dispx8+R15) */
369 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
371 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
372 R14-->(dispx4+R15) */
373 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
375 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
377 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
379 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
381 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
383 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
385 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
387 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
389 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
391 #define IS_MOV_SP_FP_MEDIA(x) \
392 (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
394 /* MOV #imm, R0 1110 0000 ssss ssss
396 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
398 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
399 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
401 /* ADD r15,r0 0011 0000 1111 1100
403 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
405 /* MOV.L R14 @-R0 0010 0000 1110 0110
406 R14-->(R0-4), R0-4-->R0 */
407 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
409 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
410 where Rm is one of r2-r9 which are the argument registers. */
411 /* FIXME: Recognize the float and double register moves too! */
412 #define IS_MEDIA_IND_ARG_MOV(x) \
413 ((((x) & 0xfc0ffc0f) == 0x0009fc00) \
414 && (((x) & 0x03f00000) >= 0x00200000 \
415 && ((x) & 0x03f00000) <= 0x00900000))
417 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
418 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
419 where Rm is one of r2-r9 which are the argument registers. */
420 #define IS_MEDIA_ARG_MOV(x) \
421 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
422 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
424 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000 */
425 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000 */
426 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000 */
427 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000 */
428 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000 */
429 #define IS_MEDIA_MOV_TO_R14(x) \
430 ((((x) & 0xfffffc0f) == 0xa0e00000) \
431 || (((x) & 0xfffffc0f) == 0xa4e00000) \
432 || (((x) & 0xfffffc0f) == 0xa8e00000) \
433 || (((x) & 0xfffffc0f) == 0xb4e00000) \
434 || (((x) & 0xfffffc0f) == 0xbce00000))
436 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
438 #define IS_COMPACT_IND_ARG_MOV(x) \
439 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) \
440 && (((x) & 0x00f0) <= 0x0090))
442 /* compact direct arg move!
443 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
444 #define IS_COMPACT_ARG_MOV(x) \
445 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) \
446 && ((x) & 0x00f0) <= 0x0090))
448 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
449 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
450 #define IS_COMPACT_MOV_TO_R14(x) \
451 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
453 #define IS_JSR_R0(x) ((x) == 0x400b)
454 #define IS_NOP(x) ((x) == 0x0009)
457 /* MOV r15,r14 0110111011110011
459 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
461 /* ADD #imm,r15 01111111iiiiiiii
463 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
465 /* Skip any prologue before the guts of a function. */
467 /* Skip the prologue using the debug information. If this fails we'll
468 fall back on the 'guess' method below. */
470 after_prologue (CORE_ADDR pc
)
472 struct symtab_and_line sal
;
473 CORE_ADDR func_addr
, func_end
;
475 /* If we can not find the symbol in the partial symbol table, then
476 there is no hope we can determine the function's start address
478 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
482 /* Get the line associated with FUNC_ADDR. */
483 sal
= find_pc_line (func_addr
, 0);
485 /* There are only two cases to consider. First, the end of the source line
486 is within the function bounds. In that case we return the end of the
487 source line. Second is the end of the source line extends beyond the
488 bounds of the current function. We need to use the slow code to
489 examine instructions in that case. */
490 if (sal
.end
< func_end
)
497 look_for_args_moves (struct gdbarch
*gdbarch
,
498 CORE_ADDR start_pc
, int media_mode
)
500 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
503 int insn_size
= (media_mode
? 4 : 2);
505 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
509 w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
510 insn_size
, byte_order
);
512 if (IS_MEDIA_IND_ARG_MOV (w
))
514 /* This must be followed by a store to r14, so the argument
515 is where the debug info says it is. This can happen after
516 the SP has been saved, unfortunately. */
518 int next_insn
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
519 insn_size
, byte_order
);
521 if (IS_MEDIA_MOV_TO_R14 (next_insn
))
524 else if (IS_MEDIA_ARG_MOV (w
))
526 /* These instructions store directly the argument in r14. */
534 w
= read_memory_integer (here
, insn_size
, byte_order
);
537 if (IS_COMPACT_IND_ARG_MOV (w
))
539 /* This must be followed by a store to r14, so the argument
540 is where the debug info says it is. This can happen after
541 the SP has been saved, unfortunately. */
543 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
,
546 if (IS_COMPACT_MOV_TO_R14 (next_insn
))
549 else if (IS_COMPACT_ARG_MOV (w
))
551 /* These instructions store directly the argument in r14. */
554 else if (IS_MOVL_R0 (w
))
556 /* There is a function that gcc calls to get the arguments
557 passed correctly to the function. Only after this
558 function call the arguments will be found at the place
559 where they are supposed to be. This happens in case the
560 argument has to be stored into a 64-bit register (for
561 instance doubles, long longs). SHcompact doesn't have
562 access to the full 64-bits, so we store the register in
563 stack slot and store the address of the stack slot in
564 the register, then do a call through a wrapper that
565 loads the memory value into the register. A SHcompact
566 callee calls an argument decoder
567 (GCC_shcompact_incoming_args) that stores the 64-bit
568 value in a stack slot and stores the address of the
569 stack slot in the register. GCC thinks the argument is
570 just passed by transparent reference, but this is only
571 true after the argument decoder is called. Such a call
572 needs to be considered part of the prologue. */
574 /* This must be followed by a JSR @r0 instruction and by
575 a NOP instruction. After these, the prologue is over! */
577 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
,
580 if (IS_JSR_R0 (next_insn
))
582 next_insn
= 0xffff & read_memory_integer (here
, insn_size
,
586 if (IS_NOP (next_insn
))
599 sh64_skip_prologue_hard_way (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
601 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
610 if (pc_is_isa32 (start_pc
) == 0)
616 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
621 int w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
622 insn_size
, byte_order
);
624 if (IS_STQ_R18_R14 (w
) || IS_STQ_R18_R15 (w
) || IS_STQ_R14_R15 (w
)
625 || IS_STL_R14_R15 (w
) || IS_STL_R18_R15 (w
)
626 || IS_ADDIL_SP_MEDIA (w
) || IS_ADDI_SP_MEDIA (w
)
627 || IS_PTABSL_R18 (w
))
631 else if (IS_MOV_SP_FP (w
) || IS_MOV_SP_FP_MEDIA(w
))
639 /* Don't bail out yet, we may have arguments stored in
640 registers here, according to the debug info, so that
641 gdb can print the frames correctly. */
642 start_pc
= look_for_args_moves (gdbarch
,
643 here
- insn_size
, media_mode
);
649 int w
= 0xffff & read_memory_integer (here
, insn_size
, byte_order
);
652 if (IS_STS_R0 (w
) || IS_STS_PR (w
)
653 || IS_MOV_TO_R15 (w
) || IS_MOV_R14 (w
)
654 || IS_MOV_R0 (w
) || IS_ADD_SP_R0 (w
) || IS_MOV_R14_R0 (w
))
658 else if (IS_MOV_SP_FP (w
))
666 /* Don't bail out yet, we may have arguments stored in
667 registers here, according to the debug info, so that
668 gdb can print the frames correctly. */
669 start_pc
= look_for_args_moves (gdbarch
,
670 here
- insn_size
, media_mode
);
680 sh64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
682 CORE_ADDR post_prologue_pc
;
684 /* See if we can determine the end of the prologue via the symbol table.
685 If so, then return either PC, or the PC after the prologue, whichever
687 post_prologue_pc
= after_prologue (pc
);
689 /* If after_prologue returned a useful address, then use it. Else
690 fall back on the instruction skipping code. */
691 if (post_prologue_pc
!= 0)
692 return std::max (pc
, post_prologue_pc
);
694 return sh64_skip_prologue_hard_way (gdbarch
, pc
);
697 /* Should call_function allocate stack space for a struct return? */
699 sh64_use_struct_convention (struct type
*type
)
701 return (TYPE_LENGTH (type
) > 8);
704 /* For vectors of 4 floating point registers. */
706 sh64_fv_reg_base_num (struct gdbarch
*gdbarch
, int fv_regnum
)
710 fp_regnum
= gdbarch_fp0_regnum (gdbarch
) + (fv_regnum
- FV0_REGNUM
) * 4;
714 /* For double precision floating point registers, i.e 2 fp regs. */
716 sh64_dr_reg_base_num (struct gdbarch
*gdbarch
, int dr_regnum
)
720 fp_regnum
= gdbarch_fp0_regnum (gdbarch
) + (dr_regnum
- DR0_REGNUM
) * 2;
724 /* For pairs of floating point registers. */
726 sh64_fpp_reg_base_num (struct gdbarch
*gdbarch
, int fpp_regnum
)
730 fp_regnum
= gdbarch_fp0_regnum (gdbarch
) + (fpp_regnum
- FPP0_REGNUM
) * 2;
736 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
737 GDB_REGNUM BASE_REGNUM
797 sh64_compact_reg_base_num (struct gdbarch
*gdbarch
, int reg_nr
)
799 int base_regnum
= reg_nr
;
801 /* general register N maps to general register N */
802 if (reg_nr
>= R0_C_REGNUM
803 && reg_nr
<= R_LAST_C_REGNUM
)
804 base_regnum
= reg_nr
- R0_C_REGNUM
;
806 /* floating point register N maps to floating point register N */
807 else if (reg_nr
>= FP0_C_REGNUM
808 && reg_nr
<= FP_LAST_C_REGNUM
)
809 base_regnum
= reg_nr
- FP0_C_REGNUM
+ gdbarch_fp0_regnum (gdbarch
);
811 /* double prec register N maps to base regnum for double prec register N */
812 else if (reg_nr
>= DR0_C_REGNUM
813 && reg_nr
<= DR_LAST_C_REGNUM
)
814 base_regnum
= sh64_dr_reg_base_num (gdbarch
,
815 DR0_REGNUM
+ reg_nr
- DR0_C_REGNUM
);
817 /* vector N maps to base regnum for vector register N */
818 else if (reg_nr
>= FV0_C_REGNUM
819 && reg_nr
<= FV_LAST_C_REGNUM
)
820 base_regnum
= sh64_fv_reg_base_num (gdbarch
,
821 FV0_REGNUM
+ reg_nr
- FV0_C_REGNUM
);
823 else if (reg_nr
== PC_C_REGNUM
)
824 base_regnum
= gdbarch_pc_regnum (gdbarch
);
826 else if (reg_nr
== GBR_C_REGNUM
)
829 else if (reg_nr
== MACH_C_REGNUM
830 || reg_nr
== MACL_C_REGNUM
)
833 else if (reg_nr
== PR_C_REGNUM
)
834 base_regnum
= PR_REGNUM
;
836 else if (reg_nr
== T_C_REGNUM
)
839 else if (reg_nr
== FPSCR_C_REGNUM
)
840 base_regnum
= FPSCR_REGNUM
; /*???? this register is a mess. */
842 else if (reg_nr
== FPUL_C_REGNUM
)
843 base_regnum
= gdbarch_fp0_regnum (gdbarch
) + 32;
849 sign_extend (int value
, int bits
)
851 value
= value
& ((1 << bits
) - 1);
852 return (value
& (1 << (bits
- 1))
853 ? value
| (~((1 << bits
) - 1))
858 sh64_analyze_prologue (struct gdbarch
*gdbarch
,
859 struct sh64_frame_cache
*cache
,
861 CORE_ADDR current_pc
)
868 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
870 cache
->sp_offset
= 0;
872 /* Loop around examining the prologue insns until we find something
873 that does not appear to be part of the prologue. But give up
874 after 20 of them, since we're getting silly then. */
878 if (cache
->media_mode
)
883 opc
= pc
+ (insn_size
* 28);
884 if (opc
> current_pc
)
886 for ( ; pc
<= opc
; pc
+= insn_size
)
888 insn
= read_memory_integer (cache
->media_mode
? UNMAKE_ISA32_ADDR (pc
)
890 insn_size
, byte_order
);
892 if (!cache
->media_mode
)
894 if (IS_STS_PR (insn
))
896 int next_insn
= read_memory_integer (pc
+ insn_size
,
897 insn_size
, byte_order
);
898 if (IS_MOV_TO_R15 (next_insn
))
900 cache
->saved_regs
[PR_REGNUM
]
901 = cache
->sp_offset
- ((((next_insn
& 0xf) ^ 0x8)
907 else if (IS_MOV_R14 (insn
))
909 cache
->saved_regs
[MEDIA_FP_REGNUM
] =
910 cache
->sp_offset
- ((((insn
& 0xf) ^ 0x8) - 0x8) << 2);
914 else if (IS_MOV_R0 (insn
))
916 /* Put in R0 the offset from SP at which to store some
917 registers. We are interested in this value, because it
918 will tell us where the given registers are stored within
920 r0_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
923 else if (IS_ADD_SP_R0 (insn
))
925 /* This instruction still prepares r0, but we don't care.
926 We already have the offset in r0_val. */
929 else if (IS_STS_R0 (insn
))
931 /* Store PR at r0_val-4 from SP. Decrement r0 by 4. */
932 cache
->saved_regs
[PR_REGNUM
] = cache
->sp_offset
- (r0_val
- 4);
936 else if (IS_MOV_R14_R0 (insn
))
938 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4. */
939 cache
->saved_regs
[MEDIA_FP_REGNUM
] = cache
->sp_offset
945 else if (IS_ADD_SP (insn
))
946 cache
->sp_offset
-= ((insn
& 0xff) ^ 0x80) - 0x80;
948 else if (IS_MOV_SP_FP (insn
))
953 if (IS_ADDIL_SP_MEDIA (insn
) || IS_ADDI_SP_MEDIA (insn
))
955 sign_extend ((((insn
& 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
957 else if (IS_STQ_R18_R15 (insn
))
958 cache
->saved_regs
[PR_REGNUM
]
959 = cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10,
962 else if (IS_STL_R18_R15 (insn
))
963 cache
->saved_regs
[PR_REGNUM
]
964 = cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10,
967 else if (IS_STQ_R14_R15 (insn
))
969 cache
->saved_regs
[MEDIA_FP_REGNUM
]
970 = cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10,
975 else if (IS_STL_R14_R15 (insn
))
977 cache
->saved_regs
[MEDIA_FP_REGNUM
]
978 = cache
->sp_offset
- (sign_extend ((insn
& 0xffc00) >> 10,
983 else if (IS_MOV_SP_FP_MEDIA (insn
))
990 sh64_frame_align (struct gdbarch
*ignore
, CORE_ADDR sp
)
995 /* Function: push_dummy_call
996 Setup the function arguments for calling a function in the inferior.
998 On the Renesas SH architecture, there are four registers (R4 to R7)
999 which are dedicated for passing function arguments. Up to the first
1000 four arguments (depending on size) may go into these registers.
1001 The rest go on the stack.
1003 Arguments that are smaller than 4 bytes will still take up a whole
1004 register or a whole 32-bit word on the stack, and will be
1005 right-justified in the register or the stack word. This includes
1006 chars, shorts, and small aggregate types.
1008 Arguments that are larger than 4 bytes may be split between two or
1009 more registers. If there are not enough registers free, an argument
1010 may be passed partly in a register (or registers), and partly on the
1011 stack. This includes doubles, long longs, and larger aggregates.
1012 As far as I know, there is no upper limit to the size of aggregates
1013 that will be passed in this way; in other words, the convention of
1014 passing a pointer to a large aggregate instead of a copy is not used.
1016 An exceptional case exists for struct arguments (and possibly other
1017 aggregates such as arrays) if the size is larger than 4 bytes but
1018 not a multiple of 4 bytes. In this case the argument is never split
1019 between the registers and the stack, but instead is copied in its
1020 entirety onto the stack, AND also copied into as many registers as
1021 there is room for. In other words, space in registers permitting,
1022 two copies of the same argument are passed in. As far as I can tell,
1023 only the one on the stack is used, although that may be a function
1024 of the level of compiler optimization. I suspect this is a compiler
1025 bug. Arguments of these odd sizes are left-justified within the
1026 word (as opposed to arguments smaller than 4 bytes, which are
1029 If the function is to return an aggregate type such as a struct, it
1030 is either returned in the normal return value register R0 (if its
1031 size is no greater than one byte), or else the caller must allocate
1032 space into which the callee will copy the return value (if the size
1033 is greater than one byte). In this case, a pointer to the return
1034 value location is passed into the callee in register R2, which does
1035 not displace any of the other arguments passed in via registers R4
1038 /* R2-R9 for integer types and integer equivalent (char, pointers) and
1039 non-scalar (struct, union) elements (even if the elements are
1041 FR0-FR11 for single precision floating point (float)
1042 DR0-DR10 for double precision floating point (double)
1044 If a float is argument number 3 (for instance) and arguments number
1045 1,2, and 4 are integer, the mapping will be:
1046 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
1048 If a float is argument number 10 (for instance) and arguments number
1049 1 through 10 are integer, the mapping will be:
1050 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
1051 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0,
1052 arg11->stack(16,SP). I.e. there is hole in the stack.
1054 Different rules apply for variable arguments functions, and for functions
1055 for which the prototype is not known. */
1058 sh64_push_dummy_call (struct gdbarch
*gdbarch
,
1059 struct value
*function
,
1060 struct regcache
*regcache
,
1062 int nargs
, struct value
**args
,
1063 CORE_ADDR sp
, int struct_return
,
1064 CORE_ADDR struct_addr
)
1066 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1067 int stack_offset
, stack_alloc
;
1069 int float_arg_index
= 0;
1070 int double_arg_index
= 0;
1074 const gdb_byte
*val
;
1080 memset (fp_args
, 0, sizeof (fp_args
));
1082 /* First force sp to a 8-byte alignment. */
1083 sp
= sh64_frame_align (gdbarch
, sp
);
1085 /* The "struct return pointer" pseudo-argument has its own dedicated
1089 regcache_cooked_write_unsigned (regcache
,
1090 STRUCT_RETURN_REGNUM
, struct_addr
);
1092 /* Now make sure there's space on the stack. */
1093 for (argnum
= 0, stack_alloc
= 0; argnum
< nargs
; argnum
++)
1094 stack_alloc
+= ((TYPE_LENGTH (value_type (args
[argnum
])) + 7) & ~7);
1095 sp
-= stack_alloc
; /* Make room on stack for args. */
1097 /* Now load as many as possible of the first arguments into
1098 registers, and push the rest onto the stack. There are 64 bytes
1099 in eight registers available. Loop thru args from first to last. */
1101 int_argreg
= ARG0_REGNUM
;
1103 for (argnum
= 0, stack_offset
= 0; argnum
< nargs
; argnum
++)
1105 type
= value_type (args
[argnum
]);
1106 len
= TYPE_LENGTH (type
);
1107 memset (valbuf
, 0, sizeof (valbuf
));
1109 if (TYPE_CODE (type
) != TYPE_CODE_FLT
)
1111 argreg_size
= register_size (gdbarch
, int_argreg
);
1113 if (len
< argreg_size
)
1115 /* value gets right-justified in the register or stack word. */
1116 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1117 memcpy (valbuf
+ argreg_size
- len
,
1118 value_contents (args
[argnum
]), len
);
1120 memcpy (valbuf
, value_contents (args
[argnum
]), len
);
1125 val
= value_contents (args
[argnum
]);
1129 if (int_argreg
> ARGLAST_REGNUM
)
1131 /* Must go on the stack. */
1132 write_memory (sp
+ stack_offset
, val
, argreg_size
);
1133 stack_offset
+= 8;/*argreg_size;*/
1135 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1136 That's because some *&^%$ things get passed on the stack
1137 AND in the registers! */
1138 if (int_argreg
<= ARGLAST_REGNUM
)
1140 /* There's room in a register. */
1141 regval
= extract_unsigned_integer (val
, argreg_size
,
1143 regcache_cooked_write_unsigned (regcache
,
1144 int_argreg
, regval
);
1146 /* Store the value 8 bytes at a time. This means that
1147 things larger than 8 bytes may go partly in registers
1148 and partly on the stack. FIXME: argreg is incremented
1149 before we use its size. */
1157 val
= value_contents (args
[argnum
]);
1160 /* Where is it going to be stored? */
1161 while (fp_args
[float_arg_index
])
1164 /* Now float_argreg points to the register where it
1165 should be stored. Are we still within the allowed
1167 if (float_arg_index
<= FLOAT_ARGLAST_REGNUM
)
1169 /* Goes in FR0...FR11 */
1170 regcache_cooked_write (regcache
,
1171 gdbarch_fp0_regnum (gdbarch
)
1174 fp_args
[float_arg_index
] = 1;
1175 /* Skip the corresponding general argument register. */
1180 /* Store it as the integers, 8 bytes at the time, if
1181 necessary spilling on the stack. */
1186 /* Where is it going to be stored? */
1187 while (fp_args
[double_arg_index
])
1188 double_arg_index
+= 2;
1189 /* Now double_argreg points to the register
1190 where it should be stored.
1191 Are we still within the allowed register set? */
1192 if (double_arg_index
< FLOAT_ARGLAST_REGNUM
)
1194 /* Goes in DR0...DR10 */
1195 /* The numbering of the DRi registers is consecutive,
1196 i.e. includes odd numbers. */
1197 int double_register_offset
= double_arg_index
/ 2;
1198 int regnum
= DR0_REGNUM
+ double_register_offset
;
1199 regcache_cooked_write (regcache
, regnum
, val
);
1200 fp_args
[double_arg_index
] = 1;
1201 fp_args
[double_arg_index
+ 1] = 1;
1202 /* Skip the corresponding general argument register. */
1207 /* Store it as the integers, 8 bytes at the time, if
1208 necessary spilling on the stack. */
1213 /* Store return address. */
1214 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1216 /* Update stack pointer. */
1217 regcache_cooked_write_unsigned (regcache
,
1218 gdbarch_sp_regnum (gdbarch
), sp
);
1223 /* Find a function's return value in the appropriate registers (in
1224 regbuf), and copy it into valbuf. Extract from an array REGBUF
1225 containing the (raw) register state a function return value of type
1226 TYPE, and copy that, in virtual format, into VALBUF. */
1228 sh64_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1231 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1232 int len
= TYPE_LENGTH (type
);
1234 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1238 /* Return value stored in gdbarch_fp0_regnum. */
1239 regcache_raw_read (regcache
,
1240 gdbarch_fp0_regnum (gdbarch
), valbuf
);
1244 /* return value stored in DR0_REGNUM. */
1248 regcache_cooked_read (regcache
, DR0_REGNUM
, buf
);
1250 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1251 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1254 floatformat_to_doublest (&floatformat_ieee_double_big
,
1256 store_typed_floating (valbuf
, type
, val
);
1265 /* Result is in register 2. If smaller than 8 bytes, it is padded
1266 at the most significant end. */
1267 regcache_raw_read (regcache
, DEFAULT_RETURN_REGNUM
, buf
);
1269 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1270 offset
= register_size (gdbarch
, DEFAULT_RETURN_REGNUM
)
1274 memcpy (valbuf
, buf
+ offset
, len
);
1277 error (_("bad size for return value"));
1281 /* Write into appropriate registers a function return value
1282 of type TYPE, given in virtual format.
1283 If the architecture is sh4 or sh3e, store a function's return value
1284 in the R0 general register or in the FP0 floating point register,
1285 depending on the type of the return value. In all the other cases
1286 the result is stored in r0, left-justified. */
1289 sh64_store_return_value (struct type
*type
, struct regcache
*regcache
,
1290 const gdb_byte
*valbuf
)
1292 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1293 gdb_byte buf
[64]; /* more than enough... */
1294 int len
= TYPE_LENGTH (type
);
1296 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1298 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1299 for (i
= 0; i
< len
; i
+= 4)
1300 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1301 regcache_raw_write (regcache
, regnum
++,
1302 valbuf
+ len
- 4 - i
);
1304 regcache_raw_write (regcache
, regnum
++, valbuf
+ i
);
1308 int return_register
= DEFAULT_RETURN_REGNUM
;
1311 if (len
<= register_size (gdbarch
, return_register
))
1313 /* Pad with zeros. */
1314 memset (buf
, 0, register_size (gdbarch
, return_register
));
1315 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1316 offset
= 0; /*register_size (gdbarch,
1317 return_register) - len;*/
1319 offset
= register_size (gdbarch
, return_register
) - len
;
1321 memcpy (buf
+ offset
, valbuf
, len
);
1322 regcache_raw_write (regcache
, return_register
, buf
);
1325 regcache_raw_write (regcache
, return_register
, valbuf
);
1329 static enum return_value_convention
1330 sh64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
1331 struct type
*type
, struct regcache
*regcache
,
1332 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1334 if (sh64_use_struct_convention (type
))
1335 return RETURN_VALUE_STRUCT_CONVENTION
;
1337 sh64_store_return_value (type
, regcache
, writebuf
);
1339 sh64_extract_return_value (type
, regcache
, readbuf
);
1340 return RETURN_VALUE_REGISTER_CONVENTION
;
1345 SH MEDIA MODE (ISA 32)
1346 general registers (64-bit) 0-63
1347 0 r0, r1, r2, r3, r4, r5, r6, r7,
1348 64 r8, r9, r10, r11, r12, r13, r14, r15,
1349 128 r16, r17, r18, r19, r20, r21, r22, r23,
1350 192 r24, r25, r26, r27, r28, r29, r30, r31,
1351 256 r32, r33, r34, r35, r36, r37, r38, r39,
1352 320 r40, r41, r42, r43, r44, r45, r46, r47,
1353 384 r48, r49, r50, r51, r52, r53, r54, r55,
1354 448 r56, r57, r58, r59, r60, r61, r62, r63,
1359 status reg., saved status reg., saved pc reg. (64-bit) 65-67
1362 target registers (64-bit) 68-75
1363 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
1365 floating point state control register (32-bit) 76
1368 single precision floating point registers (32-bit) 77-140
1369 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
1370 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
1371 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
1372 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
1373 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
1374 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
1375 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
1376 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
1378 TOTAL SPACE FOR REGISTERS: 868 bytes
1380 From here on they are all pseudo registers: no memory allocated.
1381 REGISTER_BYTE returns the register byte for the base register.
1383 double precision registers (pseudo) 141-172
1384 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
1385 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
1386 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
1387 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
1389 floating point pairs (pseudo) 173-204
1390 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
1391 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
1392 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
1393 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
1395 floating point vectors (4 floating point regs) (pseudo) 205-220
1396 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
1397 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
1399 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1400 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
1401 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
1403 gbr_c, mach_c, macl_c, pr_c, t_c,
1405 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
1406 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
1407 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
1408 fv0_c, fv4_c, fv8_c, fv12_c
1411 static struct type
*
1412 sh64_build_float_register_type (struct gdbarch
*gdbarch
, int high
)
1414 return lookup_array_range_type (builtin_type (gdbarch
)->builtin_float
,
1418 /* Return the GDB type object for the "standard" data type
1419 of data in register REG_NR. */
1420 static struct type
*
1421 sh64_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1423 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
1424 && reg_nr
<= FP_LAST_REGNUM
)
1425 || (reg_nr
>= FP0_C_REGNUM
1426 && reg_nr
<= FP_LAST_C_REGNUM
))
1427 return builtin_type (gdbarch
)->builtin_float
;
1428 else if ((reg_nr
>= DR0_REGNUM
1429 && reg_nr
<= DR_LAST_REGNUM
)
1430 || (reg_nr
>= DR0_C_REGNUM
1431 && reg_nr
<= DR_LAST_C_REGNUM
))
1432 return builtin_type (gdbarch
)->builtin_double
;
1433 else if (reg_nr
>= FPP0_REGNUM
1434 && reg_nr
<= FPP_LAST_REGNUM
)
1435 return sh64_build_float_register_type (gdbarch
, 1);
1436 else if ((reg_nr
>= FV0_REGNUM
1437 && reg_nr
<= FV_LAST_REGNUM
)
1438 ||(reg_nr
>= FV0_C_REGNUM
1439 && reg_nr
<= FV_LAST_C_REGNUM
))
1440 return sh64_build_float_register_type (gdbarch
, 3);
1441 else if (reg_nr
== FPSCR_REGNUM
)
1442 return builtin_type (gdbarch
)->builtin_int
;
1443 else if (reg_nr
>= R0_C_REGNUM
1444 && reg_nr
< FP0_C_REGNUM
)
1445 return builtin_type (gdbarch
)->builtin_int
;
1447 return builtin_type (gdbarch
)->builtin_long_long
;
1451 sh64_register_convert_to_virtual (struct gdbarch
*gdbarch
, int regnum
,
1452 struct type
*type
, gdb_byte
*from
, gdb_byte
*to
)
1454 if (gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_LITTLE
)
1456 /* It is a no-op. */
1457 memcpy (to
, from
, register_size (gdbarch
, regnum
));
1461 if ((regnum
>= DR0_REGNUM
1462 && regnum
<= DR_LAST_REGNUM
)
1463 || (regnum
>= DR0_C_REGNUM
1464 && regnum
<= DR_LAST_C_REGNUM
))
1467 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1469 store_typed_floating (to
, type
, val
);
1472 error (_("sh64_register_convert_to_virtual "
1473 "called with non DR register number"));
1477 sh64_register_convert_to_raw (struct gdbarch
*gdbarch
, struct type
*type
,
1478 int regnum
, const void *from
, void *to
)
1480 if (gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_LITTLE
)
1482 /* It is a no-op. */
1483 memcpy (to
, from
, register_size (gdbarch
, regnum
));
1487 if ((regnum
>= DR0_REGNUM
1488 && regnum
<= DR_LAST_REGNUM
)
1489 || (regnum
>= DR0_C_REGNUM
1490 && regnum
<= DR_LAST_C_REGNUM
))
1492 DOUBLEST val
= extract_typed_floating (from
, type
);
1493 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1497 error (_("sh64_register_convert_to_raw called "
1498 "with non DR register number"));
1501 /* Concatenate PORTIONS contiguous raw registers starting at
1502 BASE_REGNUM into BUFFER. */
1504 static enum register_status
1505 pseudo_register_read_portions (struct gdbarch
*gdbarch
,
1506 struct regcache
*regcache
,
1508 int base_regnum
, gdb_byte
*buffer
)
1512 for (portion
= 0; portion
< portions
; portion
++)
1514 enum register_status status
;
1517 b
= buffer
+ register_size (gdbarch
, base_regnum
) * portion
;
1518 status
= regcache_raw_read (regcache
, base_regnum
+ portion
, b
);
1519 if (status
!= REG_VALID
)
1526 static enum register_status
1527 sh64_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1528 int reg_nr
, gdb_byte
*buffer
)
1530 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1533 gdb_byte temp_buffer
[MAX_REGISTER_SIZE
];
1534 enum register_status status
;
1536 if (reg_nr
>= DR0_REGNUM
1537 && reg_nr
<= DR_LAST_REGNUM
)
1539 base_regnum
= sh64_dr_reg_base_num (gdbarch
, reg_nr
);
1541 /* Build the value in the provided buffer. */
1542 /* DR regs are double precision registers obtained by
1543 concatenating 2 single precision floating point registers. */
1544 status
= pseudo_register_read_portions (gdbarch
, regcache
,
1545 2, base_regnum
, temp_buffer
);
1546 if (status
== REG_VALID
)
1548 /* We must pay attention to the endianness. */
1549 sh64_register_convert_to_virtual (gdbarch
, reg_nr
,
1550 register_type (gdbarch
, reg_nr
),
1551 temp_buffer
, buffer
);
1557 else if (reg_nr
>= FPP0_REGNUM
1558 && reg_nr
<= FPP_LAST_REGNUM
)
1560 base_regnum
= sh64_fpp_reg_base_num (gdbarch
, reg_nr
);
1562 /* Build the value in the provided buffer. */
1563 /* FPP regs are pairs of single precision registers obtained by
1564 concatenating 2 single precision floating point registers. */
1565 return pseudo_register_read_portions (gdbarch
, regcache
,
1566 2, base_regnum
, buffer
);
1569 else if (reg_nr
>= FV0_REGNUM
1570 && reg_nr
<= FV_LAST_REGNUM
)
1572 base_regnum
= sh64_fv_reg_base_num (gdbarch
, reg_nr
);
1574 /* Build the value in the provided buffer. */
1575 /* FV regs are vectors of single precision registers obtained by
1576 concatenating 4 single precision floating point registers. */
1577 return pseudo_register_read_portions (gdbarch
, regcache
,
1578 4, base_regnum
, buffer
);
1581 /* sh compact pseudo registers. 1-to-1 with a shmedia register. */
1582 else if (reg_nr
>= R0_C_REGNUM
1583 && reg_nr
<= T_C_REGNUM
)
1585 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1587 /* Build the value in the provided buffer. */
1588 status
= regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
1589 if (status
!= REG_VALID
)
1591 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1594 temp_buffer
+ offset
, 4); /* get LOWER 32 bits only???? */
1598 else if (reg_nr
>= FP0_C_REGNUM
1599 && reg_nr
<= FP_LAST_C_REGNUM
)
1601 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1603 /* Build the value in the provided buffer. */
1604 /* Floating point registers map 1-1 to the media fp regs,
1605 they have the same size and endianness. */
1606 return regcache_raw_read (regcache
, base_regnum
, buffer
);
1609 else if (reg_nr
>= DR0_C_REGNUM
1610 && reg_nr
<= DR_LAST_C_REGNUM
)
1612 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1614 /* DR_C regs are double precision registers obtained by
1615 concatenating 2 single precision floating point registers. */
1616 status
= pseudo_register_read_portions (gdbarch
, regcache
,
1617 2, base_regnum
, temp_buffer
);
1618 if (status
== REG_VALID
)
1620 /* We must pay attention to the endianness. */
1621 sh64_register_convert_to_virtual (gdbarch
, reg_nr
,
1622 register_type (gdbarch
, reg_nr
),
1623 temp_buffer
, buffer
);
1628 else if (reg_nr
>= FV0_C_REGNUM
1629 && reg_nr
<= FV_LAST_C_REGNUM
)
1631 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1633 /* Build the value in the provided buffer. */
1634 /* FV_C regs are vectors of single precision registers obtained by
1635 concatenating 4 single precision floating point registers. */
1636 return pseudo_register_read_portions (gdbarch
, regcache
,
1637 4, base_regnum
, buffer
);
1640 else if (reg_nr
== FPSCR_C_REGNUM
)
1642 int fpscr_base_regnum
;
1644 unsigned int fpscr_value
;
1645 unsigned int sr_value
;
1646 unsigned int fpscr_c_value
;
1647 unsigned int fpscr_c_part1_value
;
1648 unsigned int fpscr_c_part2_value
;
1650 fpscr_base_regnum
= FPSCR_REGNUM
;
1651 sr_base_regnum
= SR_REGNUM
;
1653 /* Build the value in the provided buffer. */
1654 /* FPSCR_C is a very weird register that contains sparse bits
1655 from the FPSCR and the SR architectural registers.
1662 2-17 Bit 2-18 of FPSCR
1663 18-20 Bits 12,13,14 of SR
1667 /* Get FPSCR into a local buffer. */
1668 status
= regcache_raw_read (regcache
, fpscr_base_regnum
, temp_buffer
);
1669 if (status
!= REG_VALID
)
1671 /* Get value as an int. */
1672 fpscr_value
= extract_unsigned_integer (temp_buffer
, 4, byte_order
);
1673 /* Get SR into a local buffer */
1674 status
= regcache_raw_read (regcache
, sr_base_regnum
, temp_buffer
);
1675 if (status
!= REG_VALID
)
1677 /* Get value as an int. */
1678 sr_value
= extract_unsigned_integer (temp_buffer
, 4, byte_order
);
1679 /* Build the new value. */
1680 fpscr_c_part1_value
= fpscr_value
& 0x3fffd;
1681 fpscr_c_part2_value
= (sr_value
& 0x7000) << 6;
1682 fpscr_c_value
= fpscr_c_part1_value
| fpscr_c_part2_value
;
1683 /* Store that in out buffer!!! */
1684 store_unsigned_integer (buffer
, 4, byte_order
, fpscr_c_value
);
1685 /* FIXME There is surely an endianness gotcha here. */
1690 else if (reg_nr
== FPUL_C_REGNUM
)
1692 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1694 /* FPUL_C register is floating point register 32,
1695 same size, same endianness. */
1696 return regcache_raw_read (regcache
, base_regnum
, buffer
);
1699 gdb_assert_not_reached ("invalid pseudo register number");
1703 sh64_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1704 int reg_nr
, const gdb_byte
*buffer
)
1706 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1707 int base_regnum
, portion
;
1709 gdb_byte temp_buffer
[MAX_REGISTER_SIZE
];
1711 if (reg_nr
>= DR0_REGNUM
1712 && reg_nr
<= DR_LAST_REGNUM
)
1714 base_regnum
= sh64_dr_reg_base_num (gdbarch
, reg_nr
);
1715 /* We must pay attention to the endianness. */
1716 sh64_register_convert_to_raw (gdbarch
, register_type (gdbarch
, reg_nr
),
1718 buffer
, temp_buffer
);
1720 /* Write the real regs for which this one is an alias. */
1721 for (portion
= 0; portion
< 2; portion
++)
1722 regcache_raw_write (regcache
, base_regnum
+ portion
,
1724 + register_size (gdbarch
,
1725 base_regnum
) * portion
));
1728 else if (reg_nr
>= FPP0_REGNUM
1729 && reg_nr
<= FPP_LAST_REGNUM
)
1731 base_regnum
= sh64_fpp_reg_base_num (gdbarch
, reg_nr
);
1733 /* Write the real regs for which this one is an alias. */
1734 for (portion
= 0; portion
< 2; portion
++)
1735 regcache_raw_write (regcache
, base_regnum
+ portion
,
1736 (buffer
+ register_size (gdbarch
,
1737 base_regnum
) * portion
));
1740 else if (reg_nr
>= FV0_REGNUM
1741 && reg_nr
<= FV_LAST_REGNUM
)
1743 base_regnum
= sh64_fv_reg_base_num (gdbarch
, reg_nr
);
1745 /* Write the real regs for which this one is an alias. */
1746 for (portion
= 0; portion
< 4; portion
++)
1747 regcache_raw_write (regcache
, base_regnum
+ portion
,
1748 (buffer
+ register_size (gdbarch
,
1749 base_regnum
) * portion
));
1752 /* sh compact general pseudo registers. 1-to-1 with a shmedia
1753 register but only 4 bytes of it. */
1754 else if (reg_nr
>= R0_C_REGNUM
1755 && reg_nr
<= T_C_REGNUM
)
1757 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1758 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1759 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1763 /* Let's read the value of the base register into a temporary
1764 buffer, so that overwriting the last four bytes with the new
1765 value of the pseudo will leave the upper 4 bytes unchanged. */
1766 regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
1767 /* Write as an 8 byte quantity. */
1768 memcpy (temp_buffer
+ offset
, buffer
, 4);
1769 regcache_raw_write (regcache
, base_regnum
, temp_buffer
);
1772 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
1773 registers. Both are 4 bytes. */
1774 else if (reg_nr
>= FP0_C_REGNUM
1775 && reg_nr
<= FP_LAST_C_REGNUM
)
1777 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1778 regcache_raw_write (regcache
, base_regnum
, buffer
);
1781 else if (reg_nr
>= DR0_C_REGNUM
1782 && reg_nr
<= DR_LAST_C_REGNUM
)
1784 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1785 for (portion
= 0; portion
< 2; portion
++)
1787 /* We must pay attention to the endianness. */
1788 sh64_register_convert_to_raw (gdbarch
,
1789 register_type (gdbarch
, reg_nr
),
1791 buffer
, temp_buffer
);
1793 regcache_raw_write (regcache
, base_regnum
+ portion
,
1795 + register_size (gdbarch
,
1796 base_regnum
) * portion
));
1800 else if (reg_nr
>= FV0_C_REGNUM
1801 && reg_nr
<= FV_LAST_C_REGNUM
)
1803 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1805 for (portion
= 0; portion
< 4; portion
++)
1807 regcache_raw_write (regcache
, base_regnum
+ portion
,
1809 + register_size (gdbarch
,
1810 base_regnum
) * portion
));
1814 else if (reg_nr
== FPSCR_C_REGNUM
)
1816 int fpscr_base_regnum
;
1818 unsigned int fpscr_value
;
1819 unsigned int sr_value
;
1820 unsigned int old_fpscr_value
;
1821 unsigned int old_sr_value
;
1822 unsigned int fpscr_c_value
;
1823 unsigned int fpscr_mask
;
1824 unsigned int sr_mask
;
1826 fpscr_base_regnum
= FPSCR_REGNUM
;
1827 sr_base_regnum
= SR_REGNUM
;
1829 /* FPSCR_C is a very weird register that contains sparse bits
1830 from the FPSCR and the SR architectural registers.
1837 2-17 Bit 2-18 of FPSCR
1838 18-20 Bits 12,13,14 of SR
1842 /* Get value as an int. */
1843 fpscr_c_value
= extract_unsigned_integer (buffer
, 4, byte_order
);
1845 /* Build the new values. */
1846 fpscr_mask
= 0x0003fffd;
1847 sr_mask
= 0x001c0000;
1849 fpscr_value
= fpscr_c_value
& fpscr_mask
;
1850 sr_value
= (fpscr_value
& sr_mask
) >> 6;
1852 regcache_raw_read (regcache
, fpscr_base_regnum
, temp_buffer
);
1853 old_fpscr_value
= extract_unsigned_integer (temp_buffer
, 4, byte_order
);
1854 old_fpscr_value
&= 0xfffc0002;
1855 fpscr_value
|= old_fpscr_value
;
1856 store_unsigned_integer (temp_buffer
, 4, byte_order
, fpscr_value
);
1857 regcache_raw_write (regcache
, fpscr_base_regnum
, temp_buffer
);
1859 regcache_raw_read (regcache
, sr_base_regnum
, temp_buffer
);
1860 old_sr_value
= extract_unsigned_integer (temp_buffer
, 4, byte_order
);
1861 old_sr_value
&= 0xffff8fff;
1862 sr_value
|= old_sr_value
;
1863 store_unsigned_integer (temp_buffer
, 4, byte_order
, sr_value
);
1864 regcache_raw_write (regcache
, sr_base_regnum
, temp_buffer
);
1867 else if (reg_nr
== FPUL_C_REGNUM
)
1869 base_regnum
= sh64_compact_reg_base_num (gdbarch
, reg_nr
);
1870 regcache_raw_write (regcache
, base_regnum
, buffer
);
1874 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
1875 shmedia REGISTERS. */
1876 /* Control registers, compact mode. */
1878 sh64_do_cr_c_register_info (struct ui_file
*file
, struct frame_info
*frame
,
1881 switch (cr_c_regnum
)
1884 fprintf_filtered (file
, "pc_c\t0x%08x\n",
1885 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1888 fprintf_filtered (file
, "gbr_c\t0x%08x\n",
1889 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1892 fprintf_filtered (file
, "mach_c\t0x%08x\n",
1893 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1896 fprintf_filtered (file
, "macl_c\t0x%08x\n",
1897 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1900 fprintf_filtered (file
, "pr_c\t0x%08x\n",
1901 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1904 fprintf_filtered (file
, "t_c\t0x%08x\n",
1905 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1907 case FPSCR_C_REGNUM
:
1908 fprintf_filtered (file
, "fpscr_c\t0x%08x\n",
1909 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1912 fprintf_filtered (file
, "fpul_c\t0x%08x\n",
1913 (int) get_frame_register_unsigned (frame
, cr_c_regnum
));
1919 sh64_do_fp_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1920 struct frame_info
*frame
, int regnum
)
1921 { /* Do values for FP (float) regs. */
1922 unsigned char *raw_buffer
;
1923 double flt
; /* Double extracted from raw hex data. */
1926 /* Allocate space for the float. */
1927 raw_buffer
= (unsigned char *)
1928 alloca (register_size (gdbarch
, gdbarch_fp0_regnum (gdbarch
)));
1930 /* Get the data in raw format. */
1931 if (!deprecated_frame_register_read (frame
, regnum
, raw_buffer
))
1932 error (_("can't read register %d (%s)"),
1933 regnum
, gdbarch_register_name (gdbarch
, regnum
));
1935 /* Get the register as a number. */
1936 flt
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
1939 /* Print the name and some spaces. */
1940 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
1941 print_spaces_filtered (15 - strlen (gdbarch_register_name
1942 (gdbarch
, regnum
)), file
);
1944 /* Print the value. */
1946 fprintf_filtered (file
, "<invalid float>");
1948 fprintf_filtered (file
, "%-10.9g", flt
);
1950 /* Print the fp register as hex. */
1951 fprintf_filtered (file
, "\t(raw ");
1952 print_hex_chars (file
, raw_buffer
,
1953 register_size (gdbarch
, regnum
),
1954 gdbarch_byte_order (gdbarch
));
1955 fprintf_filtered (file
, ")");
1956 fprintf_filtered (file
, "\n");
1960 sh64_do_pseudo_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1961 struct frame_info
*frame
, int regnum
)
1963 /* All the sh64-compact mode registers are pseudo registers. */
1965 if (regnum
< gdbarch_num_regs (gdbarch
)
1966 || regnum
>= gdbarch_num_regs (gdbarch
)
1967 + NUM_PSEUDO_REGS_SH_MEDIA
1968 + NUM_PSEUDO_REGS_SH_COMPACT
)
1969 internal_error (__FILE__
, __LINE__
,
1970 _("Invalid pseudo register number %d\n"), regnum
);
1972 else if ((regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
))
1974 int fp_regnum
= sh64_dr_reg_base_num (gdbarch
, regnum
);
1975 fprintf_filtered (file
, "dr%d\t0x%08x%08x\n", regnum
- DR0_REGNUM
,
1976 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
1977 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1));
1980 else if ((regnum
>= DR0_C_REGNUM
&& regnum
<= DR_LAST_C_REGNUM
))
1982 int fp_regnum
= sh64_compact_reg_base_num (gdbarch
, regnum
);
1983 fprintf_filtered (file
, "dr%d_c\t0x%08x%08x\n", regnum
- DR0_C_REGNUM
,
1984 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
1985 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1));
1988 else if ((regnum
>= FV0_REGNUM
&& regnum
<= FV_LAST_REGNUM
))
1990 int fp_regnum
= sh64_fv_reg_base_num (gdbarch
, regnum
);
1991 fprintf_filtered (file
, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1992 regnum
- FV0_REGNUM
,
1993 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
1994 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1),
1995 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 2),
1996 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 3));
1999 else if ((regnum
>= FV0_C_REGNUM
&& regnum
<= FV_LAST_C_REGNUM
))
2001 int fp_regnum
= sh64_compact_reg_base_num (gdbarch
, regnum
);
2002 fprintf_filtered (file
, "fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2003 regnum
- FV0_C_REGNUM
,
2004 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
2005 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1),
2006 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 2),
2007 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 3));
2010 else if (regnum
>= FPP0_REGNUM
&& regnum
<= FPP_LAST_REGNUM
)
2012 int fp_regnum
= sh64_fpp_reg_base_num (gdbarch
, regnum
);
2013 fprintf_filtered (file
, "fpp%d\t0x%08x\t0x%08x\n", regnum
- FPP0_REGNUM
,
2014 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
),
2015 (unsigned) get_frame_register_unsigned (frame
, fp_regnum
+ 1));
2018 else if (regnum
>= R0_C_REGNUM
&& regnum
<= R_LAST_C_REGNUM
)
2020 int c_regnum
= sh64_compact_reg_base_num (gdbarch
, regnum
);
2021 fprintf_filtered (file
, "r%d_c\t0x%08x\n", regnum
- R0_C_REGNUM
,
2022 (unsigned) get_frame_register_unsigned (frame
, c_regnum
));
2024 else if (regnum
>= FP0_C_REGNUM
&& regnum
<= FP_LAST_C_REGNUM
)
2025 /* This should work also for pseudoregs. */
2026 sh64_do_fp_register (gdbarch
, file
, frame
, regnum
);
2027 else if (regnum
>= PC_C_REGNUM
&& regnum
<= FPUL_C_REGNUM
)
2028 sh64_do_cr_c_register_info (file
, frame
, regnum
);
2032 sh64_do_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2033 struct frame_info
*frame
, int regnum
)
2035 unsigned char raw_buffer
[MAX_REGISTER_SIZE
];
2036 struct value_print_options opts
;
2038 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
2039 print_spaces_filtered (15 - strlen (gdbarch_register_name
2040 (gdbarch
, regnum
)), file
);
2042 /* Get the data in raw format. */
2043 if (!deprecated_frame_register_read (frame
, regnum
, raw_buffer
))
2045 fprintf_filtered (file
, "*value not available*\n");
2049 get_formatted_print_options (&opts
, 'x');
2051 val_print (register_type (gdbarch
, regnum
), raw_buffer
, 0, 0,
2052 file
, 0, NULL
, &opts
, current_language
);
2053 fprintf_filtered (file
, "\t");
2054 get_formatted_print_options (&opts
, 0);
2056 val_print (register_type (gdbarch
, regnum
), raw_buffer
, 0, 0,
2057 file
, 0, NULL
, &opts
, current_language
);
2058 fprintf_filtered (file
, "\n");
2062 sh64_print_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2063 struct frame_info
*frame
, int regnum
)
2065 if (regnum
< 0 || regnum
>= gdbarch_num_regs (gdbarch
)
2066 + gdbarch_num_pseudo_regs (gdbarch
))
2067 internal_error (__FILE__
, __LINE__
,
2068 _("Invalid register number %d\n"), regnum
);
2070 else if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
2072 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
2073 sh64_do_fp_register (gdbarch
, file
, frame
, regnum
); /* FP regs */
2075 sh64_do_register (gdbarch
, file
, frame
, regnum
);
2078 else if (regnum
< gdbarch_num_regs (gdbarch
)
2079 + gdbarch_num_pseudo_regs (gdbarch
))
2080 sh64_do_pseudo_register (gdbarch
, file
, frame
, regnum
);
2084 sh64_media_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2085 struct frame_info
*frame
, int regnum
,
2088 if (regnum
!= -1) /* Do one specified register. */
2090 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
2091 error (_("Not a valid register for the current processor type"));
2093 sh64_print_register (gdbarch
, file
, frame
, regnum
);
2096 /* Do all (or most) registers. */
2099 while (regnum
< gdbarch_num_regs (gdbarch
))
2101 /* If the register name is empty, it is undefined for this
2102 processor, so don't display anything. */
2103 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
2104 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
2110 if (TYPE_CODE (register_type (gdbarch
, regnum
))
2115 /* true for "INFO ALL-REGISTERS" command. */
2116 sh64_do_fp_register (gdbarch
, file
, frame
, regnum
);
2120 regnum
+= FP_LAST_REGNUM
- gdbarch_fp0_regnum (gdbarch
);
2125 sh64_do_register (gdbarch
, file
, frame
, regnum
);
2131 while (regnum
< gdbarch_num_regs (gdbarch
)
2132 + gdbarch_num_pseudo_regs (gdbarch
))
2134 sh64_do_pseudo_register (gdbarch
, file
, frame
, regnum
);
2141 sh64_compact_print_registers_info (struct gdbarch
*gdbarch
,
2142 struct ui_file
*file
,
2143 struct frame_info
*frame
, int regnum
,
2146 if (regnum
!= -1) /* Do one specified register. */
2148 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
2149 error (_("Not a valid register for the current processor type"));
2151 if (regnum
>= 0 && regnum
< R0_C_REGNUM
)
2152 error (_("Not a valid register for the current processor mode."));
2154 sh64_print_register (gdbarch
, file
, frame
, regnum
);
2157 /* Do all compact registers. */
2159 regnum
= R0_C_REGNUM
;
2160 while (regnum
< gdbarch_num_regs (gdbarch
)
2161 + gdbarch_num_pseudo_regs (gdbarch
))
2163 sh64_do_pseudo_register (gdbarch
, file
, frame
, regnum
);
2170 sh64_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
2171 struct frame_info
*frame
, int regnum
, int fpregs
)
2173 if (pc_is_isa32 (get_frame_pc (frame
)))
2174 sh64_media_print_registers_info (gdbarch
, file
, frame
, regnum
, fpregs
);
2176 sh64_compact_print_registers_info (gdbarch
, file
, frame
, regnum
, fpregs
);
2179 static struct sh64_frame_cache
*
2180 sh64_alloc_frame_cache (void)
2182 struct sh64_frame_cache
*cache
;
2185 cache
= FRAME_OBSTACK_ZALLOC (struct sh64_frame_cache
);
2189 cache
->saved_sp
= 0;
2190 cache
->sp_offset
= 0;
2193 /* Frameless until proven otherwise. */
2196 /* Saved registers. We initialize these to -1 since zero is a valid
2197 offset (that's where fp is supposed to be stored). */
2198 for (i
= 0; i
< SIM_SH64_NR_REGS
; i
++)
2200 cache
->saved_regs
[i
] = -1;
2206 static struct sh64_frame_cache
*
2207 sh64_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2209 struct gdbarch
*gdbarch
;
2210 struct sh64_frame_cache
*cache
;
2211 CORE_ADDR current_pc
;
2215 return (struct sh64_frame_cache
*) *this_cache
;
2217 gdbarch
= get_frame_arch (this_frame
);
2218 cache
= sh64_alloc_frame_cache ();
2219 *this_cache
= cache
;
2221 current_pc
= get_frame_pc (this_frame
);
2222 cache
->media_mode
= pc_is_isa32 (current_pc
);
2224 /* In principle, for normal frames, fp holds the frame pointer,
2225 which holds the base address for the current stack frame.
2226 However, for functions that don't need it, the frame pointer is
2227 optional. For these "frameless" functions the frame pointer is
2228 actually the frame pointer of the calling frame. */
2229 cache
->base
= get_frame_register_unsigned (this_frame
, MEDIA_FP_REGNUM
);
2230 if (cache
->base
== 0)
2233 cache
->pc
= get_frame_func (this_frame
);
2235 sh64_analyze_prologue (gdbarch
, cache
, cache
->pc
, current_pc
);
2237 if (!cache
->uses_fp
)
2239 /* We didn't find a valid frame, which means that CACHE->base
2240 currently holds the frame pointer for our calling frame. If
2241 we're at the start of a function, or somewhere half-way its
2242 prologue, the function's frame probably hasn't been fully
2243 setup yet. Try to reconstruct the base address for the stack
2244 frame by looking at the stack pointer. For truly "frameless"
2245 functions this might work too. */
2246 cache
->base
= get_frame_register_unsigned
2247 (this_frame
, gdbarch_sp_regnum (gdbarch
));
2250 /* Now that we have the base address for the stack frame we can
2251 calculate the value of sp in the calling frame. */
2252 cache
->saved_sp
= cache
->base
+ cache
->sp_offset
;
2254 /* Adjust all the saved registers such that they contain addresses
2255 instead of offsets. */
2256 for (i
= 0; i
< SIM_SH64_NR_REGS
; i
++)
2257 if (cache
->saved_regs
[i
] != -1)
2258 cache
->saved_regs
[i
] = cache
->saved_sp
- cache
->saved_regs
[i
];
2263 static struct value
*
2264 sh64_frame_prev_register (struct frame_info
*this_frame
,
2265 void **this_cache
, int regnum
)
2267 struct sh64_frame_cache
*cache
= sh64_frame_cache (this_frame
, this_cache
);
2268 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2269 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2271 gdb_assert (regnum
>= 0);
2273 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2274 frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2276 /* The PC of the previous frame is stored in the PR register of
2277 the current frame. Frob regnum so that we pull the value from
2278 the correct place. */
2279 if (regnum
== gdbarch_pc_regnum (gdbarch
))
2282 if (regnum
< SIM_SH64_NR_REGS
&& cache
->saved_regs
[regnum
] != -1)
2284 if (gdbarch_tdep (gdbarch
)->sh_abi
== SH_ABI_32
2285 && (regnum
== MEDIA_FP_REGNUM
|| regnum
== PR_REGNUM
))
2288 val
= read_memory_unsigned_integer (cache
->saved_regs
[regnum
],
2290 return frame_unwind_got_constant (this_frame
, regnum
, val
);
2293 return frame_unwind_got_memory (this_frame
, regnum
,
2294 cache
->saved_regs
[regnum
]);
2297 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2301 sh64_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2302 struct frame_id
*this_id
)
2304 struct sh64_frame_cache
*cache
= sh64_frame_cache (this_frame
, this_cache
);
2306 /* This marks the outermost frame. */
2307 if (cache
->base
== 0)
2310 *this_id
= frame_id_build (cache
->saved_sp
, cache
->pc
);
2313 static const struct frame_unwind sh64_frame_unwind
= {
2315 default_frame_unwind_stop_reason
,
2317 sh64_frame_prev_register
,
2319 default_frame_sniffer
2323 sh64_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2325 return frame_unwind_register_unsigned (next_frame
,
2326 gdbarch_sp_regnum (gdbarch
));
2330 sh64_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2332 return frame_unwind_register_unsigned (next_frame
,
2333 gdbarch_pc_regnum (gdbarch
));
2336 static struct frame_id
2337 sh64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2339 CORE_ADDR sp
= get_frame_register_unsigned (this_frame
,
2340 gdbarch_sp_regnum (gdbarch
));
2341 return frame_id_build (sp
, get_frame_pc (this_frame
));
2345 sh64_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2347 struct sh64_frame_cache
*cache
= sh64_frame_cache (this_frame
, this_cache
);
2352 static const struct frame_base sh64_frame_base
= {
2354 sh64_frame_base_address
,
2355 sh64_frame_base_address
,
2356 sh64_frame_base_address
2361 sh64_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2363 struct gdbarch
*gdbarch
;
2364 struct gdbarch_tdep
*tdep
;
2366 /* If there is already a candidate, use it. */
2367 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2369 return arches
->gdbarch
;
2371 /* None found, create a new architecture from the information
2373 tdep
= XNEW (struct gdbarch_tdep
);
2374 gdbarch
= gdbarch_alloc (&info
, tdep
);
2376 /* Determine the ABI */
2377 if (info
.abfd
&& bfd_get_arch_size (info
.abfd
) == 64)
2379 /* If the ABI is the 64-bit one, it can only be sh-media. */
2380 tdep
->sh_abi
= SH_ABI_64
;
2381 set_gdbarch_ptr_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2382 set_gdbarch_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2386 /* If the ABI is the 32-bit one it could be either media or
2388 tdep
->sh_abi
= SH_ABI_32
;
2389 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2390 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2393 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2394 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2395 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2396 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2397 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2398 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2399 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2401 /* The number of real registers is the same whether we are in
2402 ISA16(compact) or ISA32(media). */
2403 set_gdbarch_num_regs (gdbarch
, SIM_SH64_NR_REGS
);
2404 set_gdbarch_sp_regnum (gdbarch
, 15);
2405 set_gdbarch_pc_regnum (gdbarch
, 64);
2406 set_gdbarch_fp0_regnum (gdbarch
, SIM_SH64_FR0_REGNUM
);
2407 set_gdbarch_num_pseudo_regs (gdbarch
, NUM_PSEUDO_REGS_SH_MEDIA
2408 + NUM_PSEUDO_REGS_SH_COMPACT
);
2410 set_gdbarch_register_name (gdbarch
, sh64_register_name
);
2411 set_gdbarch_register_type (gdbarch
, sh64_register_type
);
2413 set_gdbarch_pseudo_register_read (gdbarch
, sh64_pseudo_register_read
);
2414 set_gdbarch_pseudo_register_write (gdbarch
, sh64_pseudo_register_write
);
2416 SET_GDBARCH_BREAKPOINT_MANIPULATION (sh64
);
2418 set_gdbarch_print_insn (gdbarch
, print_insn_sh
);
2419 set_gdbarch_register_sim_regno (gdbarch
, legacy_register_sim_regno
);
2421 set_gdbarch_return_value (gdbarch
, sh64_return_value
);
2423 set_gdbarch_skip_prologue (gdbarch
, sh64_skip_prologue
);
2424 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2426 set_gdbarch_push_dummy_call (gdbarch
, sh64_push_dummy_call
);
2428 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2430 set_gdbarch_frame_align (gdbarch
, sh64_frame_align
);
2431 set_gdbarch_unwind_sp (gdbarch
, sh64_unwind_sp
);
2432 set_gdbarch_unwind_pc (gdbarch
, sh64_unwind_pc
);
2433 set_gdbarch_dummy_id (gdbarch
, sh64_dummy_id
);
2434 frame_base_set_default (gdbarch
, &sh64_frame_base
);
2436 set_gdbarch_print_registers_info (gdbarch
, sh64_print_registers_info
);
2438 set_gdbarch_elf_make_msymbol_special (gdbarch
,
2439 sh64_elf_make_msymbol_special
);
2441 /* Hook in ABI-specific overrides, if they have been registered. */
2442 gdbarch_init_osabi (info
, gdbarch
);
2444 dwarf2_append_unwinders (gdbarch
);
2445 frame_unwind_append_unwinder (gdbarch
, &sh64_frame_unwind
);