gdb/sparc-tdep.c

   1 /* Target-dependent code for the SPARC for GDB, the GNU debugger.
   2    Copyright 1986, 1987, 1989, 1991, 1992, 1993 Free Software Foundation, Inc.
   3
   4 This file is part of GDB.
   5
   6 This program is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 2 of the License, or
   9 (at your option) any later version.
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with this program; if not, write to the Free Software
  18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.  */
  19
  20 #include "defs.h"
  21 #include "frame.h"
  22 #include "inferior.h"
  23 #include "obstack.h"
  24 #include "target.h"
  25 #include "ieee-float.h"
  26 #include "symfile.h" /* for find_pc_section */
  27
  28 #ifdef  USE_PROC_FS
  29 #include <sys/procfs.h>
  30 #endif
  31
  32 #include "gdbcore.h"
  33
  34 /* From infrun.c */
  35 extern int stop_after_trap;
  36
  37 /* We don't store all registers immediately when requested, since they
  38    get sent over in large chunks anyway.  Instead, we accumulate most
  39    of the changes and send them over once.  "deferred_stores" keeps
  40    track of which sets of registers we have locally-changed copies of,
  41    so we only need send the groups that have changed.  */
  42
  43 int deferred_stores = 0;        /* Cumulates stores we want to do eventually. */
  44
  45 typedef enum
  46 {
  47   Error, not_branch, bicc, bicca, ba, baa, ticc, ta
  48 } branch_type;
  49
  50 /* Simulate single-step ptrace call for sun4.  Code written by Gary
  51    Beihl (beihl@mcc.com).  */
  52
  53 /* npc4 and next_pc describe the situation at the time that the
  54    step-breakpoint was set, not necessary the current value of NPC_REGNUM.  */
  55 static CORE_ADDR next_pc, npc4, target;
  56 static int brknpc4, brktrg;
  57 typedef char binsn_quantum[BREAKPOINT_MAX];
  58 static binsn_quantum break_mem[3];
  59
  60 /* Non-zero if we just simulated a single-step ptrace call.  This is
  61    needed because we cannot remove the breakpoints in the inferior
  62    process until after the `wait' in `wait_for_inferior'.  Used for
  63    sun4. */
  64
  65 int one_stepped;
  66
  67 /* single_step() is called just before we want to resume the inferior,
  68    if we want to single-step it but there is no hardware or kernel single-step
  69    support (as on all SPARCs).  We find all the possible targets of the
  70    coming instruction and breakpoint them.
  71
  72    single_step is also called just after the inferior stops.  If we had
  73    set up a simulated single-step, we undo our damage.  */
  74
  75 void
  76 single_step (ignore)
  77      int ignore; /* pid, but we don't need it */
  78 {
  79   branch_type br, isannulled();
  80   CORE_ADDR pc;
  81   long pc_instruction;
  82
  83   if (!one_stepped)
  84     {
  85       /* Always set breakpoint for NPC.  */
  86       next_pc = read_register (NPC_REGNUM);
  87       npc4 = next_pc + 4; /* branch not taken */
  88
  89       target_insert_breakpoint (next_pc, break_mem[0]);
  90       /* printf ("set break at %x\n",next_pc); */
  91
  92       pc = read_register (PC_REGNUM);
  93       pc_instruction = read_memory_integer (pc, sizeof(pc_instruction));
  94       br = isannulled (pc_instruction, pc, &target);
  95       brknpc4 = brktrg = 0;
  96
  97       if (br == bicca)
  98         {
  99           /* Conditional annulled branch will either end up at
 100              npc (if taken) or at npc+4 (if not taken).
 101              Trap npc+4.  */
 102           brknpc4 = 1;
 103           target_insert_breakpoint (npc4, break_mem[1]);
 104         }
 105       else if (br == baa && target != next_pc)
 106         {
 107           /* Unconditional annulled branch will always end up at
 108              the target.  */
 109           brktrg = 1;
 110           target_insert_breakpoint (target, break_mem[2]);
 111         }
 112
 113       /* We are ready to let it go */
 114       one_stepped = 1;
 115       return;
 116     }
 117   else
 118     {
 119       /* Remove breakpoints */
 120       target_remove_breakpoint (next_pc, break_mem[0]);
 121
 122       if (brknpc4)
 123         target_remove_breakpoint (npc4, break_mem[1]);
 124
 125       if (brktrg)
 126         target_remove_breakpoint (target, break_mem[2]);
 127
 128       one_stepped = 0;
 129     }
 130 }
 131 \f
 132 #define FRAME_SAVED_L0  0               /* Byte offset from SP */
 133 #define FRAME_SAVED_I0  32              /* Byte offset from SP */
 134
 135 CORE_ADDR
 136 sparc_frame_chain (thisframe)
 137      FRAME thisframe;
 138 {
 139   CORE_ADDR retval;
 140   int err;
 141   CORE_ADDR addr;
 142
 143   addr = thisframe->frame + FRAME_SAVED_I0 +
 144          REGISTER_RAW_SIZE(FP_REGNUM) * (FP_REGNUM - I0_REGNUM);
 145   err = target_read_memory (addr, (char *) &retval, sizeof (CORE_ADDR));
 146   if (err)
 147     return 0;
 148   SWAP_TARGET_AND_HOST (&retval, sizeof (retval));
 149   return retval;
 150 }
 151
 152 CORE_ADDR
 153 sparc_extract_struct_value_address (regbuf)
 154      char regbuf[REGISTER_BYTES];
 155 {
 156   /* FIXME, handle byte swapping */
 157   return read_memory_integer (((int *)(regbuf))[SP_REGNUM]+(16*4),
 158                               sizeof (CORE_ADDR));
 159 }
 160
 161 /* Find the pc saved in frame FRAME.  */
 162
 163 CORE_ADDR
 164 frame_saved_pc (frame)
 165      FRAME frame;
 166 {
 167   CORE_ADDR prev_pc;
 168
 169   if (get_current_frame () == frame)  /* FIXME, debug check. Remove >=gdb-4.6 */
 170     {
 171       if (read_register (SP_REGNUM) != frame->bottom) abort();
 172     }
 173
 174   read_memory ((CORE_ADDR) (frame->bottom + FRAME_SAVED_I0 +
 175                     REGISTER_RAW_SIZE(I7_REGNUM) * (I7_REGNUM - I0_REGNUM)),
 176                (char *) &prev_pc,
 177                sizeof (CORE_ADDR));
 178
 179   SWAP_TARGET_AND_HOST (&prev_pc, sizeof (prev_pc));
 180   return PC_ADJUST (prev_pc);
 181 }
 182
 183 /*
 184  * Since an individual frame in the frame cache is defined by two
 185  * arguments (a frame pointer and a stack pointer), we need two
 186  * arguments to get info for an arbitrary stack frame.  This routine
 187  * takes two arguments and makes the cached frames look as if these
 188  * two arguments defined a frame on the cache.  This allows the rest
 189  * of info frame to extract the important arguments without
 190  * difficulty.
 191  */
 192 FRAME
 193 setup_arbitrary_frame (argc, argv)
 194      int argc;
 195      FRAME_ADDR *argv;
 196 {
 197   FRAME fid;
 198
 199   if (argc != 2)
 200     error ("Sparc frame specifications require two arguments: fp and sp");
 201
 202   fid = create_new_frame (argv[0], 0);
 203
 204   if (!fid)
 205     fatal ("internal: create_new_frame returned invalid frame id");
 206
 207   fid->bottom = argv[1];
 208   fid->pc = FRAME_SAVED_PC (fid);
 209   return fid;
 210 }
 211
 212 /* This code was written by Gary Beihl (beihl@mcc.com).
 213    It was modified by Michael Tiemann (tiemann@corto.inria.fr).  */
 214
 215 /*
 216  * This routine appears to be passed a size by which to increase the
 217  * stack.  It then executes a save instruction in the inferior to
 218  * increase the stack by this amount.  Only the register window system
 219  * should be affected by this; the program counter & etc. will not be.
 220  *
 221  * This instructions used for this purpose are:
 222  *
 223  *      sethi %hi(0x0),g1                    *
 224  *      add g1,0x1ee0,g1                     *
 225  *      save sp,g1,sp
 226  *      sethi %hi(0x0),g1                    *
 227  *      add g1,0x1ee0,g1                     *
 228  *      t g0,0x1,o0
 229  *      sethi %hi(0x0),g0                    (nop)
 230  *
 231  *  I presume that these set g1 to be the negative of the size, do a
 232  * save (putting the stack pointer at sp - size) and restore the
 233  * original contents of g1.  A * indicates that the actual value of
 234  * the instruction is modified below.
 235  */
 236 static unsigned int save_insn_opcodes[] = {
 237   0x03000000, 0x82007ee0, 0x9de38001, 0x03000000,
 238   0x82007ee0, 0x91d02001, 0x01000000 };
 239
 240 /* Neither do_save_insn or do_restore_insn save stack configuration
 241    (current_frame, etc),
 242    since the stack is in an indeterminate state through the call to
 243    each of them.  That is the responsibility of the routine which calls them.  */
 244
 245 static void
 246 do_save_insn (size)
 247      int size;
 248 {
 249   int g1 = read_register (G1_REGNUM);
 250   CORE_ADDR sp = read_register (SP_REGNUM);
 251   CORE_ADDR pc = read_register (PC_REGNUM);
 252   CORE_ADDR npc = read_register (NPC_REGNUM);
 253   CORE_ADDR fake_pc = sp - sizeof (save_insn_opcodes);
 254   struct inferior_status inf_status;
 255
 256   save_inferior_status (&inf_status, 0); /* Don't restore stack info */
 257   /*
 258    * See above.
 259    */
 260   save_insn_opcodes[0] = 0x03000000 | ((-size >> 10) & 0x3fffff);
 261   save_insn_opcodes[1] = 0x82006000 | (-size & 0x3ff);
 262   save_insn_opcodes[3] = 0x03000000 | ((g1 >> 10) & 0x3fffff);
 263   save_insn_opcodes[4] = 0x82006000 | (g1 & 0x3ff);
 264   write_memory (fake_pc, (char *)save_insn_opcodes, sizeof (save_insn_opcodes));
 265
 266   clear_proceed_status ();
 267   stop_after_trap = 1;
 268   proceed (fake_pc, 0, 0);
 269
 270   write_register (PC_REGNUM, pc);
 271   write_register (NPC_REGNUM, npc);
 272   restore_inferior_status (&inf_status);
 273 }
 274
 275 /*
 276  * This routine takes a program counter value.  It restores the
 277  * register window system to the frame above the current one.
 278  * THIS ROUTINE CLOBBERS PC AND NPC IN THE TARGET!
 279  */
 280
 281 /*    The following insns translate to:
 282
 283         restore %g0,%g0,%g0
 284         t %g0,1
 285         sethi %hi(0),%g0        */
 286
 287 static unsigned int restore_insn_opcodes[] = {
 288   0x81e80000, 0x91d02001, 0x01000000 };
 289
 290 static void
 291 do_restore_insn ()
 292 {
 293   CORE_ADDR sp = read_register (SP_REGNUM);
 294   CORE_ADDR fake_pc = sp - sizeof (restore_insn_opcodes);
 295   struct inferior_status inf_status;
 296
 297   save_inferior_status (&inf_status, 0); /* Don't restore stack info */
 298
 299   write_memory (fake_pc, (char *)restore_insn_opcodes,
 300                 sizeof (restore_insn_opcodes));
 301
 302   clear_proceed_status ();
 303   stop_after_trap = 1;
 304   proceed (fake_pc, 0, 0);
 305
 306   restore_inferior_status (&inf_status);
 307 }
 308
 309 /* Given a pc value, skip it forward past the function prologue by
 310    disassembling instructions that appear to be a prologue.
 311
 312    If FRAMELESS_P is set, we are only testing to see if the function
 313    is frameless.  This allows a quicker answer.
 314
 315    This routine should be more specific in its actions; making sure
 316    that it uses the same register in the initial prologue section.  */
 317 CORE_ADDR
 318 skip_prologue (start_pc, frameless_p)
 319      CORE_ADDR start_pc;
 320      int frameless_p;
 321 {
 322   union
 323     {
 324       unsigned long int code;
 325       struct
 326         {
 327           unsigned int op:2;
 328           unsigned int rd:5;
 329           unsigned int op2:3;
 330           unsigned int imm22:22;
 331         } sethi;
 332       struct
 333         {
 334           unsigned int op:2;
 335           unsigned int rd:5;
 336           unsigned int op3:6;
 337           unsigned int rs1:5;
 338           unsigned int i:1;
 339           unsigned int simm13:13;
 340         } add;
 341       int i;
 342     } x;
 343   int dest = -1;
 344   CORE_ADDR pc = start_pc;
 345
 346   x.i = read_memory_integer (pc, 4);
 347
 348   /* Recognize the `sethi' insn and record its destination.  */
 349   if (x.sethi.op == 0 && x.sethi.op2 == 4)
 350     {
 351       dest = x.sethi.rd;
 352       pc += 4;
 353       x.i = read_memory_integer (pc, 4);
 354     }
 355
 356   /* Recognize an add immediate value to register to either %g1 or
 357      the destination register recorded above.  Actually, this might
 358      well recognize several different arithmetic operations.
 359      It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1"
 360      followed by "save %sp, %g1, %sp" is a valid prologue (Not that
 361      I imagine any compiler really does that, however).  */
 362   if (x.add.op == 2 && x.add.i && (x.add.rd == 1 || x.add.rd == dest))
 363     {
 364       pc += 4;
 365       x.i = read_memory_integer (pc, 4);
 366     }
 367
 368   /* This recognizes any SAVE insn.  But why do the XOR and then
 369      the compare?  That's identical to comparing against 60 (as long
 370      as there isn't any sign extension).  */
 371   if (x.add.op == 2 && (x.add.op3 ^ 32) == 28)
 372     {
 373       pc += 4;
 374       if (frameless_p)                  /* If the save is all we care about, */
 375         return pc;                      /* return before doing more work */
 376       x.i = read_memory_integer (pc, 4);
 377     }
 378   else
 379     {
 380       /* Without a save instruction, it's not a prologue.  */
 381       return start_pc;
 382     }
 383
 384   /* Now we need to recognize stores into the frame from the input
 385      registers.  This recognizes all non alternate stores of input
 386      register, into a location offset from the frame pointer.  */
 387   while (x.add.op == 3
 388          && (x.add.op3 & 0x3c) == 4 /* Store, non-alternate.  */
 389          && (x.add.rd & 0x18) == 0x18 /* Input register.  */
 390          && x.add.i             /* Immediate mode.  */
 391          && x.add.rs1 == 30     /* Off of frame pointer.  */
 392          /* Into reserved stack space.  */
 393          && x.add.simm13 >= 0x44
 394          && x.add.simm13 < 0x5b)
 395     {
 396       pc += 4;
 397       x.i = read_memory_integer (pc, 4);
 398     }
 399   return pc;
 400 }
 401
 402 /* Check instruction at ADDR to see if it is an annulled branch.
 403    All other instructions will go to NPC or will trap.
 404    Set *TARGET if we find a canidate branch; set to zero if not. */
 405
 406 branch_type
 407 isannulled (instruction, addr, target)
 408      long instruction;
 409      CORE_ADDR addr, *target;
 410 {
 411   branch_type val = not_branch;
 412   long int offset;              /* Must be signed for sign-extend.  */
 413   union
 414     {
 415       unsigned long int code;
 416       struct
 417         {
 418           unsigned int op:2;
 419           unsigned int a:1;
 420           unsigned int cond:4;
 421           unsigned int op2:3;
 422           unsigned int disp22:22;
 423         } b;
 424     } insn;
 425
 426   *target = 0;
 427   insn.code = instruction;
 428
 429   if (insn.b.op == 0
 430       && (insn.b.op2 == 2 || insn.b.op2 == 6 || insn.b.op2 == 7))
 431     {
 432       if (insn.b.cond == 8)
 433         val = insn.b.a ? baa : ba;
 434       else
 435         val = insn.b.a ? bicca : bicc;
 436       offset = 4 * ((int) (insn.b.disp22 << 10) >> 10);
 437       *target = addr + offset;
 438     }
 439
 440   return val;
 441 }
 442
 443 /* sparc_frame_find_saved_regs ()
 444
 445    Stores, into a struct frame_saved_regs,
 446    the addresses of the saved registers of frame described by FRAME_INFO.
 447    This includes special registers such as pc and fp saved in special
 448    ways in the stack frame.  sp is even more special:
 449    the address we return for it IS the sp for the next frame.
 450
 451    Note that on register window machines, we are currently making the
 452    assumption that window registers are being saved somewhere in the
 453    frame in which they are being used.  If they are stored in an
 454    inferior frame, find_saved_register will break.
 455
 456    On the Sun 4, the only time all registers are saved is when
 457    a dummy frame is involved.  Otherwise, the only saved registers
 458    are the LOCAL and IN registers which are saved as a result
 459    of the "save/restore" opcodes.  This condition is determined
 460    by address rather than by value.
 461
 462    The "pc" is not stored in a frame on the SPARC.  (What is stored
 463    is a return address minus 8.)  sparc_pop_frame knows how to
 464    deal with that.  Other routines might or might not.
 465
 466    See tm-sparc.h (PUSH_FRAME and friends) for CRITICAL information
 467    about how this works.  */
 468
 469 void
 470 sparc_frame_find_saved_regs (fi, saved_regs_addr)
 471      struct frame_info *fi;
 472      struct frame_saved_regs *saved_regs_addr;
 473 {
 474   register int regnum;
 475   FRAME_ADDR frame = read_register (FP_REGNUM);
 476   FRAME fid = FRAME_INFO_ID (fi);
 477
 478   if (!fid)
 479     fatal ("Bad frame info struct in FRAME_FIND_SAVED_REGS");
 480
 481   memset (saved_regs_addr, 0, sizeof (*saved_regs_addr));
 482
 483   /* Old test.
 484   if (fi->pc >= frame - CALL_DUMMY_LENGTH - 0x140
 485       && fi->pc <= frame) */
 486
 487   if (fi->pc >= (fi->bottom ? fi->bottom :
 488                    read_register (SP_REGNUM))
 489       && fi->pc <= FRAME_FP(fi))
 490     {
 491       /* Dummy frame.  All but the window regs are in there somewhere. */
 492       for (regnum = G1_REGNUM; regnum < G1_REGNUM+7; regnum++)
 493         saved_regs_addr->regs[regnum] =
 494           frame + (regnum - G0_REGNUM) * 4 - 0xa0;
 495       for (regnum = I0_REGNUM; regnum < I0_REGNUM+8; regnum++)
 496         saved_regs_addr->regs[regnum] =
 497           frame + (regnum - I0_REGNUM) * 4 - 0xc0;
 498       for (regnum = FP0_REGNUM; regnum < FP0_REGNUM + 32; regnum++)
 499         saved_regs_addr->regs[regnum] =
 500           frame + (regnum - FP0_REGNUM) * 4 - 0x80;
 501       for (regnum = Y_REGNUM; regnum < NUM_REGS; regnum++)
 502         saved_regs_addr->regs[regnum] =
 503           frame + (regnum - Y_REGNUM) * 4 - 0xe0;
 504       frame = fi->bottom ?
 505         fi->bottom : read_register (SP_REGNUM);
 506     }
 507   else
 508     {
 509       /* Normal frame.  Just Local and In registers */
 510       frame = fi->bottom ?
 511         fi->bottom : read_register (SP_REGNUM);
 512       for (regnum = L0_REGNUM; regnum < L0_REGNUM+16; regnum++)
 513         saved_regs_addr->regs[regnum] = frame + (regnum-L0_REGNUM) * 4;
 514     }
 515   if (fi->next)
 516     {
 517       /* Pull off either the next frame pointer or the stack pointer */
 518       FRAME_ADDR next_next_frame =
 519         (fi->next->bottom ?
 520          fi->next->bottom :
 521          read_register (SP_REGNUM));
 522       for (regnum = O0_REGNUM; regnum < O0_REGNUM+8; regnum++)
 523         saved_regs_addr->regs[regnum] = next_next_frame + regnum * 4;
 524     }
 525   /* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */
 526   saved_regs_addr->regs[SP_REGNUM] = FRAME_FP (fi);
 527 }
 528
 529 /* Push an empty stack frame, and record in it the current PC, regs, etc.
 530
 531    Note that the write's are of registers in the context of the newly
 532    pushed frame.  Thus the the fp*'s, the g*'s, the i*'s, and
 533    the randoms, of the new frame, are being saved.  The locals and outs
 534    are new; they don't need to be saved. The i's and l's of
 535    the last frame were saved by the do_save_insn in the register
 536    file (now on the stack, since a context switch happended imm after).
 537
 538    The return pointer register %i7 does not have
 539    the pc saved into it (return from this frame will be accomplished
 540    by a POP_FRAME).  In fact, we must leave it unclobbered, since we
 541    must preserve it in the calling routine except across call instructions.  */
 542
 543 /* Definitely see tm-sparc.h for more doc of the frame format here.  */
 544
 545 void
 546 sparc_push_dummy_frame ()
 547 {
 548   CORE_ADDR fp;
 549   char register_temp[REGISTER_BYTES];
 550
 551   do_save_insn (0x140); /* FIXME where does this value come from? */
 552   fp = read_register (FP_REGNUM);
 553
 554   read_register_bytes (REGISTER_BYTE (FP0_REGNUM), register_temp, 32 * 4);
 555   write_memory (fp - 0x80, register_temp, 32 * 4);
 556
 557   read_register_bytes (REGISTER_BYTE (G0_REGNUM), register_temp, 8 * 4);
 558   write_memory (fp - 0xa0, register_temp, 8 * 4);
 559
 560   read_register_bytes (REGISTER_BYTE (I0_REGNUM), register_temp, 8 * 4);
 561   write_memory (fp - 0xc0, register_temp, 8 * 4);
 562
 563   /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */
 564   read_register_bytes (REGISTER_BYTE (Y_REGNUM), register_temp, 8 * 4);
 565   write_memory (fp - 0xe0, register_temp, 8 * 4);
 566 }
 567
 568 /* Discard from the stack the innermost frame, restoring all saved registers.
 569
 570    Note that the values stored in fsr by get_frame_saved_regs are *in
 571    the context of the called frame*.  What this means is that the i
 572    regs of fsr must be restored into the o regs of the (calling) frame that
 573    we pop into.  We don't care about the output regs of the calling frame,
 574    since unless it's a dummy frame, it won't have any output regs in it.
 575
 576    We never have to bother with %l (local) regs, since the called routine's
 577    locals get tossed, and the calling routine's locals are already saved
 578    on its stack.  */
 579
 580 /* Definitely see tm-sparc.h for more doc of the frame format here.  */
 581
 582 void
 583 sparc_pop_frame ()
 584 {
 585   register FRAME frame = get_current_frame ();
 586   register CORE_ADDR pc;
 587   struct frame_saved_regs fsr;
 588   struct frame_info *fi;
 589   char raw_buffer[REGISTER_BYTES];
 590
 591   fi = get_frame_info (frame);
 592   get_frame_saved_regs (fi, &fsr);
 593   do_restore_insn ();
 594   if (fsr.regs[FP0_REGNUM])
 595     {
 596       read_memory (fsr.regs[FP0_REGNUM], raw_buffer, 32 * 4);
 597       write_register_bytes (REGISTER_BYTE (FP0_REGNUM), raw_buffer, 32 * 4);
 598     }
 599   if (fsr.regs[G1_REGNUM])
 600     {
 601       read_memory (fsr.regs[G1_REGNUM], raw_buffer, 7 * 4);
 602       write_register_bytes (REGISTER_BYTE (G1_REGNUM), raw_buffer, 7 * 4);
 603     }
 604   if (fsr.regs[I0_REGNUM])
 605     {
 606       read_memory (fsr.regs[I0_REGNUM], raw_buffer, 8 * 4);
 607       write_register_bytes (REGISTER_BYTE (O0_REGNUM), raw_buffer, 8 * 4);
 608     }
 609   if (fsr.regs[PS_REGNUM])
 610     write_register (PS_REGNUM, read_memory_integer (fsr.regs[PS_REGNUM], 4));
 611   if (fsr.regs[Y_REGNUM])
 612     write_register (Y_REGNUM, read_memory_integer (fsr.regs[Y_REGNUM], 4));
 613   if (fsr.regs[PC_REGNUM])
 614     {
 615       /* Explicitly specified PC (and maybe NPC) -- just restore them. */
 616       write_register (PC_REGNUM, read_memory_integer (fsr.regs[PC_REGNUM], 4));
 617       if (fsr.regs[NPC_REGNUM])
 618         write_register (NPC_REGNUM,
 619                         read_memory_integer (fsr.regs[NPC_REGNUM], 4));
 620     }
 621   else if (fsr.regs[I7_REGNUM])
 622     {
 623       /* Return address in %i7 -- adjust it, then restore PC and NPC from it */
 624       pc = PC_ADJUST (read_memory_integer (fsr.regs[I7_REGNUM], 4));
 625       write_register (PC_REGNUM,  pc);
 626       write_register (NPC_REGNUM, pc + 4);
 627     }
 628   flush_cached_frames ();
 629   set_current_frame ( create_new_frame (read_register (FP_REGNUM),
 630                                         read_pc ()));
 631 }
 632
 633 /* On the Sun 4 under SunOS, the compile will leave a fake insn which
 634    encodes the structure size being returned.  If we detect such
 635    a fake insn, step past it.  */
 636
 637 CORE_ADDR
 638 sparc_pc_adjust(pc)
 639      CORE_ADDR pc;
 640 {
 641   long insn;
 642   int err;
 643
 644   err = target_read_memory (pc + 8, (char *)&insn, sizeof(long));
 645   SWAP_TARGET_AND_HOST (&insn, sizeof(long));
 646   if ((err == 0) && (insn & 0xfffffe00) == 0)
 647     return pc+12;
 648   else
 649     return pc+8;
 650 }
 651
 652
 653 /* Structure of SPARC extended floating point numbers.
 654    This information is not currently used by GDB, since no current SPARC
 655    implementations support extended float.  */
 656
 657 const struct ext_format ext_format_sparc = {
 658 /* tot sbyte smask expbyte manbyte */
 659    16, 0,    0x80, 0,1,    4,8,         /* sparc */
 660 };
 661 \f
 662 #ifdef USE_PROC_FS      /* Target dependent support for /proc */
 663
 664 /*  The /proc interface divides the target machine's register set up into
 665     two different sets, the general register set (gregset) and the floating
 666     point register set (fpregset).  For each set, there is an ioctl to get
 667     the current register set and another ioctl to set the current values.
 668
 669     The actual structure passed through the ioctl interface is, of course,
 670     naturally machine dependent, and is different for each set of registers.
 671     For the sparc for example, the general register set is typically defined
 672     by:
 673
 674         typedef int gregset_t[38];
 675
 676         #define R_G0    0
 677         ...
 678         #define R_TBR   37
 679
 680     and the floating point set by:
 681
 682         typedef struct prfpregset {
 683                 union {
 684                         u_long  pr_regs[32];
 685                         double  pr_dregs[16];
 686                 } pr_fr;
 687                 void *  pr_filler;
 688                 u_long  pr_fsr;
 689                 u_char  pr_qcnt;
 690                 u_char  pr_q_entrysize;
 691                 u_char  pr_en;
 692                 u_long  pr_q[64];
 693         } prfpregset_t;
 694
 695     These routines provide the packing and unpacking of gregset_t and
 696     fpregset_t formatted data.
 697
 698  */
 699
 700
 701 /*  Given a pointer to a general register set in /proc format (gregset_t *),
 702     unpack the register contents and supply them as gdb's idea of the current
 703     register values. */
 704
 705 void
 706 supply_gregset (gregsetp)
 707 prgregset_t *gregsetp;
 708 {
 709   register int regi;
 710   register prgreg_t *regp = (prgreg_t *) gregsetp;
 711
 712   /* GDB register numbers for Gn, On, Ln, In all match /proc reg numbers.  */
 713   for (regi = G0_REGNUM ; regi <= I7_REGNUM ; regi++)
 714     {
 715       supply_register (regi, (char *) (regp + regi));
 716     }
 717
 718   /* These require a bit more care.  */
 719   supply_register (PS_REGNUM, (char *) (regp + R_PS));
 720   supply_register (PC_REGNUM, (char *) (regp + R_PC));
 721   supply_register (NPC_REGNUM,(char *) (regp + R_nPC));
 722   supply_register (Y_REGNUM,  (char *) (regp + R_Y));
 723 }
 724
 725 void
 726 fill_gregset (gregsetp, regno)
 727 prgregset_t *gregsetp;
 728 int regno;
 729 {
 730   int regi;
 731   register prgreg_t *regp = (prgreg_t *) gregsetp;
 732   extern char registers[];
 733
 734   for (regi = 0 ; regi <= R_I7 ; regi++)
 735     {
 736       if ((regno == -1) || (regno == regi))
 737         {
 738           *(regp + regi) = *(int *) &registers[REGISTER_BYTE (regi)];
 739         }
 740     }
 741   if ((regno == -1) || (regno == PS_REGNUM))
 742     {
 743       *(regp + R_PS) = *(int *) &registers[REGISTER_BYTE (PS_REGNUM)];
 744     }
 745   if ((regno == -1) || (regno == PC_REGNUM))
 746     {
 747       *(regp + R_PC) = *(int *) &registers[REGISTER_BYTE (PC_REGNUM)];
 748     }
 749   if ((regno == -1) || (regno == NPC_REGNUM))
 750     {
 751       *(regp + R_nPC) = *(int *) &registers[REGISTER_BYTE (NPC_REGNUM)];
 752     }
 753   if ((regno == -1) || (regno == Y_REGNUM))
 754     {
 755       *(regp + R_Y) = *(int *) &registers[REGISTER_BYTE (Y_REGNUM)];
 756     }
 757 }
 758
 759 #if defined (FP0_REGNUM)
 760
 761 /*  Given a pointer to a floating point register set in /proc format
 762     (fpregset_t *), unpack the register contents and supply them as gdb's
 763     idea of the current floating point register values. */
 764
 765 void
 766 supply_fpregset (fpregsetp)
 767 prfpregset_t *fpregsetp;
 768 {
 769   register int regi;
 770   char *from;
 771
 772   for (regi = FP0_REGNUM ; regi < FP0_REGNUM+32 ; regi++)
 773     {
 774       from = (char *) &fpregsetp->pr_fr.pr_regs[regi-FP0_REGNUM];
 775       supply_register (regi, from);
 776     }
 777   supply_register (FPS_REGNUM, (char *) &(fpregsetp->pr_fsr));
 778 }
 779
 780 /*  Given a pointer to a floating point register set in /proc format
 781     (fpregset_t *), update the register specified by REGNO from gdb's idea
 782     of the current floating point register set.  If REGNO is -1, update
 783     them all. */
 784
 785 void
 786 fill_fpregset (fpregsetp, regno)
 787 prfpregset_t *fpregsetp;
 788 int regno;
 789 {
 790   int regi;
 791   char *to;
 792   char *from;
 793   extern char registers[];
 794
 795   for (regi = FP0_REGNUM ; regi < FP0_REGNUM+32 ; regi++)
 796     {
 797       if ((regno == -1) || (regno == regi))
 798         {
 799           from = (char *) &registers[REGISTER_BYTE (regi)];
 800           to = (char *) &fpregsetp->pr_fr.pr_regs[regi-FP0_REGNUM];
 801           memcpy (to, from, REGISTER_RAW_SIZE (regi));
 802         }
 803     }
 804   if ((regno == -1) || (regno == FPS_REGNUM))
 805     {
 806       fpregsetp->pr_fsr = *(int *) &registers[REGISTER_BYTE (FPS_REGNUM)];
 807     }
 808 }
 809
 810 #endif  /* defined (FP0_REGNUM) */
 811
 812 #endif  /* USE_PROC_FS */
 813
 814
 815 #ifdef GET_LONGJMP_TARGET
 816
 817 /* Figure out where the longjmp will land.  We expect that we have just entered
 818    longjmp and haven't yet setup the stack frame, so the args are still in the
 819    output regs.  %o0 (O0_REGNUM) points at the jmp_buf structure from which we
 820    extract the pc (JB_PC) that we will land at.  The pc is copied into ADDR.
 821    This routine returns true on success */
 822
 823 int
 824 get_longjmp_target(pc)
 825      CORE_ADDR *pc;
 826 {
 827   CORE_ADDR jb_addr;
 828
 829   jb_addr = read_register(O0_REGNUM);
 830
 831   if (target_read_memory(jb_addr + JB_PC * JB_ELEMENT_SIZE, (char *) pc,
 832                          sizeof(CORE_ADDR)))
 833     return 0;
 834
 835   SWAP_TARGET_AND_HOST(pc, sizeof(CORE_ADDR));
 836
 837   return 1;
 838 }
 839 #endif /* GET_LONGJMP_TARGET */
 840
 841 /* So far used only for sparc solaris.  In sparc solaris, we recognize
 842    a trampoline by it's section name.  That is, if the pc is in a
 843    section named ".plt" then we are in a trampline.
 844
 845    Section and offset tracking belongs in objfiles.  FIXME. */
 846
 847 int
 848 in_solib_trampoline(pc, name)
 849      CORE_ADDR pc;
 850      char *name;
 851 {
 852   struct section_table *s;
 853   int retval = 0;
 854
 855   s = find_pc_section(pc);
 856
 857   retval = (s != NULL
 858             && s->sec_ptr != NULL
 859             && s->sec_ptr->name != NULL
 860             && STREQ (s->sec_ptr->name, ".plt"));
 861   return(retval);
 862 }
 863