1 /* Target-dependent code for the SPARC for GDB, the GNU debugger.
2 Copyright 1986, 1987, 1989, 1991, 1992 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
26 #include "ieee-float.h"
28 #include <sys/ptrace.h>
33 extern int stop_after_trap
;
37 Error
, not_branch
, bicc
, bicca
, ba
, baa
, ticc
, ta
40 /* Simulate single-step ptrace call for sun4. Code written by Gary
41 Beihl (beihl@mcc.com). */
43 /* npc4 and next_pc describe the situation at the time that the
44 step-breakpoint was set, not necessary the current value of NPC_REGNUM. */
45 static CORE_ADDR next_pc
, npc4
, target
;
46 static int brknpc4
, brktrg
;
47 typedef char binsn_quantum
[BREAKPOINT_MAX
];
48 static binsn_quantum break_mem
[3];
50 /* Non-zero if we just simulated a single-step ptrace call. This is
51 needed because we cannot remove the breakpoints in the inferior
52 process until after the `wait' in `wait_for_inferior'. Used for
57 /* single_step() is called just before we want to resume the inferior,
58 if we want to single-step it but there is no hardware or kernel single-step
59 support (as on all SPARCs). We find all the possible targets of the
60 coming instruction and breakpoint them.
62 single_step is also called just after the inferior stops. If we had
63 set up a simulated single-step, we undo our damage. */
67 int pid
; /* ignored */
69 branch_type br
, isannulled();
75 /* Always set breakpoint for NPC. */
76 next_pc
= read_register (NPC_REGNUM
);
77 npc4
= next_pc
+ 4; /* branch not taken */
79 target_insert_breakpoint (next_pc
, break_mem
[0]);
80 /* printf ("set break at %x\n",next_pc); */
82 pc
= read_register (PC_REGNUM
);
83 pc_instruction
= read_memory_integer (pc
, sizeof(pc_instruction
));
84 br
= isannulled (pc_instruction
, pc
, &target
);
89 /* Conditional annulled branch will either end up at
90 npc (if taken) or at npc+4 (if not taken).
93 target_insert_breakpoint (npc4
, break_mem
[1]);
95 else if (br
== baa
&& target
!= next_pc
)
97 /* Unconditional annulled branch will always end up at
100 target_insert_breakpoint (target
, break_mem
[2]);
103 /* We are ready to let it go */
109 /* Remove breakpoints */
110 target_remove_breakpoint (next_pc
, break_mem
[0]);
113 target_remove_breakpoint (npc4
, break_mem
[1]);
116 target_remove_breakpoint (target
, break_mem
[2]);
122 #define FRAME_SAVED_L0 0 /* Byte offset from SP */
123 #define FRAME_SAVED_I0 32 /* Byte offset from SP */
126 sparc_frame_chain (thisframe
)
133 addr
= thisframe
->frame
+ FRAME_SAVED_I0
+
134 REGISTER_RAW_SIZE(FP_REGNUM
) * (FP_REGNUM
- I0_REGNUM
);
135 err
= target_read_memory (addr
, (char *) &retval
, sizeof (CORE_ADDR
));
138 SWAP_TARGET_AND_HOST (&retval
, sizeof (retval
));
143 sparc_extract_struct_value_address (regbuf
)
144 char regbuf
[REGISTER_BYTES
];
146 /* FIXME, handle byte swapping */
147 return read_memory_integer (((int *)(regbuf
))[SP_REGNUM
]+(16*4),
151 /* Find the pc saved in frame FRAME. */
154 frame_saved_pc (frame
)
159 if (get_current_frame () == frame
) /* FIXME, debug check. Remove >=gdb-4.6 */
161 if (read_register (SP_REGNUM
) != frame
->bottom
) abort();
164 read_memory ((CORE_ADDR
) (frame
->bottom
+ FRAME_SAVED_I0
+
165 REGISTER_RAW_SIZE(I7_REGNUM
) * (I7_REGNUM
- I0_REGNUM
)),
169 SWAP_TARGET_AND_HOST (&prev_pc
, sizeof (prev_pc
));
170 return PC_ADJUST (prev_pc
);
174 * Since an individual frame in the frame cache is defined by two
175 * arguments (a frame pointer and a stack pointer), we need two
176 * arguments to get info for an arbitrary stack frame. This routine
177 * takes two arguments and makes the cached frames look as if these
178 * two arguments defined a frame on the cache. This allows the rest
179 * of info frame to extract the important arguments without
183 setup_arbitrary_frame (frame
, stack
)
184 FRAME_ADDR frame
, stack
;
186 FRAME fid
= create_new_frame (frame
, 0);
189 fatal ("internal: create_new_frame returned invalid frame id");
192 fid
->pc
= FRAME_SAVED_PC (fid
);
196 /* This code was written by Gary Beihl (beihl@mcc.com).
197 It was modified by Michael Tiemann (tiemann@corto.inria.fr). */
200 * This routine appears to be passed a size by which to increase the
201 * stack. It then executes a save instruction in the inferior to
202 * increase the stack by this amount. Only the register window system
203 * should be affected by this; the program counter & etc. will not be.
205 * This instructions used for this purpose are:
207 * sethi %hi(0x0),g1 *
210 * sethi %hi(0x0),g1 *
213 * sethi %hi(0x0),g0 (nop)
215 * I presume that these set g1 to be the negative of the size, do a
216 * save (putting the stack pointer at sp - size) and restore the
217 * original contents of g1. A * indicates that the actual value of
218 * the instruction is modified below.
220 static int save_insn_opcodes
[] = {
221 0x03000000, 0x82007ee0, 0x9de38001, 0x03000000,
222 0x82007ee0, 0x91d02001, 0x01000000 };
224 /* Neither do_save_insn or do_restore_insn save stack configuration
225 (current_frame, etc),
226 since the stack is in an indeterminate state through the call to
227 each of them. That responsibility of the routine which calls them. */
233 int g1
= read_register (G1_REGNUM
);
234 CORE_ADDR sp
= read_register (SP_REGNUM
);
235 CORE_ADDR pc
= read_register (PC_REGNUM
);
236 CORE_ADDR npc
= read_register (NPC_REGNUM
);
237 CORE_ADDR fake_pc
= sp
- sizeof (save_insn_opcodes
);
238 struct inferior_status inf_status
;
240 save_inferior_status (&inf_status
, 0); /* Don't restore stack info */
244 save_insn_opcodes
[0] = 0x03000000 | ((-size
>> 10) & 0x3fffff);
245 save_insn_opcodes
[1] = 0x82006000 | (-size
& 0x3ff);
246 save_insn_opcodes
[3] = 0x03000000 | ((g1
>> 10) & 0x3fffff);
247 save_insn_opcodes
[4] = 0x82006000 | (g1
& 0x3ff);
248 write_memory (fake_pc
, (char *)save_insn_opcodes
, sizeof (save_insn_opcodes
));
250 clear_proceed_status ();
252 proceed (fake_pc
, 0, 0);
254 write_register (PC_REGNUM
, pc
);
255 write_register (NPC_REGNUM
, npc
);
256 restore_inferior_status (&inf_status
);
260 * This routine takes a program counter value. It restores the
261 * register window system to the frame above the current one.
262 * THIS ROUTINE CLOBBERS PC AND NPC IN THE TARGET!
265 /* The following insns translate to:
271 static int restore_insn_opcodes
[] = { 0x81e80000, 0x91d02001, 0x01000000 };
276 CORE_ADDR sp
= read_register (SP_REGNUM
);
277 CORE_ADDR fake_pc
= sp
- sizeof (restore_insn_opcodes
);
278 struct inferior_status inf_status
;
280 save_inferior_status (&inf_status
, 0); /* Don't restore stack info */
282 write_memory (fake_pc
, (char *)restore_insn_opcodes
,
283 sizeof (restore_insn_opcodes
));
285 clear_proceed_status ();
287 proceed (fake_pc
, 0, 0);
289 restore_inferior_status (&inf_status
);
292 /* Given a pc value, skip it forward past the function prologue by
293 disassembling instructions that appear to be a prologue.
295 If FRAMELESS_P is set, we are only testing to see if the function
296 is frameless. This allows a quicker answer.
298 This routine should be more specific in its actions; making sure
299 that it uses the same register in the initial prologue section. */
301 skip_prologue (start_pc
, frameless_p
)
307 unsigned long int code
;
313 unsigned int imm22
:22;
322 unsigned int simm13
:13;
327 CORE_ADDR pc
= start_pc
;
329 x
.i
= read_memory_integer (pc
, 4);
331 /* Recognize the `sethi' insn and record its destination. */
332 if (x
.sethi
.op
== 0 && x
.sethi
.op2
== 4)
336 x
.i
= read_memory_integer (pc
, 4);
339 /* Recognize an add immediate value to register to either %g1 or
340 the destination register recorded above. Actually, this might
341 well recognize several different arithmetic operations.
342 It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1"
343 followed by "save %sp, %g1, %sp" is a valid prologue (Not that
344 I imagine any compiler really does that, however). */
345 if (x
.add
.op
== 2 && x
.add
.i
&& (x
.add
.rd
== 1 || x
.add
.rd
== dest
))
348 x
.i
= read_memory_integer (pc
, 4);
351 /* This recognizes any SAVE insn. But why do the XOR and then
352 the compare? That's identical to comparing against 60 (as long
353 as there isn't any sign extension). */
354 if (x
.add
.op
== 2 && (x
.add
.op3
^ 32) == 28)
357 if (frameless_p
) /* If the save is all we care about, */
358 return pc
; /* return before doing more work */
359 x
.i
= read_memory_integer (pc
, 4);
363 /* Without a save instruction, it's not a prologue. */
367 /* Now we need to recognize stores into the frame from the input
368 registers. This recognizes all non alternate stores of input
369 register, into a location offset from the frame pointer. */
371 && (x
.add
.op3
& 0x3c) == 4 /* Store, non-alternate. */
372 && (x
.add
.rd
& 0x18) == 0x18 /* Input register. */
373 && x
.add
.i
/* Immediate mode. */
374 && x
.add
.rs1
== 30 /* Off of frame pointer. */
375 /* Into reserved stack space. */
376 && x
.add
.simm13
>= 0x44
377 && x
.add
.simm13
< 0x5b)
380 x
.i
= read_memory_integer (pc
, 4);
385 /* Check instruction at ADDR to see if it is an annulled branch.
386 All other instructions will go to NPC or will trap.
387 Set *TARGET if we find a canidate branch; set to zero if not. */
390 isannulled (instruction
, addr
, target
)
392 CORE_ADDR addr
, *target
;
394 branch_type val
= not_branch
;
395 long int offset
; /* Must be signed for sign-extend. */
398 unsigned long int code
;
405 unsigned int disp22
:22;
410 insn
.code
= instruction
;
413 && (insn
.b
.op2
== 2 || insn
.b
.op2
== 6 || insn
.b
.op2
== 7))
415 if (insn
.b
.cond
== 8)
416 val
= insn
.b
.a
? baa
: ba
;
418 val
= insn
.b
.a
? bicca
: bicc
;
419 offset
= 4 * ((int) (insn
.b
.disp22
<< 10) >> 10);
420 *target
= addr
+ offset
;
426 /* sparc_frame_find_saved_regs ()
428 Stores, into a struct frame_saved_regs,
429 the addresses of the saved registers of frame described by FRAME_INFO.
430 This includes special registers such as pc and fp saved in special
431 ways in the stack frame. sp is even more special:
432 the address we return for it IS the sp for the next frame.
434 Note that on register window machines, we are currently making the
435 assumption that window registers are being saved somewhere in the
436 frame in which they are being used. If they are stored in an
437 inferior frame, find_saved_register will break.
439 On the Sun 4, the only time all registers are saved is when
440 a dummy frame is involved. Otherwise, the only saved registers
441 are the LOCAL and IN registers which are saved as a result
442 of the "save/restore" opcodes. This condition is determined
443 by address rather than by value.
445 The "pc" is not stored in a frame on the SPARC. (What is stored
446 is a return address minus 8.) sparc_pop_frame knows how to
447 deal with that. Other routines might or might not.
449 See tm-sparc.h (PUSH_FRAME and friends) for CRITICAL information
450 about how this works. */
453 sparc_frame_find_saved_regs (fi
, saved_regs_addr
)
454 struct frame_info
*fi
;
455 struct frame_saved_regs
*saved_regs_addr
;
458 FRAME_ADDR frame
= read_register (FP_REGNUM
);
459 FRAME fid
= FRAME_INFO_ID (fi
);
462 fatal ("Bad frame info struct in FRAME_FIND_SAVED_REGS");
464 bzero (saved_regs_addr
, sizeof (*saved_regs_addr
));
467 if (fi->pc >= frame - CALL_DUMMY_LENGTH - 0x140
468 && fi->pc <= frame) */
470 if (fi
->pc
>= (fi
->bottom
? fi
->bottom
:
471 read_register (SP_REGNUM
))
472 && fi
->pc
<= FRAME_FP(fi
))
474 /* Dummy frame. All but the window regs are in there somewhere. */
475 for (regnum
= G1_REGNUM
; regnum
< G1_REGNUM
+7; regnum
++)
476 saved_regs_addr
->regs
[regnum
] =
477 frame
+ (regnum
- G0_REGNUM
) * 4 - 0xa0;
478 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+8; regnum
++)
479 saved_regs_addr
->regs
[regnum
] =
480 frame
+ (regnum
- I0_REGNUM
) * 4 - 0xc0;
481 for (regnum
= FP0_REGNUM
; regnum
< FP0_REGNUM
+ 32; regnum
++)
482 saved_regs_addr
->regs
[regnum
] =
483 frame
+ (regnum
- FP0_REGNUM
) * 4 - 0x80;
484 for (regnum
= Y_REGNUM
; regnum
< NUM_REGS
; regnum
++)
485 saved_regs_addr
->regs
[regnum
] =
486 frame
+ (regnum
- Y_REGNUM
) * 4 - 0xe0;
488 fi
->bottom
: read_register (SP_REGNUM
);
492 /* Normal frame. Just Local and In registers */
494 fi
->bottom
: read_register (SP_REGNUM
);
495 for (regnum
= L0_REGNUM
; regnum
< L0_REGNUM
+16; regnum
++)
496 saved_regs_addr
->regs
[regnum
] = frame
+ (regnum
-L0_REGNUM
) * 4;
500 /* Pull off either the next frame pointer or the stack pointer */
501 FRAME_ADDR next_next_frame
=
504 read_register (SP_REGNUM
));
505 for (regnum
= O0_REGNUM
; regnum
< O0_REGNUM
+8; regnum
++)
506 saved_regs_addr
->regs
[regnum
] = next_next_frame
+ regnum
* 4;
508 /* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */
509 saved_regs_addr
->regs
[SP_REGNUM
] = FRAME_FP (fi
);
512 /* Push an empty stack frame, and record in it the current PC, regs, etc.
514 Note that the write's are of registers in the context of the newly
515 pushed frame. Thus the the fp*'s, the g*'s, the i*'s, and
516 the randoms, of the new frame, are being saved. The locals and outs
517 are new; they don't need to be saved. The i's and l's of
518 the last frame were saved by the do_save_insn in the register
519 file (now on the stack, since a context switch happended imm after).
521 The return pointer register %i7 does not have
522 the pc saved into it (return from this frame will be accomplished
523 by a POP_FRAME). In fact, we must leave it unclobbered, since we
524 must preserve it in the calling routine except across call instructions. */
526 /* Definitely see tm-sparc.h for more doc of the frame format here. */
529 sparc_push_dummy_frame ()
532 char register_temp
[REGISTER_BYTES
];
534 do_save_insn (0x140); /* FIXME where does this value come from? */
535 fp
= read_register (FP_REGNUM
);
537 read_register_bytes (REGISTER_BYTE (FP0_REGNUM
), register_temp
, 32 * 4);
538 write_memory (fp
- 0x80, register_temp
, 32 * 4);
540 read_register_bytes (REGISTER_BYTE (G0_REGNUM
), register_temp
, 8 * 4);
541 write_memory (fp
- 0xa0, register_temp
, 8 * 4);
543 read_register_bytes (REGISTER_BYTE (I0_REGNUM
), register_temp
, 8 * 4);
544 write_memory (fp
- 0xc0, register_temp
, 8 * 4);
546 /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */
547 read_register_bytes (REGISTER_BYTE (Y_REGNUM
), register_temp
, 8 * 4);
548 write_memory (fp
- 0xe0, register_temp
, 8 * 4);
551 /* Discard from the stack the innermost frame, restoring all saved registers.
553 Note that the values stored in fsr by get_frame_saved_regs are *in
554 the context of the called frame*. What this means is that the i
555 regs of fsr must be restored into the o regs of the (calling) frame that
556 we pop into. We don't care about the output regs of the calling frame,
557 since unless it's a dummy frame, it won't have any output regs in it.
559 We never have to bother with %l (local) regs, since the called routine's
560 locals get tossed, and the calling routine's locals are already saved
563 /* Definitely see tm-sparc.h for more doc of the frame format here. */
568 register FRAME frame
= get_current_frame ();
569 register CORE_ADDR pc
;
570 struct frame_saved_regs fsr
;
571 struct frame_info
*fi
;
572 char raw_buffer
[REGISTER_BYTES
];
574 fi
= get_frame_info (frame
);
575 get_frame_saved_regs (fi
, &fsr
);
577 if (fsr
.regs
[FP0_REGNUM
])
579 read_memory (fsr
.regs
[FP0_REGNUM
], raw_buffer
, 32 * 4);
580 write_register_bytes (REGISTER_BYTE (FP0_REGNUM
), raw_buffer
, 32 * 4);
582 if (fsr
.regs
[G1_REGNUM
])
584 read_memory (fsr
.regs
[G1_REGNUM
], raw_buffer
, 7 * 4);
585 write_register_bytes (REGISTER_BYTE (G1_REGNUM
), raw_buffer
, 7 * 4);
587 if (fsr
.regs
[I0_REGNUM
])
589 read_memory (fsr
.regs
[I0_REGNUM
], raw_buffer
, 8 * 4);
590 write_register_bytes (REGISTER_BYTE (O0_REGNUM
), raw_buffer
, 8 * 4);
592 if (fsr
.regs
[PS_REGNUM
])
593 write_register (PS_REGNUM
, read_memory_integer (fsr
.regs
[PS_REGNUM
], 4));
594 if (fsr
.regs
[Y_REGNUM
])
595 write_register (Y_REGNUM
, read_memory_integer (fsr
.regs
[Y_REGNUM
], 4));
596 if (fsr
.regs
[PC_REGNUM
])
598 /* Explicitly specified PC (and maybe NPC) -- just restore them. */
599 write_register (PC_REGNUM
, read_memory_integer (fsr
.regs
[PC_REGNUM
], 4));
600 if (fsr
.regs
[NPC_REGNUM
])
601 write_register (NPC_REGNUM
,
602 read_memory_integer (fsr
.regs
[NPC_REGNUM
], 4));
604 else if (fsr
.regs
[I7_REGNUM
])
606 /* Return address in %i7 -- adjust it, then restore PC and NPC from it */
607 pc
= PC_ADJUST (read_memory_integer (fsr
.regs
[I7_REGNUM
], 4));
608 write_register (PC_REGNUM
, pc
);
609 write_register (NPC_REGNUM
, pc
+ 4);
611 flush_cached_frames ();
612 set_current_frame ( create_new_frame (read_register (FP_REGNUM
),
616 /* On the Sun 4 under SunOS, the compile will leave a fake insn which
617 encodes the structure size being returned. If we detect such
618 a fake insn, step past it. */
627 err
= target_read_memory (pc
+ 8, (char *)&insn
, sizeof(long));
628 SWAP_TARGET_AND_HOST (&insn
, sizeof(long));
629 if ((err
== 0) && (insn
& 0xfffffe00) == 0)
636 /* Structure of SPARC extended floating point numbers.
637 This information is not currently used by GDB, since no current SPARC
638 implementations support extended float. */
640 const struct ext_format ext_format_sparc
= {
641 /* tot sbyte smask expbyte manbyte */
642 16, 0, 0x80, 0,1, 4,8, /* sparc */
645 /* Figure out where the longjmp will land. We expect that we have just entered
646 longjmp and haven't yet setup the stack frame, so the args are still in the
647 output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we
648 extract the pc (JB_PC) that we will land at. The pc is copied into ADDR.
649 This routine returns true on success */
652 get_longjmp_target(pc
)
657 jb_addr
= read_register(O0_REGNUM
);
659 if (target_read_memory(jb_addr
+ JB_PC
* JB_ELEMENT_SIZE
, (char *) pc
,
663 SWAP_TARGET_AND_HOST(pc
, sizeof(CORE_ADDR
));