1 /* Target-dependent code for SPARC.
3 Copyright (C) 2003-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "arch-utils.h"
23 #include "dwarf2-frame.h"
24 #include "floatformat.h"
26 #include "frame-base.h"
27 #include "frame-unwind.h"
36 #include "target-descriptions.h"
39 #include "sparc-tdep.h"
40 #include "sparc-ravenscar-thread.h"
45 /* This file implements the SPARC 32-bit ABI as defined by the section
46 "Low-Level System Information" of the SPARC Compliance Definition
47 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
48 lists changes with respect to the original 32-bit psABI as defined
49 in the "System V ABI, SPARC Processor Supplement".
51 Note that if we talk about SunOS, we mean SunOS 4.x, which was
52 BSD-based, which is sometimes (retroactively?) referred to as
53 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
54 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
55 suffering from severe version number inflation). Solaris 2.x is
56 also known as SunOS 5.x, since that's what uname(1) says. Solaris
59 /* Please use the sparc32_-prefix for 32-bit specific code, the
60 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
61 code that can handle both. The 64-bit specific code lives in
62 sparc64-tdep.c; don't add any here. */
64 /* The SPARC Floating-Point Quad-Precision format is similar to
65 big-endian IA-64 Quad-Precision format. */
66 #define floatformats_sparc_quad floatformats_ia64_quad
68 /* The stack pointer is offset from the stack frame by a BIAS of 2047
69 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
70 hosts, so undefine it first. */
74 /* Macros to extract fields from SPARC instructions. */
75 #define X_OP(i) (((i) >> 30) & 0x3)
76 #define X_RD(i) (((i) >> 25) & 0x1f)
77 #define X_A(i) (((i) >> 29) & 1)
78 #define X_COND(i) (((i) >> 25) & 0xf)
79 #define X_OP2(i) (((i) >> 22) & 0x7)
80 #define X_IMM22(i) ((i) & 0x3fffff)
81 #define X_OP3(i) (((i) >> 19) & 0x3f)
82 #define X_RS1(i) (((i) >> 14) & 0x1f)
83 #define X_RS2(i) ((i) & 0x1f)
84 #define X_I(i) (((i) >> 13) & 1)
85 /* Sign extension macros. */
86 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
87 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
88 #define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200)
89 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
90 /* Macros to identify some instructions. */
91 /* RETURN (RETT in V8) */
92 #define X_RETTURN(i) ((X_OP (i) == 0x2) && (X_OP3 (i) == 0x39))
94 /* Fetch the instruction at PC. Instructions are always big-endian
95 even if the processor operates in little-endian mode. */
98 sparc_fetch_instruction (CORE_ADDR pc
)
104 /* If we can't read the instruction at PC, return zero. */
105 if (target_read_memory (pc
, buf
, sizeof (buf
)))
109 for (i
= 0; i
< sizeof (buf
); i
++)
110 insn
= (insn
<< 8) | buf
[i
];
115 /* Return non-zero if the instruction corresponding to PC is an "unimp"
119 sparc_is_unimp_insn (CORE_ADDR pc
)
121 const unsigned long insn
= sparc_fetch_instruction (pc
);
123 return ((insn
& 0xc1c00000) == 0);
126 /* Return non-zero if the instruction corresponding to PC is an
127 "annulled" branch, i.e. the annul bit is set. */
130 sparc_is_annulled_branch_insn (CORE_ADDR pc
)
132 /* The branch instructions featuring an annul bit can be identified
133 by the following bit patterns:
136 OP2=1: Branch on Integer Condition Codes with Prediction (BPcc).
137 OP2=2: Branch on Integer Condition Codes (Bcc).
138 OP2=5: Branch on FP Condition Codes with Prediction (FBfcc).
139 OP2=6: Branch on FP Condition Codes (FBcc).
141 Branch on Integer Register with Prediction (BPr).
143 This leaves out ILLTRAP (OP2=0), SETHI/NOP (OP2=4) and the V8
144 coprocessor branch instructions (Op2=7). */
146 const unsigned long insn
= sparc_fetch_instruction (pc
);
147 const unsigned op2
= X_OP2 (insn
);
149 if ((X_OP (insn
) == 0)
150 && ((op2
== 1) || (op2
== 2) || (op2
== 5) || (op2
== 6)
151 || ((op2
== 3) && ((insn
& 0x10000000) == 0))))
157 /* OpenBSD/sparc includes StackGhost, which according to the author's
158 website http://stackghost.cerias.purdue.edu "... transparently and
159 automatically protects applications' stack frames; more
160 specifically, it guards the return pointers. The protection
161 mechanisms require no application source or binary modification and
162 imposes only a negligible performance penalty."
164 The same website provides the following description of how
167 "StackGhost interfaces with the kernel trap handler that would
168 normally write out registers to the stack and the handler that
169 would read them back in. By XORing a cookie into the
170 return-address saved in the user stack when it is actually written
171 to the stack, and then XOR it out when the return-address is pulled
172 from the stack, StackGhost can cause attacker corrupted return
173 pointers to behave in a manner the attacker cannot predict.
174 StackGhost can also use several unused bits in the return pointer
175 to detect a smashed return pointer and abort the process."
177 For GDB this means that whenever we're reading %i7 from a stack
178 frame's window save area, we'll have to XOR the cookie.
180 More information on StackGuard can be found on in:
182 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
183 Stack Protection." 2001. Published in USENIX Security Symposium
186 /* Fetch StackGhost Per-Process XOR cookie. */
189 sparc_fetch_wcookie (struct gdbarch
*gdbarch
)
191 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
192 struct target_ops
*ops
= ¤t_target
;
196 len
= target_read (ops
, TARGET_OBJECT_WCOOKIE
, NULL
, buf
, 0, 8);
200 /* We should have either an 32-bit or an 64-bit cookie. */
201 gdb_assert (len
== 4 || len
== 8);
203 return extract_unsigned_integer (buf
, len
, byte_order
);
207 /* The functions on this page are intended to be used to classify
208 function arguments. */
210 /* Check whether TYPE is "Integral or Pointer". */
213 sparc_integral_or_pointer_p (const struct type
*type
)
215 int len
= TYPE_LENGTH (type
);
217 switch (TYPE_CODE (type
))
223 case TYPE_CODE_RANGE
:
224 /* We have byte, half-word, word and extended-word/doubleword
225 integral types. The doubleword is an extension to the
226 original 32-bit ABI by the SCD 2.4.x. */
227 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
230 /* Allow either 32-bit or 64-bit pointers. */
231 return (len
== 4 || len
== 8);
239 /* Check whether TYPE is "Floating". */
242 sparc_floating_p (const struct type
*type
)
244 switch (TYPE_CODE (type
))
248 int len
= TYPE_LENGTH (type
);
249 return (len
== 4 || len
== 8 || len
== 16);
258 /* Check whether TYPE is "Complex Floating". */
261 sparc_complex_floating_p (const struct type
*type
)
263 switch (TYPE_CODE (type
))
265 case TYPE_CODE_COMPLEX
:
267 int len
= TYPE_LENGTH (type
);
268 return (len
== 8 || len
== 16 || len
== 32);
277 /* Check whether TYPE is "Structure or Union".
279 In terms of Ada subprogram calls, arrays are treated the same as
280 struct and union types. So this function also returns non-zero
284 sparc_structure_or_union_p (const struct type
*type
)
286 switch (TYPE_CODE (type
))
288 case TYPE_CODE_STRUCT
:
289 case TYPE_CODE_UNION
:
290 case TYPE_CODE_ARRAY
:
299 /* Register information. */
300 #define SPARC32_FPU_REGISTERS \
301 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
302 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
303 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \
304 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
305 #define SPARC32_CP0_REGISTERS \
306 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
308 static const char *sparc_core_register_names
[] = { SPARC_CORE_REGISTERS
};
309 static const char *sparc32_fpu_register_names
[] = { SPARC32_FPU_REGISTERS
};
310 static const char *sparc32_cp0_register_names
[] = { SPARC32_CP0_REGISTERS
};
312 static const char *sparc32_register_names
[] =
314 SPARC_CORE_REGISTERS
,
315 SPARC32_FPU_REGISTERS
,
316 SPARC32_CP0_REGISTERS
319 /* Total number of registers. */
320 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
322 /* We provide the aliases %d0..%d30 for the floating registers as
323 "psuedo" registers. */
325 static const char *sparc32_pseudo_register_names
[] =
327 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
328 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
331 /* Total number of pseudo registers. */
332 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
334 /* Return the name of pseudo register REGNUM. */
337 sparc32_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
339 regnum
-= gdbarch_num_regs (gdbarch
);
341 if (regnum
< SPARC32_NUM_PSEUDO_REGS
)
342 return sparc32_pseudo_register_names
[regnum
];
344 internal_error (__FILE__
, __LINE__
,
345 _("sparc32_pseudo_register_name: bad register number %d"),
349 /* Return the name of register REGNUM. */
352 sparc32_register_name (struct gdbarch
*gdbarch
, int regnum
)
354 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
355 return tdesc_register_name (gdbarch
, regnum
);
357 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
358 return sparc32_register_names
[regnum
];
360 return sparc32_pseudo_register_name (gdbarch
, regnum
);
363 /* Construct types for ISA-specific registers. */
366 sparc_psr_type (struct gdbarch
*gdbarch
)
368 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
370 if (!tdep
->sparc_psr_type
)
374 type
= arch_flags_type (gdbarch
, "builtin_type_sparc_psr", 4);
375 append_flags_type_flag (type
, 5, "ET");
376 append_flags_type_flag (type
, 6, "PS");
377 append_flags_type_flag (type
, 7, "S");
378 append_flags_type_flag (type
, 12, "EF");
379 append_flags_type_flag (type
, 13, "EC");
381 tdep
->sparc_psr_type
= type
;
384 return tdep
->sparc_psr_type
;
388 sparc_fsr_type (struct gdbarch
*gdbarch
)
390 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
392 if (!tdep
->sparc_fsr_type
)
396 type
= arch_flags_type (gdbarch
, "builtin_type_sparc_fsr", 4);
397 append_flags_type_flag (type
, 0, "NXA");
398 append_flags_type_flag (type
, 1, "DZA");
399 append_flags_type_flag (type
, 2, "UFA");
400 append_flags_type_flag (type
, 3, "OFA");
401 append_flags_type_flag (type
, 4, "NVA");
402 append_flags_type_flag (type
, 5, "NXC");
403 append_flags_type_flag (type
, 6, "DZC");
404 append_flags_type_flag (type
, 7, "UFC");
405 append_flags_type_flag (type
, 8, "OFC");
406 append_flags_type_flag (type
, 9, "NVC");
407 append_flags_type_flag (type
, 22, "NS");
408 append_flags_type_flag (type
, 23, "NXM");
409 append_flags_type_flag (type
, 24, "DZM");
410 append_flags_type_flag (type
, 25, "UFM");
411 append_flags_type_flag (type
, 26, "OFM");
412 append_flags_type_flag (type
, 27, "NVM");
414 tdep
->sparc_fsr_type
= type
;
417 return tdep
->sparc_fsr_type
;
420 /* Return the GDB type object for the "standard" data type of data in
421 pseudo register REGNUM. */
424 sparc32_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
426 regnum
-= gdbarch_num_regs (gdbarch
);
428 if (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
)
429 return builtin_type (gdbarch
)->builtin_double
;
431 internal_error (__FILE__
, __LINE__
,
432 _("sparc32_pseudo_register_type: bad register number %d"),
436 /* Return the GDB type object for the "standard" data type of data in
440 sparc32_register_type (struct gdbarch
*gdbarch
, int regnum
)
442 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
443 return tdesc_register_type (gdbarch
, regnum
);
445 if (regnum
>= SPARC_F0_REGNUM
&& regnum
<= SPARC_F31_REGNUM
)
446 return builtin_type (gdbarch
)->builtin_float
;
448 if (regnum
== SPARC_SP_REGNUM
|| regnum
== SPARC_FP_REGNUM
)
449 return builtin_type (gdbarch
)->builtin_data_ptr
;
451 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
452 return builtin_type (gdbarch
)->builtin_func_ptr
;
454 if (regnum
== SPARC32_PSR_REGNUM
)
455 return sparc_psr_type (gdbarch
);
457 if (regnum
== SPARC32_FSR_REGNUM
)
458 return sparc_fsr_type (gdbarch
);
460 if (regnum
>= gdbarch_num_regs (gdbarch
))
461 return sparc32_pseudo_register_type (gdbarch
, regnum
);
463 return builtin_type (gdbarch
)->builtin_int32
;
466 static enum register_status
467 sparc32_pseudo_register_read (struct gdbarch
*gdbarch
,
468 struct regcache
*regcache
,
469 int regnum
, gdb_byte
*buf
)
471 enum register_status status
;
473 regnum
-= gdbarch_num_regs (gdbarch
);
474 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
476 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
477 status
= regcache_raw_read (regcache
, regnum
, buf
);
478 if (status
== REG_VALID
)
479 status
= regcache_raw_read (regcache
, regnum
+ 1, buf
+ 4);
484 sparc32_pseudo_register_write (struct gdbarch
*gdbarch
,
485 struct regcache
*regcache
,
486 int regnum
, const gdb_byte
*buf
)
488 regnum
-= gdbarch_num_regs (gdbarch
);
489 gdb_assert (regnum
>= SPARC32_D0_REGNUM
&& regnum
<= SPARC32_D30_REGNUM
);
491 regnum
= SPARC_F0_REGNUM
+ 2 * (regnum
- SPARC32_D0_REGNUM
);
492 regcache_raw_write (regcache
, regnum
, buf
);
493 regcache_raw_write (regcache
, regnum
+ 1, buf
+ 4);
496 /* Implement the stack_frame_destroyed_p gdbarch method. */
499 sparc_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
501 /* This function must return true if we are one instruction after an
502 instruction that destroyed the stack frame of the current
503 function. The SPARC instructions used to restore the callers
504 stack frame are RESTORE and RETURN/RETT.
506 Of these RETURN/RETT is a branch instruction and thus we return
507 true if we are in its delay slot.
509 RESTORE is almost always found in the delay slot of a branch
510 instruction that transfers control to the caller, such as JMPL.
511 Thus the next instruction is in the caller frame and we don't
512 need to do anything about it. */
514 unsigned int insn
= sparc_fetch_instruction (pc
- 4);
516 return X_RETTURN (insn
);
521 sparc32_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
523 /* The ABI requires double-word alignment. */
524 return address
& ~0x7;
528 sparc32_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
530 struct value
**args
, int nargs
,
531 struct type
*value_type
,
532 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
533 struct regcache
*regcache
)
535 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
540 if (using_struct_return (gdbarch
, NULL
, value_type
))
544 /* This is an UNIMP instruction. */
545 store_unsigned_integer (buf
, 4, byte_order
,
546 TYPE_LENGTH (value_type
) & 0x1fff);
547 write_memory (sp
- 8, buf
, 4);
555 sparc32_store_arguments (struct regcache
*regcache
, int nargs
,
556 struct value
**args
, CORE_ADDR sp
,
557 int struct_return
, CORE_ADDR struct_addr
)
559 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
560 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
561 /* Number of words in the "parameter array". */
562 int num_elements
= 0;
566 for (i
= 0; i
< nargs
; i
++)
568 struct type
*type
= value_type (args
[i
]);
569 int len
= TYPE_LENGTH (type
);
571 if (sparc_structure_or_union_p (type
)
572 || (sparc_floating_p (type
) && len
== 16)
573 || sparc_complex_floating_p (type
))
575 /* Structure, Union and Quad-Precision Arguments. */
578 /* Use doubleword alignment for these values. That's always
579 correct, and wasting a few bytes shouldn't be a problem. */
582 write_memory (sp
, value_contents (args
[i
]), len
);
583 args
[i
] = value_from_pointer (lookup_pointer_type (type
), sp
);
586 else if (sparc_floating_p (type
))
588 /* Floating arguments. */
589 gdb_assert (len
== 4 || len
== 8);
590 num_elements
+= (len
/ 4);
594 /* Integral and pointer arguments. */
595 gdb_assert (sparc_integral_or_pointer_p (type
));
598 args
[i
] = value_cast (builtin_type (gdbarch
)->builtin_int32
,
600 num_elements
+= ((len
+ 3) / 4);
604 /* Always allocate at least six words. */
605 sp
-= std::max (6, num_elements
) * 4;
607 /* The psABI says that "Software convention requires space for the
608 struct/union return value pointer, even if the word is unused." */
611 /* The psABI says that "Although software convention and the
612 operating system require every stack frame to be doubleword
616 for (i
= 0; i
< nargs
; i
++)
618 const bfd_byte
*valbuf
= value_contents (args
[i
]);
619 struct type
*type
= value_type (args
[i
]);
620 int len
= TYPE_LENGTH (type
);
622 gdb_assert (len
== 4 || len
== 8);
626 int regnum
= SPARC_O0_REGNUM
+ element
;
628 regcache_cooked_write (regcache
, regnum
, valbuf
);
629 if (len
> 4 && element
< 5)
630 regcache_cooked_write (regcache
, regnum
+ 1, valbuf
+ 4);
633 /* Always store the argument in memory. */
634 write_memory (sp
+ 4 + element
* 4, valbuf
, len
);
638 gdb_assert (element
== num_elements
);
644 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
645 write_memory (sp
, buf
, 4);
652 sparc32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
653 struct regcache
*regcache
, CORE_ADDR bp_addr
,
654 int nargs
, struct value
**args
, CORE_ADDR sp
,
655 int struct_return
, CORE_ADDR struct_addr
)
657 CORE_ADDR call_pc
= (struct_return
? (bp_addr
- 12) : (bp_addr
- 8));
659 /* Set return address. */
660 regcache_cooked_write_unsigned (regcache
, SPARC_O7_REGNUM
, call_pc
);
662 /* Set up function arguments. */
663 sp
= sparc32_store_arguments (regcache
, nargs
, args
, sp
,
664 struct_return
, struct_addr
);
666 /* Allocate the 16-word window save area. */
669 /* Stack should be doubleword aligned at this point. */
670 gdb_assert (sp
% 8 == 0);
672 /* Finally, update the stack pointer. */
673 regcache_cooked_write_unsigned (regcache
, SPARC_SP_REGNUM
, sp
);
679 /* Use the program counter to determine the contents and size of a
680 breakpoint instruction. Return a pointer to a string of bytes that
681 encode a breakpoint instruction, store the length of the string in
682 *LEN and optionally adjust *PC to point to the correct memory
683 location for inserting the breakpoint. */
684 constexpr gdb_byte sparc_break_insn
[] = { 0x91, 0xd0, 0x20, 0x01 };
686 typedef BP_MANIPULATION (sparc_break_insn
) sparc_breakpoint
;
689 /* Allocate and initialize a frame cache. */
691 static struct sparc_frame_cache
*
692 sparc_alloc_frame_cache (void)
694 struct sparc_frame_cache
*cache
;
696 cache
= FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache
);
702 /* Frameless until proven otherwise. */
703 cache
->frameless_p
= 1;
704 cache
->frame_offset
= 0;
705 cache
->saved_regs_mask
= 0;
706 cache
->copied_regs_mask
= 0;
707 cache
->struct_return_p
= 0;
712 /* GCC generates several well-known sequences of instructions at the begining
713 of each function prologue when compiling with -fstack-check. If one of
714 such sequences starts at START_PC, then return the address of the
715 instruction immediately past this sequence. Otherwise, return START_PC. */
718 sparc_skip_stack_check (const CORE_ADDR start_pc
)
720 CORE_ADDR pc
= start_pc
;
722 int probing_loop
= 0;
724 /* With GCC, all stack checking sequences begin with the same two
725 instructions, plus an optional one in the case of a probing loop:
727 sethi <some immediate>, %g1
732 sethi <some immediate>, %g1
733 sethi <some immediate>, %g4
738 sethi <some immediate>, %g1
740 sethi <some immediate>, %g4
742 If the optional instruction is found (setting g4), assume that a
743 probing loop will follow. */
745 /* sethi <some immediate>, %g1 */
746 insn
= sparc_fetch_instruction (pc
);
748 if (!(X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 1))
751 /* optional: sethi <some immediate>, %g4 */
752 insn
= sparc_fetch_instruction (pc
);
754 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 4)
757 insn
= sparc_fetch_instruction (pc
);
761 /* sub %sp, %g1, %g1 */
762 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
763 && X_RD (insn
) == 1 && X_RS1 (insn
) == 14 && X_RS2 (insn
) == 1))
766 insn
= sparc_fetch_instruction (pc
);
769 /* optional: sethi <some immediate>, %g4 */
770 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x4 && X_RD (insn
) == 4)
773 insn
= sparc_fetch_instruction (pc
);
777 /* First possible sequence:
778 [first two instructions above]
779 clr [%g1 - some immediate] */
781 /* clr [%g1 - some immediate] */
782 if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
783 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
785 /* Valid stack-check sequence, return the new PC. */
789 /* Second possible sequence: A small number of probes.
790 [first two instructions above]
792 add %g1, -<some immediate>, %g1
794 [repeat the two instructions above any (small) number of times]
795 clr [%g1 - some immediate] */
798 else if (X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
799 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0)
803 /* add %g1, -<some immediate>, %g1 */
804 insn
= sparc_fetch_instruction (pc
);
806 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
807 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
811 insn
= sparc_fetch_instruction (pc
);
813 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && !X_I(insn
)
814 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1))
818 /* clr [%g1 - some immediate] */
819 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
820 && X_RS1 (insn
) == 1 && X_RD (insn
) == 0))
823 /* We found a valid stack-check sequence, return the new PC. */
827 /* Third sequence: A probing loop.
828 [first three instructions above]
832 add %g1, -<some immediate>, %g1
836 And an optional last probe for the remainder:
838 clr [%g4 - some immediate] */
842 /* sub %g1, %g4, %g4 */
843 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x4 && !X_I(insn
)
844 && X_RD (insn
) == 4 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
848 insn
= sparc_fetch_instruction (pc
);
850 if (!(X_OP (insn
) == 2 && X_OP3 (insn
) == 0x14 && !X_I(insn
)
851 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1 && X_RS2 (insn
) == 4))
855 insn
= sparc_fetch_instruction (pc
);
857 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x1))
860 /* add %g1, -<some immediate>, %g1 */
861 insn
= sparc_fetch_instruction (pc
);
863 if (!(X_OP (insn
) == 2 && X_OP3(insn
) == 0 && X_I(insn
)
864 && X_RS1 (insn
) == 1 && X_RD (insn
) == 1))
868 insn
= sparc_fetch_instruction (pc
);
870 if (!(X_OP (insn
) == 0 && X_COND (insn
) == 0x8))
873 /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */
874 insn
= sparc_fetch_instruction (pc
);
876 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4
877 && X_RD (insn
) == 0 && X_RS1 (insn
) == 1
878 && (!X_I(insn
) || X_SIMM13 (insn
) == 0)))
881 /* We found a valid stack-check sequence, return the new PC. */
883 /* optional: clr [%g4 - some immediate] */
884 insn
= sparc_fetch_instruction (pc
);
886 if (!(X_OP (insn
) == 3 && X_OP3(insn
) == 0x4 && X_I(insn
)
887 && X_RS1 (insn
) == 4 && X_RD (insn
) == 0))
893 /* No stack check code in our prologue, return the start_pc. */
897 /* Record the effect of a SAVE instruction on CACHE. */
900 sparc_record_save_insn (struct sparc_frame_cache
*cache
)
902 /* The frame is set up. */
903 cache
->frameless_p
= 0;
905 /* The frame pointer contains the CFA. */
906 cache
->frame_offset
= 0;
908 /* The `local' and `in' registers are all saved. */
909 cache
->saved_regs_mask
= 0xffff;
911 /* The `out' registers are all renamed. */
912 cache
->copied_regs_mask
= 0xff;
915 /* Do a full analysis of the prologue at PC and update CACHE accordingly.
916 Bail out early if CURRENT_PC is reached. Return the address where
917 the analysis stopped.
919 We handle both the traditional register window model and the single
920 register window (aka flat) model. */
923 sparc_analyze_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
924 CORE_ADDR current_pc
, struct sparc_frame_cache
*cache
)
926 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
931 pc
= sparc_skip_stack_check (pc
);
933 if (current_pc
<= pc
)
936 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
937 SPARC the linker usually defines a symbol (typically
938 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
939 This symbol makes us end up here with PC pointing at the start of
940 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
941 would do our normal prologue analysis, we would probably conclude
942 that we've got a frame when in reality we don't, since the
943 dynamic linker patches up the first PLT with some code that
944 starts with a SAVE instruction. Patch up PC such that it points
945 at the start of our PLT entry. */
946 if (tdep
->plt_entry_size
> 0 && in_plt_section (current_pc
))
947 pc
= current_pc
- ((current_pc
- pc
) % tdep
->plt_entry_size
);
949 insn
= sparc_fetch_instruction (pc
);
951 /* Recognize store insns and record their sources. */
952 while (X_OP (insn
) == 3
953 && (X_OP3 (insn
) == 0x4 /* stw */
954 || X_OP3 (insn
) == 0x7 /* std */
955 || X_OP3 (insn
) == 0xe) /* stx */
956 && X_RS1 (insn
) == SPARC_SP_REGNUM
)
958 int regnum
= X_RD (insn
);
960 /* Recognize stores into the corresponding stack slots. */
961 if (regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
963 && X_SIMM13 (insn
) == (X_OP3 (insn
) == 0xe
964 ? (regnum
- SPARC_L0_REGNUM
) * 8 + BIAS
965 : (regnum
- SPARC_L0_REGNUM
) * 4))
966 || (!X_I (insn
) && regnum
== SPARC_L0_REGNUM
)))
968 cache
->saved_regs_mask
|= (1 << (regnum
- SPARC_L0_REGNUM
));
969 if (X_OP3 (insn
) == 0x7)
970 cache
->saved_regs_mask
|= (1 << (regnum
+ 1 - SPARC_L0_REGNUM
));
975 insn
= sparc_fetch_instruction (pc
+ offset
);
978 /* Recognize a SETHI insn and record its destination. */
979 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 0x04)
984 insn
= sparc_fetch_instruction (pc
+ offset
);
987 /* Allow for an arithmetic operation on DEST or %g1. */
988 if (X_OP (insn
) == 2 && X_I (insn
)
989 && (X_RD (insn
) == 1 || X_RD (insn
) == dest
))
993 insn
= sparc_fetch_instruction (pc
+ offset
);
996 /* Check for the SAVE instruction that sets up the frame. */
997 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3c)
999 sparc_record_save_insn (cache
);
1004 /* Check for an arithmetic operation on %sp. */
1005 if (X_OP (insn
) == 2
1006 && (X_OP3 (insn
) == 0 || X_OP3 (insn
) == 0x4)
1007 && X_RS1 (insn
) == SPARC_SP_REGNUM
1008 && X_RD (insn
) == SPARC_SP_REGNUM
)
1012 cache
->frame_offset
= X_SIMM13 (insn
);
1013 if (X_OP3 (insn
) == 0)
1014 cache
->frame_offset
= -cache
->frame_offset
;
1018 insn
= sparc_fetch_instruction (pc
+ offset
);
1020 /* Check for an arithmetic operation that sets up the frame. */
1021 if (X_OP (insn
) == 2
1022 && (X_OP3 (insn
) == 0 || X_OP3 (insn
) == 0x4)
1023 && X_RS1 (insn
) == SPARC_SP_REGNUM
1024 && X_RD (insn
) == SPARC_FP_REGNUM
)
1026 cache
->frameless_p
= 0;
1027 cache
->frame_offset
= 0;
1028 /* We could check that the amount subtracted to %sp above is the
1029 same as the one added here, but this seems superfluous. */
1030 cache
->copied_regs_mask
|= 0x40;
1033 insn
= sparc_fetch_instruction (pc
+ offset
);
1036 /* Check for a move (or) operation that copies the return register. */
1037 if (X_OP (insn
) == 2
1038 && X_OP3 (insn
) == 0x2
1040 && X_RS1 (insn
) == SPARC_G0_REGNUM
1041 && X_RS2 (insn
) == SPARC_O7_REGNUM
1042 && X_RD (insn
) == SPARC_I7_REGNUM
)
1044 cache
->copied_regs_mask
|= 0x80;
1055 sparc_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1057 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1058 return frame_unwind_register_unsigned (this_frame
, tdep
->pc_regnum
);
1061 /* Return PC of first real instruction of the function starting at
1065 sparc32_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1067 struct symtab_and_line sal
;
1068 CORE_ADDR func_start
, func_end
;
1069 struct sparc_frame_cache cache
;
1071 /* This is the preferred method, find the end of the prologue by
1072 using the debugging information. */
1073 if (find_pc_partial_function (start_pc
, NULL
, &func_start
, &func_end
))
1075 sal
= find_pc_line (func_start
, 0);
1077 if (sal
.end
< func_end
1078 && start_pc
<= sal
.end
)
1082 start_pc
= sparc_analyze_prologue (gdbarch
, start_pc
, 0xffffffffUL
, &cache
);
1084 /* The psABI says that "Although the first 6 words of arguments
1085 reside in registers, the standard stack frame reserves space for
1086 them.". It also suggests that a function may use that space to
1087 "write incoming arguments 0 to 5" into that space, and that's
1088 indeed what GCC seems to be doing. In that case GCC will
1089 generate debug information that points to the stack slots instead
1090 of the registers, so we should consider the instructions that
1091 write out these incoming arguments onto the stack. */
1095 unsigned long insn
= sparc_fetch_instruction (start_pc
);
1097 /* Recognize instructions that store incoming arguments into the
1098 corresponding stack slots. */
1099 if (X_OP (insn
) == 3 && (X_OP3 (insn
) & 0x3c) == 0x04
1100 && X_I (insn
) && X_RS1 (insn
) == SPARC_FP_REGNUM
)
1102 int regnum
= X_RD (insn
);
1104 /* Case of arguments still in %o[0..5]. */
1105 if (regnum
>= SPARC_O0_REGNUM
&& regnum
<= SPARC_O5_REGNUM
1106 && !(cache
.copied_regs_mask
& (1 << (regnum
- SPARC_O0_REGNUM
)))
1107 && X_SIMM13 (insn
) == 68 + (regnum
- SPARC_O0_REGNUM
) * 4)
1113 /* Case of arguments copied into %i[0..5]. */
1114 if (regnum
>= SPARC_I0_REGNUM
&& regnum
<= SPARC_I5_REGNUM
1115 && (cache
.copied_regs_mask
& (1 << (regnum
- SPARC_I0_REGNUM
)))
1116 && X_SIMM13 (insn
) == 68 + (regnum
- SPARC_I0_REGNUM
) * 4)
1129 /* Normal frames. */
1131 struct sparc_frame_cache
*
1132 sparc_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1134 struct sparc_frame_cache
*cache
;
1137 return (struct sparc_frame_cache
*) *this_cache
;
1139 cache
= sparc_alloc_frame_cache ();
1140 *this_cache
= cache
;
1142 cache
->pc
= get_frame_func (this_frame
);
1144 sparc_analyze_prologue (get_frame_arch (this_frame
), cache
->pc
,
1145 get_frame_pc (this_frame
), cache
);
1147 if (cache
->frameless_p
)
1149 /* This function is frameless, so %fp (%i6) holds the frame
1150 pointer for our calling frame. Use %sp (%o6) as this frame's
1153 get_frame_register_unsigned (this_frame
, SPARC_SP_REGNUM
);
1157 /* For normal frames, %fp (%i6) holds the frame pointer, the
1158 base address for the current stack frame. */
1160 get_frame_register_unsigned (this_frame
, SPARC_FP_REGNUM
);
1163 cache
->base
+= cache
->frame_offset
;
1165 if (cache
->base
& 1)
1166 cache
->base
+= BIAS
;
1172 sparc32_struct_return_from_sym (struct symbol
*sym
)
1174 struct type
*type
= check_typedef (SYMBOL_TYPE (sym
));
1175 enum type_code code
= TYPE_CODE (type
);
1177 if (code
== TYPE_CODE_FUNC
|| code
== TYPE_CODE_METHOD
)
1179 type
= check_typedef (TYPE_TARGET_TYPE (type
));
1180 if (sparc_structure_or_union_p (type
)
1181 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
1188 struct sparc_frame_cache
*
1189 sparc32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1191 struct sparc_frame_cache
*cache
;
1195 return (struct sparc_frame_cache
*) *this_cache
;
1197 cache
= sparc_frame_cache (this_frame
, this_cache
);
1199 sym
= find_pc_function (cache
->pc
);
1202 cache
->struct_return_p
= sparc32_struct_return_from_sym (sym
);
1206 /* There is no debugging information for this function to
1207 help us determine whether this function returns a struct
1208 or not. So we rely on another heuristic which is to check
1209 the instruction at the return address and see if this is
1210 an "unimp" instruction. If it is, then it is a struct-return
1214 (cache
->copied_regs_mask
& 0x80) ? SPARC_I7_REGNUM
: SPARC_O7_REGNUM
;
1216 pc
= get_frame_register_unsigned (this_frame
, regnum
) + 8;
1217 if (sparc_is_unimp_insn (pc
))
1218 cache
->struct_return_p
= 1;
1225 sparc32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1226 struct frame_id
*this_id
)
1228 struct sparc_frame_cache
*cache
=
1229 sparc32_frame_cache (this_frame
, this_cache
);
1231 /* This marks the outermost frame. */
1232 if (cache
->base
== 0)
1235 (*this_id
) = frame_id_build (cache
->base
, cache
->pc
);
1238 static struct value
*
1239 sparc32_frame_prev_register (struct frame_info
*this_frame
,
1240 void **this_cache
, int regnum
)
1242 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1243 struct sparc_frame_cache
*cache
=
1244 sparc32_frame_cache (this_frame
, this_cache
);
1246 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== SPARC32_NPC_REGNUM
)
1248 CORE_ADDR pc
= (regnum
== SPARC32_NPC_REGNUM
) ? 4 : 0;
1250 /* If this functions has a Structure, Union or Quad-Precision
1251 return value, we have to skip the UNIMP instruction that encodes
1252 the size of the structure. */
1253 if (cache
->struct_return_p
)
1257 (cache
->copied_regs_mask
& 0x80) ? SPARC_I7_REGNUM
: SPARC_O7_REGNUM
;
1258 pc
+= get_frame_register_unsigned (this_frame
, regnum
) + 8;
1259 return frame_unwind_got_constant (this_frame
, regnum
, pc
);
1262 /* Handle StackGhost. */
1264 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1266 if (wcookie
!= 0 && !cache
->frameless_p
&& regnum
== SPARC_I7_REGNUM
)
1268 CORE_ADDR addr
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
1271 /* Read the value in from memory. */
1272 i7
= get_frame_memory_unsigned (this_frame
, addr
, 4);
1273 return frame_unwind_got_constant (this_frame
, regnum
, i7
^ wcookie
);
1277 /* The previous frame's `local' and `in' registers may have been saved
1278 in the register save area. */
1279 if (regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
1280 && (cache
->saved_regs_mask
& (1 << (regnum
- SPARC_L0_REGNUM
))))
1282 CORE_ADDR addr
= cache
->base
+ (regnum
- SPARC_L0_REGNUM
) * 4;
1284 return frame_unwind_got_memory (this_frame
, regnum
, addr
);
1287 /* The previous frame's `out' registers may be accessible as the current
1288 frame's `in' registers. */
1289 if (regnum
>= SPARC_O0_REGNUM
&& regnum
<= SPARC_O7_REGNUM
1290 && (cache
->copied_regs_mask
& (1 << (regnum
- SPARC_O0_REGNUM
))))
1291 regnum
+= (SPARC_I0_REGNUM
- SPARC_O0_REGNUM
);
1293 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1296 static const struct frame_unwind sparc32_frame_unwind
=
1299 default_frame_unwind_stop_reason
,
1300 sparc32_frame_this_id
,
1301 sparc32_frame_prev_register
,
1303 default_frame_sniffer
1308 sparc32_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1310 struct sparc_frame_cache
*cache
=
1311 sparc32_frame_cache (this_frame
, this_cache
);
1316 static const struct frame_base sparc32_frame_base
=
1318 &sparc32_frame_unwind
,
1319 sparc32_frame_base_address
,
1320 sparc32_frame_base_address
,
1321 sparc32_frame_base_address
1324 static struct frame_id
1325 sparc_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1329 sp
= get_frame_register_unsigned (this_frame
, SPARC_SP_REGNUM
);
1332 return frame_id_build (sp
, get_frame_pc (this_frame
));
1336 /* Extract a function return value of TYPE from REGCACHE, and copy
1337 that into VALBUF. */
1340 sparc32_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1343 int len
= TYPE_LENGTH (type
);
1346 gdb_assert (!sparc_structure_or_union_p (type
));
1347 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1349 if (sparc_floating_p (type
) || sparc_complex_floating_p (type
))
1351 /* Floating return values. */
1352 regcache_cooked_read (regcache
, SPARC_F0_REGNUM
, buf
);
1354 regcache_cooked_read (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1357 regcache_cooked_read (regcache
, SPARC_F2_REGNUM
, buf
+ 8);
1358 regcache_cooked_read (regcache
, SPARC_F3_REGNUM
, buf
+ 12);
1362 regcache_cooked_read (regcache
, SPARC_F4_REGNUM
, buf
+ 16);
1363 regcache_cooked_read (regcache
, SPARC_F5_REGNUM
, buf
+ 20);
1364 regcache_cooked_read (regcache
, SPARC_F6_REGNUM
, buf
+ 24);
1365 regcache_cooked_read (regcache
, SPARC_F7_REGNUM
, buf
+ 28);
1367 memcpy (valbuf
, buf
, len
);
1371 /* Integral and pointer return values. */
1372 gdb_assert (sparc_integral_or_pointer_p (type
));
1374 regcache_cooked_read (regcache
, SPARC_O0_REGNUM
, buf
);
1377 regcache_cooked_read (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1378 gdb_assert (len
== 8);
1379 memcpy (valbuf
, buf
, 8);
1383 /* Just stripping off any unused bytes should preserve the
1384 signed-ness just fine. */
1385 memcpy (valbuf
, buf
+ 4 - len
, len
);
1390 /* Store the function return value of type TYPE from VALBUF into
1394 sparc32_store_return_value (struct type
*type
, struct regcache
*regcache
,
1395 const gdb_byte
*valbuf
)
1397 int len
= TYPE_LENGTH (type
);
1400 gdb_assert (!sparc_structure_or_union_p (type
));
1401 gdb_assert (!(sparc_floating_p (type
) && len
== 16));
1402 gdb_assert (len
<= 8);
1404 if (sparc_floating_p (type
) || sparc_complex_floating_p (type
))
1406 /* Floating return values. */
1407 memcpy (buf
, valbuf
, len
);
1408 regcache_cooked_write (regcache
, SPARC_F0_REGNUM
, buf
);
1410 regcache_cooked_write (regcache
, SPARC_F1_REGNUM
, buf
+ 4);
1413 regcache_cooked_write (regcache
, SPARC_F2_REGNUM
, buf
+ 8);
1414 regcache_cooked_write (regcache
, SPARC_F3_REGNUM
, buf
+ 12);
1418 regcache_cooked_write (regcache
, SPARC_F4_REGNUM
, buf
+ 16);
1419 regcache_cooked_write (regcache
, SPARC_F5_REGNUM
, buf
+ 20);
1420 regcache_cooked_write (regcache
, SPARC_F6_REGNUM
, buf
+ 24);
1421 regcache_cooked_write (regcache
, SPARC_F7_REGNUM
, buf
+ 28);
1426 /* Integral and pointer return values. */
1427 gdb_assert (sparc_integral_or_pointer_p (type
));
1431 gdb_assert (len
== 8);
1432 memcpy (buf
, valbuf
, 8);
1433 regcache_cooked_write (regcache
, SPARC_O1_REGNUM
, buf
+ 4);
1437 /* ??? Do we need to do any sign-extension here? */
1438 memcpy (buf
+ 4 - len
, valbuf
, len
);
1440 regcache_cooked_write (regcache
, SPARC_O0_REGNUM
, buf
);
1444 static enum return_value_convention
1445 sparc32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
1446 struct type
*type
, struct regcache
*regcache
,
1447 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1449 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1451 /* The psABI says that "...every stack frame reserves the word at
1452 %fp+64. If a function returns a structure, union, or
1453 quad-precision value, this word should hold the address of the
1454 object into which the return value should be copied." This
1455 guarantees that we can always find the return value, not just
1456 before the function returns. */
1458 if (sparc_structure_or_union_p (type
)
1459 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16))
1466 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1467 addr
= read_memory_unsigned_integer (sp
+ 64, 4, byte_order
);
1468 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
1472 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
1473 addr
= read_memory_unsigned_integer (sp
+ 64, 4, byte_order
);
1474 write_memory (addr
, writebuf
, TYPE_LENGTH (type
));
1477 return RETURN_VALUE_ABI_PRESERVES_ADDRESS
;
1481 sparc32_extract_return_value (type
, regcache
, readbuf
);
1483 sparc32_store_return_value (type
, regcache
, writebuf
);
1485 return RETURN_VALUE_REGISTER_CONVENTION
;
1489 sparc32_stabs_argument_has_addr (struct gdbarch
*gdbarch
, struct type
*type
)
1491 return (sparc_structure_or_union_p (type
)
1492 || (sparc_floating_p (type
) && TYPE_LENGTH (type
) == 16)
1493 || sparc_complex_floating_p (type
));
1497 sparc32_dwarf2_struct_return_p (struct frame_info
*this_frame
)
1499 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1500 struct symbol
*sym
= find_pc_function (pc
);
1503 return sparc32_struct_return_from_sym (sym
);
1508 sparc32_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1509 struct dwarf2_frame_state_reg
*reg
,
1510 struct frame_info
*this_frame
)
1516 case SPARC_G0_REGNUM
:
1517 /* Since %g0 is always zero, there is no point in saving it, and
1518 people will be inclined omit it from the CFI. Make sure we
1519 don't warn about that. */
1520 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1522 case SPARC_SP_REGNUM
:
1523 reg
->how
= DWARF2_FRAME_REG_CFA
;
1525 case SPARC32_PC_REGNUM
:
1526 case SPARC32_NPC_REGNUM
:
1527 reg
->how
= DWARF2_FRAME_REG_RA_OFFSET
;
1529 if (sparc32_dwarf2_struct_return_p (this_frame
))
1531 if (regnum
== SPARC32_NPC_REGNUM
)
1533 reg
->loc
.offset
= off
;
1539 /* The SPARC Architecture doesn't have hardware single-step support,
1540 and most operating systems don't implement it either, so we provide
1541 software single-step mechanism. */
1544 sparc_analyze_control_transfer (struct regcache
*regcache
,
1545 CORE_ADDR pc
, CORE_ADDR
*npc
)
1547 unsigned long insn
= sparc_fetch_instruction (pc
);
1548 int conditional_p
= X_COND (insn
) & 0x7;
1549 int branch_p
= 0, fused_p
= 0;
1550 long offset
= 0; /* Must be signed for sign-extend. */
1552 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 3)
1554 if ((insn
& 0x10000000) == 0)
1556 /* Branch on Integer Register with Prediction (BPr). */
1562 /* Compare and Branch */
1565 offset
= 4 * X_DISP10 (insn
);
1568 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 6)
1570 /* Branch on Floating-Point Condition Codes (FBfcc). */
1572 offset
= 4 * X_DISP22 (insn
);
1574 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 5)
1576 /* Branch on Floating-Point Condition Codes with Prediction
1579 offset
= 4 * X_DISP19 (insn
);
1581 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 2)
1583 /* Branch on Integer Condition Codes (Bicc). */
1585 offset
= 4 * X_DISP22 (insn
);
1587 else if (X_OP (insn
) == 0 && X_OP2 (insn
) == 1)
1589 /* Branch on Integer Condition Codes with Prediction (BPcc). */
1591 offset
= 4 * X_DISP19 (insn
);
1593 else if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3a)
1595 struct frame_info
*frame
= get_current_frame ();
1597 /* Trap instruction (TRAP). */
1598 return gdbarch_tdep (get_regcache_arch (regcache
))->step_trap (frame
,
1602 /* FIXME: Handle DONE and RETRY instructions. */
1608 /* Fused compare-and-branch instructions are non-delayed,
1609 and do not have an annuling capability. So we need to
1610 always set a breakpoint on both the NPC and the branch
1612 gdb_assert (offset
!= 0);
1615 else if (conditional_p
)
1617 /* For conditional branches, return nPC + 4 iff the annul
1619 return (X_A (insn
) ? *npc
+ 4 : 0);
1623 /* For unconditional branches, return the target if its
1624 specified condition is "always" and return nPC + 4 if the
1625 condition is "never". If the annul bit is 1, set *NPC to
1627 if (X_COND (insn
) == 0x0)
1628 pc
= *npc
, offset
= 4;
1640 sparc_step_trap (struct frame_info
*frame
, unsigned long insn
)
1645 static VEC (CORE_ADDR
) *
1646 sparc_software_single_step (struct regcache
*regcache
)
1648 struct gdbarch
*arch
= get_regcache_arch (regcache
);
1649 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
1650 CORE_ADDR npc
, nnpc
;
1652 CORE_ADDR pc
, orig_npc
;
1653 VEC (CORE_ADDR
) *next_pcs
= NULL
;
1655 pc
= regcache_raw_get_unsigned (regcache
, tdep
->pc_regnum
);
1656 orig_npc
= npc
= regcache_raw_get_unsigned (regcache
, tdep
->npc_regnum
);
1658 /* Analyze the instruction at PC. */
1659 nnpc
= sparc_analyze_control_transfer (regcache
, pc
, &npc
);
1661 VEC_safe_push (CORE_ADDR
, next_pcs
, npc
);
1664 VEC_safe_push (CORE_ADDR
, next_pcs
, nnpc
);
1666 /* Assert that we have set at least one breakpoint, and that
1667 they're not set at the same spot - unless we're going
1668 from here straight to NULL, i.e. a call or jump to 0. */
1669 gdb_assert (npc
!= 0 || nnpc
!= 0 || orig_npc
== 0);
1670 gdb_assert (nnpc
!= npc
|| orig_npc
== 0);
1676 sparc_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1678 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_regcache_arch (regcache
));
1680 regcache_cooked_write_unsigned (regcache
, tdep
->pc_regnum
, pc
);
1681 regcache_cooked_write_unsigned (regcache
, tdep
->npc_regnum
, pc
+ 4);
1685 /* Iterate over core file register note sections. */
1688 sparc_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
1689 iterate_over_regset_sections_cb
*cb
,
1691 const struct regcache
*regcache
)
1693 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1695 cb (".reg", tdep
->sizeof_gregset
, tdep
->gregset
, NULL
, cb_data
);
1696 cb (".reg2", tdep
->sizeof_fpregset
, tdep
->fpregset
, NULL
, cb_data
);
1701 validate_tdesc_registers (const struct target_desc
*tdesc
,
1702 struct tdesc_arch_data
*tdesc_data
,
1703 const char *feature_name
,
1704 const char *register_names
[],
1705 unsigned int registers_num
,
1706 unsigned int reg_start
)
1709 const struct tdesc_feature
*feature
;
1711 feature
= tdesc_find_feature (tdesc
, feature_name
);
1712 if (feature
== NULL
)
1715 for (unsigned int i
= 0; i
< registers_num
; i
++)
1716 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
1723 static struct gdbarch
*
1724 sparc32_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1726 struct gdbarch_tdep
*tdep
;
1727 const struct target_desc
*tdesc
= info
.target_desc
;
1728 struct gdbarch
*gdbarch
;
1731 /* If there is already a candidate, use it. */
1732 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1734 return arches
->gdbarch
;
1736 /* Allocate space for the new architecture. */
1737 tdep
= XCNEW (struct gdbarch_tdep
);
1738 gdbarch
= gdbarch_alloc (&info
, tdep
);
1740 tdep
->pc_regnum
= SPARC32_PC_REGNUM
;
1741 tdep
->npc_regnum
= SPARC32_NPC_REGNUM
;
1742 tdep
->step_trap
= sparc_step_trap
;
1743 tdep
->fpu_register_names
= sparc32_fpu_register_names
;
1744 tdep
->fpu_registers_num
= ARRAY_SIZE (sparc32_fpu_register_names
);
1745 tdep
->cp0_register_names
= sparc32_cp0_register_names
;
1746 tdep
->cp0_registers_num
= ARRAY_SIZE (sparc32_cp0_register_names
);
1748 set_gdbarch_long_double_bit (gdbarch
, 128);
1749 set_gdbarch_long_double_format (gdbarch
, floatformats_sparc_quad
);
1751 set_gdbarch_num_regs (gdbarch
, SPARC32_NUM_REGS
);
1752 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
1753 set_gdbarch_register_type (gdbarch
, sparc32_register_type
);
1754 set_gdbarch_num_pseudo_regs (gdbarch
, SPARC32_NUM_PSEUDO_REGS
);
1755 set_tdesc_pseudo_register_name (gdbarch
, sparc32_pseudo_register_name
);
1756 set_tdesc_pseudo_register_type (gdbarch
, sparc32_pseudo_register_type
);
1757 set_gdbarch_pseudo_register_read (gdbarch
, sparc32_pseudo_register_read
);
1758 set_gdbarch_pseudo_register_write (gdbarch
, sparc32_pseudo_register_write
);
1760 /* Register numbers of various important registers. */
1761 set_gdbarch_sp_regnum (gdbarch
, SPARC_SP_REGNUM
); /* %sp */
1762 set_gdbarch_pc_regnum (gdbarch
, SPARC32_PC_REGNUM
); /* %pc */
1763 set_gdbarch_fp0_regnum (gdbarch
, SPARC_F0_REGNUM
); /* %f0 */
1765 /* Call dummy code. */
1766 set_gdbarch_frame_align (gdbarch
, sparc32_frame_align
);
1767 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
1768 set_gdbarch_push_dummy_code (gdbarch
, sparc32_push_dummy_code
);
1769 set_gdbarch_push_dummy_call (gdbarch
, sparc32_push_dummy_call
);
1771 set_gdbarch_return_value (gdbarch
, sparc32_return_value
);
1772 set_gdbarch_stabs_argument_has_addr
1773 (gdbarch
, sparc32_stabs_argument_has_addr
);
1775 set_gdbarch_skip_prologue (gdbarch
, sparc32_skip_prologue
);
1777 /* Stack grows downward. */
1778 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1780 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
1781 sparc_breakpoint::kind_from_pc
);
1782 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
1783 sparc_breakpoint::bp_from_kind
);
1785 set_gdbarch_frame_args_skip (gdbarch
, 8);
1787 set_gdbarch_print_insn (gdbarch
, print_insn_sparc
);
1789 set_gdbarch_software_single_step (gdbarch
, sparc_software_single_step
);
1790 set_gdbarch_write_pc (gdbarch
, sparc_write_pc
);
1792 set_gdbarch_dummy_id (gdbarch
, sparc_dummy_id
);
1794 set_gdbarch_unwind_pc (gdbarch
, sparc_unwind_pc
);
1796 frame_base_set_default (gdbarch
, &sparc32_frame_base
);
1798 /* Hook in the DWARF CFI frame unwinder. */
1799 dwarf2_frame_set_init_reg (gdbarch
, sparc32_dwarf2_frame_init_reg
);
1800 /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1801 StackGhost issues have been resolved. */
1803 /* Hook in ABI-specific overrides, if they have been registered. */
1804 gdbarch_init_osabi (info
, gdbarch
);
1806 frame_unwind_append_unwinder (gdbarch
, &sparc32_frame_unwind
);
1808 if (tdesc_has_registers (tdesc
))
1810 struct tdesc_arch_data
*tdesc_data
= tdesc_data_alloc ();
1812 /* Validate that the descriptor provides the mandatory registers
1813 and allocate their numbers. */
1814 valid_p
&= validate_tdesc_registers (tdesc
, tdesc_data
,
1815 "org.gnu.gdb.sparc.cpu",
1816 sparc_core_register_names
,
1817 ARRAY_SIZE (sparc_core_register_names
),
1819 valid_p
&= validate_tdesc_registers (tdesc
, tdesc_data
,
1820 "org.gnu.gdb.sparc.fpu",
1821 tdep
->fpu_register_names
,
1822 tdep
->fpu_registers_num
,
1824 valid_p
&= validate_tdesc_registers (tdesc
, tdesc_data
,
1825 "org.gnu.gdb.sparc.cp0",
1826 tdep
->cp0_register_names
,
1827 tdep
->cp0_registers_num
,
1829 tdep
->fpu_registers_num
);
1832 tdesc_data_cleanup (tdesc_data
);
1836 /* Target description may have changed. */
1837 info
.tdep_info
= tdesc_data
;
1838 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
1841 /* If we have register sets, enable the generic core file support. */
1843 set_gdbarch_iterate_over_regset_sections
1844 (gdbarch
, sparc_iterate_over_regset_sections
);
1846 register_sparc_ravenscar_ops (gdbarch
);
1851 /* Helper functions for dealing with register windows. */
1854 sparc_supply_rwindow (struct regcache
*regcache
, CORE_ADDR sp
, int regnum
)
1856 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1857 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1864 /* Registers are 64-bit. */
1867 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1869 if (regnum
== i
|| regnum
== -1)
1871 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1873 /* Handle StackGhost. */
1874 if (i
== SPARC_I7_REGNUM
)
1876 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1879 i7
= extract_unsigned_integer (buf
+ offset
, 8, byte_order
);
1880 store_unsigned_integer (buf
+ offset
, 8, byte_order
,
1884 regcache_raw_supply (regcache
, i
, buf
);
1890 /* Registers are 32-bit. Toss any sign-extension of the stack
1894 /* Clear out the top half of the temporary buffer, and put the
1895 register value in the bottom half if we're in 64-bit mode. */
1896 if (gdbarch_ptr_bit (get_regcache_arch (regcache
)) == 64)
1902 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1904 if (regnum
== i
|| regnum
== -1)
1906 target_read_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
1909 /* Handle StackGhost. */
1910 if (i
== SPARC_I7_REGNUM
)
1912 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1915 i7
= extract_unsigned_integer (buf
+ offset
, 4, byte_order
);
1916 store_unsigned_integer (buf
+ offset
, 4, byte_order
,
1920 regcache_raw_supply (regcache
, i
, buf
);
1927 sparc_collect_rwindow (const struct regcache
*regcache
,
1928 CORE_ADDR sp
, int regnum
)
1930 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1931 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1938 /* Registers are 64-bit. */
1941 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1943 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
1945 regcache_raw_collect (regcache
, i
, buf
);
1947 /* Handle StackGhost. */
1948 if (i
== SPARC_I7_REGNUM
)
1950 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1953 i7
= extract_unsigned_integer (buf
+ offset
, 8, byte_order
);
1954 store_unsigned_integer (buf
, 8, byte_order
, i7
^ wcookie
);
1957 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 8), buf
, 8);
1963 /* Registers are 32-bit. Toss any sign-extension of the stack
1967 /* Only use the bottom half if we're in 64-bit mode. */
1968 if (gdbarch_ptr_bit (get_regcache_arch (regcache
)) == 64)
1971 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
1973 if (regnum
== -1 || regnum
== SPARC_SP_REGNUM
|| regnum
== i
)
1975 regcache_raw_collect (regcache
, i
, buf
);
1977 /* Handle StackGhost. */
1978 if (i
== SPARC_I7_REGNUM
)
1980 ULONGEST wcookie
= sparc_fetch_wcookie (gdbarch
);
1983 i7
= extract_unsigned_integer (buf
+ offset
, 4, byte_order
);
1984 store_unsigned_integer (buf
+ offset
, 4, byte_order
,
1988 target_write_memory (sp
+ ((i
- SPARC_L0_REGNUM
) * 4),
1995 /* Helper functions for dealing with register sets. */
1998 sparc32_supply_gregset (const struct sparc_gregmap
*gregmap
,
1999 struct regcache
*regcache
,
2000 int regnum
, const void *gregs
)
2002 const gdb_byte
*regs
= (const gdb_byte
*) gregs
;
2003 gdb_byte zero
[4] = { 0 };
2006 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
2007 regcache_raw_supply (regcache
, SPARC32_PSR_REGNUM
,
2008 regs
+ gregmap
->r_psr_offset
);
2010 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
2011 regcache_raw_supply (regcache
, SPARC32_PC_REGNUM
,
2012 regs
+ gregmap
->r_pc_offset
);
2014 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
2015 regcache_raw_supply (regcache
, SPARC32_NPC_REGNUM
,
2016 regs
+ gregmap
->r_npc_offset
);
2018 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
2019 regcache_raw_supply (regcache
, SPARC32_Y_REGNUM
,
2020 regs
+ gregmap
->r_y_offset
);
2022 if (regnum
== SPARC_G0_REGNUM
|| regnum
== -1)
2023 regcache_raw_supply (regcache
, SPARC_G0_REGNUM
, &zero
);
2025 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
2027 int offset
= gregmap
->r_g1_offset
;
2029 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
2031 if (regnum
== i
|| regnum
== -1)
2032 regcache_raw_supply (regcache
, i
, regs
+ offset
);
2037 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
2039 /* Not all of the register set variants include Locals and
2040 Inputs. For those that don't, we read them off the stack. */
2041 if (gregmap
->r_l0_offset
== -1)
2045 regcache_cooked_read_unsigned (regcache
, SPARC_SP_REGNUM
, &sp
);
2046 sparc_supply_rwindow (regcache
, sp
, regnum
);
2050 int offset
= gregmap
->r_l0_offset
;
2052 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
2054 if (regnum
== i
|| regnum
== -1)
2055 regcache_raw_supply (regcache
, i
, regs
+ offset
);
2063 sparc32_collect_gregset (const struct sparc_gregmap
*gregmap
,
2064 const struct regcache
*regcache
,
2065 int regnum
, void *gregs
)
2067 gdb_byte
*regs
= (gdb_byte
*) gregs
;
2070 if (regnum
== SPARC32_PSR_REGNUM
|| regnum
== -1)
2071 regcache_raw_collect (regcache
, SPARC32_PSR_REGNUM
,
2072 regs
+ gregmap
->r_psr_offset
);
2074 if (regnum
== SPARC32_PC_REGNUM
|| regnum
== -1)
2075 regcache_raw_collect (regcache
, SPARC32_PC_REGNUM
,
2076 regs
+ gregmap
->r_pc_offset
);
2078 if (regnum
== SPARC32_NPC_REGNUM
|| regnum
== -1)
2079 regcache_raw_collect (regcache
, SPARC32_NPC_REGNUM
,
2080 regs
+ gregmap
->r_npc_offset
);
2082 if (regnum
== SPARC32_Y_REGNUM
|| regnum
== -1)
2083 regcache_raw_collect (regcache
, SPARC32_Y_REGNUM
,
2084 regs
+ gregmap
->r_y_offset
);
2086 if ((regnum
>= SPARC_G1_REGNUM
&& regnum
<= SPARC_O7_REGNUM
) || regnum
== -1)
2088 int offset
= gregmap
->r_g1_offset
;
2090 /* %g0 is always zero. */
2091 for (i
= SPARC_G1_REGNUM
; i
<= SPARC_O7_REGNUM
; i
++)
2093 if (regnum
== i
|| regnum
== -1)
2094 regcache_raw_collect (regcache
, i
, regs
+ offset
);
2099 if ((regnum
>= SPARC_L0_REGNUM
&& regnum
<= SPARC_I7_REGNUM
) || regnum
== -1)
2101 /* Not all of the register set variants include Locals and
2102 Inputs. For those that don't, we read them off the stack. */
2103 if (gregmap
->r_l0_offset
!= -1)
2105 int offset
= gregmap
->r_l0_offset
;
2107 for (i
= SPARC_L0_REGNUM
; i
<= SPARC_I7_REGNUM
; i
++)
2109 if (regnum
== i
|| regnum
== -1)
2110 regcache_raw_collect (regcache
, i
, regs
+ offset
);
2118 sparc32_supply_fpregset (const struct sparc_fpregmap
*fpregmap
,
2119 struct regcache
*regcache
,
2120 int regnum
, const void *fpregs
)
2122 const gdb_byte
*regs
= (const gdb_byte
*) fpregs
;
2125 for (i
= 0; i
< 32; i
++)
2127 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
2128 regcache_raw_supply (regcache
, SPARC_F0_REGNUM
+ i
,
2129 regs
+ fpregmap
->r_f0_offset
+ (i
* 4));
2132 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
2133 regcache_raw_supply (regcache
, SPARC32_FSR_REGNUM
,
2134 regs
+ fpregmap
->r_fsr_offset
);
2138 sparc32_collect_fpregset (const struct sparc_fpregmap
*fpregmap
,
2139 const struct regcache
*regcache
,
2140 int regnum
, void *fpregs
)
2142 gdb_byte
*regs
= (gdb_byte
*) fpregs
;
2145 for (i
= 0; i
< 32; i
++)
2147 if (regnum
== (SPARC_F0_REGNUM
+ i
) || regnum
== -1)
2148 regcache_raw_collect (regcache
, SPARC_F0_REGNUM
+ i
,
2149 regs
+ fpregmap
->r_f0_offset
+ (i
* 4));
2152 if (regnum
== SPARC32_FSR_REGNUM
|| regnum
== -1)
2153 regcache_raw_collect (regcache
, SPARC32_FSR_REGNUM
,
2154 regs
+ fpregmap
->r_fsr_offset
);
2160 /* From <machine/reg.h>. */
2161 const struct sparc_gregmap sparc32_sunos4_gregmap
=
2173 const struct sparc_fpregmap sparc32_sunos4_fpregmap
=
2179 const struct sparc_fpregmap sparc32_bsd_fpregmap
=
2186 /* Provide a prototype to silence -Wmissing-prototypes. */
2187 void _initialize_sparc_tdep (void);
2190 _initialize_sparc_tdep (void)
2192 register_gdbarch_init (bfd_arch_sparc
, sparc32_gdbarch_init
);