1 /* Target-dependent code for the SPARC for GDB, the GNU debugger.
2 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* ??? Support for calling functions from gdb in sparc64 is unfinished. */
25 #include "arch-utils.h"
32 #include "gdb_string.h"
35 #include <sys/procfs.h>
40 #include "symfile.h" /* for 'entry_point_address' */
43 * Some local macros that have multi-arch and non-multi-arch versions:
46 #if (GDB_MULTI_ARCH > 0)
48 /* Does the target have Floating Point registers? */
49 #define SPARC_HAS_FPU (gdbarch_tdep (current_gdbarch)->has_fpu)
50 /* Number of bytes devoted to Floating Point registers: */
51 #define FP_REGISTER_BYTES (gdbarch_tdep (current_gdbarch)->fp_register_bytes)
52 /* Highest numbered Floating Point register. */
53 #define FP_MAX_REGNUM (gdbarch_tdep (current_gdbarch)->fp_max_regnum)
54 /* Size of a general (integer) register: */
55 #define SPARC_INTREG_SIZE (gdbarch_tdep (current_gdbarch)->intreg_size)
56 /* Offset within the call dummy stack of the saved registers. */
57 #define DUMMY_REG_SAVE_OFFSET (gdbarch_tdep (current_gdbarch)->reg_save_offset)
59 #else /* non-multi-arch */
62 /* Does the target have Floating Point registers? */
63 #if defined(TARGET_SPARCLET) || defined(TARGET_SPARCLITE)
64 #define SPARC_HAS_FPU 0
66 #define SPARC_HAS_FPU 1
69 /* Number of bytes devoted to Floating Point registers: */
70 #if (GDB_TARGET_IS_SPARC64)
71 #define FP_REGISTER_BYTES (64 * 4)
74 #define FP_REGISTER_BYTES (32 * 4)
76 #define FP_REGISTER_BYTES 0
80 /* Highest numbered Floating Point register. */
81 #if (GDB_TARGET_IS_SPARC64)
82 #define FP_MAX_REGNUM (FP0_REGNUM + 48)
84 #define FP_MAX_REGNUM (FP0_REGNUM + 32)
87 /* Size of a general (integer) register: */
88 #define SPARC_INTREG_SIZE (REGISTER_RAW_SIZE (G0_REGNUM))
90 /* Offset within the call dummy stack of the saved registers. */
91 #if (GDB_TARGET_IS_SPARC64)
92 #define DUMMY_REG_SAVE_OFFSET (128 + 16)
94 #define DUMMY_REG_SAVE_OFFSET 0x60
97 #endif /* GDB_MULTI_ARCH */
102 int fp_register_bytes
;
107 int call_dummy_call_offset
;
111 /* Now make GDB_TARGET_IS_SPARC64 a runtime test. */
112 /* FIXME MVS: or try testing bfd_arch_info.arch and bfd_arch_info.mach ...
113 * define GDB_TARGET_IS_SPARC64 \
114 * (TARGET_ARCHITECTURE->arch == bfd_arch_sparc && \
115 * (TARGET_ARCHITECTURE->mach == bfd_mach_sparc_v9 || \
116 * TARGET_ARCHITECTURE->mach == bfd_mach_sparc_v9a))
120 extern int stop_after_trap
;
122 /* We don't store all registers immediately when requested, since they
123 get sent over in large chunks anyway. Instead, we accumulate most
124 of the changes and send them over once. "deferred_stores" keeps
125 track of which sets of registers we have locally-changed copies of,
126 so we only need send the groups that have changed. */
128 int deferred_stores
= 0; /* Accumulated stores we want to do eventually. */
131 /* Some machines, such as Fujitsu SPARClite 86x, have a bi-endian mode
132 where instructions are big-endian and data are little-endian.
133 This flag is set when we detect that the target is of this type. */
138 /* Fetch a single instruction. Even on bi-endian machines
139 such as sparc86x, instructions are always big-endian. */
142 fetch_instruction (pc
)
145 unsigned long retval
;
147 unsigned char buf
[4];
149 read_memory (pc
, buf
, sizeof (buf
));
151 /* Start at the most significant end of the integer, and work towards
152 the least significant. */
154 for (i
= 0; i
< sizeof (buf
); ++i
)
155 retval
= (retval
<< 8) | buf
[i
];
160 /* Branches with prediction are treated like their non-predicting cousins. */
161 /* FIXME: What about floating point branches? */
163 /* Macros to extract fields from sparc instructions. */
164 #define X_OP(i) (((i) >> 30) & 0x3)
165 #define X_RD(i) (((i) >> 25) & 0x1f)
166 #define X_A(i) (((i) >> 29) & 1)
167 #define X_COND(i) (((i) >> 25) & 0xf)
168 #define X_OP2(i) (((i) >> 22) & 0x7)
169 #define X_IMM22(i) ((i) & 0x3fffff)
170 #define X_OP3(i) (((i) >> 19) & 0x3f)
171 #define X_RS1(i) (((i) >> 14) & 0x1f)
172 #define X_I(i) (((i) >> 13) & 1)
173 #define X_IMM13(i) ((i) & 0x1fff)
174 /* Sign extension macros. */
175 #define X_SIMM13(i) ((X_IMM13 (i) ^ 0x1000) - 0x1000)
176 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
177 #define X_CC(i) (((i) >> 20) & 3)
178 #define X_P(i) (((i) >> 19) & 1)
179 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
180 #define X_RCOND(i) (((i) >> 25) & 7)
181 #define X_DISP16(i) ((((((i) >> 6) && 0xc000) | ((i) & 0x3fff)) ^ 0x8000) - 0x8000)
182 #define X_FCN(i) (((i) >> 25) & 31)
186 Error
, not_branch
, bicc
, bicca
, ba
, baa
, ticc
, ta
, done_retry
189 /* Simulate single-step ptrace call for sun4. Code written by Gary
190 Beihl (beihl@mcc.com). */
192 /* npc4 and next_pc describe the situation at the time that the
193 step-breakpoint was set, not necessary the current value of NPC_REGNUM. */
194 static CORE_ADDR next_pc
, npc4
, target
;
195 static int brknpc4
, brktrg
;
196 typedef char binsn_quantum
[BREAKPOINT_MAX
];
197 static binsn_quantum break_mem
[3];
199 static branch_type
isbranch (long, CORE_ADDR
, CORE_ADDR
*);
201 /* single_step() is called just before we want to resume the inferior,
202 if we want to single-step it but there is no hardware or kernel single-step
203 support (as on all SPARCs). We find all the possible targets of the
204 coming instruction and breakpoint them.
206 single_step is also called just after the inferior stops. If we had
207 set up a simulated single-step, we undo our damage. */
210 sparc_software_single_step (ignore
, insert_breakpoints_p
)
211 enum target_signal ignore
; /* pid, but we don't need it */
212 int insert_breakpoints_p
;
218 if (insert_breakpoints_p
)
220 /* Always set breakpoint for NPC. */
221 next_pc
= read_register (NPC_REGNUM
);
222 npc4
= next_pc
+ 4; /* branch not taken */
224 target_insert_breakpoint (next_pc
, break_mem
[0]);
225 /* printf_unfiltered ("set break at %x\n",next_pc); */
227 pc
= read_register (PC_REGNUM
);
228 pc_instruction
= fetch_instruction (pc
);
229 br
= isbranch (pc_instruction
, pc
, &target
);
230 brknpc4
= brktrg
= 0;
234 /* Conditional annulled branch will either end up at
235 npc (if taken) or at npc+4 (if not taken).
238 target_insert_breakpoint (npc4
, break_mem
[1]);
240 else if (br
== baa
&& target
!= next_pc
)
242 /* Unconditional annulled branch will always end up at
245 target_insert_breakpoint (target
, break_mem
[2]);
247 else if (GDB_TARGET_IS_SPARC64
&& br
== done_retry
)
250 target_insert_breakpoint (target
, break_mem
[2]);
255 /* Remove breakpoints */
256 target_remove_breakpoint (next_pc
, break_mem
[0]);
259 target_remove_breakpoint (npc4
, break_mem
[1]);
262 target_remove_breakpoint (target
, break_mem
[2]);
266 struct frame_extra_info
271 /* Following fields only relevant for flat frames. */
274 /* Add this to ->frame to get the value of the stack pointer at the
275 time of the register saves. */
279 /* Call this for each newly created frame. For SPARC, we need to
280 calculate the bottom of the frame, and do some extra work if the
281 prologue has been generated via the -mflat option to GCC. In
282 particular, we need to know where the previous fp and the pc have
283 been stashed, since their exact position within the frame may vary. */
286 sparc_init_extra_frame_info (fromleaf
, fi
)
288 struct frame_info
*fi
;
291 CORE_ADDR prologue_start
, prologue_end
;
294 fi
->extra_info
= (struct frame_extra_info
*)
295 frame_obstack_alloc (sizeof (struct frame_extra_info
));
296 frame_saved_regs_zalloc (fi
);
298 fi
->extra_info
->bottom
=
300 (fi
->frame
== fi
->next
->frame
? fi
->next
->extra_info
->bottom
:
301 fi
->next
->frame
) : read_sp ());
303 /* If fi->next is NULL, then we already set ->frame by passing read_fp()
304 to create_new_frame. */
309 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
311 /* Compute ->frame as if not flat. If it is flat, we'll change
313 if (fi
->next
->next
!= NULL
314 && (fi
->next
->next
->signal_handler_caller
315 || frame_in_dummy (fi
->next
->next
))
316 && frameless_look_for_prologue (fi
->next
))
318 /* A frameless function interrupted by a signal did not change
319 the frame pointer, fix up frame pointer accordingly. */
320 fi
->frame
= FRAME_FP (fi
->next
);
321 fi
->extra_info
->bottom
= fi
->next
->extra_info
->bottom
;
325 /* Should we adjust for stack bias here? */
326 get_saved_register (buf
, 0, 0, fi
, FP_REGNUM
, 0);
327 fi
->frame
= extract_address (buf
, REGISTER_RAW_SIZE (FP_REGNUM
));
329 if (GDB_TARGET_IS_SPARC64
&& (fi
->frame
& 1))
334 /* Decide whether this is a function with a ``flat register window''
335 frame. For such functions, the frame pointer is actually in %i7. */
336 fi
->extra_info
->flat
= 0;
337 fi
->extra_info
->in_prologue
= 0;
338 if (find_pc_partial_function (fi
->pc
, &name
, &prologue_start
, &prologue_end
))
340 /* See if the function starts with an add (which will be of a
341 negative number if a flat frame) to the sp. FIXME: Does not
342 handle large frames which will need more than one instruction
344 insn
= fetch_instruction (prologue_start
, 4);
345 if (X_OP (insn
) == 2 && X_RD (insn
) == 14 && X_OP3 (insn
) == 0
346 && X_I (insn
) && X_SIMM13 (insn
) < 0)
348 int offset
= X_SIMM13 (insn
);
350 /* Then look for a save of %i7 into the frame. */
351 insn
= fetch_instruction (prologue_start
+ 4);
355 && X_RS1 (insn
) == 14)
359 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
361 /* We definitely have a flat frame now. */
362 fi
->extra_info
->flat
= 1;
364 fi
->extra_info
->sp_offset
= offset
;
366 /* Overwrite the frame's address with the value in %i7. */
367 get_saved_register (buf
, 0, 0, fi
, I7_REGNUM
, 0);
368 fi
->frame
= extract_address (buf
, REGISTER_RAW_SIZE (I7_REGNUM
));
370 if (GDB_TARGET_IS_SPARC64
&& (fi
->frame
& 1))
373 /* Record where the fp got saved. */
374 fi
->extra_info
->fp_addr
=
375 fi
->frame
+ fi
->extra_info
->sp_offset
+ X_SIMM13 (insn
);
377 /* Also try to collect where the pc got saved to. */
378 fi
->extra_info
->pc_addr
= 0;
379 insn
= fetch_instruction (prologue_start
+ 12);
383 && X_RS1 (insn
) == 14)
384 fi
->extra_info
->pc_addr
=
385 fi
->frame
+ fi
->extra_info
->sp_offset
+ X_SIMM13 (insn
);
390 /* Check if the PC is in the function prologue before a SAVE
391 instruction has been executed yet. If so, set the frame
392 to the current value of the stack pointer and set
393 the in_prologue flag. */
395 struct symtab_and_line sal
;
397 sal
= find_pc_line (prologue_start
, 0);
398 if (sal
.line
== 0) /* no line info, use PC */
399 prologue_end
= fi
->pc
;
400 else if (sal
.end
< prologue_end
)
401 prologue_end
= sal
.end
;
402 if (fi
->pc
< prologue_end
)
404 for (addr
= prologue_start
; addr
< fi
->pc
; addr
+= 4)
406 insn
= read_memory_integer (addr
, 4);
407 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3c)
408 break; /* SAVE seen, stop searching */
412 fi
->extra_info
->in_prologue
= 1;
413 fi
->frame
= read_register (SP_REGNUM
);
418 if (fi
->next
&& fi
->frame
== 0)
420 /* Kludge to cause init_prev_frame_info to destroy the new frame. */
421 fi
->frame
= fi
->next
->frame
;
422 fi
->pc
= fi
->next
->pc
;
427 sparc_frame_chain (frame
)
428 struct frame_info
*frame
;
430 /* Value that will cause FRAME_CHAIN_VALID to not worry about the chain
431 value. If it realy is zero, we detect it later in
432 sparc_init_prev_frame. */
433 return (CORE_ADDR
) 1;
437 sparc_extract_struct_value_address (regbuf
)
440 return extract_address (regbuf
+ REGISTER_BYTE (O0_REGNUM
),
441 REGISTER_RAW_SIZE (O0_REGNUM
));
444 /* Find the pc saved in frame FRAME. */
447 sparc_frame_saved_pc (frame
)
448 struct frame_info
*frame
;
453 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
454 if (frame
->signal_handler_caller
)
456 /* This is the signal trampoline frame.
457 Get the saved PC from the sigcontext structure. */
459 #ifndef SIGCONTEXT_PC_OFFSET
460 #define SIGCONTEXT_PC_OFFSET 12
463 CORE_ADDR sigcontext_addr
;
465 int saved_pc_offset
= SIGCONTEXT_PC_OFFSET
;
468 scbuf
= alloca (TARGET_PTR_BIT
/ HOST_CHAR_BIT
);
470 /* Solaris2 ucbsigvechandler passes a pointer to a sigcontext
471 as the third parameter. The offset to the saved pc is 12. */
472 find_pc_partial_function (frame
->pc
, &name
,
473 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
474 if (name
&& STREQ (name
, "ucbsigvechandler"))
475 saved_pc_offset
= 12;
477 /* The sigcontext address is contained in register O2. */
478 get_saved_register (buf
, (int *) NULL
, (CORE_ADDR
*) NULL
,
479 frame
, O0_REGNUM
+ 2, (enum lval_type
*) NULL
);
480 sigcontext_addr
= extract_address (buf
, REGISTER_RAW_SIZE (O0_REGNUM
+ 2));
482 /* Don't cause a memory_error when accessing sigcontext in case the
483 stack layout has changed or the stack is corrupt. */
484 target_read_memory (sigcontext_addr
+ saved_pc_offset
,
485 scbuf
, sizeof (scbuf
));
486 return extract_address (scbuf
, sizeof (scbuf
));
488 else if (frame
->extra_info
->in_prologue
||
489 (frame
->next
!= NULL
&&
490 (frame
->next
->signal_handler_caller
||
491 frame_in_dummy (frame
->next
)) &&
492 frameless_look_for_prologue (frame
)))
494 /* A frameless function interrupted by a signal did not save
495 the PC, it is still in %o7. */
496 get_saved_register (buf
, (int *) NULL
, (CORE_ADDR
*) NULL
,
497 frame
, O7_REGNUM
, (enum lval_type
*) NULL
);
498 return PC_ADJUST (extract_address (buf
, SPARC_INTREG_SIZE
));
500 if (frame
->extra_info
->flat
)
501 addr
= frame
->extra_info
->pc_addr
;
503 addr
= frame
->extra_info
->bottom
+ FRAME_SAVED_I0
+
504 SPARC_INTREG_SIZE
* (I7_REGNUM
- I0_REGNUM
);
507 /* A flat frame leaf function might not save the PC anywhere,
508 just leave it in %o7. */
509 return PC_ADJUST (read_register (O7_REGNUM
));
511 read_memory (addr
, buf
, SPARC_INTREG_SIZE
);
512 return PC_ADJUST (extract_address (buf
, SPARC_INTREG_SIZE
));
515 /* Since an individual frame in the frame cache is defined by two
516 arguments (a frame pointer and a stack pointer), we need two
517 arguments to get info for an arbitrary stack frame. This routine
518 takes two arguments and makes the cached frames look as if these
519 two arguments defined a frame on the cache. This allows the rest
520 of info frame to extract the important arguments without
524 setup_arbitrary_frame (argc
, argv
)
528 struct frame_info
*frame
;
531 error ("Sparc frame specifications require two arguments: fp and sp");
533 frame
= create_new_frame (argv
[0], 0);
536 internal_error ("create_new_frame returned invalid frame");
538 frame
->extra_info
->bottom
= argv
[1];
539 frame
->pc
= FRAME_SAVED_PC (frame
);
543 /* Given a pc value, skip it forward past the function prologue by
544 disassembling instructions that appear to be a prologue.
546 If FRAMELESS_P is set, we are only testing to see if the function
547 is frameless. This allows a quicker answer.
549 This routine should be more specific in its actions; making sure
550 that it uses the same register in the initial prologue section. */
552 static CORE_ADDR
examine_prologue (CORE_ADDR
, int, struct frame_info
*,
556 examine_prologue (start_pc
, frameless_p
, fi
, saved_regs
)
559 struct frame_info
*fi
;
560 CORE_ADDR
*saved_regs
;
564 CORE_ADDR pc
= start_pc
;
567 insn
= fetch_instruction (pc
);
569 /* Recognize the `sethi' insn and record its destination. */
570 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 4)
574 insn
= fetch_instruction (pc
);
577 /* Recognize an add immediate value to register to either %g1 or
578 the destination register recorded above. Actually, this might
579 well recognize several different arithmetic operations.
580 It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1"
581 followed by "save %sp, %g1, %sp" is a valid prologue (Not that
582 I imagine any compiler really does that, however). */
585 && (X_RD (insn
) == 1 || X_RD (insn
) == dest
))
588 insn
= fetch_instruction (pc
);
591 /* Recognize any SAVE insn. */
592 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 60)
595 if (frameless_p
) /* If the save is all we care about, */
596 return pc
; /* return before doing more work */
597 insn
= fetch_instruction (pc
);
599 /* Recognize add to %sp. */
600 else if (X_OP (insn
) == 2 && X_RD (insn
) == 14 && X_OP3 (insn
) == 0)
603 if (frameless_p
) /* If the add is all we care about, */
604 return pc
; /* return before doing more work */
606 insn
= fetch_instruction (pc
);
607 /* Recognize store of frame pointer (i7). */
611 && X_RS1 (insn
) == 14)
614 insn
= fetch_instruction (pc
);
616 /* Recognize sub %sp, <anything>, %i7. */
619 && X_RS1 (insn
) == 14
620 && X_RD (insn
) == 31)
623 insn
= fetch_instruction (pc
);
632 /* Without a save or add instruction, it's not a prologue. */
637 /* Recognize stores into the frame from the input registers.
638 This recognizes all non alternate stores of an input register,
639 into a location offset from the frame pointer between
642 /* The above will fail for arguments that are promoted
643 (eg. shorts to ints or floats to doubles), because the compiler
644 will pass them in positive-offset frame space, but the prologue
645 will save them (after conversion) in negative frame space at an
646 unpredictable offset. Therefore I am going to remove the
647 restriction on the target-address of the save, on the theory
648 that any unbroken sequence of saves from input registers must
649 be part of the prologue. In un-optimized code (at least), I'm
650 fairly sure that the compiler would emit SOME other instruction
651 (eg. a move or add) before emitting another save that is actually
652 a part of the function body.
654 Besides, the reserved stack space is different for SPARC64 anyway.
659 && (X_OP3 (insn
) & 0x3c) == 4 /* Store, non-alternate. */
660 && (X_RD (insn
) & 0x18) == 0x18 /* Input register. */
661 && X_I (insn
) /* Immediate mode. */
662 && X_RS1 (insn
) == 30) /* Off of frame pointer. */
663 ; /* empty statement -- fall thru to end of loop */
664 else if (GDB_TARGET_IS_SPARC64
666 && (X_OP3 (insn
) & 0x3c) == 12 /* store, extended (64-bit) */
667 && (X_RD (insn
) & 0x18) == 0x18 /* input register */
668 && X_I (insn
) /* immediate mode */
669 && X_RS1 (insn
) == 30) /* off of frame pointer */
670 ; /* empty statement -- fall thru to end of loop */
671 else if (X_OP (insn
) == 3
672 && (X_OP3 (insn
) & 0x3c) == 36 /* store, floating-point */
673 && X_I (insn
) /* immediate mode */
674 && X_RS1 (insn
) == 30) /* off of frame pointer */
675 ; /* empty statement -- fall thru to end of loop */
678 && X_OP3 (insn
) == 4 /* store? */
679 && X_RS1 (insn
) == 14) /* off of frame pointer */
681 if (saved_regs
&& X_I (insn
))
682 saved_regs
[X_RD (insn
)] =
683 fi
->frame
+ fi
->extra_info
->sp_offset
+ X_SIMM13 (insn
);
688 insn
= fetch_instruction (pc
);
695 sparc_skip_prologue (start_pc
, frameless_p
)
699 return examine_prologue (start_pc
, frameless_p
, NULL
, NULL
);
702 /* Check instruction at ADDR to see if it is a branch.
703 All non-annulled instructions will go to NPC or will trap.
704 Set *TARGET if we find a candidate branch; set to zero if not.
706 This isn't static as it's used by remote-sa.sparc.c. */
709 isbranch (instruction
, addr
, target
)
711 CORE_ADDR addr
, *target
;
713 branch_type val
= not_branch
;
714 long int offset
= 0; /* Must be signed for sign-extend. */
718 if (X_OP (instruction
) == 0
719 && (X_OP2 (instruction
) == 2
720 || X_OP2 (instruction
) == 6
721 || X_OP2 (instruction
) == 1
722 || X_OP2 (instruction
) == 3
723 || X_OP2 (instruction
) == 5
724 || (GDB_TARGET_IS_SPARC64
&& X_OP2 (instruction
) == 7)))
726 if (X_COND (instruction
) == 8)
727 val
= X_A (instruction
) ? baa
: ba
;
729 val
= X_A (instruction
) ? bicca
: bicc
;
730 switch (X_OP2 (instruction
))
733 if (!GDB_TARGET_IS_SPARC64
)
738 offset
= 4 * X_DISP22 (instruction
);
742 offset
= 4 * X_DISP19 (instruction
);
745 offset
= 4 * X_DISP16 (instruction
);
748 *target
= addr
+ offset
;
750 else if (GDB_TARGET_IS_SPARC64
751 && X_OP (instruction
) == 2
752 && X_OP3 (instruction
) == 62)
754 if (X_FCN (instruction
) == 0)
757 *target
= read_register (TNPC_REGNUM
);
760 else if (X_FCN (instruction
) == 1)
763 *target
= read_register (TPC_REGNUM
);
771 /* Find register number REGNUM relative to FRAME and put its
772 (raw) contents in *RAW_BUFFER. Set *OPTIMIZED if the variable
773 was optimized out (and thus can't be fetched). If the variable
774 was fetched from memory, set *ADDRP to where it was fetched from,
775 otherwise it was fetched from a register.
777 The argument RAW_BUFFER must point to aligned memory. */
780 sparc_get_saved_register (raw_buffer
, optimized
, addrp
, frame
, regnum
, lval
)
784 struct frame_info
*frame
;
786 enum lval_type
*lval
;
788 struct frame_info
*frame1
;
791 if (!target_has_registers
)
792 error ("No registers.");
799 /* FIXME This code extracted from infcmd.c; should put elsewhere! */
802 /* error ("No selected frame."); */
803 if (!target_has_registers
)
804 error ("The program has no registers now.");
805 if (selected_frame
== NULL
)
806 error ("No selected frame.");
807 /* Try to use selected frame */
808 frame
= get_prev_frame (selected_frame
);
810 error ("Cmd not meaningful in the outermost frame.");
814 frame1
= frame
->next
;
816 /* Get saved PC from the frame info if not in innermost frame. */
817 if (regnum
== PC_REGNUM
&& frame1
!= NULL
)
821 if (raw_buffer
!= NULL
)
823 /* Put it back in target format. */
824 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), frame
->pc
);
831 while (frame1
!= NULL
)
833 /* FIXME MVS: wrong test for dummy frame at entry. */
835 if (frame1
->pc
>= (frame1
->extra_info
->bottom
?
836 frame1
->extra_info
->bottom
: read_sp ())
837 && frame1
->pc
<= FRAME_FP (frame1
))
839 /* Dummy frame. All but the window regs are in there somewhere.
840 The window registers are saved on the stack, just like in a
842 if (regnum
>= G1_REGNUM
&& regnum
< G1_REGNUM
+ 7)
843 addr
= frame1
->frame
+ (regnum
- G0_REGNUM
) * SPARC_INTREG_SIZE
844 - (FP_REGISTER_BYTES
+ 8 * SPARC_INTREG_SIZE
);
845 else if (regnum
>= I0_REGNUM
&& regnum
< I0_REGNUM
+ 8)
846 addr
= (frame1
->prev
->extra_info
->bottom
847 + (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
849 else if (regnum
>= L0_REGNUM
&& regnum
< L0_REGNUM
+ 8)
850 addr
= (frame1
->prev
->extra_info
->bottom
851 + (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
853 else if (regnum
>= O0_REGNUM
&& regnum
< O0_REGNUM
+ 8)
854 addr
= frame1
->frame
+ (regnum
- O0_REGNUM
) * SPARC_INTREG_SIZE
855 - (FP_REGISTER_BYTES
+ 16 * SPARC_INTREG_SIZE
);
856 else if (SPARC_HAS_FPU
&&
857 regnum
>= FP0_REGNUM
&& regnum
< FP0_REGNUM
+ 32)
858 addr
= frame1
->frame
+ (regnum
- FP0_REGNUM
) * 4
859 - (FP_REGISTER_BYTES
);
860 else if (GDB_TARGET_IS_SPARC64
&& SPARC_HAS_FPU
&&
861 regnum
>= FP0_REGNUM
+ 32 && regnum
< FP_MAX_REGNUM
)
862 addr
= frame1
->frame
+ 32 * 4 + (regnum
- FP0_REGNUM
- 32) * 8
863 - (FP_REGISTER_BYTES
);
864 else if (regnum
>= Y_REGNUM
&& regnum
< NUM_REGS
)
865 addr
= frame1
->frame
+ (regnum
- Y_REGNUM
) * SPARC_INTREG_SIZE
866 - (FP_REGISTER_BYTES
+ 24 * SPARC_INTREG_SIZE
);
868 else if (frame1
->extra_info
->flat
)
871 if (regnum
== RP_REGNUM
)
872 addr
= frame1
->extra_info
->pc_addr
;
873 else if (regnum
== I7_REGNUM
)
874 addr
= frame1
->extra_info
->fp_addr
;
877 CORE_ADDR func_start
;
880 regs
= alloca (NUM_REGS
* sizeof (CORE_ADDR
));
881 memset (regs
, 0, NUM_REGS
* sizeof (CORE_ADDR
));
883 find_pc_partial_function (frame1
->pc
, NULL
, &func_start
, NULL
);
884 examine_prologue (func_start
, 0, frame1
, regs
);
890 /* Normal frame. Local and In registers are saved on stack. */
891 if (regnum
>= I0_REGNUM
&& regnum
< I0_REGNUM
+ 8)
892 addr
= (frame1
->prev
->extra_info
->bottom
893 + (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
895 else if (regnum
>= L0_REGNUM
&& regnum
< L0_REGNUM
+ 8)
896 addr
= (frame1
->prev
->extra_info
->bottom
897 + (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
899 else if (regnum
>= O0_REGNUM
&& regnum
< O0_REGNUM
+ 8)
901 /* Outs become ins. */
902 get_saved_register (raw_buffer
, optimized
, addrp
, frame1
,
903 (regnum
- O0_REGNUM
+ I0_REGNUM
), lval
);
909 frame1
= frame1
->next
;
915 if (regnum
== SP_REGNUM
)
917 if (raw_buffer
!= NULL
)
919 /* Put it back in target format. */
920 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), addr
);
926 if (raw_buffer
!= NULL
)
927 read_memory (addr
, raw_buffer
, REGISTER_RAW_SIZE (regnum
));
932 *lval
= lval_register
;
933 addr
= REGISTER_BYTE (regnum
);
934 if (raw_buffer
!= NULL
)
935 read_register_gen (regnum
, raw_buffer
);
941 /* Push an empty stack frame, and record in it the current PC, regs, etc.
943 We save the non-windowed registers and the ins. The locals and outs
944 are new; they don't need to be saved. The i's and l's of
945 the last frame were already saved on the stack. */
947 /* Definitely see tm-sparc.h for more doc of the frame format here. */
949 /* See tm-sparc.h for how this is calculated. */
951 #define DUMMY_STACK_REG_BUF_SIZE \
952 (((8+8+8) * SPARC_INTREG_SIZE) + FP_REGISTER_BYTES)
953 #define DUMMY_STACK_SIZE \
954 (DUMMY_STACK_REG_BUF_SIZE + DUMMY_REG_SAVE_OFFSET)
957 sparc_push_dummy_frame ()
959 CORE_ADDR sp
, old_sp
;
962 register_temp
= alloca (DUMMY_STACK_SIZE
);
964 old_sp
= sp
= read_sp ();
966 if (GDB_TARGET_IS_SPARC64
)
968 /* PC, NPC, CCR, FSR, FPRS, Y, ASI */
969 read_register_bytes (REGISTER_BYTE (PC_REGNUM
), ®ister_temp
[0],
970 REGISTER_RAW_SIZE (PC_REGNUM
) * 7);
971 read_register_bytes (REGISTER_BYTE (PSTATE_REGNUM
),
972 ®ister_temp
[7 * SPARC_INTREG_SIZE
],
973 REGISTER_RAW_SIZE (PSTATE_REGNUM
));
974 /* FIXME: not sure what needs to be saved here. */
978 /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */
979 read_register_bytes (REGISTER_BYTE (Y_REGNUM
), ®ister_temp
[0],
980 REGISTER_RAW_SIZE (Y_REGNUM
) * 8);
983 read_register_bytes (REGISTER_BYTE (O0_REGNUM
),
984 ®ister_temp
[8 * SPARC_INTREG_SIZE
],
985 SPARC_INTREG_SIZE
* 8);
987 read_register_bytes (REGISTER_BYTE (G0_REGNUM
),
988 ®ister_temp
[16 * SPARC_INTREG_SIZE
],
989 SPARC_INTREG_SIZE
* 8);
992 read_register_bytes (REGISTER_BYTE (FP0_REGNUM
),
993 ®ister_temp
[24 * SPARC_INTREG_SIZE
],
996 sp
-= DUMMY_STACK_SIZE
;
1000 write_memory (sp
+ DUMMY_REG_SAVE_OFFSET
, ®ister_temp
[0],
1001 DUMMY_STACK_REG_BUF_SIZE
);
1003 if (strcmp (target_shortname
, "sim") != 0)
1007 /* Set return address register for the call dummy to the current PC. */
1008 write_register (I7_REGNUM
, read_pc () - 8);
1012 /* The call dummy will write this value to FP before executing
1013 the 'save'. This ensures that register window flushes work
1014 correctly in the simulator. */
1015 write_register (G0_REGNUM
+ 1, read_register (FP_REGNUM
));
1017 /* The call dummy will write this value to FP after executing
1019 write_register (G0_REGNUM
+ 2, old_sp
);
1021 /* The call dummy will write this value to the return address (%i7) after
1022 executing the 'save'. */
1023 write_register (G0_REGNUM
+ 3, read_pc () - 8);
1025 /* Set the FP that the call dummy will be using after the 'save'.
1026 This makes backtraces from an inferior function call work properly. */
1027 write_register (FP_REGNUM
, old_sp
);
1031 /* sparc_frame_find_saved_regs (). This function is here only because
1032 pop_frame uses it. Note there is an interesting corner case which
1033 I think few ports of GDB get right--if you are popping a frame
1034 which does not save some register that *is* saved by a more inner
1035 frame (such a frame will never be a dummy frame because dummy
1036 frames save all registers). Rewriting pop_frame to use
1037 get_saved_register would solve this problem and also get rid of the
1038 ugly duplication between sparc_frame_find_saved_regs and
1041 Stores, into an array of CORE_ADDR,
1042 the addresses of the saved registers of frame described by FRAME_INFO.
1043 This includes special registers such as pc and fp saved in special
1044 ways in the stack frame. sp is even more special:
1045 the address we return for it IS the sp for the next frame.
1047 Note that on register window machines, we are currently making the
1048 assumption that window registers are being saved somewhere in the
1049 frame in which they are being used. If they are stored in an
1050 inferior frame, find_saved_register will break.
1052 On the Sun 4, the only time all registers are saved is when
1053 a dummy frame is involved. Otherwise, the only saved registers
1054 are the LOCAL and IN registers which are saved as a result
1055 of the "save/restore" opcodes. This condition is determined
1056 by address rather than by value.
1058 The "pc" is not stored in a frame on the SPARC. (What is stored
1059 is a return address minus 8.) sparc_pop_frame knows how to
1060 deal with that. Other routines might or might not.
1062 See tm-sparc.h (PUSH_DUMMY_FRAME and friends) for CRITICAL information
1063 about how this works. */
1065 static void sparc_frame_find_saved_regs (struct frame_info
*, CORE_ADDR
*);
1068 sparc_frame_find_saved_regs (fi
, saved_regs_addr
)
1069 struct frame_info
*fi
;
1070 CORE_ADDR
*saved_regs_addr
;
1072 register int regnum
;
1073 CORE_ADDR frame_addr
= FRAME_FP (fi
);
1076 internal_error ("Bad frame info struct in FRAME_FIND_SAVED_REGS");
1078 memset (saved_regs_addr
, 0, NUM_REGS
* sizeof (CORE_ADDR
));
1080 if (fi
->pc
>= (fi
->extra_info
->bottom
?
1081 fi
->extra_info
->bottom
: read_sp ())
1082 && fi
->pc
<= FRAME_FP (fi
))
1084 /* Dummy frame. All but the window regs are in there somewhere. */
1085 for (regnum
= G1_REGNUM
; regnum
< G1_REGNUM
+ 7; regnum
++)
1086 saved_regs_addr
[regnum
] =
1087 frame_addr
+ (regnum
- G0_REGNUM
) * SPARC_INTREG_SIZE
1088 - DUMMY_STACK_REG_BUF_SIZE
+ 16 * SPARC_INTREG_SIZE
;
1090 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+ 8; regnum
++)
1091 saved_regs_addr
[regnum
] =
1092 frame_addr
+ (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
1093 - DUMMY_STACK_REG_BUF_SIZE
+ 8 * SPARC_INTREG_SIZE
;
1096 for (regnum
= FP0_REGNUM
; regnum
< FP_MAX_REGNUM
; regnum
++)
1097 saved_regs_addr
[regnum
] = frame_addr
+ (regnum
- FP0_REGNUM
) * 4
1098 - DUMMY_STACK_REG_BUF_SIZE
+ 24 * SPARC_INTREG_SIZE
;
1100 if (GDB_TARGET_IS_SPARC64
)
1102 for (regnum
= PC_REGNUM
; regnum
< PC_REGNUM
+ 7; regnum
++)
1104 saved_regs_addr
[regnum
] =
1105 frame_addr
+ (regnum
- PC_REGNUM
) * SPARC_INTREG_SIZE
1106 - DUMMY_STACK_REG_BUF_SIZE
;
1108 saved_regs_addr
[PSTATE_REGNUM
] =
1109 frame_addr
+ 8 * SPARC_INTREG_SIZE
- DUMMY_STACK_REG_BUF_SIZE
;
1112 for (regnum
= Y_REGNUM
; regnum
< NUM_REGS
; regnum
++)
1113 saved_regs_addr
[regnum
] =
1114 frame_addr
+ (regnum
- Y_REGNUM
) * SPARC_INTREG_SIZE
1115 - DUMMY_STACK_REG_BUF_SIZE
;
1117 frame_addr
= fi
->extra_info
->bottom
?
1118 fi
->extra_info
->bottom
: read_sp ();
1120 else if (fi
->extra_info
->flat
)
1122 CORE_ADDR func_start
;
1123 find_pc_partial_function (fi
->pc
, NULL
, &func_start
, NULL
);
1124 examine_prologue (func_start
, 0, fi
, saved_regs_addr
);
1126 /* Flat register window frame. */
1127 saved_regs_addr
[RP_REGNUM
] = fi
->extra_info
->pc_addr
;
1128 saved_regs_addr
[I7_REGNUM
] = fi
->extra_info
->fp_addr
;
1132 /* Normal frame. Just Local and In registers */
1133 frame_addr
= fi
->extra_info
->bottom
?
1134 fi
->extra_info
->bottom
: read_sp ();
1135 for (regnum
= L0_REGNUM
; regnum
< L0_REGNUM
+ 8; regnum
++)
1136 saved_regs_addr
[regnum
] =
1137 (frame_addr
+ (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
1139 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+ 8; regnum
++)
1140 saved_regs_addr
[regnum
] =
1141 (frame_addr
+ (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
1146 if (fi
->extra_info
->flat
)
1148 saved_regs_addr
[O7_REGNUM
] = fi
->extra_info
->pc_addr
;
1152 /* Pull off either the next frame pointer or the stack pointer */
1153 CORE_ADDR next_next_frame_addr
=
1154 (fi
->next
->extra_info
->bottom
?
1155 fi
->next
->extra_info
->bottom
: read_sp ());
1156 for (regnum
= O0_REGNUM
; regnum
< O0_REGNUM
+ 8; regnum
++)
1157 saved_regs_addr
[regnum
] =
1158 (next_next_frame_addr
1159 + (regnum
- O0_REGNUM
) * SPARC_INTREG_SIZE
1163 /* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */
1164 /* FIXME -- should this adjust for the sparc64 offset? */
1165 saved_regs_addr
[SP_REGNUM
] = FRAME_FP (fi
);
1168 /* Discard from the stack the innermost frame, restoring all saved registers.
1170 Note that the values stored in fsr by get_frame_saved_regs are *in
1171 the context of the called frame*. What this means is that the i
1172 regs of fsr must be restored into the o regs of the (calling) frame that
1173 we pop into. We don't care about the output regs of the calling frame,
1174 since unless it's a dummy frame, it won't have any output regs in it.
1176 We never have to bother with %l (local) regs, since the called routine's
1177 locals get tossed, and the calling routine's locals are already saved
1180 /* Definitely see tm-sparc.h for more doc of the frame format here. */
1185 register struct frame_info
*frame
= get_current_frame ();
1186 register CORE_ADDR pc
;
1191 fsr
= alloca (NUM_REGS
* sizeof (CORE_ADDR
));
1192 raw_buffer
= alloca (REGISTER_BYTES
);
1193 sparc_frame_find_saved_regs (frame
, &fsr
[0]);
1196 if (fsr
[FP0_REGNUM
])
1198 read_memory (fsr
[FP0_REGNUM
], raw_buffer
, FP_REGISTER_BYTES
);
1199 write_register_bytes (REGISTER_BYTE (FP0_REGNUM
),
1200 raw_buffer
, FP_REGISTER_BYTES
);
1202 if (!(GDB_TARGET_IS_SPARC64
))
1204 if (fsr
[FPS_REGNUM
])
1206 read_memory (fsr
[FPS_REGNUM
], raw_buffer
, SPARC_INTREG_SIZE
);
1207 write_register_gen (FPS_REGNUM
, raw_buffer
);
1209 if (fsr
[CPS_REGNUM
])
1211 read_memory (fsr
[CPS_REGNUM
], raw_buffer
, SPARC_INTREG_SIZE
);
1212 write_register_gen (CPS_REGNUM
, raw_buffer
);
1218 read_memory (fsr
[G1_REGNUM
], raw_buffer
, 7 * SPARC_INTREG_SIZE
);
1219 write_register_bytes (REGISTER_BYTE (G1_REGNUM
), raw_buffer
,
1220 7 * SPARC_INTREG_SIZE
);
1223 if (frame
->extra_info
->flat
)
1225 /* Each register might or might not have been saved, need to test
1227 for (regnum
= L0_REGNUM
; regnum
< L0_REGNUM
+ 8; ++regnum
)
1229 write_register (regnum
, read_memory_integer (fsr
[regnum
],
1230 SPARC_INTREG_SIZE
));
1231 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+ 8; ++regnum
)
1233 write_register (regnum
, read_memory_integer (fsr
[regnum
],
1234 SPARC_INTREG_SIZE
));
1236 /* Handle all outs except stack pointer (o0-o5; o7). */
1237 for (regnum
= O0_REGNUM
; regnum
< O0_REGNUM
+ 6; ++regnum
)
1239 write_register (regnum
, read_memory_integer (fsr
[regnum
],
1240 SPARC_INTREG_SIZE
));
1241 if (fsr
[O0_REGNUM
+ 7])
1242 write_register (O0_REGNUM
+ 7,
1243 read_memory_integer (fsr
[O0_REGNUM
+ 7],
1244 SPARC_INTREG_SIZE
));
1246 write_sp (frame
->frame
);
1248 else if (fsr
[I0_REGNUM
])
1254 reg_temp
= alloca (REGISTER_BYTES
);
1256 read_memory (fsr
[I0_REGNUM
], raw_buffer
, 8 * SPARC_INTREG_SIZE
);
1258 /* Get the ins and locals which we are about to restore. Just
1259 moving the stack pointer is all that is really needed, except
1260 store_inferior_registers is then going to write the ins and
1261 locals from the registers array, so we need to muck with the
1263 sp
= fsr
[SP_REGNUM
];
1265 if (GDB_TARGET_IS_SPARC64
&& (sp
& 1))
1268 read_memory (sp
, reg_temp
, SPARC_INTREG_SIZE
* 16);
1270 /* Restore the out registers.
1271 Among other things this writes the new stack pointer. */
1272 write_register_bytes (REGISTER_BYTE (O0_REGNUM
), raw_buffer
,
1273 SPARC_INTREG_SIZE
* 8);
1275 write_register_bytes (REGISTER_BYTE (L0_REGNUM
), reg_temp
,
1276 SPARC_INTREG_SIZE
* 16);
1279 if (!(GDB_TARGET_IS_SPARC64
))
1281 write_register (PS_REGNUM
,
1282 read_memory_integer (fsr
[PS_REGNUM
],
1283 REGISTER_RAW_SIZE (PS_REGNUM
)));
1286 write_register (Y_REGNUM
,
1287 read_memory_integer (fsr
[Y_REGNUM
],
1288 REGISTER_RAW_SIZE (Y_REGNUM
)));
1291 /* Explicitly specified PC (and maybe NPC) -- just restore them. */
1292 write_register (PC_REGNUM
,
1293 read_memory_integer (fsr
[PC_REGNUM
],
1294 REGISTER_RAW_SIZE (PC_REGNUM
)));
1295 if (fsr
[NPC_REGNUM
])
1296 write_register (NPC_REGNUM
,
1297 read_memory_integer (fsr
[NPC_REGNUM
],
1298 REGISTER_RAW_SIZE (NPC_REGNUM
)));
1300 else if (frame
->extra_info
->flat
)
1302 if (frame
->extra_info
->pc_addr
)
1303 pc
= PC_ADJUST ((CORE_ADDR
)
1304 read_memory_integer (frame
->extra_info
->pc_addr
,
1305 REGISTER_RAW_SIZE (PC_REGNUM
)));
1308 /* I think this happens only in the innermost frame, if so then
1309 it is a complicated way of saying
1310 "pc = read_register (O7_REGNUM);". */
1313 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
1314 get_saved_register (buf
, 0, 0, frame
, O7_REGNUM
, 0);
1315 pc
= PC_ADJUST (extract_address
1316 (buf
, REGISTER_RAW_SIZE (O7_REGNUM
)));
1319 write_register (PC_REGNUM
, pc
);
1320 write_register (NPC_REGNUM
, pc
+ 4);
1322 else if (fsr
[I7_REGNUM
])
1324 /* Return address in %i7 -- adjust it, then restore PC and NPC from it */
1325 pc
= PC_ADJUST ((CORE_ADDR
) read_memory_integer (fsr
[I7_REGNUM
],
1326 SPARC_INTREG_SIZE
));
1327 write_register (PC_REGNUM
, pc
);
1328 write_register (NPC_REGNUM
, pc
+ 4);
1330 flush_cached_frames ();
1333 /* On the Sun 4 under SunOS, the compile will leave a fake insn which
1334 encodes the structure size being returned. If we detect such
1335 a fake insn, step past it. */
1338 sparc_pc_adjust (pc
)
1345 err
= target_read_memory (pc
+ 8, buf
, 4);
1346 insn
= extract_unsigned_integer (buf
, 4);
1347 if ((err
== 0) && (insn
& 0xffc00000) == 0)
1353 /* If pc is in a shared library trampoline, return its target.
1354 The SunOs 4.x linker rewrites the jump table entries for PIC
1355 compiled modules in the main executable to bypass the dynamic linker
1356 with jumps of the form
1359 and removes the corresponding jump table relocation entry in the
1360 dynamic relocations.
1361 find_solib_trampoline_target relies on the presence of the jump
1362 table relocation entry, so we have to detect these jump instructions
1366 sunos4_skip_trampoline_code (pc
)
1369 unsigned long insn1
;
1373 err
= target_read_memory (pc
, buf
, 4);
1374 insn1
= extract_unsigned_integer (buf
, 4);
1375 if (err
== 0 && (insn1
& 0xffc00000) == 0x03000000)
1377 unsigned long insn2
;
1379 err
= target_read_memory (pc
+ 4, buf
, 4);
1380 insn2
= extract_unsigned_integer (buf
, 4);
1381 if (err
== 0 && (insn2
& 0xffffe000) == 0x81c06000)
1383 CORE_ADDR target_pc
= (insn1
& 0x3fffff) << 10;
1384 int delta
= insn2
& 0x1fff;
1386 /* Sign extend the displacement. */
1389 return target_pc
+ delta
;
1392 return find_solib_trampoline_target (pc
);
1395 #ifdef USE_PROC_FS /* Target dependent support for /proc */
1397 /* The /proc interface divides the target machine's register set up into
1398 two different sets, the general register set (gregset) and the floating
1399 point register set (fpregset). For each set, there is an ioctl to get
1400 the current register set and another ioctl to set the current values.
1402 The actual structure passed through the ioctl interface is, of course,
1403 naturally machine dependent, and is different for each set of registers.
1404 For the sparc for example, the general register set is typically defined
1407 typedef int gregset_t[38];
1413 and the floating point set by:
1415 typedef struct prfpregset {
1418 double pr_dregs[16];
1423 u_char pr_q_entrysize;
1428 These routines provide the packing and unpacking of gregset_t and
1429 fpregset_t formatted data.
1436 /* Given a pointer to a general register set in /proc format (gregset_t *),
1437 unpack the register contents and supply them as gdb's idea of the current
1441 supply_gregset (gregsetp
)
1442 prgregset_t
*gregsetp
;
1444 prgreg_t
*regp
= (prgreg_t
*) gregsetp
;
1445 int regi
, offset
= 0;
1447 /* If the host is 64-bit sparc, but the target is 32-bit sparc,
1448 then the gregset may contain 64-bit ints while supply_register
1449 is expecting 32-bit ints. Compensate. */
1450 if (sizeof (regp
[0]) == 8 && SPARC_INTREG_SIZE
== 4)
1453 /* GDB register numbers for Gn, On, Ln, In all match /proc reg numbers. */
1454 /* FIXME MVS: assumes the order of the first 32 elements... */
1455 for (regi
= G0_REGNUM
; regi
<= I7_REGNUM
; regi
++)
1457 supply_register (regi
, ((char *) (regp
+ regi
)) + offset
);
1460 /* These require a bit more care. */
1461 supply_register (PC_REGNUM
, ((char *) (regp
+ R_PC
)) + offset
);
1462 supply_register (NPC_REGNUM
, ((char *) (regp
+ R_nPC
)) + offset
);
1463 supply_register (Y_REGNUM
, ((char *) (regp
+ R_Y
)) + offset
);
1465 if (GDB_TARGET_IS_SPARC64
)
1468 supply_register (CCR_REGNUM
, ((char *) (regp
+ R_CCR
)) + offset
);
1470 supply_register (CCR_REGNUM
, NULL
);
1473 supply_register (FPRS_REGNUM
, ((char *) (regp
+ R_FPRS
)) + offset
);
1475 supply_register (FPRS_REGNUM
, NULL
);
1478 supply_register (ASI_REGNUM
, ((char *) (regp
+ R_ASI
)) + offset
);
1480 supply_register (ASI_REGNUM
, NULL
);
1486 supply_register (PS_REGNUM
, ((char *) (regp
+ R_PS
)) + offset
);
1488 supply_register (PS_REGNUM
, NULL
);
1491 /* For 64-bit hosts, R_WIM and R_TBR may not be defined.
1492 Steal R_ASI and R_FPRS, and hope for the best! */
1494 #if !defined (R_WIM) && defined (R_ASI)
1498 #if !defined (R_TBR) && defined (R_FPRS)
1499 #define R_TBR R_FPRS
1503 supply_register (WIM_REGNUM
, ((char *) (regp
+ R_WIM
)) + offset
);
1505 supply_register (WIM_REGNUM
, NULL
);
1509 supply_register (TBR_REGNUM
, ((char *) (regp
+ R_TBR
)) + offset
);
1511 supply_register (TBR_REGNUM
, NULL
);
1515 /* Fill inaccessible registers with zero. */
1516 if (GDB_TARGET_IS_SPARC64
)
1519 * don't know how to get value of any of the following:
1521 supply_register (VER_REGNUM
, NULL
);
1522 supply_register (TICK_REGNUM
, NULL
);
1523 supply_register (PIL_REGNUM
, NULL
);
1524 supply_register (PSTATE_REGNUM
, NULL
);
1525 supply_register (TSTATE_REGNUM
, NULL
);
1526 supply_register (TBA_REGNUM
, NULL
);
1527 supply_register (TL_REGNUM
, NULL
);
1528 supply_register (TT_REGNUM
, NULL
);
1529 supply_register (TPC_REGNUM
, NULL
);
1530 supply_register (TNPC_REGNUM
, NULL
);
1531 supply_register (WSTATE_REGNUM
, NULL
);
1532 supply_register (CWP_REGNUM
, NULL
);
1533 supply_register (CANSAVE_REGNUM
, NULL
);
1534 supply_register (CANRESTORE_REGNUM
, NULL
);
1535 supply_register (CLEANWIN_REGNUM
, NULL
);
1536 supply_register (OTHERWIN_REGNUM
, NULL
);
1537 supply_register (ASR16_REGNUM
, NULL
);
1538 supply_register (ASR17_REGNUM
, NULL
);
1539 supply_register (ASR18_REGNUM
, NULL
);
1540 supply_register (ASR19_REGNUM
, NULL
);
1541 supply_register (ASR20_REGNUM
, NULL
);
1542 supply_register (ASR21_REGNUM
, NULL
);
1543 supply_register (ASR22_REGNUM
, NULL
);
1544 supply_register (ASR23_REGNUM
, NULL
);
1545 supply_register (ASR24_REGNUM
, NULL
);
1546 supply_register (ASR25_REGNUM
, NULL
);
1547 supply_register (ASR26_REGNUM
, NULL
);
1548 supply_register (ASR27_REGNUM
, NULL
);
1549 supply_register (ASR28_REGNUM
, NULL
);
1550 supply_register (ASR29_REGNUM
, NULL
);
1551 supply_register (ASR30_REGNUM
, NULL
);
1552 supply_register (ASR31_REGNUM
, NULL
);
1553 supply_register (ICC_REGNUM
, NULL
);
1554 supply_register (XCC_REGNUM
, NULL
);
1558 supply_register (CPS_REGNUM
, NULL
);
1563 fill_gregset (gregsetp
, regno
)
1564 prgregset_t
*gregsetp
;
1567 prgreg_t
*regp
= (prgreg_t
*) gregsetp
;
1568 int regi
, offset
= 0;
1570 /* If the host is 64-bit sparc, but the target is 32-bit sparc,
1571 then the gregset may contain 64-bit ints while supply_register
1572 is expecting 32-bit ints. Compensate. */
1573 if (sizeof (regp
[0]) == 8 && SPARC_INTREG_SIZE
== 4)
1576 for (regi
= 0; regi
<= R_I7
; regi
++)
1577 if ((regno
== -1) || (regno
== regi
))
1578 read_register_gen (regi
, (char *) (regp
+ regi
) + offset
);
1580 if ((regno
== -1) || (regno
== PC_REGNUM
))
1581 read_register_gen (PC_REGNUM
, (char *) (regp
+ R_PC
) + offset
);
1583 if ((regno
== -1) || (regno
== NPC_REGNUM
))
1584 read_register_gen (NPC_REGNUM
, (char *) (regp
+ R_nPC
) + offset
);
1586 if ((regno
== -1) || (regno
== Y_REGNUM
))
1587 read_register_gen (Y_REGNUM
, (char *) (regp
+ R_Y
) + offset
);
1589 if (GDB_TARGET_IS_SPARC64
)
1592 if (regno
== -1 || regno
== CCR_REGNUM
)
1593 read_register_gen (CCR_REGNUM
, ((char *) (regp
+ R_CCR
)) + offset
);
1596 if (regno
== -1 || regno
== FPRS_REGNUM
)
1597 read_register_gen (FPRS_REGNUM
, ((char *) (regp
+ R_FPRS
)) + offset
);
1600 if (regno
== -1 || regno
== ASI_REGNUM
)
1601 read_register_gen (ASI_REGNUM
, ((char *) (regp
+ R_ASI
)) + offset
);
1607 if (regno
== -1 || regno
== PS_REGNUM
)
1608 read_register_gen (PS_REGNUM
, ((char *) (regp
+ R_PS
)) + offset
);
1611 /* For 64-bit hosts, R_WIM and R_TBR may not be defined.
1612 Steal R_ASI and R_FPRS, and hope for the best! */
1614 #if !defined (R_WIM) && defined (R_ASI)
1618 #if !defined (R_TBR) && defined (R_FPRS)
1619 #define R_TBR R_FPRS
1623 if (regno
== -1 || regno
== WIM_REGNUM
)
1624 read_register_gen (WIM_REGNUM
, ((char *) (regp
+ R_WIM
)) + offset
);
1626 if (regno
== -1 || regno
== WIM_REGNUM
)
1627 read_register_gen (WIM_REGNUM
, NULL
);
1631 if (regno
== -1 || regno
== TBR_REGNUM
)
1632 read_register_gen (TBR_REGNUM
, ((char *) (regp
+ R_TBR
)) + offset
);
1634 if (regno
== -1 || regno
== TBR_REGNUM
)
1635 read_register_gen (TBR_REGNUM
, NULL
);
1640 /* Given a pointer to a floating point register set in /proc format
1641 (fpregset_t *), unpack the register contents and supply them as gdb's
1642 idea of the current floating point register values. */
1645 supply_fpregset (fpregsetp
)
1646 prfpregset_t
*fpregsetp
;
1654 for (regi
= FP0_REGNUM
; regi
< FP_MAX_REGNUM
; regi
++)
1656 from
= (char *) &fpregsetp
->pr_fr
.pr_regs
[regi
- FP0_REGNUM
];
1657 supply_register (regi
, from
);
1660 if (GDB_TARGET_IS_SPARC64
)
1663 * don't know how to get value of the following.
1665 supply_register (FSR_REGNUM
, NULL
); /* zero it out for now */
1666 supply_register (FCC0_REGNUM
, NULL
);
1667 supply_register (FCC1_REGNUM
, NULL
); /* don't know how to get value */
1668 supply_register (FCC2_REGNUM
, NULL
); /* don't know how to get value */
1669 supply_register (FCC3_REGNUM
, NULL
); /* don't know how to get value */
1673 supply_register (FPS_REGNUM
, (char *) &(fpregsetp
->pr_fsr
));
1677 /* Given a pointer to a floating point register set in /proc format
1678 (fpregset_t *), update the register specified by REGNO from gdb's idea
1679 of the current floating point register set. If REGNO is -1, update
1681 /* This will probably need some changes for sparc64. */
1684 fill_fpregset (fpregsetp
, regno
)
1685 prfpregset_t
*fpregsetp
;
1695 for (regi
= FP0_REGNUM
; regi
< FP_MAX_REGNUM
; regi
++)
1697 if ((regno
== -1) || (regno
== regi
))
1699 from
= (char *) ®isters
[REGISTER_BYTE (regi
)];
1700 to
= (char *) &fpregsetp
->pr_fr
.pr_regs
[regi
- FP0_REGNUM
];
1701 memcpy (to
, from
, REGISTER_RAW_SIZE (regi
));
1705 if (!(GDB_TARGET_IS_SPARC64
)) /* FIXME: does Sparc64 have this register? */
1706 if ((regno
== -1) || (regno
== FPS_REGNUM
))
1708 from
= (char *)®isters
[REGISTER_BYTE (FPS_REGNUM
)];
1709 to
= (char *) &fpregsetp
->pr_fsr
;
1710 memcpy (to
, from
, REGISTER_RAW_SIZE (FPS_REGNUM
));
1714 #endif /* USE_PROC_FS */
1717 #ifdef GET_LONGJMP_TARGET
1719 /* Figure out where the longjmp will land. We expect that we have just entered
1720 longjmp and haven't yet setup the stack frame, so the args are still in the
1721 output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we
1722 extract the pc (JB_PC) that we will land at. The pc is copied into ADDR.
1723 This routine returns true on success */
1726 get_longjmp_target (pc
)
1730 #define LONGJMP_TARGET_SIZE 4
1731 char buf
[LONGJMP_TARGET_SIZE
];
1733 jb_addr
= read_register (O0_REGNUM
);
1735 if (target_read_memory (jb_addr
+ JB_PC
* JB_ELEMENT_SIZE
, buf
,
1736 LONGJMP_TARGET_SIZE
))
1739 *pc
= extract_address (buf
, LONGJMP_TARGET_SIZE
);
1743 #endif /* GET_LONGJMP_TARGET */
1745 #ifdef STATIC_TRANSFORM_NAME
1746 /* SunPRO (3.0 at least), encodes the static variables. This is not
1747 related to C++ mangling, it is done for C too. */
1750 sunpro_static_transform_name (name
)
1756 /* For file-local statics there will be a dollar sign, a bunch
1757 of junk (the contents of which match a string given in the
1758 N_OPT), a period and the name. For function-local statics
1759 there will be a bunch of junk (which seems to change the
1760 second character from 'A' to 'B'), a period, the name of the
1761 function, and the name. So just skip everything before the
1763 p
= strrchr (name
, '.');
1769 #endif /* STATIC_TRANSFORM_NAME */
1772 /* Utilities for printing registers.
1773 Page numbers refer to the SPARC Architecture Manual. */
1775 static void dump_ccreg (char *, int);
1778 dump_ccreg (reg
, val
)
1783 printf_unfiltered ("%s:%s,%s,%s,%s", reg
,
1784 val
& 8 ? "N" : "NN",
1785 val
& 4 ? "Z" : "NZ",
1786 val
& 2 ? "O" : "NO",
1787 val
& 1 ? "C" : "NC");
1798 return "ASI_NUCLEUS";
1800 return "ASI_NUCLEUS_LITTLE";
1802 return "ASI_AS_IF_USER_PRIMARY";
1804 return "ASI_AS_IF_USER_SECONDARY";
1806 return "ASI_AS_IF_USER_PRIMARY_LITTLE";
1808 return "ASI_AS_IF_USER_SECONDARY_LITTLE";
1810 return "ASI_PRIMARY";
1812 return "ASI_SECONDARY";
1814 return "ASI_PRIMARY_NOFAULT";
1816 return "ASI_SECONDARY_NOFAULT";
1818 return "ASI_PRIMARY_LITTLE";
1820 return "ASI_SECONDARY_LITTLE";
1822 return "ASI_PRIMARY_NOFAULT_LITTLE";
1824 return "ASI_SECONDARY_NOFAULT_LITTLE";
1830 /* PRINT_REGISTER_HOOK routine.
1831 Pretty print various registers. */
1832 /* FIXME: Would be nice if this did some fancy things for 32 bit sparc. */
1835 sparc_print_register_hook (regno
)
1840 /* Handle double/quad versions of lower 32 fp regs. */
1841 if (regno
>= FP0_REGNUM
&& regno
< FP0_REGNUM
+ 32
1842 && (regno
& 1) == 0)
1846 if (!read_relative_register_raw_bytes (regno
, value
)
1847 && !read_relative_register_raw_bytes (regno
+ 1, value
+ 4))
1849 printf_unfiltered ("\t");
1850 print_floating (value
, builtin_type_double
, gdb_stdout
);
1852 #if 0 /* FIXME: gdb doesn't handle long doubles */
1853 if ((regno
& 3) == 0)
1855 if (!read_relative_register_raw_bytes (regno
+ 2, value
+ 8)
1856 && !read_relative_register_raw_bytes (regno
+ 3, value
+ 12))
1858 printf_unfiltered ("\t");
1859 print_floating (value
, builtin_type_long_double
, gdb_stdout
);
1866 #if 0 /* FIXME: gdb doesn't handle long doubles */
1867 /* Print upper fp regs as long double if appropriate. */
1868 if (regno
>= FP0_REGNUM
+ 32 && regno
< FP_MAX_REGNUM
1869 /* We test for even numbered regs and not a multiple of 4 because
1870 the upper fp regs are recorded as doubles. */
1871 && (regno
& 1) == 0)
1875 if (!read_relative_register_raw_bytes (regno
, value
)
1876 && !read_relative_register_raw_bytes (regno
+ 1, value
+ 8))
1878 printf_unfiltered ("\t");
1879 print_floating (value
, builtin_type_long_double
, gdb_stdout
);
1885 /* FIXME: Some of these are priviledged registers.
1886 Not sure how they should be handled. */
1888 #define BITS(n, mask) ((int) (((val) >> (n)) & (mask)))
1890 val
= read_register (regno
);
1893 if (GDB_TARGET_IS_SPARC64
)
1897 printf_unfiltered ("\t");
1898 dump_ccreg ("xcc", val
>> 4);
1899 printf_unfiltered (", ");
1900 dump_ccreg ("icc", val
& 15);
1903 printf ("\tfef:%d, du:%d, dl:%d",
1904 BITS (2, 1), BITS (1, 1), BITS (0, 1));
1908 static char *fcc
[4] =
1909 {"=", "<", ">", "?"};
1910 static char *rd
[4] =
1911 {"N", "0", "+", "-"};
1912 /* Long, but I'd rather leave it as is and use a wide screen. */
1913 printf_filtered ("\t0:%s, 1:%s, 2:%s, 3:%s, rd:%s, tem:%d, ",
1914 fcc
[BITS (10, 3)], fcc
[BITS (32, 3)],
1915 fcc
[BITS (34, 3)], fcc
[BITS (36, 3)],
1916 rd
[BITS (30, 3)], BITS (23, 31));
1917 printf_filtered ("ns:%d, ver:%d, ftt:%d, qne:%d, aexc:%d, cexc:%d",
1918 BITS (22, 1), BITS (17, 7), BITS (14, 7),
1919 BITS (13, 1), BITS (5, 31), BITS (0, 31));
1924 char *asi
= decode_asi (val
);
1926 printf ("\t%s", asi
);
1930 printf ("\tmanuf:%d, impl:%d, mask:%d, maxtl:%d, maxwin:%d",
1931 BITS (48, 0xffff), BITS (32, 0xffff),
1932 BITS (24, 0xff), BITS (8, 0xff), BITS (0, 31));
1936 static char *mm
[4] =
1937 {"tso", "pso", "rso", "?"};
1938 printf_filtered ("\tcle:%d, tle:%d, mm:%s, red:%d, ",
1939 BITS (9, 1), BITS (8, 1),
1940 mm
[BITS (6, 3)], BITS (5, 1));
1941 printf_filtered ("pef:%d, am:%d, priv:%d, ie:%d, ag:%d",
1942 BITS (4, 1), BITS (3, 1), BITS (2, 1),
1943 BITS (1, 1), BITS (0, 1));
1947 /* FIXME: print all 4? */
1950 /* FIXME: print all 4? */
1953 /* FIXME: print all 4? */
1956 /* FIXME: print all 4? */
1959 printf ("\tother:%d, normal:%d", BITS (3, 7), BITS (0, 7));
1962 printf ("\t%d", BITS (0, 31));
1964 case CANSAVE_REGNUM
:
1965 printf ("\t%-2d before spill", BITS (0, 31));
1967 case CANRESTORE_REGNUM
:
1968 printf ("\t%-2d before fill", BITS (0, 31));
1970 case CLEANWIN_REGNUM
:
1971 printf ("\t%-2d before clean", BITS (0, 31));
1973 case OTHERWIN_REGNUM
:
1974 printf ("\t%d", BITS (0, 31));
1981 printf ("\ticc:%c%c%c%c, pil:%d, s:%d, ps:%d, et:%d, cwp:%d",
1982 BITS (23, 1) ? 'N' : '-', BITS (22, 1) ? 'Z' : '-',
1983 BITS (21, 1) ? 'V' : '-', BITS (20, 1) ? 'C' : '-',
1984 BITS (8, 15), BITS (7, 1), BITS (6, 1), BITS (5, 1),
1989 static char *fcc
[4] =
1990 {"=", "<", ">", "?"};
1991 static char *rd
[4] =
1992 {"N", "0", "+", "-"};
1993 /* Long, but I'd rather leave it as is and use a wide screen. */
1994 printf ("\trd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, "
1995 "fcc:%s, aexc:%d, cexc:%d",
1996 rd
[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7),
1997 BITS (14, 7), BITS (13, 1), fcc
[BITS (10, 3)], BITS (5, 31),
2007 gdb_print_insn_sparc (memaddr
, info
)
2009 disassemble_info
*info
;
2011 /* It's necessary to override mach again because print_insn messes it up. */
2012 info
->mach
= TARGET_ARCHITECTURE
->mach
;
2014 /* Selects sparc/sparclite/sparclet/sparc64 */
2015 tm_print_insn_info
.mach
= gdbarch_tdep (current_gdbarch
) -> print_insn_mach
;
2017 return print_insn_sparc (memaddr
, info
);
2020 /* The SPARC passes the arguments on the stack; arguments smaller
2021 than an int are promoted to an int. The first 6 words worth of
2022 args are also passed in registers o0 - o5. */
2025 sparc32_push_arguments (nargs
, args
, sp
, struct_return
, struct_addr
)
2030 CORE_ADDR struct_addr
;
2033 int accumulate_size
= 0;
2040 struct sparc_arg
*sparc_args
=
2041 (struct sparc_arg
*) alloca (nargs
* sizeof (struct sparc_arg
));
2042 struct sparc_arg
*m_arg
;
2044 /* Promote arguments if necessary, and calculate their stack offsets
2046 for (i
= 0, m_arg
= sparc_args
; i
< nargs
; i
++, m_arg
++)
2048 value_ptr arg
= args
[i
];
2049 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2050 /* Cast argument to long if necessary as the compiler does it too. */
2051 switch (TYPE_CODE (arg_type
))
2054 case TYPE_CODE_BOOL
:
2055 case TYPE_CODE_CHAR
:
2056 case TYPE_CODE_RANGE
:
2057 case TYPE_CODE_ENUM
:
2058 if (TYPE_LENGTH (arg_type
) < TYPE_LENGTH (builtin_type_long
))
2060 arg_type
= builtin_type_long
;
2061 arg
= value_cast (arg_type
, arg
);
2067 m_arg
->len
= TYPE_LENGTH (arg_type
);
2068 m_arg
->offset
= accumulate_size
;
2069 accumulate_size
= (accumulate_size
+ m_arg
->len
+ 3) & ~3;
2070 m_arg
->contents
= VALUE_CONTENTS (arg
);
2073 /* Make room for the arguments on the stack. */
2074 accumulate_size
+= CALL_DUMMY_STACK_ADJUST
;
2075 sp
= ((sp
- accumulate_size
) & ~7) + CALL_DUMMY_STACK_ADJUST
;
2077 /* `Push' arguments on the stack. */
2078 for (i
= 0, oregnum
= 0, m_arg
= sparc_args
;
2082 write_memory (sp
+ m_arg
->offset
, m_arg
->contents
, m_arg
->len
);
2084 j
< m_arg
->len
&& oregnum
< 6;
2085 j
+= SPARC_INTREG_SIZE
, oregnum
++)
2086 write_register_gen (O0_REGNUM
+ oregnum
, m_arg
->contents
+ j
);
2093 /* Extract from an array REGBUF containing the (raw) register state
2094 a function return value of type TYPE, and copy that, in virtual format,
2098 sparc32_extract_return_value (type
, regbuf
, valbuf
)
2103 int typelen
= TYPE_LENGTH (type
);
2104 int regsize
= REGISTER_RAW_SIZE (O0_REGNUM
);
2106 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2107 memcpy (valbuf
, ®buf
[REGISTER_BYTE (FP0_REGNUM
)], typelen
);
2110 ®buf
[O0_REGNUM
* regsize
+
2112 || TARGET_BYTE_ORDER
== LITTLE_ENDIAN
? 0
2113 : regsize
- typelen
)],
2118 /* Write into appropriate registers a function return value
2119 of type TYPE, given in virtual format. On SPARCs with FPUs,
2120 float values are returned in %f0 (and %f1). In all other cases,
2121 values are returned in register %o0. */
2124 sparc_store_return_value (type
, valbuf
)
2131 buffer
= alloca(MAX_REGISTER_RAW_SIZE
);
2133 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2134 /* Floating-point values are returned in the register pair */
2135 /* formed by %f0 and %f1 (doubles are, anyway). */
2138 /* Other values are returned in register %o0. */
2141 /* Add leading zeros to the value. */
2142 if (TYPE_LENGTH (type
) < REGISTER_RAW_SIZE (regno
))
2144 memset (buffer
, 0, REGISTER_RAW_SIZE (regno
));
2145 memcpy (buffer
+ REGISTER_RAW_SIZE (regno
) - TYPE_LENGTH (type
), valbuf
,
2146 TYPE_LENGTH (type
));
2147 write_register_gen (regno
, buffer
);
2150 write_register_bytes (REGISTER_BYTE (regno
), valbuf
, TYPE_LENGTH (type
));
2154 sparclet_store_return_value (struct type
*type
, char *valbuf
)
2156 /* Other values are returned in register %o0. */
2157 write_register_bytes (REGISTER_BYTE (O0_REGNUM
), valbuf
,
2158 TYPE_LENGTH (type
));
2162 #ifndef CALL_DUMMY_CALL_OFFSET
2163 #define CALL_DUMMY_CALL_OFFSET \
2164 (gdbarch_tdep (current_gdbarch)->call_dummy_call_offset)
2165 #endif /* CALL_DUMMY_CALL_OFFSET */
2167 /* Insert the function address into a call dummy instruction sequence
2170 For structs and unions, if the function was compiled with Sun cc,
2171 it expects 'unimp' after the call. But gcc doesn't use that
2172 (twisted) convention. So leave a nop there for gcc (FIX_CALL_DUMMY
2173 can assume it is operating on a pristine CALL_DUMMY, not one that
2174 has already been customized for a different function). */
2177 sparc_fix_call_dummy (dummy
, pc
, fun
, value_type
, using_gcc
)
2181 struct type
*value_type
;
2186 /* Store the relative adddress of the target function into the
2187 'call' instruction. */
2188 store_unsigned_integer (dummy
+ CALL_DUMMY_CALL_OFFSET
, 4,
2190 | (((fun
- (pc
+ CALL_DUMMY_CALL_OFFSET
)) >> 2)
2193 /* Comply with strange Sun cc calling convention for struct-returning
2196 && (TYPE_CODE (value_type
) == TYPE_CODE_STRUCT
2197 || TYPE_CODE (value_type
) == TYPE_CODE_UNION
))
2198 store_unsigned_integer (dummy
+ CALL_DUMMY_CALL_OFFSET
+ 8, 4,
2199 TYPE_LENGTH (value_type
) & 0x1fff);
2201 if (!(GDB_TARGET_IS_SPARC64
))
2203 /* If this is not a simulator target, change the first four
2204 instructions of the call dummy to NOPs. Those instructions
2205 include a 'save' instruction and are designed to work around
2206 problems with register window flushing in the simulator. */
2208 if (strcmp (target_shortname
, "sim") != 0)
2210 for (i
= 0; i
< 4; i
++)
2211 store_unsigned_integer (dummy
+ (i
* 4), 4, 0x01000000);
2215 /* If this is a bi-endian target, GDB has written the call dummy
2216 in little-endian order. We must byte-swap it back to big-endian. */
2219 for (i
= 0; i
< CALL_DUMMY_LENGTH
; i
+= 4)
2221 char tmp
= dummy
[i
];
2222 dummy
[i
] = dummy
[i
+ 3];
2225 dummy
[i
+ 1] = dummy
[i
+ 2];
2232 /* Set target byte order based on machine type. */
2235 sparc_target_architecture_hook (ap
)
2236 const bfd_arch_info_type
*ap
;
2240 if (ap
->mach
== bfd_mach_sparc_sparclite_le
)
2242 if (TARGET_BYTE_ORDER_SELECTABLE_P
)
2244 target_byte_order
= LITTLE_ENDIAN
;
2249 warning ("This GDB does not support little endian sparclite.");
2259 * Module "constructor" function.
2262 static struct gdbarch
* sparc_gdbarch_init (struct gdbarch_info info
,
2263 struct gdbarch_list
*arches
);
2266 _initialize_sparc_tdep ()
2268 /* Hook us into the gdbarch mechanism. */
2269 register_gdbarch_init (bfd_arch_sparc
, sparc_gdbarch_init
);
2271 tm_print_insn
= gdb_print_insn_sparc
;
2272 tm_print_insn_info
.mach
= TM_PRINT_INSN_MACH
; /* Selects sparc/sparclite */
2273 target_architecture_hook
= sparc_target_architecture_hook
;
2276 /* Compensate for stack bias. Note that we currently don't handle
2277 mixed 32/64 bit code. */
2280 sparc64_read_sp (void)
2282 CORE_ADDR sp
= read_register (SP_REGNUM
);
2290 sparc64_read_fp (void)
2292 CORE_ADDR fp
= read_register (FP_REGNUM
);
2300 sparc64_write_sp (val
)
2303 CORE_ADDR oldsp
= read_register (SP_REGNUM
);
2305 write_register (SP_REGNUM
, val
- 2047);
2307 write_register (SP_REGNUM
, val
);
2311 sparc64_write_fp (val
)
2314 CORE_ADDR oldfp
= read_register (FP_REGNUM
);
2316 write_register (FP_REGNUM
, val
- 2047);
2318 write_register (FP_REGNUM
, val
);
2321 /* The SPARC 64 ABI passes floating-point arguments in FP0 to FP31,
2322 and all other arguments in O0 to O5. They are also copied onto
2323 the stack in the correct places. Apparently (empirically),
2324 structs of less than 16 bytes are passed member-by-member in
2325 separate registers, but I am unable to figure out the algorithm.
2326 Some members go in floating point regs, but I don't know which.
2328 FIXME: Handle small structs (less than 16 bytes containing floats).
2330 The counting regimen for using both integer and FP registers
2331 for argument passing is rather odd -- a single counter is used
2332 for both; this means that if the arguments alternate between
2333 int and float, we will waste every other register of both types. */
2336 sparc64_push_arguments (nargs
, args
, sp
, struct_return
, struct_retaddr
)
2341 CORE_ADDR struct_retaddr
;
2343 int i
, j
, register_counter
= 0;
2345 struct type
*sparc_intreg_type
=
2346 TYPE_LENGTH (builtin_type_long
) == SPARC_INTREG_SIZE
?
2347 builtin_type_long
: builtin_type_long_long
;
2349 sp
= (sp
& ~(((unsigned long) SPARC_INTREG_SIZE
) - 1UL));
2351 /* Figure out how much space we'll need. */
2352 for (i
= nargs
- 1; i
>= 0; i
--)
2354 int len
= TYPE_LENGTH (check_typedef (VALUE_TYPE (args
[i
])));
2355 value_ptr copyarg
= args
[i
];
2358 if (copylen
< SPARC_INTREG_SIZE
)
2360 copyarg
= value_cast (sparc_intreg_type
, copyarg
);
2361 copylen
= SPARC_INTREG_SIZE
;
2370 /* if STRUCT_RETURN, then first argument is the struct return location. */
2372 write_register (O0_REGNUM
+ register_counter
++, struct_retaddr
);
2374 /* Now write the arguments onto the stack, while writing FP
2375 arguments into the FP registers, and other arguments into the
2376 first six 'O' registers. */
2378 for (i
= 0; i
< nargs
; i
++)
2380 int len
= TYPE_LENGTH (check_typedef (VALUE_TYPE (args
[i
])));
2381 value_ptr copyarg
= args
[i
];
2382 enum type_code typecode
= TYPE_CODE (VALUE_TYPE (args
[i
]));
2385 if (typecode
== TYPE_CODE_INT
||
2386 typecode
== TYPE_CODE_BOOL
||
2387 typecode
== TYPE_CODE_CHAR
||
2388 typecode
== TYPE_CODE_RANGE
||
2389 typecode
== TYPE_CODE_ENUM
)
2390 if (len
< SPARC_INTREG_SIZE
)
2392 /* Small ints will all take up the size of one intreg on
2394 copyarg
= value_cast (sparc_intreg_type
, copyarg
);
2395 copylen
= SPARC_INTREG_SIZE
;
2398 write_memory (tempsp
, VALUE_CONTENTS (copyarg
), copylen
);
2401 /* Corner case: Structs consisting of a single float member are floats.
2402 * FIXME! I don't know about structs containing multiple floats!
2403 * Structs containing mixed floats and ints are even more weird.
2408 /* Separate float args from all other args. */
2409 if (typecode
== TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2411 if (register_counter
< 16)
2413 /* This arg gets copied into a FP register. */
2417 case 4: /* Single-precision (float) */
2418 fpreg
= FP0_REGNUM
+ 2 * register_counter
+ 1;
2419 register_counter
+= 1;
2421 case 8: /* Double-precision (double) */
2422 fpreg
= FP0_REGNUM
+ 2 * register_counter
;
2423 register_counter
+= 1;
2425 case 16: /* Quad-precision (long double) */
2426 fpreg
= FP0_REGNUM
+ 2 * register_counter
;
2427 register_counter
+= 2;
2430 write_register_bytes (REGISTER_BYTE (fpreg
),
2431 VALUE_CONTENTS (args
[i
]),
2435 else /* all other args go into the first six 'o' registers */
2438 j
< len
&& register_counter
< 6;
2439 j
+= SPARC_INTREG_SIZE
)
2441 int oreg
= O0_REGNUM
+ register_counter
;
2443 write_register_gen (oreg
, VALUE_CONTENTS (copyarg
) + j
);
2444 register_counter
+= 1;
2451 /* Values <= 32 bytes are returned in o0-o3 (floating-point values are
2452 returned in f0-f3). */
2455 sp64_extract_return_value (type
, regbuf
, valbuf
, bitoffset
)
2461 int typelen
= TYPE_LENGTH (type
);
2462 int regsize
= REGISTER_RAW_SIZE (O0_REGNUM
);
2464 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2466 memcpy (valbuf
, ®buf
[REGISTER_BYTE (FP0_REGNUM
)], typelen
);
2470 if (TYPE_CODE (type
) != TYPE_CODE_STRUCT
2471 || (TYPE_LENGTH (type
) > 32))
2474 ®buf
[O0_REGNUM
* regsize
+
2475 (typelen
>= regsize
? 0 : regsize
- typelen
)],
2481 char *o0
= ®buf
[O0_REGNUM
* regsize
];
2482 char *f0
= ®buf
[FP0_REGNUM
* regsize
];
2485 for (x
= 0; x
< TYPE_NFIELDS (type
); x
++)
2487 struct field
*f
= &TYPE_FIELDS (type
)[x
];
2488 /* FIXME: We may need to handle static fields here. */
2489 int whichreg
= (f
->loc
.bitpos
+ bitoffset
) / 32;
2490 int remainder
= ((f
->loc
.bitpos
+ bitoffset
) % 32) / 8;
2491 int where
= (f
->loc
.bitpos
+ bitoffset
) / 8;
2492 int size
= TYPE_LENGTH (f
->type
);
2493 int typecode
= TYPE_CODE (f
->type
);
2495 if (typecode
== TYPE_CODE_STRUCT
)
2497 sp64_extract_return_value (f
->type
,
2500 bitoffset
+ f
->loc
.bitpos
);
2502 else if (typecode
== TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2504 memcpy (valbuf
+ where
, &f0
[whichreg
* 4] + remainder
, size
);
2508 memcpy (valbuf
+ where
, &o0
[whichreg
* 4] + remainder
, size
);
2515 sparc64_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2517 sp64_extract_return_value (type
, regbuf
, valbuf
, 0);
2521 sparclet_extract_return_value (struct type
*type
,
2525 regbuf
+= REGISTER_RAW_SIZE (O0_REGNUM
) * 8;
2526 if (TYPE_LENGTH (type
) < REGISTER_RAW_SIZE (O0_REGNUM
))
2527 regbuf
+= REGISTER_RAW_SIZE (O0_REGNUM
) - TYPE_LENGTH (type
);
2529 memcpy ((void *) valbuf
, regbuf
, TYPE_LENGTH (type
));
2534 sparc32_stack_align (CORE_ADDR addr
)
2536 return ((addr
+ 7) & -8);
2540 sparc64_stack_align (CORE_ADDR addr
)
2542 return ((addr
+ 15) & -16);
2546 sparc_print_extra_frame_info (struct frame_info
*fi
)
2548 if (fi
&& fi
->extra_info
&& fi
->extra_info
->flat
)
2549 printf_filtered (" flat, pc saved at 0x%s, fp saved at 0x%s\n",
2550 paddr_nz (fi
->extra_info
->pc_addr
),
2551 paddr_nz (fi
->extra_info
->fp_addr
));
2554 /* MULTI_ARCH support */
2557 sparc32_register_name (int regno
)
2559 static char *register_names
[] =
2560 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2561 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2562 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2563 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2565 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2566 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2567 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2568 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
2570 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
2574 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2577 return register_names
[regno
];
2581 sparc64_register_name (int regno
)
2583 static char *register_names
[] =
2584 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2585 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2586 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2587 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2589 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2590 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2591 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2592 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
2593 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
2594 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
2596 "pc", "npc", "ccr", "fsr", "fprs", "y", "asi", "ver",
2597 "tick", "pil", "pstate", "tstate", "tba", "tl", "tt", "tpc",
2598 "tnpc", "wstate", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
2599 "asr16", "asr17", "asr18", "asr19", "asr20", "asr21", "asr22", "asr23",
2600 "asr24", "asr25", "asr26", "asr27", "asr28", "asr29", "asr30", "asr31",
2601 /* These are here at the end to simplify removing them if we have to. */
2602 "icc", "xcc", "fcc0", "fcc1", "fcc2", "fcc3"
2606 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2609 return register_names
[regno
];
2613 sparclite_register_name (int regno
)
2615 static char *register_names
[] =
2616 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2617 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2618 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2619 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2621 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2622 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2623 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2624 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
2626 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr",
2627 "dia1", "dia2", "dda1", "dda2", "ddv1", "ddv2", "dcr", "dsr"
2631 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2634 return register_names
[regno
];
2638 sparclet_register_name (int regno
)
2640 static char *register_names
[] =
2641 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2642 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2643 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2644 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2646 "", "", "", "", "", "", "", "", /* no floating point registers */
2647 "", "", "", "", "", "", "", "",
2648 "", "", "", "", "", "", "", "",
2649 "", "", "", "", "", "", "", "",
2651 "y", "psr", "wim", "tbr", "pc", "npc", "", "", /* no FPSR or CPSR */
2652 "ccsr", "ccpr", "cccrcr", "ccor", "ccobr", "ccibr", "ccir", "",
2654 /* ASR15 ASR19 (don't display them) */
2655 "asr1", "", "asr17", "asr18", "", "asr20", "asr21", "asr22"
2656 /* None of the rest get displayed */
2658 "awr0", "awr1", "awr2", "awr3", "awr4", "awr5", "awr6", "awr7",
2659 "awr8", "awr9", "awr10", "awr11", "awr12", "awr13", "awr14", "awr15",
2660 "awr16", "awr17", "awr18", "awr19", "awr20", "awr21", "awr22", "awr23",
2661 "awr24", "awr25", "awr26", "awr27", "awr28", "awr29", "awr30", "awr31",
2667 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2670 return register_names
[regno
];
2674 sparc_push_return_address (CORE_ADDR pc_unused
, CORE_ADDR sp
)
2676 if (CALL_DUMMY_LOCATION
== AT_ENTRY_POINT
)
2678 /* The return PC of the dummy_frame is the former 'current' PC
2679 (where we were before we made the target function call).
2680 This is saved in %i7 by push_dummy_frame.
2682 We will save the 'call dummy location' (ie. the address
2683 to which the target function will return) in %o7.
2684 This address will actually be the program's entry point.
2685 There will be a special call_dummy breakpoint there. */
2687 write_register (O7_REGNUM
,
2688 CALL_DUMMY_ADDRESS () - 8);
2694 /* Should call_function allocate stack space for a struct return? */
2697 sparc64_use_struct_convention (int gcc_p
, struct type
*type
)
2699 return (TYPE_LENGTH (type
) > 32);
2702 /* Store the address of the place in which to copy the structure the
2703 subroutine will return. This is called from call_function_by_hand.
2704 The ultimate mystery is, tho, what is the value "16"?
2706 MVS: That's the offset from where the sp is now, to where the
2707 subroutine is gonna expect to find the struct return address. */
2710 sparc32_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
2715 val
= alloca (SPARC_INTREG_SIZE
);
2716 store_unsigned_integer (val
, SPARC_INTREG_SIZE
, addr
);
2717 write_memory (sp
+ (16 * SPARC_INTREG_SIZE
), val
, SPARC_INTREG_SIZE
);
2719 if (CALL_DUMMY_LOCATION
== AT_ENTRY_POINT
)
2721 /* Now adjust the value of the link register, which was previously
2722 stored by push_return_address. Functions that return structs are
2723 peculiar in that they return to link register + 12, rather than
2724 link register + 8. */
2726 o7
= read_register (O7_REGNUM
);
2727 write_register (O7_REGNUM
, o7
- 4);
2732 sparc64_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
2734 /* FIXME: V9 uses %o0 for this. */
2735 /* FIXME MVS: Only for small enough structs!!! */
2737 target_write_memory (sp
+ (16 * SPARC_INTREG_SIZE
),
2738 (char *) &addr
, SPARC_INTREG_SIZE
);
2740 if (CALL_DUMMY_LOCATION
== AT_ENTRY_POINT
)
2742 /* Now adjust the value of the link register, which was previously
2743 stored by push_return_address. Functions that return structs are
2744 peculiar in that they return to link register + 12, rather than
2745 link register + 8. */
2747 write_register (O7_REGNUM
, read_register (O7_REGNUM
) - 4);
2752 /* Default target data type for register REGNO. */
2754 static struct type
*
2755 sparc32_register_virtual_type (int regno
)
2757 if (regno
== PC_REGNUM
||
2758 regno
== FP_REGNUM
||
2760 return builtin_type_unsigned_int
;
2762 return builtin_type_int
;
2764 return builtin_type_float
;
2765 return builtin_type_int
;
2768 static struct type
*
2769 sparc64_register_virtual_type (int regno
)
2771 if (regno
== PC_REGNUM
||
2772 regno
== FP_REGNUM
||
2774 return builtin_type_unsigned_long_long
;
2776 return builtin_type_long_long
;
2778 return builtin_type_float
;
2780 return builtin_type_double
;
2781 return builtin_type_long_long
;
2784 /* Number of bytes of storage in the actual machine representation for
2788 sparc32_register_size (int regno
)
2794 sparc64_register_size (int regno
)
2796 return (regno
< 32 ? 8 : regno
< 64 ? 4 : 8);
2799 /* Index within the `registers' buffer of the first byte of the space
2800 for register REGNO. */
2803 sparc32_register_byte (int regno
)
2809 sparc64_register_byte (int regno
)
2813 else if (regno
< 64)
2814 return 32 * 8 + (regno
- 32) * 4;
2815 else if (regno
< 80)
2816 return 32 * 8 + 32 * 4 + (regno
- 64) * 8;
2818 return 64 * 8 + (regno
- 80) * 8;
2821 /* Advance PC across any function entry prologue instructions to reach
2822 some "real" code. SKIP_PROLOGUE_FRAMELESS_P advances the PC past
2823 some of the prologue, but stops as soon as it knows that the
2824 function has a frame. Its result is equal to its input PC if the
2825 function is frameless, unequal otherwise. */
2828 sparc_gdbarch_skip_prologue (CORE_ADDR ip
)
2830 return examine_prologue (ip
, 0, NULL
, NULL
);
2833 /* Immediately after a function call, return the saved pc.
2834 Can't go through the frames for this because on some machines
2835 the new frame is not set up until the new function executes
2836 some instructions. */
2839 sparc_saved_pc_after_call (struct frame_info
*fi
)
2841 return sparc_pc_adjust (read_register (RP_REGNUM
));
2844 /* Convert registers between 'raw' and 'virtual' formats.
2845 They are the same on sparc, so there's nothing to do. */
2848 sparc_convert_to_virtual (int regnum
, struct type
*type
, char *from
, char *to
)
2849 { /* do nothing (should never be called) */
2853 sparc_convert_to_raw (struct type
*type
, int regnum
, char *from
, char *to
)
2854 { /* do nothing (should never be called) */
2857 /* Init saved regs: nothing to do, just a place-holder function. */
2860 sparc_frame_init_saved_regs (struct frame_info
*fi_ignored
)
2864 /* The frame address: stored in the 'frame' field of the frame_info. */
2867 sparc_frame_address (struct frame_info
*fi
)
2872 /* gdbarch fix call dummy:
2873 All this function does is rearrange the arguments before calling
2874 sparc_fix_call_dummy (which does the real work). */
2877 sparc_gdbarch_fix_call_dummy (char *dummy
,
2881 struct value
**args
,
2885 if (CALL_DUMMY_LOCATION
== ON_STACK
)
2886 sparc_fix_call_dummy (dummy
, pc
, fun
, type
, gcc_p
);
2889 /* Coerce float to double: a no-op. */
2892 sparc_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
2897 /* CALL_DUMMY_ADDRESS: fetch the breakpoint address for a call dummy. */
2900 sparc_call_dummy_address (void)
2902 return (CALL_DUMMY_START_OFFSET
) + CALL_DUMMY_BREAKPOINT_OFFSET
;
2905 /* Supply the Y register number to those that need it. */
2908 sparc_y_regnum (void)
2910 return gdbarch_tdep (current_gdbarch
)->y_regnum
;
2914 sparc_reg_struct_has_addr (int gcc_p
, struct type
*type
)
2916 if (GDB_TARGET_IS_SPARC64
)
2917 return (TYPE_LENGTH (type
) > 32);
2919 return (gcc_p
!= 1);
2923 sparc_intreg_size (void)
2925 return SPARC_INTREG_SIZE
;
2929 sparc_return_value_on_stack (struct type
*type
)
2931 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&&
2932 TYPE_LENGTH (type
) > 8)
2939 * Gdbarch "constructor" function.
2942 #define SPARC32_CALL_DUMMY_ON_STACK
2944 #define SPARC_SP_REGNUM 14
2945 #define SPARC_FP_REGNUM 30
2946 #define SPARC_FP0_REGNUM 32
2947 #define SPARC32_NPC_REGNUM 69
2948 #define SPARC32_PC_REGNUM 68
2949 #define SPARC32_Y_REGNUM 64
2950 #define SPARC64_PC_REGNUM 80
2951 #define SPARC64_NPC_REGNUM 81
2952 #define SPARC64_Y_REGNUM 85
2954 static struct gdbarch
*
2955 sparc_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2957 struct gdbarch
*gdbarch
;
2958 struct gdbarch_tdep
*tdep
;
2960 static LONGEST call_dummy_32
[] =
2961 { 0xbc100001, 0x9de38000, 0xbc100002, 0xbe100003,
2962 0xda03a058, 0xd803a054, 0xd603a050, 0xd403a04c,
2963 0xd203a048, 0x40000000, 0xd003a044, 0x01000000,
2964 0x91d02001, 0x01000000
2966 static LONGEST call_dummy_64
[] =
2967 { 0x9de3bec0fd3fa7f7LL
, 0xf93fa7eff53fa7e7LL
,
2968 0xf13fa7dfed3fa7d7LL
, 0xe93fa7cfe53fa7c7LL
,
2969 0xe13fa7bfdd3fa7b7LL
, 0xd93fa7afd53fa7a7LL
,
2970 0xd13fa79fcd3fa797LL
, 0xc93fa78fc53fa787LL
,
2971 0xc13fa77fcc3fa777LL
, 0xc83fa76fc43fa767LL
,
2972 0xc03fa75ffc3fa757LL
, 0xf83fa74ff43fa747LL
,
2973 0xf03fa73f01000000LL
, 0x0100000001000000LL
,
2974 0x0100000091580000LL
, 0xd027a72b93500000LL
,
2975 0xd027a72791480000LL
, 0xd027a72391400000LL
,
2976 0xd027a71fda5ba8a7LL
, 0xd85ba89fd65ba897LL
,
2977 0xd45ba88fd25ba887LL
, 0x9fc02000d05ba87fLL
,
2978 0x0100000091d02001LL
, 0x0100000001000000LL
2980 static LONGEST call_dummy_nil
[] = {0};
2982 /* First see if there is already a gdbarch that can satisfy the request. */
2983 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2985 return arches
->gdbarch
;
2987 /* None found: is the request for a sparc architecture? */
2988 if (info
.bfd_architecture
!= bfd_arch_sparc
)
2989 return NULL
; /* No; then it's not for us. */
2991 /* Yes: create a new gdbarch for the specified machine type. */
2992 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
2993 gdbarch
= gdbarch_alloc (&info
, tdep
);
2995 /* First set settings that are common for all sparc architectures. */
2996 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2997 set_gdbarch_breakpoint_from_pc (gdbarch
, memory_breakpoint_from_pc
);
2998 set_gdbarch_coerce_float_to_double (gdbarch
,
2999 sparc_coerce_float_to_double
);
3000 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
3001 set_gdbarch_call_dummy_p (gdbarch
, 1);
3002 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 1);
3003 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
3004 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3005 set_gdbarch_extract_struct_value_address (gdbarch
,
3006 sparc_extract_struct_value_address
);
3007 set_gdbarch_fix_call_dummy (gdbarch
, sparc_gdbarch_fix_call_dummy
);
3008 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3009 set_gdbarch_fp_regnum (gdbarch
, SPARC_FP_REGNUM
);
3010 set_gdbarch_fp0_regnum (gdbarch
, SPARC_FP0_REGNUM
);
3011 set_gdbarch_frame_args_address (gdbarch
, sparc_frame_address
);
3012 set_gdbarch_frame_chain (gdbarch
, sparc_frame_chain
);
3013 set_gdbarch_frame_init_saved_regs (gdbarch
, sparc_frame_init_saved_regs
);
3014 set_gdbarch_frame_locals_address (gdbarch
, sparc_frame_address
);
3015 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
3016 set_gdbarch_frame_saved_pc (gdbarch
, sparc_frame_saved_pc
);
3017 set_gdbarch_frameless_function_invocation (gdbarch
,
3018 frameless_look_for_prologue
);
3019 set_gdbarch_get_saved_register (gdbarch
, sparc_get_saved_register
);
3020 set_gdbarch_ieee_float (gdbarch
, 1);
3021 set_gdbarch_init_extra_frame_info (gdbarch
, sparc_init_extra_frame_info
);
3022 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3023 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3024 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
3025 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3026 set_gdbarch_max_register_raw_size (gdbarch
, 8);
3027 set_gdbarch_max_register_virtual_size (gdbarch
, 8);
3028 #ifdef DO_CALL_DUMMY_ON_STACK
3029 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_on_stack
);
3031 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
3033 set_gdbarch_pop_frame (gdbarch
, sparc_pop_frame
);
3034 set_gdbarch_push_return_address (gdbarch
, sparc_push_return_address
);
3035 set_gdbarch_push_dummy_frame (gdbarch
, sparc_push_dummy_frame
);
3036 set_gdbarch_read_pc (gdbarch
, generic_target_read_pc
);
3037 set_gdbarch_register_convert_to_raw (gdbarch
, sparc_convert_to_raw
);
3038 set_gdbarch_register_convert_to_virtual (gdbarch
,
3039 sparc_convert_to_virtual
);
3040 set_gdbarch_register_convertible (gdbarch
,
3041 generic_register_convertible_not
);
3042 set_gdbarch_reg_struct_has_addr (gdbarch
, sparc_reg_struct_has_addr
);
3043 set_gdbarch_return_value_on_stack (gdbarch
, sparc_return_value_on_stack
);
3044 set_gdbarch_saved_pc_after_call (gdbarch
, sparc_saved_pc_after_call
);
3045 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
3046 set_gdbarch_skip_prologue (gdbarch
, sparc_gdbarch_skip_prologue
);
3047 set_gdbarch_sp_regnum (gdbarch
, SPARC_SP_REGNUM
);
3048 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
3049 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
3052 * Settings that depend only on 32/64 bit word size
3055 switch (info
.bfd_arch_info
->mach
)
3057 case bfd_mach_sparc
:
3058 case bfd_mach_sparc_sparclet
:
3059 case bfd_mach_sparc_sparclite
:
3060 case bfd_mach_sparc_v8plus
:
3061 case bfd_mach_sparc_v8plusa
:
3062 case bfd_mach_sparc_sparclite_le
:
3063 /* 32-bit machine types: */
3065 #ifdef SPARC32_CALL_DUMMY_ON_STACK
3066 set_gdbarch_call_dummy_address (gdbarch
, sparc_call_dummy_address
);
3067 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0x30);
3068 set_gdbarch_call_dummy_length (gdbarch
, 0x38);
3069 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
3070 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_32
);
3072 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
3073 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
3074 set_gdbarch_call_dummy_length (gdbarch
, 0);
3075 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
3076 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_nil
);
3078 set_gdbarch_call_dummy_stack_adjust (gdbarch
, 68);
3079 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
3080 set_gdbarch_frame_args_skip (gdbarch
, 68);
3081 set_gdbarch_function_start_offset (gdbarch
, 0);
3082 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3083 set_gdbarch_npc_regnum (gdbarch
, SPARC32_NPC_REGNUM
);
3084 set_gdbarch_pc_regnum (gdbarch
, SPARC32_PC_REGNUM
);
3085 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3086 set_gdbarch_push_arguments (gdbarch
, sparc32_push_arguments
);
3087 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
3088 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
3090 set_gdbarch_register_byte (gdbarch
, sparc32_register_byte
);
3091 set_gdbarch_register_raw_size (gdbarch
, sparc32_register_size
);
3092 set_gdbarch_register_size (gdbarch
, 4);
3093 set_gdbarch_register_virtual_size (gdbarch
, sparc32_register_size
);
3094 set_gdbarch_register_virtual_type (gdbarch
,
3095 sparc32_register_virtual_type
);
3096 #ifdef SPARC32_CALL_DUMMY_ON_STACK
3097 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (call_dummy_32
));
3099 set_gdbarch_sizeof_call_dummy_words (gdbarch
, 0);
3101 set_gdbarch_stack_align (gdbarch
, sparc32_stack_align
);
3102 set_gdbarch_store_struct_return (gdbarch
, sparc32_store_struct_return
);
3103 set_gdbarch_use_struct_convention (gdbarch
,
3104 generic_use_struct_convention
);
3105 set_gdbarch_write_fp (gdbarch
, generic_target_write_fp
);
3106 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
3107 tdep
->y_regnum
= SPARC32_Y_REGNUM
;
3108 tdep
->fp_max_regnum
= SPARC_FP0_REGNUM
+ 32;
3109 tdep
->intreg_size
= 4;
3110 tdep
->reg_save_offset
= 0x60;
3111 tdep
->call_dummy_call_offset
= 0x24;
3114 case bfd_mach_sparc_v9
:
3115 case bfd_mach_sparc_v9a
:
3116 /* 64-bit machine types: */
3117 default: /* Any new machine type is likely to be 64-bit. */
3119 #ifdef SPARC64_CALL_DUMMY_ON_STACK
3120 set_gdbarch_call_dummy_address (gdbarch
, sparc_call_dummy_address
);
3121 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 8 * 4);
3122 set_gdbarch_call_dummy_length (gdbarch
, 192);
3123 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
3124 set_gdbarch_call_dummy_start_offset (gdbarch
, 148);
3125 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_64
);
3127 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
3128 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
3129 set_gdbarch_call_dummy_length (gdbarch
, 0);
3130 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
3131 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
3132 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_nil
);
3134 set_gdbarch_call_dummy_stack_adjust (gdbarch
, 128);
3135 set_gdbarch_frame_args_skip (gdbarch
, 136);
3136 set_gdbarch_function_start_offset (gdbarch
, 0);
3137 set_gdbarch_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3138 set_gdbarch_npc_regnum (gdbarch
, SPARC64_NPC_REGNUM
);
3139 set_gdbarch_pc_regnum (gdbarch
, SPARC64_PC_REGNUM
);
3140 set_gdbarch_ptr_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3141 set_gdbarch_push_arguments (gdbarch
, sparc64_push_arguments
);
3142 /* NOTE different for at_entry */
3143 set_gdbarch_read_fp (gdbarch
, sparc64_read_fp
);
3144 set_gdbarch_read_sp (gdbarch
, sparc64_read_sp
);
3145 /* Some of the registers aren't 64 bits, but it's a lot simpler just
3146 to assume they all are (since most of them are). */
3147 set_gdbarch_register_byte (gdbarch
, sparc64_register_byte
);
3148 set_gdbarch_register_raw_size (gdbarch
, sparc64_register_size
);
3149 set_gdbarch_register_size (gdbarch
, 8);
3150 set_gdbarch_register_virtual_size (gdbarch
, sparc64_register_size
);
3151 set_gdbarch_register_virtual_type (gdbarch
,
3152 sparc64_register_virtual_type
);
3153 #ifdef SPARC64_CALL_DUMMY_ON_STACK
3154 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (call_dummy_64
));
3156 set_gdbarch_sizeof_call_dummy_words (gdbarch
, 0);
3158 set_gdbarch_stack_align (gdbarch
, sparc64_stack_align
);
3159 set_gdbarch_store_struct_return (gdbarch
, sparc64_store_struct_return
);
3160 set_gdbarch_use_struct_convention (gdbarch
,
3161 sparc64_use_struct_convention
);
3162 set_gdbarch_write_fp (gdbarch
, sparc64_write_fp
);
3163 set_gdbarch_write_sp (gdbarch
, sparc64_write_sp
);
3164 tdep
->y_regnum
= SPARC64_Y_REGNUM
;
3165 tdep
->fp_max_regnum
= SPARC_FP0_REGNUM
+ 48;
3166 tdep
->intreg_size
= 8;
3167 tdep
->reg_save_offset
= 0x90;
3168 tdep
->call_dummy_call_offset
= 148 + 4 * 5;
3173 * Settings that vary per-architecture:
3176 switch (info
.bfd_arch_info
->mach
)
3178 case bfd_mach_sparc
:
3179 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3180 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3181 set_gdbarch_num_regs (gdbarch
, 72);
3182 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4);
3183 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
3184 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3185 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3186 tdep
->fp_register_bytes
= 32 * 4;
3187 tdep
->print_insn_mach
= bfd_mach_sparc
;
3189 case bfd_mach_sparc_sparclet
:
3190 set_gdbarch_extract_return_value (gdbarch
,
3191 sparclet_extract_return_value
);
3192 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3193 set_gdbarch_num_regs (gdbarch
, 32 + 32 + 8 + 8 + 8);
3194 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4 + 8*4 + 8*4);
3195 set_gdbarch_register_name (gdbarch
, sparclet_register_name
);
3196 set_gdbarch_store_return_value (gdbarch
, sparclet_store_return_value
);
3197 tdep
->has_fpu
= 0; /* (all but sparclet and sparclite) */
3198 tdep
->fp_register_bytes
= 0;
3199 tdep
->print_insn_mach
= bfd_mach_sparc_sparclet
;
3201 case bfd_mach_sparc_sparclite
:
3202 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3203 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
3204 set_gdbarch_num_regs (gdbarch
, 80);
3205 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4 + 8*4);
3206 set_gdbarch_register_name (gdbarch
, sparclite_register_name
);
3207 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3208 tdep
->has_fpu
= 0; /* (all but sparclet and sparclite) */
3209 tdep
->fp_register_bytes
= 0;
3210 tdep
->print_insn_mach
= bfd_mach_sparc_sparclite
;
3212 case bfd_mach_sparc_v8plus
:
3213 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3214 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3215 set_gdbarch_num_regs (gdbarch
, 72);
3216 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4);
3217 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
3218 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3219 tdep
->print_insn_mach
= bfd_mach_sparc
;
3220 tdep
->fp_register_bytes
= 32 * 4;
3221 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3223 case bfd_mach_sparc_v8plusa
:
3224 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3225 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3226 set_gdbarch_num_regs (gdbarch
, 72);
3227 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4);
3228 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
3229 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3230 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3231 tdep
->fp_register_bytes
= 32 * 4;
3232 tdep
->print_insn_mach
= bfd_mach_sparc
;
3234 case bfd_mach_sparc_sparclite_le
:
3235 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3236 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
3237 set_gdbarch_num_regs (gdbarch
, 80);
3238 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4 + 8*4);
3239 set_gdbarch_register_name (gdbarch
, sparclite_register_name
);
3240 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3241 tdep
->has_fpu
= 0; /* (all but sparclet and sparclite) */
3242 tdep
->fp_register_bytes
= 0;
3243 tdep
->print_insn_mach
= bfd_mach_sparc_sparclite
;
3245 case bfd_mach_sparc_v9
:
3246 set_gdbarch_extract_return_value (gdbarch
, sparc64_extract_return_value
);
3247 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3248 set_gdbarch_num_regs (gdbarch
, 125);
3249 set_gdbarch_register_bytes (gdbarch
, 32*8 + 32*8 + 45*8);
3250 set_gdbarch_register_name (gdbarch
, sparc64_register_name
);
3251 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3252 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3253 tdep
->fp_register_bytes
= 64 * 4;
3254 tdep
->print_insn_mach
= bfd_mach_sparc_v9a
;
3256 case bfd_mach_sparc_v9a
:
3257 set_gdbarch_extract_return_value (gdbarch
, sparc64_extract_return_value
);
3258 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3259 set_gdbarch_num_regs (gdbarch
, 125);
3260 set_gdbarch_register_bytes (gdbarch
, 32*8 + 32*8 + 45*8);
3261 set_gdbarch_register_name (gdbarch
, sparc64_register_name
);
3262 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3263 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3264 tdep
->fp_register_bytes
= 64 * 4;
3265 tdep
->print_insn_mach
= bfd_mach_sparc_v9a
;