1 /* Target-dependent code for the SPARC for GDB, the GNU debugger.
2 Copyright 1986, 1987, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
3 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* ??? Support for calling functions from gdb in sparc64 is unfinished. */
25 #include "arch-utils.h"
32 #include "gdb_string.h"
36 #include <sys/procfs.h>
37 /* Prototypes for supply_gregset etc. */
43 #include "symfile.h" /* for 'entry_point_address' */
46 * Some local macros that have multi-arch and non-multi-arch versions:
49 #if (GDB_MULTI_ARCH > 0)
51 /* Does the target have Floating Point registers? */
52 #define SPARC_HAS_FPU (gdbarch_tdep (current_gdbarch)->has_fpu)
53 /* Number of bytes devoted to Floating Point registers: */
54 #define FP_REGISTER_BYTES (gdbarch_tdep (current_gdbarch)->fp_register_bytes)
55 /* Highest numbered Floating Point register. */
56 #define FP_MAX_REGNUM (gdbarch_tdep (current_gdbarch)->fp_max_regnum)
57 /* Size of a general (integer) register: */
58 #define SPARC_INTREG_SIZE (gdbarch_tdep (current_gdbarch)->intreg_size)
59 /* Offset within the call dummy stack of the saved registers. */
60 #define DUMMY_REG_SAVE_OFFSET (gdbarch_tdep (current_gdbarch)->reg_save_offset)
62 #else /* non-multi-arch */
65 /* Does the target have Floating Point registers? */
66 #if defined(TARGET_SPARCLET) || defined(TARGET_SPARCLITE)
67 #define SPARC_HAS_FPU 0
69 #define SPARC_HAS_FPU 1
72 /* Number of bytes devoted to Floating Point registers: */
73 #if (GDB_TARGET_IS_SPARC64)
74 #define FP_REGISTER_BYTES (64 * 4)
77 #define FP_REGISTER_BYTES (32 * 4)
79 #define FP_REGISTER_BYTES 0
83 /* Highest numbered Floating Point register. */
84 #if (GDB_TARGET_IS_SPARC64)
85 #define FP_MAX_REGNUM (FP0_REGNUM + 48)
87 #define FP_MAX_REGNUM (FP0_REGNUM + 32)
90 /* Size of a general (integer) register: */
91 #define SPARC_INTREG_SIZE (REGISTER_RAW_SIZE (G0_REGNUM))
93 /* Offset within the call dummy stack of the saved registers. */
94 #if (GDB_TARGET_IS_SPARC64)
95 #define DUMMY_REG_SAVE_OFFSET (128 + 16)
97 #define DUMMY_REG_SAVE_OFFSET 0x60
100 #endif /* GDB_MULTI_ARCH */
105 int fp_register_bytes
;
110 int call_dummy_call_offset
;
114 /* Now make GDB_TARGET_IS_SPARC64 a runtime test. */
115 /* FIXME MVS: or try testing bfd_arch_info.arch and bfd_arch_info.mach ...
116 * define GDB_TARGET_IS_SPARC64 \
117 * (TARGET_ARCHITECTURE->arch == bfd_arch_sparc && \
118 * (TARGET_ARCHITECTURE->mach == bfd_mach_sparc_v9 || \
119 * TARGET_ARCHITECTURE->mach == bfd_mach_sparc_v9a))
123 extern int stop_after_trap
;
125 /* We don't store all registers immediately when requested, since they
126 get sent over in large chunks anyway. Instead, we accumulate most
127 of the changes and send them over once. "deferred_stores" keeps
128 track of which sets of registers we have locally-changed copies of,
129 so we only need send the groups that have changed. */
131 int deferred_stores
= 0; /* Accumulated stores we want to do eventually. */
134 /* Some machines, such as Fujitsu SPARClite 86x, have a bi-endian mode
135 where instructions are big-endian and data are little-endian.
136 This flag is set when we detect that the target is of this type. */
141 /* Fetch a single instruction. Even on bi-endian machines
142 such as sparc86x, instructions are always big-endian. */
145 fetch_instruction (CORE_ADDR pc
)
147 unsigned long retval
;
149 unsigned char buf
[4];
151 read_memory (pc
, buf
, sizeof (buf
));
153 /* Start at the most significant end of the integer, and work towards
154 the least significant. */
156 for (i
= 0; i
< sizeof (buf
); ++i
)
157 retval
= (retval
<< 8) | buf
[i
];
162 /* Branches with prediction are treated like their non-predicting cousins. */
163 /* FIXME: What about floating point branches? */
165 /* Macros to extract fields from sparc instructions. */
166 #define X_OP(i) (((i) >> 30) & 0x3)
167 #define X_RD(i) (((i) >> 25) & 0x1f)
168 #define X_A(i) (((i) >> 29) & 1)
169 #define X_COND(i) (((i) >> 25) & 0xf)
170 #define X_OP2(i) (((i) >> 22) & 0x7)
171 #define X_IMM22(i) ((i) & 0x3fffff)
172 #define X_OP3(i) (((i) >> 19) & 0x3f)
173 #define X_RS1(i) (((i) >> 14) & 0x1f)
174 #define X_I(i) (((i) >> 13) & 1)
175 #define X_IMM13(i) ((i) & 0x1fff)
176 /* Sign extension macros. */
177 #define X_SIMM13(i) ((X_IMM13 (i) ^ 0x1000) - 0x1000)
178 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
179 #define X_CC(i) (((i) >> 20) & 3)
180 #define X_P(i) (((i) >> 19) & 1)
181 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
182 #define X_RCOND(i) (((i) >> 25) & 7)
183 #define X_DISP16(i) ((((((i) >> 6) && 0xc000) | ((i) & 0x3fff)) ^ 0x8000) - 0x8000)
184 #define X_FCN(i) (((i) >> 25) & 31)
188 Error
, not_branch
, bicc
, bicca
, ba
, baa
, ticc
, ta
, done_retry
191 /* Simulate single-step ptrace call for sun4. Code written by Gary
192 Beihl (beihl@mcc.com). */
194 /* npc4 and next_pc describe the situation at the time that the
195 step-breakpoint was set, not necessary the current value of NPC_REGNUM. */
196 static CORE_ADDR next_pc
, npc4
, target
;
197 static int brknpc4
, brktrg
;
198 typedef char binsn_quantum
[BREAKPOINT_MAX
];
199 static binsn_quantum break_mem
[3];
201 static branch_type
isbranch (long, CORE_ADDR
, CORE_ADDR
*);
203 /* single_step() is called just before we want to resume the inferior,
204 if we want to single-step it but there is no hardware or kernel single-step
205 support (as on all SPARCs). We find all the possible targets of the
206 coming instruction and breakpoint them.
208 single_step is also called just after the inferior stops. If we had
209 set up a simulated single-step, we undo our damage. */
212 sparc_software_single_step (enum target_signal ignore
, /* pid, but we don't need it */
213 int insert_breakpoints_p
)
219 if (insert_breakpoints_p
)
221 /* Always set breakpoint for NPC. */
222 next_pc
= read_register (NPC_REGNUM
);
223 npc4
= next_pc
+ 4; /* branch not taken */
225 target_insert_breakpoint (next_pc
, break_mem
[0]);
226 /* printf_unfiltered ("set break at %x\n",next_pc); */
228 pc
= read_register (PC_REGNUM
);
229 pc_instruction
= fetch_instruction (pc
);
230 br
= isbranch (pc_instruction
, pc
, &target
);
231 brknpc4
= brktrg
= 0;
235 /* Conditional annulled branch will either end up at
236 npc (if taken) or at npc+4 (if not taken).
239 target_insert_breakpoint (npc4
, break_mem
[1]);
241 else if (br
== baa
&& target
!= next_pc
)
243 /* Unconditional annulled branch will always end up at
246 target_insert_breakpoint (target
, break_mem
[2]);
248 else if (GDB_TARGET_IS_SPARC64
&& br
== done_retry
)
251 target_insert_breakpoint (target
, break_mem
[2]);
256 /* Remove breakpoints */
257 target_remove_breakpoint (next_pc
, break_mem
[0]);
260 target_remove_breakpoint (npc4
, break_mem
[1]);
263 target_remove_breakpoint (target
, break_mem
[2]);
267 struct frame_extra_info
272 /* Following fields only relevant for flat frames. */
275 /* Add this to ->frame to get the value of the stack pointer at the
276 time of the register saves. */
280 /* Call this for each newly created frame. For SPARC, we need to
281 calculate the bottom of the frame, and do some extra work if the
282 prologue has been generated via the -mflat option to GCC. In
283 particular, we need to know where the previous fp and the pc have
284 been stashed, since their exact position within the frame may vary. */
287 sparc_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
290 CORE_ADDR prologue_start
, prologue_end
;
293 fi
->extra_info
= (struct frame_extra_info
*)
294 frame_obstack_alloc (sizeof (struct frame_extra_info
));
295 frame_saved_regs_zalloc (fi
);
297 fi
->extra_info
->bottom
=
299 (fi
->frame
== fi
->next
->frame
? fi
->next
->extra_info
->bottom
:
300 fi
->next
->frame
) : read_sp ());
302 /* If fi->next is NULL, then we already set ->frame by passing read_fp()
303 to create_new_frame. */
308 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
310 /* Compute ->frame as if not flat. If it is flat, we'll change
312 if (fi
->next
->next
!= NULL
313 && (fi
->next
->next
->signal_handler_caller
314 || frame_in_dummy (fi
->next
->next
))
315 && frameless_look_for_prologue (fi
->next
))
317 /* A frameless function interrupted by a signal did not change
318 the frame pointer, fix up frame pointer accordingly. */
319 fi
->frame
= FRAME_FP (fi
->next
);
320 fi
->extra_info
->bottom
= fi
->next
->extra_info
->bottom
;
324 /* Should we adjust for stack bias here? */
325 get_saved_register (buf
, 0, 0, fi
, FP_REGNUM
, 0);
326 fi
->frame
= extract_address (buf
, REGISTER_RAW_SIZE (FP_REGNUM
));
328 if (GDB_TARGET_IS_SPARC64
&& (fi
->frame
& 1))
333 /* Decide whether this is a function with a ``flat register window''
334 frame. For such functions, the frame pointer is actually in %i7. */
335 fi
->extra_info
->flat
= 0;
336 fi
->extra_info
->in_prologue
= 0;
337 if (find_pc_partial_function (fi
->pc
, &name
, &prologue_start
, &prologue_end
))
339 /* See if the function starts with an add (which will be of a
340 negative number if a flat frame) to the sp. FIXME: Does not
341 handle large frames which will need more than one instruction
343 insn
= fetch_instruction (prologue_start
);
344 if (X_OP (insn
) == 2 && X_RD (insn
) == 14 && X_OP3 (insn
) == 0
345 && X_I (insn
) && X_SIMM13 (insn
) < 0)
347 int offset
= X_SIMM13 (insn
);
349 /* Then look for a save of %i7 into the frame. */
350 insn
= fetch_instruction (prologue_start
+ 4);
354 && X_RS1 (insn
) == 14)
358 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
360 /* We definitely have a flat frame now. */
361 fi
->extra_info
->flat
= 1;
363 fi
->extra_info
->sp_offset
= offset
;
365 /* Overwrite the frame's address with the value in %i7. */
366 get_saved_register (buf
, 0, 0, fi
, I7_REGNUM
, 0);
367 fi
->frame
= extract_address (buf
, REGISTER_RAW_SIZE (I7_REGNUM
));
369 if (GDB_TARGET_IS_SPARC64
&& (fi
->frame
& 1))
372 /* Record where the fp got saved. */
373 fi
->extra_info
->fp_addr
=
374 fi
->frame
+ fi
->extra_info
->sp_offset
+ X_SIMM13 (insn
);
376 /* Also try to collect where the pc got saved to. */
377 fi
->extra_info
->pc_addr
= 0;
378 insn
= fetch_instruction (prologue_start
+ 12);
382 && X_RS1 (insn
) == 14)
383 fi
->extra_info
->pc_addr
=
384 fi
->frame
+ fi
->extra_info
->sp_offset
+ X_SIMM13 (insn
);
389 /* Check if the PC is in the function prologue before a SAVE
390 instruction has been executed yet. If so, set the frame
391 to the current value of the stack pointer and set
392 the in_prologue flag. */
394 struct symtab_and_line sal
;
396 sal
= find_pc_line (prologue_start
, 0);
397 if (sal
.line
== 0) /* no line info, use PC */
398 prologue_end
= fi
->pc
;
399 else if (sal
.end
< prologue_end
)
400 prologue_end
= sal
.end
;
401 if (fi
->pc
< prologue_end
)
403 for (addr
= prologue_start
; addr
< fi
->pc
; addr
+= 4)
405 insn
= read_memory_integer (addr
, 4);
406 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3c)
407 break; /* SAVE seen, stop searching */
411 fi
->extra_info
->in_prologue
= 1;
412 fi
->frame
= read_register (SP_REGNUM
);
417 if (fi
->next
&& fi
->frame
== 0)
419 /* Kludge to cause init_prev_frame_info to destroy the new frame. */
420 fi
->frame
= fi
->next
->frame
;
421 fi
->pc
= fi
->next
->pc
;
426 sparc_frame_chain (struct frame_info
*frame
)
428 /* Value that will cause FRAME_CHAIN_VALID to not worry about the chain
429 value. If it really is zero, we detect it later in
430 sparc_init_prev_frame. */
431 return (CORE_ADDR
) 1;
435 sparc_extract_struct_value_address (char *regbuf
)
437 return extract_address (regbuf
+ REGISTER_BYTE (O0_REGNUM
),
438 REGISTER_RAW_SIZE (O0_REGNUM
));
441 /* Find the pc saved in frame FRAME. */
444 sparc_frame_saved_pc (struct frame_info
*frame
)
449 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
450 if (frame
->signal_handler_caller
)
452 /* This is the signal trampoline frame.
453 Get the saved PC from the sigcontext structure. */
455 #ifndef SIGCONTEXT_PC_OFFSET
456 #define SIGCONTEXT_PC_OFFSET 12
459 CORE_ADDR sigcontext_addr
;
461 int saved_pc_offset
= SIGCONTEXT_PC_OFFSET
;
464 scbuf
= alloca (TARGET_PTR_BIT
/ HOST_CHAR_BIT
);
466 /* Solaris2 ucbsigvechandler passes a pointer to a sigcontext
467 as the third parameter. The offset to the saved pc is 12. */
468 find_pc_partial_function (frame
->pc
, &name
,
469 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
470 if (name
&& STREQ (name
, "ucbsigvechandler"))
471 saved_pc_offset
= 12;
473 /* The sigcontext address is contained in register O2. */
474 get_saved_register (buf
, (int *) NULL
, (CORE_ADDR
*) NULL
,
475 frame
, O0_REGNUM
+ 2, (enum lval_type
*) NULL
);
476 sigcontext_addr
= extract_address (buf
, REGISTER_RAW_SIZE (O0_REGNUM
+ 2));
478 /* Don't cause a memory_error when accessing sigcontext in case the
479 stack layout has changed or the stack is corrupt. */
480 target_read_memory (sigcontext_addr
+ saved_pc_offset
,
481 scbuf
, sizeof (scbuf
));
482 return extract_address (scbuf
, sizeof (scbuf
));
484 else if (frame
->extra_info
->in_prologue
||
485 (frame
->next
!= NULL
&&
486 (frame
->next
->signal_handler_caller
||
487 frame_in_dummy (frame
->next
)) &&
488 frameless_look_for_prologue (frame
)))
490 /* A frameless function interrupted by a signal did not save
491 the PC, it is still in %o7. */
492 get_saved_register (buf
, (int *) NULL
, (CORE_ADDR
*) NULL
,
493 frame
, O7_REGNUM
, (enum lval_type
*) NULL
);
494 return PC_ADJUST (extract_address (buf
, SPARC_INTREG_SIZE
));
496 if (frame
->extra_info
->flat
)
497 addr
= frame
->extra_info
->pc_addr
;
499 addr
= frame
->extra_info
->bottom
+ FRAME_SAVED_I0
+
500 SPARC_INTREG_SIZE
* (I7_REGNUM
- I0_REGNUM
);
503 /* A flat frame leaf function might not save the PC anywhere,
504 just leave it in %o7. */
505 return PC_ADJUST (read_register (O7_REGNUM
));
507 read_memory (addr
, buf
, SPARC_INTREG_SIZE
);
508 return PC_ADJUST (extract_address (buf
, SPARC_INTREG_SIZE
));
511 /* Since an individual frame in the frame cache is defined by two
512 arguments (a frame pointer and a stack pointer), we need two
513 arguments to get info for an arbitrary stack frame. This routine
514 takes two arguments and makes the cached frames look as if these
515 two arguments defined a frame on the cache. This allows the rest
516 of info frame to extract the important arguments without
520 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
522 struct frame_info
*frame
;
525 error ("Sparc frame specifications require two arguments: fp and sp");
527 frame
= create_new_frame (argv
[0], 0);
530 internal_error (__FILE__
, __LINE__
,
531 "create_new_frame returned invalid frame");
533 frame
->extra_info
->bottom
= argv
[1];
534 frame
->pc
= FRAME_SAVED_PC (frame
);
538 /* Given a pc value, skip it forward past the function prologue by
539 disassembling instructions that appear to be a prologue.
541 If FRAMELESS_P is set, we are only testing to see if the function
542 is frameless. This allows a quicker answer.
544 This routine should be more specific in its actions; making sure
545 that it uses the same register in the initial prologue section. */
547 static CORE_ADDR
examine_prologue (CORE_ADDR
, int, struct frame_info
*,
551 examine_prologue (CORE_ADDR start_pc
, int frameless_p
, struct frame_info
*fi
,
552 CORE_ADDR
*saved_regs
)
556 CORE_ADDR pc
= start_pc
;
559 insn
= fetch_instruction (pc
);
561 /* Recognize the `sethi' insn and record its destination. */
562 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 4)
566 insn
= fetch_instruction (pc
);
569 /* Recognize an add immediate value to register to either %g1 or
570 the destination register recorded above. Actually, this might
571 well recognize several different arithmetic operations.
572 It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1"
573 followed by "save %sp, %g1, %sp" is a valid prologue (Not that
574 I imagine any compiler really does that, however). */
577 && (X_RD (insn
) == 1 || X_RD (insn
) == dest
))
580 insn
= fetch_instruction (pc
);
583 /* Recognize any SAVE insn. */
584 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 60)
587 if (frameless_p
) /* If the save is all we care about, */
588 return pc
; /* return before doing more work */
589 insn
= fetch_instruction (pc
);
591 /* Recognize add to %sp. */
592 else if (X_OP (insn
) == 2 && X_RD (insn
) == 14 && X_OP3 (insn
) == 0)
595 if (frameless_p
) /* If the add is all we care about, */
596 return pc
; /* return before doing more work */
598 insn
= fetch_instruction (pc
);
599 /* Recognize store of frame pointer (i7). */
603 && X_RS1 (insn
) == 14)
606 insn
= fetch_instruction (pc
);
608 /* Recognize sub %sp, <anything>, %i7. */
611 && X_RS1 (insn
) == 14
612 && X_RD (insn
) == 31)
615 insn
= fetch_instruction (pc
);
624 /* Without a save or add instruction, it's not a prologue. */
629 /* Recognize stores into the frame from the input registers.
630 This recognizes all non alternate stores of an input register,
631 into a location offset from the frame pointer between
634 /* The above will fail for arguments that are promoted
635 (eg. shorts to ints or floats to doubles), because the compiler
636 will pass them in positive-offset frame space, but the prologue
637 will save them (after conversion) in negative frame space at an
638 unpredictable offset. Therefore I am going to remove the
639 restriction on the target-address of the save, on the theory
640 that any unbroken sequence of saves from input registers must
641 be part of the prologue. In un-optimized code (at least), I'm
642 fairly sure that the compiler would emit SOME other instruction
643 (eg. a move or add) before emitting another save that is actually
644 a part of the function body.
646 Besides, the reserved stack space is different for SPARC64 anyway.
651 && (X_OP3 (insn
) & 0x3c) == 4 /* Store, non-alternate. */
652 && (X_RD (insn
) & 0x18) == 0x18 /* Input register. */
653 && X_I (insn
) /* Immediate mode. */
654 && X_RS1 (insn
) == 30) /* Off of frame pointer. */
655 ; /* empty statement -- fall thru to end of loop */
656 else if (GDB_TARGET_IS_SPARC64
658 && (X_OP3 (insn
) & 0x3c) == 12 /* store, extended (64-bit) */
659 && (X_RD (insn
) & 0x18) == 0x18 /* input register */
660 && X_I (insn
) /* immediate mode */
661 && X_RS1 (insn
) == 30) /* off of frame pointer */
662 ; /* empty statement -- fall thru to end of loop */
663 else if (X_OP (insn
) == 3
664 && (X_OP3 (insn
) & 0x3c) == 36 /* store, floating-point */
665 && X_I (insn
) /* immediate mode */
666 && X_RS1 (insn
) == 30) /* off of frame pointer */
667 ; /* empty statement -- fall thru to end of loop */
670 && X_OP3 (insn
) == 4 /* store? */
671 && X_RS1 (insn
) == 14) /* off of frame pointer */
673 if (saved_regs
&& X_I (insn
))
674 saved_regs
[X_RD (insn
)] =
675 fi
->frame
+ fi
->extra_info
->sp_offset
+ X_SIMM13 (insn
);
680 insn
= fetch_instruction (pc
);
687 sparc_skip_prologue (CORE_ADDR start_pc
, int frameless_p
)
689 return examine_prologue (start_pc
, frameless_p
, NULL
, NULL
);
692 /* Check instruction at ADDR to see if it is a branch.
693 All non-annulled instructions will go to NPC or will trap.
694 Set *TARGET if we find a candidate branch; set to zero if not.
696 This isn't static as it's used by remote-sa.sparc.c. */
699 isbranch (long instruction
, CORE_ADDR addr
, CORE_ADDR
*target
)
701 branch_type val
= not_branch
;
702 long int offset
= 0; /* Must be signed for sign-extend. */
706 if (X_OP (instruction
) == 0
707 && (X_OP2 (instruction
) == 2
708 || X_OP2 (instruction
) == 6
709 || X_OP2 (instruction
) == 1
710 || X_OP2 (instruction
) == 3
711 || X_OP2 (instruction
) == 5
712 || (GDB_TARGET_IS_SPARC64
&& X_OP2 (instruction
) == 7)))
714 if (X_COND (instruction
) == 8)
715 val
= X_A (instruction
) ? baa
: ba
;
717 val
= X_A (instruction
) ? bicca
: bicc
;
718 switch (X_OP2 (instruction
))
721 if (!GDB_TARGET_IS_SPARC64
)
726 offset
= 4 * X_DISP22 (instruction
);
730 offset
= 4 * X_DISP19 (instruction
);
733 offset
= 4 * X_DISP16 (instruction
);
736 *target
= addr
+ offset
;
738 else if (GDB_TARGET_IS_SPARC64
739 && X_OP (instruction
) == 2
740 && X_OP3 (instruction
) == 62)
742 if (X_FCN (instruction
) == 0)
745 *target
= read_register (TNPC_REGNUM
);
748 else if (X_FCN (instruction
) == 1)
751 *target
= read_register (TPC_REGNUM
);
759 /* Find register number REGNUM relative to FRAME and put its
760 (raw) contents in *RAW_BUFFER. Set *OPTIMIZED if the variable
761 was optimized out (and thus can't be fetched). If the variable
762 was fetched from memory, set *ADDRP to where it was fetched from,
763 otherwise it was fetched from a register.
765 The argument RAW_BUFFER must point to aligned memory. */
768 sparc_get_saved_register (char *raw_buffer
, int *optimized
, CORE_ADDR
*addrp
,
769 struct frame_info
*frame
, int regnum
,
770 enum lval_type
*lval
)
772 struct frame_info
*frame1
;
775 if (!target_has_registers
)
776 error ("No registers.");
783 /* FIXME This code extracted from infcmd.c; should put elsewhere! */
786 /* error ("No selected frame."); */
787 if (!target_has_registers
)
788 error ("The program has no registers now.");
789 if (selected_frame
== NULL
)
790 error ("No selected frame.");
791 /* Try to use selected frame */
792 frame
= get_prev_frame (selected_frame
);
794 error ("Cmd not meaningful in the outermost frame.");
798 frame1
= frame
->next
;
800 /* Get saved PC from the frame info if not in innermost frame. */
801 if (regnum
== PC_REGNUM
&& frame1
!= NULL
)
805 if (raw_buffer
!= NULL
)
807 /* Put it back in target format. */
808 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), frame
->pc
);
815 while (frame1
!= NULL
)
817 /* FIXME MVS: wrong test for dummy frame at entry. */
819 if (frame1
->pc
>= (frame1
->extra_info
->bottom
?
820 frame1
->extra_info
->bottom
: read_sp ())
821 && frame1
->pc
<= FRAME_FP (frame1
))
823 /* Dummy frame. All but the window regs are in there somewhere.
824 The window registers are saved on the stack, just like in a
826 if (regnum
>= G1_REGNUM
&& regnum
< G1_REGNUM
+ 7)
827 addr
= frame1
->frame
+ (regnum
- G0_REGNUM
) * SPARC_INTREG_SIZE
828 - (FP_REGISTER_BYTES
+ 8 * SPARC_INTREG_SIZE
);
829 else if (regnum
>= I0_REGNUM
&& regnum
< I0_REGNUM
+ 8)
830 addr
= (frame1
->prev
->extra_info
->bottom
831 + (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
833 else if (regnum
>= L0_REGNUM
&& regnum
< L0_REGNUM
+ 8)
834 addr
= (frame1
->prev
->extra_info
->bottom
835 + (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
837 else if (regnum
>= O0_REGNUM
&& regnum
< O0_REGNUM
+ 8)
838 addr
= frame1
->frame
+ (regnum
- O0_REGNUM
) * SPARC_INTREG_SIZE
839 - (FP_REGISTER_BYTES
+ 16 * SPARC_INTREG_SIZE
);
840 else if (SPARC_HAS_FPU
&&
841 regnum
>= FP0_REGNUM
&& regnum
< FP0_REGNUM
+ 32)
842 addr
= frame1
->frame
+ (regnum
- FP0_REGNUM
) * 4
843 - (FP_REGISTER_BYTES
);
844 else if (GDB_TARGET_IS_SPARC64
&& SPARC_HAS_FPU
&&
845 regnum
>= FP0_REGNUM
+ 32 && regnum
< FP_MAX_REGNUM
)
846 addr
= frame1
->frame
+ 32 * 4 + (regnum
- FP0_REGNUM
- 32) * 8
847 - (FP_REGISTER_BYTES
);
848 else if (regnum
>= Y_REGNUM
&& regnum
< NUM_REGS
)
849 addr
= frame1
->frame
+ (regnum
- Y_REGNUM
) * SPARC_INTREG_SIZE
850 - (FP_REGISTER_BYTES
+ 24 * SPARC_INTREG_SIZE
);
852 else if (frame1
->extra_info
->flat
)
855 if (regnum
== RP_REGNUM
)
856 addr
= frame1
->extra_info
->pc_addr
;
857 else if (regnum
== I7_REGNUM
)
858 addr
= frame1
->extra_info
->fp_addr
;
861 CORE_ADDR func_start
;
864 regs
= alloca (NUM_REGS
* sizeof (CORE_ADDR
));
865 memset (regs
, 0, NUM_REGS
* sizeof (CORE_ADDR
));
867 find_pc_partial_function (frame1
->pc
, NULL
, &func_start
, NULL
);
868 examine_prologue (func_start
, 0, frame1
, regs
);
874 /* Normal frame. Local and In registers are saved on stack. */
875 if (regnum
>= I0_REGNUM
&& regnum
< I0_REGNUM
+ 8)
876 addr
= (frame1
->prev
->extra_info
->bottom
877 + (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
879 else if (regnum
>= L0_REGNUM
&& regnum
< L0_REGNUM
+ 8)
880 addr
= (frame1
->prev
->extra_info
->bottom
881 + (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
883 else if (regnum
>= O0_REGNUM
&& regnum
< O0_REGNUM
+ 8)
885 /* Outs become ins. */
886 get_saved_register (raw_buffer
, optimized
, addrp
, frame1
,
887 (regnum
- O0_REGNUM
+ I0_REGNUM
), lval
);
893 frame1
= frame1
->next
;
899 if (regnum
== SP_REGNUM
)
901 if (raw_buffer
!= NULL
)
903 /* Put it back in target format. */
904 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), addr
);
910 if (raw_buffer
!= NULL
)
911 read_memory (addr
, raw_buffer
, REGISTER_RAW_SIZE (regnum
));
916 *lval
= lval_register
;
917 addr
= REGISTER_BYTE (regnum
);
918 if (raw_buffer
!= NULL
)
919 read_register_gen (regnum
, raw_buffer
);
925 /* Push an empty stack frame, and record in it the current PC, regs, etc.
927 We save the non-windowed registers and the ins. The locals and outs
928 are new; they don't need to be saved. The i's and l's of
929 the last frame were already saved on the stack. */
931 /* Definitely see tm-sparc.h for more doc of the frame format here. */
933 /* See tm-sparc.h for how this is calculated. */
935 #define DUMMY_STACK_REG_BUF_SIZE \
936 (((8+8+8) * SPARC_INTREG_SIZE) + FP_REGISTER_BYTES)
937 #define DUMMY_STACK_SIZE \
938 (DUMMY_STACK_REG_BUF_SIZE + DUMMY_REG_SAVE_OFFSET)
941 sparc_push_dummy_frame (void)
943 CORE_ADDR sp
, old_sp
;
946 register_temp
= alloca (DUMMY_STACK_SIZE
);
948 old_sp
= sp
= read_sp ();
950 if (GDB_TARGET_IS_SPARC64
)
952 /* PC, NPC, CCR, FSR, FPRS, Y, ASI */
953 read_register_bytes (REGISTER_BYTE (PC_REGNUM
), ®ister_temp
[0],
954 REGISTER_RAW_SIZE (PC_REGNUM
) * 7);
955 read_register_bytes (REGISTER_BYTE (PSTATE_REGNUM
),
956 ®ister_temp
[7 * SPARC_INTREG_SIZE
],
957 REGISTER_RAW_SIZE (PSTATE_REGNUM
));
958 /* FIXME: not sure what needs to be saved here. */
962 /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */
963 read_register_bytes (REGISTER_BYTE (Y_REGNUM
), ®ister_temp
[0],
964 REGISTER_RAW_SIZE (Y_REGNUM
) * 8);
967 read_register_bytes (REGISTER_BYTE (O0_REGNUM
),
968 ®ister_temp
[8 * SPARC_INTREG_SIZE
],
969 SPARC_INTREG_SIZE
* 8);
971 read_register_bytes (REGISTER_BYTE (G0_REGNUM
),
972 ®ister_temp
[16 * SPARC_INTREG_SIZE
],
973 SPARC_INTREG_SIZE
* 8);
976 read_register_bytes (REGISTER_BYTE (FP0_REGNUM
),
977 ®ister_temp
[24 * SPARC_INTREG_SIZE
],
980 sp
-= DUMMY_STACK_SIZE
;
984 write_memory (sp
+ DUMMY_REG_SAVE_OFFSET
, ®ister_temp
[0],
985 DUMMY_STACK_REG_BUF_SIZE
);
987 if (strcmp (target_shortname
, "sim") != 0)
989 /* NOTE: cagney/2002-04-04: The code below originally contained
990 GDB's _only_ call to write_fp(). That call was eliminated by
991 inlining the corresponding code. For the 64 bit case, the
992 old function (sparc64_write_fp) did the below although I'm
993 not clear why. The same goes for why this is only done when
994 the underlying target is a simulator. */
995 if (gdbarch_tdep (current_gdbarch
)->intreg_size
== 8)
997 /* Target is a 64 bit SPARC. */
998 CORE_ADDR oldfp
= read_register (FP_REGNUM
);
1000 write_register (FP_REGNUM
, old_sp
- 2047);
1002 write_register (FP_REGNUM
, old_sp
);
1006 /* Target is a 32 bit SPARC. */
1007 write_register (FP_REGNUM
, old_sp
);
1009 /* Set return address register for the call dummy to the current PC. */
1010 write_register (I7_REGNUM
, read_pc () - 8);
1014 /* The call dummy will write this value to FP before executing
1015 the 'save'. This ensures that register window flushes work
1016 correctly in the simulator. */
1017 write_register (G0_REGNUM
+ 1, read_register (FP_REGNUM
));
1019 /* The call dummy will write this value to FP after executing
1021 write_register (G0_REGNUM
+ 2, old_sp
);
1023 /* The call dummy will write this value to the return address (%i7) after
1024 executing the 'save'. */
1025 write_register (G0_REGNUM
+ 3, read_pc () - 8);
1027 /* Set the FP that the call dummy will be using after the 'save'.
1028 This makes backtraces from an inferior function call work properly. */
1029 write_register (FP_REGNUM
, old_sp
);
1033 /* sparc_frame_find_saved_regs (). This function is here only because
1034 pop_frame uses it. Note there is an interesting corner case which
1035 I think few ports of GDB get right--if you are popping a frame
1036 which does not save some register that *is* saved by a more inner
1037 frame (such a frame will never be a dummy frame because dummy
1038 frames save all registers). Rewriting pop_frame to use
1039 get_saved_register would solve this problem and also get rid of the
1040 ugly duplication between sparc_frame_find_saved_regs and
1043 Stores, into an array of CORE_ADDR,
1044 the addresses of the saved registers of frame described by FRAME_INFO.
1045 This includes special registers such as pc and fp saved in special
1046 ways in the stack frame. sp is even more special:
1047 the address we return for it IS the sp for the next frame.
1049 Note that on register window machines, we are currently making the
1050 assumption that window registers are being saved somewhere in the
1051 frame in which they are being used. If they are stored in an
1052 inferior frame, find_saved_register will break.
1054 On the Sun 4, the only time all registers are saved is when
1055 a dummy frame is involved. Otherwise, the only saved registers
1056 are the LOCAL and IN registers which are saved as a result
1057 of the "save/restore" opcodes. This condition is determined
1058 by address rather than by value.
1060 The "pc" is not stored in a frame on the SPARC. (What is stored
1061 is a return address minus 8.) sparc_pop_frame knows how to
1062 deal with that. Other routines might or might not.
1064 See tm-sparc.h (PUSH_DUMMY_FRAME and friends) for CRITICAL information
1065 about how this works. */
1067 static void sparc_frame_find_saved_regs (struct frame_info
*, CORE_ADDR
*);
1070 sparc_frame_find_saved_regs (struct frame_info
*fi
, CORE_ADDR
*saved_regs_addr
)
1072 register int regnum
;
1073 CORE_ADDR frame_addr
= FRAME_FP (fi
);
1076 internal_error (__FILE__
, __LINE__
,
1077 "Bad frame info struct in FRAME_FIND_SAVED_REGS");
1079 memset (saved_regs_addr
, 0, NUM_REGS
* sizeof (CORE_ADDR
));
1081 if (fi
->pc
>= (fi
->extra_info
->bottom
?
1082 fi
->extra_info
->bottom
: read_sp ())
1083 && fi
->pc
<= FRAME_FP (fi
))
1085 /* Dummy frame. All but the window regs are in there somewhere. */
1086 for (regnum
= G1_REGNUM
; regnum
< G1_REGNUM
+ 7; regnum
++)
1087 saved_regs_addr
[regnum
] =
1088 frame_addr
+ (regnum
- G0_REGNUM
) * SPARC_INTREG_SIZE
1089 - DUMMY_STACK_REG_BUF_SIZE
+ 16 * SPARC_INTREG_SIZE
;
1091 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+ 8; regnum
++)
1092 saved_regs_addr
[regnum
] =
1093 frame_addr
+ (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
1094 - DUMMY_STACK_REG_BUF_SIZE
+ 8 * SPARC_INTREG_SIZE
;
1097 for (regnum
= FP0_REGNUM
; regnum
< FP_MAX_REGNUM
; regnum
++)
1098 saved_regs_addr
[regnum
] = frame_addr
+ (regnum
- FP0_REGNUM
) * 4
1099 - DUMMY_STACK_REG_BUF_SIZE
+ 24 * SPARC_INTREG_SIZE
;
1101 if (GDB_TARGET_IS_SPARC64
)
1103 for (regnum
= PC_REGNUM
; regnum
< PC_REGNUM
+ 7; regnum
++)
1105 saved_regs_addr
[regnum
] =
1106 frame_addr
+ (regnum
- PC_REGNUM
) * SPARC_INTREG_SIZE
1107 - DUMMY_STACK_REG_BUF_SIZE
;
1109 saved_regs_addr
[PSTATE_REGNUM
] =
1110 frame_addr
+ 8 * SPARC_INTREG_SIZE
- DUMMY_STACK_REG_BUF_SIZE
;
1113 for (regnum
= Y_REGNUM
; regnum
< NUM_REGS
; regnum
++)
1114 saved_regs_addr
[regnum
] =
1115 frame_addr
+ (regnum
- Y_REGNUM
) * SPARC_INTREG_SIZE
1116 - DUMMY_STACK_REG_BUF_SIZE
;
1118 frame_addr
= fi
->extra_info
->bottom
?
1119 fi
->extra_info
->bottom
: read_sp ();
1121 else if (fi
->extra_info
->flat
)
1123 CORE_ADDR func_start
;
1124 find_pc_partial_function (fi
->pc
, NULL
, &func_start
, NULL
);
1125 examine_prologue (func_start
, 0, fi
, saved_regs_addr
);
1127 /* Flat register window frame. */
1128 saved_regs_addr
[RP_REGNUM
] = fi
->extra_info
->pc_addr
;
1129 saved_regs_addr
[I7_REGNUM
] = fi
->extra_info
->fp_addr
;
1133 /* Normal frame. Just Local and In registers */
1134 frame_addr
= fi
->extra_info
->bottom
?
1135 fi
->extra_info
->bottom
: read_sp ();
1136 for (regnum
= L0_REGNUM
; regnum
< L0_REGNUM
+ 8; regnum
++)
1137 saved_regs_addr
[regnum
] =
1138 (frame_addr
+ (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
1140 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+ 8; regnum
++)
1141 saved_regs_addr
[regnum
] =
1142 (frame_addr
+ (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
1147 if (fi
->extra_info
->flat
)
1149 saved_regs_addr
[O7_REGNUM
] = fi
->extra_info
->pc_addr
;
1153 /* Pull off either the next frame pointer or the stack pointer */
1154 CORE_ADDR next_next_frame_addr
=
1155 (fi
->next
->extra_info
->bottom
?
1156 fi
->next
->extra_info
->bottom
: read_sp ());
1157 for (regnum
= O0_REGNUM
; regnum
< O0_REGNUM
+ 8; regnum
++)
1158 saved_regs_addr
[regnum
] =
1159 (next_next_frame_addr
1160 + (regnum
- O0_REGNUM
) * SPARC_INTREG_SIZE
1164 /* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */
1165 /* FIXME -- should this adjust for the sparc64 offset? */
1166 saved_regs_addr
[SP_REGNUM
] = FRAME_FP (fi
);
1169 /* Discard from the stack the innermost frame, restoring all saved registers.
1171 Note that the values stored in fsr by get_frame_saved_regs are *in
1172 the context of the called frame*. What this means is that the i
1173 regs of fsr must be restored into the o regs of the (calling) frame that
1174 we pop into. We don't care about the output regs of the calling frame,
1175 since unless it's a dummy frame, it won't have any output regs in it.
1177 We never have to bother with %l (local) regs, since the called routine's
1178 locals get tossed, and the calling routine's locals are already saved
1181 /* Definitely see tm-sparc.h for more doc of the frame format here. */
1184 sparc_pop_frame (void)
1186 register struct frame_info
*frame
= get_current_frame ();
1187 register CORE_ADDR pc
;
1192 fsr
= alloca (NUM_REGS
* sizeof (CORE_ADDR
));
1193 raw_buffer
= alloca (REGISTER_BYTES
);
1194 sparc_frame_find_saved_regs (frame
, &fsr
[0]);
1197 if (fsr
[FP0_REGNUM
])
1199 read_memory (fsr
[FP0_REGNUM
], raw_buffer
, FP_REGISTER_BYTES
);
1200 write_register_bytes (REGISTER_BYTE (FP0_REGNUM
),
1201 raw_buffer
, FP_REGISTER_BYTES
);
1203 if (!(GDB_TARGET_IS_SPARC64
))
1205 if (fsr
[FPS_REGNUM
])
1207 read_memory (fsr
[FPS_REGNUM
], raw_buffer
, SPARC_INTREG_SIZE
);
1208 write_register_gen (FPS_REGNUM
, raw_buffer
);
1210 if (fsr
[CPS_REGNUM
])
1212 read_memory (fsr
[CPS_REGNUM
], raw_buffer
, SPARC_INTREG_SIZE
);
1213 write_register_gen (CPS_REGNUM
, raw_buffer
);
1219 read_memory (fsr
[G1_REGNUM
], raw_buffer
, 7 * SPARC_INTREG_SIZE
);
1220 write_register_bytes (REGISTER_BYTE (G1_REGNUM
), raw_buffer
,
1221 7 * SPARC_INTREG_SIZE
);
1224 if (frame
->extra_info
->flat
)
1226 /* Each register might or might not have been saved, need to test
1228 for (regnum
= L0_REGNUM
; regnum
< L0_REGNUM
+ 8; ++regnum
)
1230 write_register (regnum
, read_memory_integer (fsr
[regnum
],
1231 SPARC_INTREG_SIZE
));
1232 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+ 8; ++regnum
)
1234 write_register (regnum
, read_memory_integer (fsr
[regnum
],
1235 SPARC_INTREG_SIZE
));
1237 /* Handle all outs except stack pointer (o0-o5; o7). */
1238 for (regnum
= O0_REGNUM
; regnum
< O0_REGNUM
+ 6; ++regnum
)
1240 write_register (regnum
, read_memory_integer (fsr
[regnum
],
1241 SPARC_INTREG_SIZE
));
1242 if (fsr
[O0_REGNUM
+ 7])
1243 write_register (O0_REGNUM
+ 7,
1244 read_memory_integer (fsr
[O0_REGNUM
+ 7],
1245 SPARC_INTREG_SIZE
));
1247 write_sp (frame
->frame
);
1249 else if (fsr
[I0_REGNUM
])
1255 reg_temp
= alloca (REGISTER_BYTES
);
1257 read_memory (fsr
[I0_REGNUM
], raw_buffer
, 8 * SPARC_INTREG_SIZE
);
1259 /* Get the ins and locals which we are about to restore. Just
1260 moving the stack pointer is all that is really needed, except
1261 store_inferior_registers is then going to write the ins and
1262 locals from the registers array, so we need to muck with the
1264 sp
= fsr
[SP_REGNUM
];
1266 if (GDB_TARGET_IS_SPARC64
&& (sp
& 1))
1269 read_memory (sp
, reg_temp
, SPARC_INTREG_SIZE
* 16);
1271 /* Restore the out registers.
1272 Among other things this writes the new stack pointer. */
1273 write_register_bytes (REGISTER_BYTE (O0_REGNUM
), raw_buffer
,
1274 SPARC_INTREG_SIZE
* 8);
1276 write_register_bytes (REGISTER_BYTE (L0_REGNUM
), reg_temp
,
1277 SPARC_INTREG_SIZE
* 16);
1280 if (!(GDB_TARGET_IS_SPARC64
))
1282 write_register (PS_REGNUM
,
1283 read_memory_integer (fsr
[PS_REGNUM
],
1284 REGISTER_RAW_SIZE (PS_REGNUM
)));
1287 write_register (Y_REGNUM
,
1288 read_memory_integer (fsr
[Y_REGNUM
],
1289 REGISTER_RAW_SIZE (Y_REGNUM
)));
1292 /* Explicitly specified PC (and maybe NPC) -- just restore them. */
1293 write_register (PC_REGNUM
,
1294 read_memory_integer (fsr
[PC_REGNUM
],
1295 REGISTER_RAW_SIZE (PC_REGNUM
)));
1296 if (fsr
[NPC_REGNUM
])
1297 write_register (NPC_REGNUM
,
1298 read_memory_integer (fsr
[NPC_REGNUM
],
1299 REGISTER_RAW_SIZE (NPC_REGNUM
)));
1301 else if (frame
->extra_info
->flat
)
1303 if (frame
->extra_info
->pc_addr
)
1304 pc
= PC_ADJUST ((CORE_ADDR
)
1305 read_memory_integer (frame
->extra_info
->pc_addr
,
1306 REGISTER_RAW_SIZE (PC_REGNUM
)));
1309 /* I think this happens only in the innermost frame, if so then
1310 it is a complicated way of saying
1311 "pc = read_register (O7_REGNUM);". */
1314 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
1315 get_saved_register (buf
, 0, 0, frame
, O7_REGNUM
, 0);
1316 pc
= PC_ADJUST (extract_address
1317 (buf
, REGISTER_RAW_SIZE (O7_REGNUM
)));
1320 write_register (PC_REGNUM
, pc
);
1321 write_register (NPC_REGNUM
, pc
+ 4);
1323 else if (fsr
[I7_REGNUM
])
1325 /* Return address in %i7 -- adjust it, then restore PC and NPC from it */
1326 pc
= PC_ADJUST ((CORE_ADDR
) read_memory_integer (fsr
[I7_REGNUM
],
1327 SPARC_INTREG_SIZE
));
1328 write_register (PC_REGNUM
, pc
);
1329 write_register (NPC_REGNUM
, pc
+ 4);
1331 flush_cached_frames ();
1334 /* On the Sun 4 under SunOS, the compile will leave a fake insn which
1335 encodes the structure size being returned. If we detect such
1336 a fake insn, step past it. */
1339 sparc_pc_adjust (CORE_ADDR pc
)
1345 err
= target_read_memory (pc
+ 8, buf
, 4);
1346 insn
= extract_unsigned_integer (buf
, 4);
1347 if ((err
== 0) && (insn
& 0xffc00000) == 0)
1353 /* If pc is in a shared library trampoline, return its target.
1354 The SunOs 4.x linker rewrites the jump table entries for PIC
1355 compiled modules in the main executable to bypass the dynamic linker
1356 with jumps of the form
1359 and removes the corresponding jump table relocation entry in the
1360 dynamic relocations.
1361 find_solib_trampoline_target relies on the presence of the jump
1362 table relocation entry, so we have to detect these jump instructions
1366 sunos4_skip_trampoline_code (CORE_ADDR pc
)
1368 unsigned long insn1
;
1372 err
= target_read_memory (pc
, buf
, 4);
1373 insn1
= extract_unsigned_integer (buf
, 4);
1374 if (err
== 0 && (insn1
& 0xffc00000) == 0x03000000)
1376 unsigned long insn2
;
1378 err
= target_read_memory (pc
+ 4, buf
, 4);
1379 insn2
= extract_unsigned_integer (buf
, 4);
1380 if (err
== 0 && (insn2
& 0xffffe000) == 0x81c06000)
1382 CORE_ADDR target_pc
= (insn1
& 0x3fffff) << 10;
1383 int delta
= insn2
& 0x1fff;
1385 /* Sign extend the displacement. */
1388 return target_pc
+ delta
;
1391 return find_solib_trampoline_target (pc
);
1394 #ifdef USE_PROC_FS /* Target dependent support for /proc */
1396 /* The /proc interface divides the target machine's register set up into
1397 two different sets, the general register set (gregset) and the floating
1398 point register set (fpregset). For each set, there is an ioctl to get
1399 the current register set and another ioctl to set the current values.
1401 The actual structure passed through the ioctl interface is, of course,
1402 naturally machine dependent, and is different for each set of registers.
1403 For the sparc for example, the general register set is typically defined
1406 typedef int gregset_t[38];
1412 and the floating point set by:
1414 typedef struct prfpregset {
1417 double pr_dregs[16];
1422 u_char pr_q_entrysize;
1427 These routines provide the packing and unpacking of gregset_t and
1428 fpregset_t formatted data.
1433 /* Given a pointer to a general register set in /proc format (gregset_t *),
1434 unpack the register contents and supply them as gdb's idea of the current
1438 supply_gregset (gdb_gregset_t
*gregsetp
)
1440 prgreg_t
*regp
= (prgreg_t
*) gregsetp
;
1441 int regi
, offset
= 0;
1443 /* If the host is 64-bit sparc, but the target is 32-bit sparc,
1444 then the gregset may contain 64-bit ints while supply_register
1445 is expecting 32-bit ints. Compensate. */
1446 if (sizeof (regp
[0]) == 8 && SPARC_INTREG_SIZE
== 4)
1449 /* GDB register numbers for Gn, On, Ln, In all match /proc reg numbers. */
1450 /* FIXME MVS: assumes the order of the first 32 elements... */
1451 for (regi
= G0_REGNUM
; regi
<= I7_REGNUM
; regi
++)
1453 supply_register (regi
, ((char *) (regp
+ regi
)) + offset
);
1456 /* These require a bit more care. */
1457 supply_register (PC_REGNUM
, ((char *) (regp
+ R_PC
)) + offset
);
1458 supply_register (NPC_REGNUM
, ((char *) (regp
+ R_nPC
)) + offset
);
1459 supply_register (Y_REGNUM
, ((char *) (regp
+ R_Y
)) + offset
);
1461 if (GDB_TARGET_IS_SPARC64
)
1464 supply_register (CCR_REGNUM
, ((char *) (regp
+ R_CCR
)) + offset
);
1466 supply_register (CCR_REGNUM
, NULL
);
1469 supply_register (FPRS_REGNUM
, ((char *) (regp
+ R_FPRS
)) + offset
);
1471 supply_register (FPRS_REGNUM
, NULL
);
1474 supply_register (ASI_REGNUM
, ((char *) (regp
+ R_ASI
)) + offset
);
1476 supply_register (ASI_REGNUM
, NULL
);
1482 supply_register (PS_REGNUM
, ((char *) (regp
+ R_PS
)) + offset
);
1484 supply_register (PS_REGNUM
, NULL
);
1487 /* For 64-bit hosts, R_WIM and R_TBR may not be defined.
1488 Steal R_ASI and R_FPRS, and hope for the best! */
1490 #if !defined (R_WIM) && defined (R_ASI)
1494 #if !defined (R_TBR) && defined (R_FPRS)
1495 #define R_TBR R_FPRS
1499 supply_register (WIM_REGNUM
, ((char *) (regp
+ R_WIM
)) + offset
);
1501 supply_register (WIM_REGNUM
, NULL
);
1505 supply_register (TBR_REGNUM
, ((char *) (regp
+ R_TBR
)) + offset
);
1507 supply_register (TBR_REGNUM
, NULL
);
1511 /* Fill inaccessible registers with zero. */
1512 if (GDB_TARGET_IS_SPARC64
)
1515 * don't know how to get value of any of the following:
1517 supply_register (VER_REGNUM
, NULL
);
1518 supply_register (TICK_REGNUM
, NULL
);
1519 supply_register (PIL_REGNUM
, NULL
);
1520 supply_register (PSTATE_REGNUM
, NULL
);
1521 supply_register (TSTATE_REGNUM
, NULL
);
1522 supply_register (TBA_REGNUM
, NULL
);
1523 supply_register (TL_REGNUM
, NULL
);
1524 supply_register (TT_REGNUM
, NULL
);
1525 supply_register (TPC_REGNUM
, NULL
);
1526 supply_register (TNPC_REGNUM
, NULL
);
1527 supply_register (WSTATE_REGNUM
, NULL
);
1528 supply_register (CWP_REGNUM
, NULL
);
1529 supply_register (CANSAVE_REGNUM
, NULL
);
1530 supply_register (CANRESTORE_REGNUM
, NULL
);
1531 supply_register (CLEANWIN_REGNUM
, NULL
);
1532 supply_register (OTHERWIN_REGNUM
, NULL
);
1533 supply_register (ASR16_REGNUM
, NULL
);
1534 supply_register (ASR17_REGNUM
, NULL
);
1535 supply_register (ASR18_REGNUM
, NULL
);
1536 supply_register (ASR19_REGNUM
, NULL
);
1537 supply_register (ASR20_REGNUM
, NULL
);
1538 supply_register (ASR21_REGNUM
, NULL
);
1539 supply_register (ASR22_REGNUM
, NULL
);
1540 supply_register (ASR23_REGNUM
, NULL
);
1541 supply_register (ASR24_REGNUM
, NULL
);
1542 supply_register (ASR25_REGNUM
, NULL
);
1543 supply_register (ASR26_REGNUM
, NULL
);
1544 supply_register (ASR27_REGNUM
, NULL
);
1545 supply_register (ASR28_REGNUM
, NULL
);
1546 supply_register (ASR29_REGNUM
, NULL
);
1547 supply_register (ASR30_REGNUM
, NULL
);
1548 supply_register (ASR31_REGNUM
, NULL
);
1549 supply_register (ICC_REGNUM
, NULL
);
1550 supply_register (XCC_REGNUM
, NULL
);
1554 supply_register (CPS_REGNUM
, NULL
);
1559 fill_gregset (gdb_gregset_t
*gregsetp
, int regno
)
1561 prgreg_t
*regp
= (prgreg_t
*) gregsetp
;
1562 int regi
, offset
= 0;
1564 /* If the host is 64-bit sparc, but the target is 32-bit sparc,
1565 then the gregset may contain 64-bit ints while supply_register
1566 is expecting 32-bit ints. Compensate. */
1567 if (sizeof (regp
[0]) == 8 && SPARC_INTREG_SIZE
== 4)
1570 for (regi
= 0; regi
<= R_I7
; regi
++)
1571 if ((regno
== -1) || (regno
== regi
))
1572 read_register_gen (regi
, (char *) (regp
+ regi
) + offset
);
1574 if ((regno
== -1) || (regno
== PC_REGNUM
))
1575 read_register_gen (PC_REGNUM
, (char *) (regp
+ R_PC
) + offset
);
1577 if ((regno
== -1) || (regno
== NPC_REGNUM
))
1578 read_register_gen (NPC_REGNUM
, (char *) (regp
+ R_nPC
) + offset
);
1580 if ((regno
== -1) || (regno
== Y_REGNUM
))
1581 read_register_gen (Y_REGNUM
, (char *) (regp
+ R_Y
) + offset
);
1583 if (GDB_TARGET_IS_SPARC64
)
1586 if (regno
== -1 || regno
== CCR_REGNUM
)
1587 read_register_gen (CCR_REGNUM
, ((char *) (regp
+ R_CCR
)) + offset
);
1590 if (regno
== -1 || regno
== FPRS_REGNUM
)
1591 read_register_gen (FPRS_REGNUM
, ((char *) (regp
+ R_FPRS
)) + offset
);
1594 if (regno
== -1 || regno
== ASI_REGNUM
)
1595 read_register_gen (ASI_REGNUM
, ((char *) (regp
+ R_ASI
)) + offset
);
1601 if (regno
== -1 || regno
== PS_REGNUM
)
1602 read_register_gen (PS_REGNUM
, ((char *) (regp
+ R_PS
)) + offset
);
1605 /* For 64-bit hosts, R_WIM and R_TBR may not be defined.
1606 Steal R_ASI and R_FPRS, and hope for the best! */
1608 #if !defined (R_WIM) && defined (R_ASI)
1612 #if !defined (R_TBR) && defined (R_FPRS)
1613 #define R_TBR R_FPRS
1617 if (regno
== -1 || regno
== WIM_REGNUM
)
1618 read_register_gen (WIM_REGNUM
, ((char *) (regp
+ R_WIM
)) + offset
);
1620 if (regno
== -1 || regno
== WIM_REGNUM
)
1621 read_register_gen (WIM_REGNUM
, NULL
);
1625 if (regno
== -1 || regno
== TBR_REGNUM
)
1626 read_register_gen (TBR_REGNUM
, ((char *) (regp
+ R_TBR
)) + offset
);
1628 if (regno
== -1 || regno
== TBR_REGNUM
)
1629 read_register_gen (TBR_REGNUM
, NULL
);
1634 /* Given a pointer to a floating point register set in /proc format
1635 (fpregset_t *), unpack the register contents and supply them as gdb's
1636 idea of the current floating point register values. */
1639 supply_fpregset (gdb_fpregset_t
*fpregsetp
)
1647 for (regi
= FP0_REGNUM
; regi
< FP_MAX_REGNUM
; regi
++)
1649 from
= (char *) &fpregsetp
->pr_fr
.pr_regs
[regi
- FP0_REGNUM
];
1650 supply_register (regi
, from
);
1653 if (GDB_TARGET_IS_SPARC64
)
1656 * don't know how to get value of the following.
1658 supply_register (FSR_REGNUM
, NULL
); /* zero it out for now */
1659 supply_register (FCC0_REGNUM
, NULL
);
1660 supply_register (FCC1_REGNUM
, NULL
); /* don't know how to get value */
1661 supply_register (FCC2_REGNUM
, NULL
); /* don't know how to get value */
1662 supply_register (FCC3_REGNUM
, NULL
); /* don't know how to get value */
1666 supply_register (FPS_REGNUM
, (char *) &(fpregsetp
->pr_fsr
));
1670 /* Given a pointer to a floating point register set in /proc format
1671 (fpregset_t *), update the register specified by REGNO from gdb's idea
1672 of the current floating point register set. If REGNO is -1, update
1674 /* This will probably need some changes for sparc64. */
1677 fill_fpregset (gdb_fpregset_t
*fpregsetp
, int regno
)
1686 for (regi
= FP0_REGNUM
; regi
< FP_MAX_REGNUM
; regi
++)
1688 if ((regno
== -1) || (regno
== regi
))
1690 from
= (char *) ®isters
[REGISTER_BYTE (regi
)];
1691 to
= (char *) &fpregsetp
->pr_fr
.pr_regs
[regi
- FP0_REGNUM
];
1692 memcpy (to
, from
, REGISTER_RAW_SIZE (regi
));
1696 if (!(GDB_TARGET_IS_SPARC64
)) /* FIXME: does Sparc64 have this register? */
1697 if ((regno
== -1) || (regno
== FPS_REGNUM
))
1699 from
= (char *)®isters
[REGISTER_BYTE (FPS_REGNUM
)];
1700 to
= (char *) &fpregsetp
->pr_fsr
;
1701 memcpy (to
, from
, REGISTER_RAW_SIZE (FPS_REGNUM
));
1705 #endif /* USE_PROC_FS */
1707 /* Because of Multi-arch, GET_LONGJMP_TARGET is always defined. So test
1708 for a definition of JB_PC. */
1711 /* Figure out where the longjmp will land. We expect that we have just entered
1712 longjmp and haven't yet setup the stack frame, so the args are still in the
1713 output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we
1714 extract the pc (JB_PC) that we will land at. The pc is copied into ADDR.
1715 This routine returns true on success */
1718 get_longjmp_target (CORE_ADDR
*pc
)
1721 #define LONGJMP_TARGET_SIZE 4
1722 char buf
[LONGJMP_TARGET_SIZE
];
1724 jb_addr
= read_register (O0_REGNUM
);
1726 if (target_read_memory (jb_addr
+ JB_PC
* JB_ELEMENT_SIZE
, buf
,
1727 LONGJMP_TARGET_SIZE
))
1730 *pc
= extract_address (buf
, LONGJMP_TARGET_SIZE
);
1734 #endif /* GET_LONGJMP_TARGET */
1736 #ifdef STATIC_TRANSFORM_NAME
1737 /* SunPRO (3.0 at least), encodes the static variables. This is not
1738 related to C++ mangling, it is done for C too. */
1741 sunpro_static_transform_name (char *name
)
1746 /* For file-local statics there will be a dollar sign, a bunch
1747 of junk (the contents of which match a string given in the
1748 N_OPT), a period and the name. For function-local statics
1749 there will be a bunch of junk (which seems to change the
1750 second character from 'A' to 'B'), a period, the name of the
1751 function, and the name. So just skip everything before the
1753 p
= strrchr (name
, '.');
1759 #endif /* STATIC_TRANSFORM_NAME */
1762 /* Utilities for printing registers.
1763 Page numbers refer to the SPARC Architecture Manual. */
1765 static void dump_ccreg (char *, int);
1768 dump_ccreg (char *reg
, int val
)
1771 printf_unfiltered ("%s:%s,%s,%s,%s", reg
,
1772 val
& 8 ? "N" : "NN",
1773 val
& 4 ? "Z" : "NZ",
1774 val
& 2 ? "O" : "NO",
1775 val
& 1 ? "C" : "NC");
1779 decode_asi (int val
)
1785 return "ASI_NUCLEUS";
1787 return "ASI_NUCLEUS_LITTLE";
1789 return "ASI_AS_IF_USER_PRIMARY";
1791 return "ASI_AS_IF_USER_SECONDARY";
1793 return "ASI_AS_IF_USER_PRIMARY_LITTLE";
1795 return "ASI_AS_IF_USER_SECONDARY_LITTLE";
1797 return "ASI_PRIMARY";
1799 return "ASI_SECONDARY";
1801 return "ASI_PRIMARY_NOFAULT";
1803 return "ASI_SECONDARY_NOFAULT";
1805 return "ASI_PRIMARY_LITTLE";
1807 return "ASI_SECONDARY_LITTLE";
1809 return "ASI_PRIMARY_NOFAULT_LITTLE";
1811 return "ASI_SECONDARY_NOFAULT_LITTLE";
1817 /* PRINT_REGISTER_HOOK routine.
1818 Pretty print various registers. */
1819 /* FIXME: Would be nice if this did some fancy things for 32 bit sparc. */
1822 sparc_print_register_hook (int regno
)
1826 /* Handle double/quad versions of lower 32 fp regs. */
1827 if (regno
>= FP0_REGNUM
&& regno
< FP0_REGNUM
+ 32
1828 && (regno
& 1) == 0)
1832 if (!read_relative_register_raw_bytes (regno
, value
)
1833 && !read_relative_register_raw_bytes (regno
+ 1, value
+ 4))
1835 printf_unfiltered ("\t");
1836 print_floating (value
, builtin_type_double
, gdb_stdout
);
1838 #if 0 /* FIXME: gdb doesn't handle long doubles */
1839 if ((regno
& 3) == 0)
1841 if (!read_relative_register_raw_bytes (regno
+ 2, value
+ 8)
1842 && !read_relative_register_raw_bytes (regno
+ 3, value
+ 12))
1844 printf_unfiltered ("\t");
1845 print_floating (value
, builtin_type_long_double
, gdb_stdout
);
1852 #if 0 /* FIXME: gdb doesn't handle long doubles */
1853 /* Print upper fp regs as long double if appropriate. */
1854 if (regno
>= FP0_REGNUM
+ 32 && regno
< FP_MAX_REGNUM
1855 /* We test for even numbered regs and not a multiple of 4 because
1856 the upper fp regs are recorded as doubles. */
1857 && (regno
& 1) == 0)
1861 if (!read_relative_register_raw_bytes (regno
, value
)
1862 && !read_relative_register_raw_bytes (regno
+ 1, value
+ 8))
1864 printf_unfiltered ("\t");
1865 print_floating (value
, builtin_type_long_double
, gdb_stdout
);
1871 /* FIXME: Some of these are priviledged registers.
1872 Not sure how they should be handled. */
1874 #define BITS(n, mask) ((int) (((val) >> (n)) & (mask)))
1876 val
= read_register (regno
);
1879 if (GDB_TARGET_IS_SPARC64
)
1883 printf_unfiltered ("\t");
1884 dump_ccreg ("xcc", val
>> 4);
1885 printf_unfiltered (", ");
1886 dump_ccreg ("icc", val
& 15);
1889 printf ("\tfef:%d, du:%d, dl:%d",
1890 BITS (2, 1), BITS (1, 1), BITS (0, 1));
1894 static char *fcc
[4] =
1895 {"=", "<", ">", "?"};
1896 static char *rd
[4] =
1897 {"N", "0", "+", "-"};
1898 /* Long, but I'd rather leave it as is and use a wide screen. */
1899 printf_filtered ("\t0:%s, 1:%s, 2:%s, 3:%s, rd:%s, tem:%d, ",
1900 fcc
[BITS (10, 3)], fcc
[BITS (32, 3)],
1901 fcc
[BITS (34, 3)], fcc
[BITS (36, 3)],
1902 rd
[BITS (30, 3)], BITS (23, 31));
1903 printf_filtered ("ns:%d, ver:%d, ftt:%d, qne:%d, aexc:%d, cexc:%d",
1904 BITS (22, 1), BITS (17, 7), BITS (14, 7),
1905 BITS (13, 1), BITS (5, 31), BITS (0, 31));
1910 char *asi
= decode_asi (val
);
1912 printf ("\t%s", asi
);
1916 printf ("\tmanuf:%d, impl:%d, mask:%d, maxtl:%d, maxwin:%d",
1917 BITS (48, 0xffff), BITS (32, 0xffff),
1918 BITS (24, 0xff), BITS (8, 0xff), BITS (0, 31));
1922 static char *mm
[4] =
1923 {"tso", "pso", "rso", "?"};
1924 printf_filtered ("\tcle:%d, tle:%d, mm:%s, red:%d, ",
1925 BITS (9, 1), BITS (8, 1),
1926 mm
[BITS (6, 3)], BITS (5, 1));
1927 printf_filtered ("pef:%d, am:%d, priv:%d, ie:%d, ag:%d",
1928 BITS (4, 1), BITS (3, 1), BITS (2, 1),
1929 BITS (1, 1), BITS (0, 1));
1933 /* FIXME: print all 4? */
1936 /* FIXME: print all 4? */
1939 /* FIXME: print all 4? */
1942 /* FIXME: print all 4? */
1945 printf ("\tother:%d, normal:%d", BITS (3, 7), BITS (0, 7));
1948 printf ("\t%d", BITS (0, 31));
1950 case CANSAVE_REGNUM
:
1951 printf ("\t%-2d before spill", BITS (0, 31));
1953 case CANRESTORE_REGNUM
:
1954 printf ("\t%-2d before fill", BITS (0, 31));
1956 case CLEANWIN_REGNUM
:
1957 printf ("\t%-2d before clean", BITS (0, 31));
1959 case OTHERWIN_REGNUM
:
1960 printf ("\t%d", BITS (0, 31));
1967 printf ("\ticc:%c%c%c%c, pil:%d, s:%d, ps:%d, et:%d, cwp:%d",
1968 BITS (23, 1) ? 'N' : '-', BITS (22, 1) ? 'Z' : '-',
1969 BITS (21, 1) ? 'V' : '-', BITS (20, 1) ? 'C' : '-',
1970 BITS (8, 15), BITS (7, 1), BITS (6, 1), BITS (5, 1),
1975 static char *fcc
[4] =
1976 {"=", "<", ">", "?"};
1977 static char *rd
[4] =
1978 {"N", "0", "+", "-"};
1979 /* Long, but I'd rather leave it as is and use a wide screen. */
1980 printf ("\trd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, "
1981 "fcc:%s, aexc:%d, cexc:%d",
1982 rd
[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7),
1983 BITS (14, 7), BITS (13, 1), fcc
[BITS (10, 3)], BITS (5, 31),
1993 gdb_print_insn_sparc (bfd_vma memaddr
, disassemble_info
*info
)
1995 /* It's necessary to override mach again because print_insn messes it up. */
1996 info
->mach
= TARGET_ARCHITECTURE
->mach
;
1997 return print_insn_sparc (memaddr
, info
);
2000 /* The SPARC passes the arguments on the stack; arguments smaller
2001 than an int are promoted to an int. The first 6 words worth of
2002 args are also passed in registers o0 - o5. */
2005 sparc32_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
2006 int struct_return
, CORE_ADDR struct_addr
)
2009 int accumulate_size
= 0;
2016 struct sparc_arg
*sparc_args
=
2017 (struct sparc_arg
*) alloca (nargs
* sizeof (struct sparc_arg
));
2018 struct sparc_arg
*m_arg
;
2020 /* Promote arguments if necessary, and calculate their stack offsets
2022 for (i
= 0, m_arg
= sparc_args
; i
< nargs
; i
++, m_arg
++)
2024 struct value
*arg
= args
[i
];
2025 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2026 /* Cast argument to long if necessary as the compiler does it too. */
2027 switch (TYPE_CODE (arg_type
))
2030 case TYPE_CODE_BOOL
:
2031 case TYPE_CODE_CHAR
:
2032 case TYPE_CODE_RANGE
:
2033 case TYPE_CODE_ENUM
:
2034 if (TYPE_LENGTH (arg_type
) < TYPE_LENGTH (builtin_type_long
))
2036 arg_type
= builtin_type_long
;
2037 arg
= value_cast (arg_type
, arg
);
2043 m_arg
->len
= TYPE_LENGTH (arg_type
);
2044 m_arg
->offset
= accumulate_size
;
2045 accumulate_size
= (accumulate_size
+ m_arg
->len
+ 3) & ~3;
2046 m_arg
->contents
= VALUE_CONTENTS (arg
);
2049 /* Make room for the arguments on the stack. */
2050 accumulate_size
+= CALL_DUMMY_STACK_ADJUST
;
2051 sp
= ((sp
- accumulate_size
) & ~7) + CALL_DUMMY_STACK_ADJUST
;
2053 /* `Push' arguments on the stack. */
2054 for (i
= 0, oregnum
= 0, m_arg
= sparc_args
;
2058 write_memory (sp
+ m_arg
->offset
, m_arg
->contents
, m_arg
->len
);
2060 j
< m_arg
->len
&& oregnum
< 6;
2061 j
+= SPARC_INTREG_SIZE
, oregnum
++)
2062 write_register_gen (O0_REGNUM
+ oregnum
, m_arg
->contents
+ j
);
2069 /* Extract from an array REGBUF containing the (raw) register state
2070 a function return value of type TYPE, and copy that, in virtual format,
2074 sparc32_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2076 int typelen
= TYPE_LENGTH (type
);
2077 int regsize
= REGISTER_RAW_SIZE (O0_REGNUM
);
2079 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2080 memcpy (valbuf
, ®buf
[REGISTER_BYTE (FP0_REGNUM
)], typelen
);
2083 ®buf
[O0_REGNUM
* regsize
+
2085 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
? 0
2086 : regsize
- typelen
)],
2091 /* Write into appropriate registers a function return value
2092 of type TYPE, given in virtual format. On SPARCs with FPUs,
2093 float values are returned in %f0 (and %f1). In all other cases,
2094 values are returned in register %o0. */
2097 sparc_store_return_value (struct type
*type
, char *valbuf
)
2102 buffer
= alloca (MAX_REGISTER_RAW_SIZE
);
2104 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2105 /* Floating-point values are returned in the register pair */
2106 /* formed by %f0 and %f1 (doubles are, anyway). */
2109 /* Other values are returned in register %o0. */
2112 /* Add leading zeros to the value. */
2113 if (TYPE_LENGTH (type
) < REGISTER_RAW_SIZE (regno
))
2115 memset (buffer
, 0, REGISTER_RAW_SIZE (regno
));
2116 memcpy (buffer
+ REGISTER_RAW_SIZE (regno
) - TYPE_LENGTH (type
), valbuf
,
2117 TYPE_LENGTH (type
));
2118 write_register_gen (regno
, buffer
);
2121 write_register_bytes (REGISTER_BYTE (regno
), valbuf
, TYPE_LENGTH (type
));
2125 sparclet_store_return_value (struct type
*type
, char *valbuf
)
2127 /* Other values are returned in register %o0. */
2128 write_register_bytes (REGISTER_BYTE (O0_REGNUM
), valbuf
,
2129 TYPE_LENGTH (type
));
2133 #ifndef CALL_DUMMY_CALL_OFFSET
2134 #define CALL_DUMMY_CALL_OFFSET \
2135 (gdbarch_tdep (current_gdbarch)->call_dummy_call_offset)
2136 #endif /* CALL_DUMMY_CALL_OFFSET */
2138 /* Insert the function address into a call dummy instruction sequence
2141 For structs and unions, if the function was compiled with Sun cc,
2142 it expects 'unimp' after the call. But gcc doesn't use that
2143 (twisted) convention. So leave a nop there for gcc (FIX_CALL_DUMMY
2144 can assume it is operating on a pristine CALL_DUMMY, not one that
2145 has already been customized for a different function). */
2148 sparc_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
,
2149 struct type
*value_type
, int using_gcc
)
2153 /* Store the relative adddress of the target function into the
2154 'call' instruction. */
2155 store_unsigned_integer (dummy
+ CALL_DUMMY_CALL_OFFSET
, 4,
2157 | (((fun
- (pc
+ CALL_DUMMY_CALL_OFFSET
)) >> 2)
2160 /* If the called function returns an aggregate value, fill in the UNIMP
2161 instruction containing the size of the returned aggregate return value,
2162 which follows the call instruction.
2163 For details see the SPARC Architecture Manual Version 8, Appendix D.3.
2165 Adjust the call_dummy_breakpoint_offset for the bp_call_dummy breakpoint
2166 to the proper address in the call dummy, so that `finish' after a stop
2167 in a call dummy works.
2168 Tweeking current_gdbarch is not an optimal solution, but the call to
2169 sparc_fix_call_dummy is immediately followed by a call to run_stack_dummy,
2170 which is the only function where dummy_breakpoint_offset is actually
2171 used, if it is non-zero. */
2172 if (TYPE_CODE (value_type
) == TYPE_CODE_STRUCT
2173 || TYPE_CODE (value_type
) == TYPE_CODE_UNION
)
2175 store_unsigned_integer (dummy
+ CALL_DUMMY_CALL_OFFSET
+ 8, 4,
2176 TYPE_LENGTH (value_type
) & 0x1fff);
2177 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch
, 0x30);
2180 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch
, 0x2c);
2182 if (!(GDB_TARGET_IS_SPARC64
))
2184 /* If this is not a simulator target, change the first four
2185 instructions of the call dummy to NOPs. Those instructions
2186 include a 'save' instruction and are designed to work around
2187 problems with register window flushing in the simulator. */
2189 if (strcmp (target_shortname
, "sim") != 0)
2191 for (i
= 0; i
< 4; i
++)
2192 store_unsigned_integer (dummy
+ (i
* 4), 4, 0x01000000);
2196 /* If this is a bi-endian target, GDB has written the call dummy
2197 in little-endian order. We must byte-swap it back to big-endian. */
2200 for (i
= 0; i
< CALL_DUMMY_LENGTH
; i
+= 4)
2202 char tmp
= dummy
[i
];
2203 dummy
[i
] = dummy
[i
+ 3];
2206 dummy
[i
+ 1] = dummy
[i
+ 2];
2213 /* Set target byte order based on machine type. */
2216 sparc_target_architecture_hook (const bfd_arch_info_type
*ap
)
2220 if (ap
->mach
== bfd_mach_sparc_sparclite_le
)
2222 target_byte_order
= BFD_ENDIAN_LITTLE
;
2232 * Module "constructor" function.
2235 static struct gdbarch
* sparc_gdbarch_init (struct gdbarch_info info
,
2236 struct gdbarch_list
*arches
);
2239 _initialize_sparc_tdep (void)
2241 /* Hook us into the gdbarch mechanism. */
2242 register_gdbarch_init (bfd_arch_sparc
, sparc_gdbarch_init
);
2244 tm_print_insn
= gdb_print_insn_sparc
;
2245 tm_print_insn_info
.mach
= TM_PRINT_INSN_MACH
; /* Selects sparc/sparclite */
2246 target_architecture_hook
= sparc_target_architecture_hook
;
2249 /* Compensate for stack bias. Note that we currently don't handle
2250 mixed 32/64 bit code. */
2253 sparc64_read_sp (void)
2255 CORE_ADDR sp
= read_register (SP_REGNUM
);
2263 sparc64_read_fp (void)
2265 CORE_ADDR fp
= read_register (FP_REGNUM
);
2273 sparc64_write_sp (CORE_ADDR val
)
2275 CORE_ADDR oldsp
= read_register (SP_REGNUM
);
2277 write_register (SP_REGNUM
, val
- 2047);
2279 write_register (SP_REGNUM
, val
);
2282 /* The SPARC 64 ABI passes floating-point arguments in FP0 to FP31,
2283 and all other arguments in O0 to O5. They are also copied onto
2284 the stack in the correct places. Apparently (empirically),
2285 structs of less than 16 bytes are passed member-by-member in
2286 separate registers, but I am unable to figure out the algorithm.
2287 Some members go in floating point regs, but I don't know which.
2289 FIXME: Handle small structs (less than 16 bytes containing floats).
2291 The counting regimen for using both integer and FP registers
2292 for argument passing is rather odd -- a single counter is used
2293 for both; this means that if the arguments alternate between
2294 int and float, we will waste every other register of both types. */
2297 sparc64_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
2298 int struct_return
, CORE_ADDR struct_retaddr
)
2300 int i
, j
, register_counter
= 0;
2302 struct type
*sparc_intreg_type
=
2303 TYPE_LENGTH (builtin_type_long
) == SPARC_INTREG_SIZE
?
2304 builtin_type_long
: builtin_type_long_long
;
2306 sp
= (sp
& ~(((unsigned long) SPARC_INTREG_SIZE
) - 1UL));
2308 /* Figure out how much space we'll need. */
2309 for (i
= nargs
- 1; i
>= 0; i
--)
2311 int len
= TYPE_LENGTH (check_typedef (VALUE_TYPE (args
[i
])));
2312 struct value
*copyarg
= args
[i
];
2315 if (copylen
< SPARC_INTREG_SIZE
)
2317 copyarg
= value_cast (sparc_intreg_type
, copyarg
);
2318 copylen
= SPARC_INTREG_SIZE
;
2327 /* if STRUCT_RETURN, then first argument is the struct return location. */
2329 write_register (O0_REGNUM
+ register_counter
++, struct_retaddr
);
2331 /* Now write the arguments onto the stack, while writing FP
2332 arguments into the FP registers, and other arguments into the
2333 first six 'O' registers. */
2335 for (i
= 0; i
< nargs
; i
++)
2337 int len
= TYPE_LENGTH (check_typedef (VALUE_TYPE (args
[i
])));
2338 struct value
*copyarg
= args
[i
];
2339 enum type_code typecode
= TYPE_CODE (VALUE_TYPE (args
[i
]));
2342 if (typecode
== TYPE_CODE_INT
||
2343 typecode
== TYPE_CODE_BOOL
||
2344 typecode
== TYPE_CODE_CHAR
||
2345 typecode
== TYPE_CODE_RANGE
||
2346 typecode
== TYPE_CODE_ENUM
)
2347 if (len
< SPARC_INTREG_SIZE
)
2349 /* Small ints will all take up the size of one intreg on
2351 copyarg
= value_cast (sparc_intreg_type
, copyarg
);
2352 copylen
= SPARC_INTREG_SIZE
;
2355 write_memory (tempsp
, VALUE_CONTENTS (copyarg
), copylen
);
2358 /* Corner case: Structs consisting of a single float member are floats.
2359 * FIXME! I don't know about structs containing multiple floats!
2360 * Structs containing mixed floats and ints are even more weird.
2365 /* Separate float args from all other args. */
2366 if (typecode
== TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2368 if (register_counter
< 16)
2370 /* This arg gets copied into a FP register. */
2374 case 4: /* Single-precision (float) */
2375 fpreg
= FP0_REGNUM
+ 2 * register_counter
+ 1;
2376 register_counter
+= 1;
2378 case 8: /* Double-precision (double) */
2379 fpreg
= FP0_REGNUM
+ 2 * register_counter
;
2380 register_counter
+= 1;
2382 case 16: /* Quad-precision (long double) */
2383 fpreg
= FP0_REGNUM
+ 2 * register_counter
;
2384 register_counter
+= 2;
2387 internal_error (__FILE__
, __LINE__
, "bad switch");
2389 write_register_bytes (REGISTER_BYTE (fpreg
),
2390 VALUE_CONTENTS (args
[i
]),
2394 else /* all other args go into the first six 'o' registers */
2397 j
< len
&& register_counter
< 6;
2398 j
+= SPARC_INTREG_SIZE
)
2400 int oreg
= O0_REGNUM
+ register_counter
;
2402 write_register_gen (oreg
, VALUE_CONTENTS (copyarg
) + j
);
2403 register_counter
+= 1;
2410 /* Values <= 32 bytes are returned in o0-o3 (floating-point values are
2411 returned in f0-f3). */
2414 sp64_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
,
2417 int typelen
= TYPE_LENGTH (type
);
2418 int regsize
= REGISTER_RAW_SIZE (O0_REGNUM
);
2420 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2422 memcpy (valbuf
, ®buf
[REGISTER_BYTE (FP0_REGNUM
)], typelen
);
2426 if (TYPE_CODE (type
) != TYPE_CODE_STRUCT
2427 || (TYPE_LENGTH (type
) > 32))
2430 ®buf
[O0_REGNUM
* regsize
+
2431 (typelen
>= regsize
? 0 : regsize
- typelen
)],
2437 char *o0
= ®buf
[O0_REGNUM
* regsize
];
2438 char *f0
= ®buf
[FP0_REGNUM
* regsize
];
2441 for (x
= 0; x
< TYPE_NFIELDS (type
); x
++)
2443 struct field
*f
= &TYPE_FIELDS (type
)[x
];
2444 /* FIXME: We may need to handle static fields here. */
2445 int whichreg
= (f
->loc
.bitpos
+ bitoffset
) / 32;
2446 int remainder
= ((f
->loc
.bitpos
+ bitoffset
) % 32) / 8;
2447 int where
= (f
->loc
.bitpos
+ bitoffset
) / 8;
2448 int size
= TYPE_LENGTH (f
->type
);
2449 int typecode
= TYPE_CODE (f
->type
);
2451 if (typecode
== TYPE_CODE_STRUCT
)
2453 sp64_extract_return_value (f
->type
,
2456 bitoffset
+ f
->loc
.bitpos
);
2458 else if (typecode
== TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2460 memcpy (valbuf
+ where
, &f0
[whichreg
* 4] + remainder
, size
);
2464 memcpy (valbuf
+ where
, &o0
[whichreg
* 4] + remainder
, size
);
2471 sparc64_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2473 sp64_extract_return_value (type
, regbuf
, valbuf
, 0);
2477 sparclet_extract_return_value (struct type
*type
,
2481 regbuf
+= REGISTER_RAW_SIZE (O0_REGNUM
) * 8;
2482 if (TYPE_LENGTH (type
) < REGISTER_RAW_SIZE (O0_REGNUM
))
2483 regbuf
+= REGISTER_RAW_SIZE (O0_REGNUM
) - TYPE_LENGTH (type
);
2485 memcpy ((void *) valbuf
, regbuf
, TYPE_LENGTH (type
));
2490 sparc32_stack_align (CORE_ADDR addr
)
2492 return ((addr
+ 7) & -8);
2496 sparc64_stack_align (CORE_ADDR addr
)
2498 return ((addr
+ 15) & -16);
2502 sparc_print_extra_frame_info (struct frame_info
*fi
)
2504 if (fi
&& fi
->extra_info
&& fi
->extra_info
->flat
)
2505 printf_filtered (" flat, pc saved at 0x%s, fp saved at 0x%s\n",
2506 paddr_nz (fi
->extra_info
->pc_addr
),
2507 paddr_nz (fi
->extra_info
->fp_addr
));
2510 /* MULTI_ARCH support */
2513 sparc32_register_name (int regno
)
2515 static char *register_names
[] =
2516 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2517 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2518 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2519 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2521 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2522 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2523 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2524 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
2526 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
2530 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2533 return register_names
[regno
];
2537 sparc64_register_name (int regno
)
2539 static char *register_names
[] =
2540 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2541 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2542 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2543 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2545 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2546 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2547 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2548 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
2549 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
2550 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
2552 "pc", "npc", "ccr", "fsr", "fprs", "y", "asi", "ver",
2553 "tick", "pil", "pstate", "tstate", "tba", "tl", "tt", "tpc",
2554 "tnpc", "wstate", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
2555 "asr16", "asr17", "asr18", "asr19", "asr20", "asr21", "asr22", "asr23",
2556 "asr24", "asr25", "asr26", "asr27", "asr28", "asr29", "asr30", "asr31",
2557 /* These are here at the end to simplify removing them if we have to. */
2558 "icc", "xcc", "fcc0", "fcc1", "fcc2", "fcc3"
2562 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2565 return register_names
[regno
];
2569 sparclite_register_name (int regno
)
2571 static char *register_names
[] =
2572 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2573 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2574 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2575 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2577 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2578 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2579 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2580 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
2582 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr",
2583 "dia1", "dia2", "dda1", "dda2", "ddv1", "ddv2", "dcr", "dsr"
2587 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2590 return register_names
[regno
];
2594 sparclet_register_name (int regno
)
2596 static char *register_names
[] =
2597 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2598 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2599 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2600 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2602 "", "", "", "", "", "", "", "", /* no floating point registers */
2603 "", "", "", "", "", "", "", "",
2604 "", "", "", "", "", "", "", "",
2605 "", "", "", "", "", "", "", "",
2607 "y", "psr", "wim", "tbr", "pc", "npc", "", "", /* no FPSR or CPSR */
2608 "ccsr", "ccpr", "cccrcr", "ccor", "ccobr", "ccibr", "ccir", "",
2610 /* ASR15 ASR19 (don't display them) */
2611 "asr1", "", "asr17", "asr18", "", "asr20", "asr21", "asr22"
2612 /* None of the rest get displayed */
2614 "awr0", "awr1", "awr2", "awr3", "awr4", "awr5", "awr6", "awr7",
2615 "awr8", "awr9", "awr10", "awr11", "awr12", "awr13", "awr14", "awr15",
2616 "awr16", "awr17", "awr18", "awr19", "awr20", "awr21", "awr22", "awr23",
2617 "awr24", "awr25", "awr26", "awr27", "awr28", "awr29", "awr30", "awr31",
2623 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2626 return register_names
[regno
];
2630 sparc_push_return_address (CORE_ADDR pc_unused
, CORE_ADDR sp
)
2632 if (CALL_DUMMY_LOCATION
== AT_ENTRY_POINT
)
2634 /* The return PC of the dummy_frame is the former 'current' PC
2635 (where we were before we made the target function call).
2636 This is saved in %i7 by push_dummy_frame.
2638 We will save the 'call dummy location' (ie. the address
2639 to which the target function will return) in %o7.
2640 This address will actually be the program's entry point.
2641 There will be a special call_dummy breakpoint there. */
2643 write_register (O7_REGNUM
,
2644 CALL_DUMMY_ADDRESS () - 8);
2650 /* Should call_function allocate stack space for a struct return? */
2653 sparc64_use_struct_convention (int gcc_p
, struct type
*type
)
2655 return (TYPE_LENGTH (type
) > 32);
2658 /* Store the address of the place in which to copy the structure the
2659 subroutine will return. This is called from call_function_by_hand.
2660 The ultimate mystery is, tho, what is the value "16"?
2662 MVS: That's the offset from where the sp is now, to where the
2663 subroutine is gonna expect to find the struct return address. */
2666 sparc32_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
2671 val
= alloca (SPARC_INTREG_SIZE
);
2672 store_unsigned_integer (val
, SPARC_INTREG_SIZE
, addr
);
2673 write_memory (sp
+ (16 * SPARC_INTREG_SIZE
), val
, SPARC_INTREG_SIZE
);
2675 if (CALL_DUMMY_LOCATION
== AT_ENTRY_POINT
)
2677 /* Now adjust the value of the link register, which was previously
2678 stored by push_return_address. Functions that return structs are
2679 peculiar in that they return to link register + 12, rather than
2680 link register + 8. */
2682 o7
= read_register (O7_REGNUM
);
2683 write_register (O7_REGNUM
, o7
- 4);
2688 sparc64_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
2690 /* FIXME: V9 uses %o0 for this. */
2691 /* FIXME MVS: Only for small enough structs!!! */
2693 target_write_memory (sp
+ (16 * SPARC_INTREG_SIZE
),
2694 (char *) &addr
, SPARC_INTREG_SIZE
);
2696 if (CALL_DUMMY_LOCATION
== AT_ENTRY_POINT
)
2698 /* Now adjust the value of the link register, which was previously
2699 stored by push_return_address. Functions that return structs are
2700 peculiar in that they return to link register + 12, rather than
2701 link register + 8. */
2703 write_register (O7_REGNUM
, read_register (O7_REGNUM
) - 4);
2708 /* Default target data type for register REGNO. */
2710 static struct type
*
2711 sparc32_register_virtual_type (int regno
)
2713 if (regno
== PC_REGNUM
||
2714 regno
== FP_REGNUM
||
2716 return builtin_type_unsigned_int
;
2718 return builtin_type_int
;
2720 return builtin_type_float
;
2721 return builtin_type_int
;
2724 static struct type
*
2725 sparc64_register_virtual_type (int regno
)
2727 if (regno
== PC_REGNUM
||
2728 regno
== FP_REGNUM
||
2730 return builtin_type_unsigned_long_long
;
2732 return builtin_type_long_long
;
2734 return builtin_type_float
;
2736 return builtin_type_double
;
2737 return builtin_type_long_long
;
2740 /* Number of bytes of storage in the actual machine representation for
2744 sparc32_register_size (int regno
)
2750 sparc64_register_size (int regno
)
2752 return (regno
< 32 ? 8 : regno
< 64 ? 4 : 8);
2755 /* Index within the `registers' buffer of the first byte of the space
2756 for register REGNO. */
2759 sparc32_register_byte (int regno
)
2765 sparc64_register_byte (int regno
)
2769 else if (regno
< 64)
2770 return 32 * 8 + (regno
- 32) * 4;
2771 else if (regno
< 80)
2772 return 32 * 8 + 32 * 4 + (regno
- 64) * 8;
2774 return 64 * 8 + (regno
- 80) * 8;
2777 /* Advance PC across any function entry prologue instructions to reach
2778 some "real" code. SKIP_PROLOGUE_FRAMELESS_P advances the PC past
2779 some of the prologue, but stops as soon as it knows that the
2780 function has a frame. Its result is equal to its input PC if the
2781 function is frameless, unequal otherwise. */
2784 sparc_gdbarch_skip_prologue (CORE_ADDR ip
)
2786 return examine_prologue (ip
, 0, NULL
, NULL
);
2789 /* Immediately after a function call, return the saved pc.
2790 Can't go through the frames for this because on some machines
2791 the new frame is not set up until the new function executes
2792 some instructions. */
2795 sparc_saved_pc_after_call (struct frame_info
*fi
)
2797 return sparc_pc_adjust (read_register (RP_REGNUM
));
2800 /* Convert registers between 'raw' and 'virtual' formats.
2801 They are the same on sparc, so there's nothing to do. */
2804 sparc_convert_to_virtual (int regnum
, struct type
*type
, char *from
, char *to
)
2805 { /* do nothing (should never be called) */
2809 sparc_convert_to_raw (struct type
*type
, int regnum
, char *from
, char *to
)
2810 { /* do nothing (should never be called) */
2813 /* Init saved regs: nothing to do, just a place-holder function. */
2816 sparc_frame_init_saved_regs (struct frame_info
*fi_ignored
)
2820 /* gdbarch fix call dummy:
2821 All this function does is rearrange the arguments before calling
2822 sparc_fix_call_dummy (which does the real work). */
2825 sparc_gdbarch_fix_call_dummy (char *dummy
,
2829 struct value
**args
,
2833 if (CALL_DUMMY_LOCATION
== ON_STACK
)
2834 sparc_fix_call_dummy (dummy
, pc
, fun
, type
, gcc_p
);
2837 /* Coerce float to double: a no-op. */
2840 sparc_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
2845 /* CALL_DUMMY_ADDRESS: fetch the breakpoint address for a call dummy. */
2848 sparc_call_dummy_address (void)
2850 return (CALL_DUMMY_START_OFFSET
) + CALL_DUMMY_BREAKPOINT_OFFSET
;
2853 /* Supply the Y register number to those that need it. */
2856 sparc_y_regnum (void)
2858 return gdbarch_tdep (current_gdbarch
)->y_regnum
;
2862 sparc_reg_struct_has_addr (int gcc_p
, struct type
*type
)
2864 if (GDB_TARGET_IS_SPARC64
)
2865 return (TYPE_LENGTH (type
) > 32);
2867 return (gcc_p
!= 1);
2871 sparc_intreg_size (void)
2873 return SPARC_INTREG_SIZE
;
2877 sparc_return_value_on_stack (struct type
*type
)
2879 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&&
2880 TYPE_LENGTH (type
) > 8)
2887 * Gdbarch "constructor" function.
2890 #define SPARC32_CALL_DUMMY_ON_STACK
2892 #define SPARC_SP_REGNUM 14
2893 #define SPARC_FP_REGNUM 30
2894 #define SPARC_FP0_REGNUM 32
2895 #define SPARC32_NPC_REGNUM 69
2896 #define SPARC32_PC_REGNUM 68
2897 #define SPARC32_Y_REGNUM 64
2898 #define SPARC64_PC_REGNUM 80
2899 #define SPARC64_NPC_REGNUM 81
2900 #define SPARC64_Y_REGNUM 85
2902 static struct gdbarch
*
2903 sparc_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2905 struct gdbarch
*gdbarch
;
2906 struct gdbarch_tdep
*tdep
;
2908 static LONGEST call_dummy_32
[] =
2909 { 0xbc100001, 0x9de38000, 0xbc100002, 0xbe100003,
2910 0xda03a058, 0xd803a054, 0xd603a050, 0xd403a04c,
2911 0xd203a048, 0x40000000, 0xd003a044, 0x01000000,
2912 0x91d02001, 0x01000000
2914 static LONGEST call_dummy_64
[] =
2915 { 0x9de3bec0fd3fa7f7LL
, 0xf93fa7eff53fa7e7LL
,
2916 0xf13fa7dfed3fa7d7LL
, 0xe93fa7cfe53fa7c7LL
,
2917 0xe13fa7bfdd3fa7b7LL
, 0xd93fa7afd53fa7a7LL
,
2918 0xd13fa79fcd3fa797LL
, 0xc93fa78fc53fa787LL
,
2919 0xc13fa77fcc3fa777LL
, 0xc83fa76fc43fa767LL
,
2920 0xc03fa75ffc3fa757LL
, 0xf83fa74ff43fa747LL
,
2921 0xf03fa73f01000000LL
, 0x0100000001000000LL
,
2922 0x0100000091580000LL
, 0xd027a72b93500000LL
,
2923 0xd027a72791480000LL
, 0xd027a72391400000LL
,
2924 0xd027a71fda5ba8a7LL
, 0xd85ba89fd65ba897LL
,
2925 0xd45ba88fd25ba887LL
, 0x9fc02000d05ba87fLL
,
2926 0x0100000091d02001LL
, 0x0100000001000000LL
2928 static LONGEST call_dummy_nil
[] = {0};
2930 /* First see if there is already a gdbarch that can satisfy the request. */
2931 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2933 return arches
->gdbarch
;
2935 /* None found: is the request for a sparc architecture? */
2936 if (info
.bfd_arch_info
->arch
!= bfd_arch_sparc
)
2937 return NULL
; /* No; then it's not for us. */
2939 /* Yes: create a new gdbarch for the specified machine type. */
2940 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
2941 gdbarch
= gdbarch_alloc (&info
, tdep
);
2943 /* First set settings that are common for all sparc architectures. */
2944 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2945 set_gdbarch_breakpoint_from_pc (gdbarch
, memory_breakpoint_from_pc
);
2946 set_gdbarch_coerce_float_to_double (gdbarch
,
2947 sparc_coerce_float_to_double
);
2948 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
2949 set_gdbarch_call_dummy_p (gdbarch
, 1);
2950 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 1);
2951 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
2952 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2953 set_gdbarch_extract_struct_value_address (gdbarch
,
2954 sparc_extract_struct_value_address
);
2955 set_gdbarch_fix_call_dummy (gdbarch
, sparc_gdbarch_fix_call_dummy
);
2956 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2957 set_gdbarch_fp_regnum (gdbarch
, SPARC_FP_REGNUM
);
2958 set_gdbarch_fp0_regnum (gdbarch
, SPARC_FP0_REGNUM
);
2959 set_gdbarch_frame_args_address (gdbarch
, default_frame_address
);
2960 set_gdbarch_frame_chain (gdbarch
, sparc_frame_chain
);
2961 set_gdbarch_frame_init_saved_regs (gdbarch
, sparc_frame_init_saved_regs
);
2962 set_gdbarch_frame_locals_address (gdbarch
, default_frame_address
);
2963 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
2964 set_gdbarch_frame_saved_pc (gdbarch
, sparc_frame_saved_pc
);
2965 set_gdbarch_frameless_function_invocation (gdbarch
,
2966 frameless_look_for_prologue
);
2967 set_gdbarch_get_saved_register (gdbarch
, sparc_get_saved_register
);
2968 set_gdbarch_init_extra_frame_info (gdbarch
, sparc_init_extra_frame_info
);
2969 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2970 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2971 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
2972 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2973 set_gdbarch_max_register_raw_size (gdbarch
, 8);
2974 set_gdbarch_max_register_virtual_size (gdbarch
, 8);
2975 set_gdbarch_pop_frame (gdbarch
, sparc_pop_frame
);
2976 set_gdbarch_push_return_address (gdbarch
, sparc_push_return_address
);
2977 set_gdbarch_push_dummy_frame (gdbarch
, sparc_push_dummy_frame
);
2978 set_gdbarch_read_pc (gdbarch
, generic_target_read_pc
);
2979 set_gdbarch_register_convert_to_raw (gdbarch
, sparc_convert_to_raw
);
2980 set_gdbarch_register_convert_to_virtual (gdbarch
,
2981 sparc_convert_to_virtual
);
2982 set_gdbarch_register_convertible (gdbarch
,
2983 generic_register_convertible_not
);
2984 set_gdbarch_reg_struct_has_addr (gdbarch
, sparc_reg_struct_has_addr
);
2985 set_gdbarch_return_value_on_stack (gdbarch
, sparc_return_value_on_stack
);
2986 set_gdbarch_saved_pc_after_call (gdbarch
, sparc_saved_pc_after_call
);
2987 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2988 set_gdbarch_skip_prologue (gdbarch
, sparc_gdbarch_skip_prologue
);
2989 set_gdbarch_sp_regnum (gdbarch
, SPARC_SP_REGNUM
);
2990 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
2991 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
2994 * Settings that depend only on 32/64 bit word size
2997 switch (info
.bfd_arch_info
->mach
)
2999 case bfd_mach_sparc
:
3000 case bfd_mach_sparc_sparclet
:
3001 case bfd_mach_sparc_sparclite
:
3002 case bfd_mach_sparc_v8plus
:
3003 case bfd_mach_sparc_v8plusa
:
3004 case bfd_mach_sparc_sparclite_le
:
3005 /* 32-bit machine types: */
3007 #ifdef SPARC32_CALL_DUMMY_ON_STACK
3008 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_on_stack
);
3009 set_gdbarch_call_dummy_address (gdbarch
, sparc_call_dummy_address
);
3010 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0x30);
3011 set_gdbarch_call_dummy_length (gdbarch
, 0x38);
3012 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
3013 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_32
);
3015 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
3016 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
3017 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
3018 set_gdbarch_call_dummy_length (gdbarch
, 0);
3019 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
3020 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_nil
);
3022 set_gdbarch_call_dummy_stack_adjust (gdbarch
, 68);
3023 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
3024 set_gdbarch_frame_args_skip (gdbarch
, 68);
3025 set_gdbarch_function_start_offset (gdbarch
, 0);
3026 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3027 set_gdbarch_npc_regnum (gdbarch
, SPARC32_NPC_REGNUM
);
3028 set_gdbarch_pc_regnum (gdbarch
, SPARC32_PC_REGNUM
);
3029 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3030 set_gdbarch_push_arguments (gdbarch
, sparc32_push_arguments
);
3031 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
3032 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
3034 set_gdbarch_register_byte (gdbarch
, sparc32_register_byte
);
3035 set_gdbarch_register_raw_size (gdbarch
, sparc32_register_size
);
3036 set_gdbarch_register_size (gdbarch
, 4);
3037 set_gdbarch_register_virtual_size (gdbarch
, sparc32_register_size
);
3038 set_gdbarch_register_virtual_type (gdbarch
,
3039 sparc32_register_virtual_type
);
3040 #ifdef SPARC32_CALL_DUMMY_ON_STACK
3041 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (call_dummy_32
));
3043 set_gdbarch_sizeof_call_dummy_words (gdbarch
, 0);
3045 set_gdbarch_stack_align (gdbarch
, sparc32_stack_align
);
3046 set_gdbarch_store_struct_return (gdbarch
, sparc32_store_struct_return
);
3047 set_gdbarch_use_struct_convention (gdbarch
,
3048 generic_use_struct_convention
);
3049 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
3050 tdep
->y_regnum
= SPARC32_Y_REGNUM
;
3051 tdep
->fp_max_regnum
= SPARC_FP0_REGNUM
+ 32;
3052 tdep
->intreg_size
= 4;
3053 tdep
->reg_save_offset
= 0x60;
3054 tdep
->call_dummy_call_offset
= 0x24;
3057 case bfd_mach_sparc_v9
:
3058 case bfd_mach_sparc_v9a
:
3059 /* 64-bit machine types: */
3060 default: /* Any new machine type is likely to be 64-bit. */
3062 #ifdef SPARC64_CALL_DUMMY_ON_STACK
3063 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_on_stack
);
3064 set_gdbarch_call_dummy_address (gdbarch
, sparc_call_dummy_address
);
3065 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 8 * 4);
3066 set_gdbarch_call_dummy_length (gdbarch
, 192);
3067 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
3068 set_gdbarch_call_dummy_start_offset (gdbarch
, 148);
3069 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_64
);
3071 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
3072 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
3073 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
3074 set_gdbarch_call_dummy_length (gdbarch
, 0);
3075 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
3076 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
3077 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_nil
);
3079 set_gdbarch_call_dummy_stack_adjust (gdbarch
, 128);
3080 set_gdbarch_frame_args_skip (gdbarch
, 136);
3081 set_gdbarch_function_start_offset (gdbarch
, 0);
3082 set_gdbarch_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3083 set_gdbarch_npc_regnum (gdbarch
, SPARC64_NPC_REGNUM
);
3084 set_gdbarch_pc_regnum (gdbarch
, SPARC64_PC_REGNUM
);
3085 set_gdbarch_ptr_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3086 set_gdbarch_push_arguments (gdbarch
, sparc64_push_arguments
);
3087 /* NOTE different for at_entry */
3088 set_gdbarch_read_fp (gdbarch
, sparc64_read_fp
);
3089 set_gdbarch_read_sp (gdbarch
, sparc64_read_sp
);
3090 /* Some of the registers aren't 64 bits, but it's a lot simpler just
3091 to assume they all are (since most of them are). */
3092 set_gdbarch_register_byte (gdbarch
, sparc64_register_byte
);
3093 set_gdbarch_register_raw_size (gdbarch
, sparc64_register_size
);
3094 set_gdbarch_register_size (gdbarch
, 8);
3095 set_gdbarch_register_virtual_size (gdbarch
, sparc64_register_size
);
3096 set_gdbarch_register_virtual_type (gdbarch
,
3097 sparc64_register_virtual_type
);
3098 #ifdef SPARC64_CALL_DUMMY_ON_STACK
3099 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (call_dummy_64
));
3101 set_gdbarch_sizeof_call_dummy_words (gdbarch
, 0);
3103 set_gdbarch_stack_align (gdbarch
, sparc64_stack_align
);
3104 set_gdbarch_store_struct_return (gdbarch
, sparc64_store_struct_return
);
3105 set_gdbarch_use_struct_convention (gdbarch
,
3106 sparc64_use_struct_convention
);
3107 set_gdbarch_write_sp (gdbarch
, sparc64_write_sp
);
3108 tdep
->y_regnum
= SPARC64_Y_REGNUM
;
3109 tdep
->fp_max_regnum
= SPARC_FP0_REGNUM
+ 48;
3110 tdep
->intreg_size
= 8;
3111 tdep
->reg_save_offset
= 0x90;
3112 tdep
->call_dummy_call_offset
= 148 + 4 * 5;
3117 * Settings that vary per-architecture:
3120 switch (info
.bfd_arch_info
->mach
)
3122 case bfd_mach_sparc
:
3123 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3124 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3125 set_gdbarch_num_regs (gdbarch
, 72);
3126 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4);
3127 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
3128 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3129 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3130 tdep
->fp_register_bytes
= 32 * 4;
3131 tdep
->print_insn_mach
= bfd_mach_sparc
;
3133 case bfd_mach_sparc_sparclet
:
3134 set_gdbarch_extract_return_value (gdbarch
,
3135 sparclet_extract_return_value
);
3136 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3137 set_gdbarch_num_regs (gdbarch
, 32 + 32 + 8 + 8 + 8);
3138 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4 + 8*4 + 8*4);
3139 set_gdbarch_register_name (gdbarch
, sparclet_register_name
);
3140 set_gdbarch_store_return_value (gdbarch
, sparclet_store_return_value
);
3141 tdep
->has_fpu
= 0; /* (all but sparclet and sparclite) */
3142 tdep
->fp_register_bytes
= 0;
3143 tdep
->print_insn_mach
= bfd_mach_sparc_sparclet
;
3145 case bfd_mach_sparc_sparclite
:
3146 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3147 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
3148 set_gdbarch_num_regs (gdbarch
, 80);
3149 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4 + 8*4);
3150 set_gdbarch_register_name (gdbarch
, sparclite_register_name
);
3151 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3152 tdep
->has_fpu
= 0; /* (all but sparclet and sparclite) */
3153 tdep
->fp_register_bytes
= 0;
3154 tdep
->print_insn_mach
= bfd_mach_sparc_sparclite
;
3156 case bfd_mach_sparc_v8plus
:
3157 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3158 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3159 set_gdbarch_num_regs (gdbarch
, 72);
3160 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4);
3161 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
3162 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3163 tdep
->print_insn_mach
= bfd_mach_sparc
;
3164 tdep
->fp_register_bytes
= 32 * 4;
3165 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3167 case bfd_mach_sparc_v8plusa
:
3168 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3169 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3170 set_gdbarch_num_regs (gdbarch
, 72);
3171 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4);
3172 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
3173 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3174 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3175 tdep
->fp_register_bytes
= 32 * 4;
3176 tdep
->print_insn_mach
= bfd_mach_sparc
;
3178 case bfd_mach_sparc_sparclite_le
:
3179 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3180 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
3181 set_gdbarch_num_regs (gdbarch
, 80);
3182 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4 + 8*4);
3183 set_gdbarch_register_name (gdbarch
, sparclite_register_name
);
3184 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3185 tdep
->has_fpu
= 0; /* (all but sparclet and sparclite) */
3186 tdep
->fp_register_bytes
= 0;
3187 tdep
->print_insn_mach
= bfd_mach_sparc_sparclite
;
3189 case bfd_mach_sparc_v9
:
3190 set_gdbarch_extract_return_value (gdbarch
, sparc64_extract_return_value
);
3191 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3192 set_gdbarch_num_regs (gdbarch
, 125);
3193 set_gdbarch_register_bytes (gdbarch
, 32*8 + 32*8 + 45*8);
3194 set_gdbarch_register_name (gdbarch
, sparc64_register_name
);
3195 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3196 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3197 tdep
->fp_register_bytes
= 64 * 4;
3198 tdep
->print_insn_mach
= bfd_mach_sparc_v9a
;
3200 case bfd_mach_sparc_v9a
:
3201 set_gdbarch_extract_return_value (gdbarch
, sparc64_extract_return_value
);
3202 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3203 set_gdbarch_num_regs (gdbarch
, 125);
3204 set_gdbarch_register_bytes (gdbarch
, 32*8 + 32*8 + 45*8);
3205 set_gdbarch_register_name (gdbarch
, sparc64_register_name
);
3206 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3207 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3208 tdep
->fp_register_bytes
= 64 * 4;
3209 tdep
->print_insn_mach
= bfd_mach_sparc_v9a
;