1 /* Target-dependent code for the SPARC for GDB, the GNU debugger.
3 Copyright 1986, 1987, 1989, 1990, 1991, 1992, 1993, 1994, 1995,
4 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation,
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 /* ??? Support for calling functions from gdb in sparc64 is unfinished. */
27 #include "arch-utils.h"
34 #include "gdb_string.h"
38 #include <sys/procfs.h>
39 /* Prototypes for supply_gregset etc. */
45 #include "symfile.h" /* for 'entry_point_address' */
48 * Some local macros that have multi-arch and non-multi-arch versions:
51 #if (GDB_MULTI_ARCH > 0)
53 /* Does the target have Floating Point registers? */
54 #define SPARC_HAS_FPU (gdbarch_tdep (current_gdbarch)->has_fpu)
55 /* Number of bytes devoted to Floating Point registers: */
56 #define FP_REGISTER_BYTES (gdbarch_tdep (current_gdbarch)->fp_register_bytes)
57 /* Highest numbered Floating Point register. */
58 #define FP_MAX_REGNUM (gdbarch_tdep (current_gdbarch)->fp_max_regnum)
59 /* Size of a general (integer) register: */
60 #define SPARC_INTREG_SIZE (gdbarch_tdep (current_gdbarch)->intreg_size)
61 /* Offset within the call dummy stack of the saved registers. */
62 #define DUMMY_REG_SAVE_OFFSET (gdbarch_tdep (current_gdbarch)->reg_save_offset)
64 #else /* non-multi-arch */
67 /* Does the target have Floating Point registers? */
68 #if defined(TARGET_SPARCLET) || defined(TARGET_SPARCLITE)
69 #define SPARC_HAS_FPU 0
71 #define SPARC_HAS_FPU 1
74 /* Number of bytes devoted to Floating Point registers: */
75 #if (GDB_TARGET_IS_SPARC64)
76 #define FP_REGISTER_BYTES (64 * 4)
79 #define FP_REGISTER_BYTES (32 * 4)
81 #define FP_REGISTER_BYTES 0
85 /* Highest numbered Floating Point register. */
86 #if (GDB_TARGET_IS_SPARC64)
87 #define FP_MAX_REGNUM (FP0_REGNUM + 48)
89 #define FP_MAX_REGNUM (FP0_REGNUM + 32)
92 /* Size of a general (integer) register: */
93 #define SPARC_INTREG_SIZE (REGISTER_RAW_SIZE (G0_REGNUM))
95 /* Offset within the call dummy stack of the saved registers. */
96 #if (GDB_TARGET_IS_SPARC64)
97 #define DUMMY_REG_SAVE_OFFSET (128 + 16)
99 #define DUMMY_REG_SAVE_OFFSET 0x60
102 #endif /* GDB_MULTI_ARCH */
107 int fp_register_bytes
;
112 int call_dummy_call_offset
;
116 /* Now make GDB_TARGET_IS_SPARC64 a runtime test. */
117 /* FIXME MVS: or try testing bfd_arch_info.arch and bfd_arch_info.mach ...
118 * define GDB_TARGET_IS_SPARC64 \
119 * (TARGET_ARCHITECTURE->arch == bfd_arch_sparc && \
120 * (TARGET_ARCHITECTURE->mach == bfd_mach_sparc_v9 || \
121 * TARGET_ARCHITECTURE->mach == bfd_mach_sparc_v9a))
125 extern int stop_after_trap
;
127 /* We don't store all registers immediately when requested, since they
128 get sent over in large chunks anyway. Instead, we accumulate most
129 of the changes and send them over once. "deferred_stores" keeps
130 track of which sets of registers we have locally-changed copies of,
131 so we only need send the groups that have changed. */
133 int deferred_stores
= 0; /* Accumulated stores we want to do eventually. */
136 /* Some machines, such as Fujitsu SPARClite 86x, have a bi-endian mode
137 where instructions are big-endian and data are little-endian.
138 This flag is set when we detect that the target is of this type. */
143 /* Fetch a single instruction. Even on bi-endian machines
144 such as sparc86x, instructions are always big-endian. */
147 fetch_instruction (CORE_ADDR pc
)
149 unsigned long retval
;
151 unsigned char buf
[4];
153 read_memory (pc
, buf
, sizeof (buf
));
155 /* Start at the most significant end of the integer, and work towards
156 the least significant. */
158 for (i
= 0; i
< sizeof (buf
); ++i
)
159 retval
= (retval
<< 8) | buf
[i
];
164 /* Branches with prediction are treated like their non-predicting cousins. */
165 /* FIXME: What about floating point branches? */
167 /* Macros to extract fields from sparc instructions. */
168 #define X_OP(i) (((i) >> 30) & 0x3)
169 #define X_RD(i) (((i) >> 25) & 0x1f)
170 #define X_A(i) (((i) >> 29) & 1)
171 #define X_COND(i) (((i) >> 25) & 0xf)
172 #define X_OP2(i) (((i) >> 22) & 0x7)
173 #define X_IMM22(i) ((i) & 0x3fffff)
174 #define X_OP3(i) (((i) >> 19) & 0x3f)
175 #define X_RS1(i) (((i) >> 14) & 0x1f)
176 #define X_I(i) (((i) >> 13) & 1)
177 #define X_IMM13(i) ((i) & 0x1fff)
178 /* Sign extension macros. */
179 #define X_SIMM13(i) ((X_IMM13 (i) ^ 0x1000) - 0x1000)
180 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
181 #define X_CC(i) (((i) >> 20) & 3)
182 #define X_P(i) (((i) >> 19) & 1)
183 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
184 #define X_RCOND(i) (((i) >> 25) & 7)
185 #define X_DISP16(i) ((((((i) >> 6) && 0xc000) | ((i) & 0x3fff)) ^ 0x8000) - 0x8000)
186 #define X_FCN(i) (((i) >> 25) & 31)
190 Error
, not_branch
, bicc
, bicca
, ba
, baa
, ticc
, ta
, done_retry
193 /* Simulate single-step ptrace call for sun4. Code written by Gary
194 Beihl (beihl@mcc.com). */
196 /* npc4 and next_pc describe the situation at the time that the
197 step-breakpoint was set, not necessary the current value of NPC_REGNUM. */
198 static CORE_ADDR next_pc
, npc4
, target
;
199 static int brknpc4
, brktrg
;
200 typedef char binsn_quantum
[BREAKPOINT_MAX
];
201 static binsn_quantum break_mem
[3];
203 static branch_type
isbranch (long, CORE_ADDR
, CORE_ADDR
*);
205 /* single_step() is called just before we want to resume the inferior,
206 if we want to single-step it but there is no hardware or kernel single-step
207 support (as on all SPARCs). We find all the possible targets of the
208 coming instruction and breakpoint them.
210 single_step is also called just after the inferior stops. If we had
211 set up a simulated single-step, we undo our damage. */
214 sparc_software_single_step (enum target_signal ignore
, /* pid, but we don't need it */
215 int insert_breakpoints_p
)
221 if (insert_breakpoints_p
)
223 /* Always set breakpoint for NPC. */
224 next_pc
= read_register (NPC_REGNUM
);
225 npc4
= next_pc
+ 4; /* branch not taken */
227 target_insert_breakpoint (next_pc
, break_mem
[0]);
228 /* printf_unfiltered ("set break at %x\n",next_pc); */
230 pc
= read_register (PC_REGNUM
);
231 pc_instruction
= fetch_instruction (pc
);
232 br
= isbranch (pc_instruction
, pc
, &target
);
233 brknpc4
= brktrg
= 0;
237 /* Conditional annulled branch will either end up at
238 npc (if taken) or at npc+4 (if not taken).
241 target_insert_breakpoint (npc4
, break_mem
[1]);
243 else if (br
== baa
&& target
!= next_pc
)
245 /* Unconditional annulled branch will always end up at
248 target_insert_breakpoint (target
, break_mem
[2]);
250 else if (GDB_TARGET_IS_SPARC64
&& br
== done_retry
)
253 target_insert_breakpoint (target
, break_mem
[2]);
258 /* Remove breakpoints */
259 target_remove_breakpoint (next_pc
, break_mem
[0]);
262 target_remove_breakpoint (npc4
, break_mem
[1]);
265 target_remove_breakpoint (target
, break_mem
[2]);
269 struct frame_extra_info
274 /* Following fields only relevant for flat frames. */
277 /* Add this to ->frame to get the value of the stack pointer at the
278 time of the register saves. */
282 /* Call this for each newly created frame. For SPARC, we need to
283 calculate the bottom of the frame, and do some extra work if the
284 prologue has been generated via the -mflat option to GCC. In
285 particular, we need to know where the previous fp and the pc have
286 been stashed, since their exact position within the frame may vary. */
289 sparc_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
292 CORE_ADDR prologue_start
, prologue_end
;
295 fi
->extra_info
= (struct frame_extra_info
*)
296 frame_obstack_alloc (sizeof (struct frame_extra_info
));
297 frame_saved_regs_zalloc (fi
);
299 fi
->extra_info
->bottom
=
301 (fi
->frame
== fi
->next
->frame
? fi
->next
->extra_info
->bottom
:
302 fi
->next
->frame
) : read_sp ());
304 /* If fi->next is NULL, then we already set ->frame by passing read_fp()
305 to create_new_frame. */
310 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
312 /* Compute ->frame as if not flat. If it is flat, we'll change
314 if (fi
->next
->next
!= NULL
315 && (fi
->next
->next
->signal_handler_caller
316 || frame_in_dummy (fi
->next
->next
))
317 && frameless_look_for_prologue (fi
->next
))
319 /* A frameless function interrupted by a signal did not change
320 the frame pointer, fix up frame pointer accordingly. */
321 fi
->frame
= FRAME_FP (fi
->next
);
322 fi
->extra_info
->bottom
= fi
->next
->extra_info
->bottom
;
326 /* Should we adjust for stack bias here? */
327 get_saved_register (buf
, 0, 0, fi
, FP_REGNUM
, 0);
328 fi
->frame
= extract_address (buf
, REGISTER_RAW_SIZE (FP_REGNUM
));
330 if (GDB_TARGET_IS_SPARC64
&& (fi
->frame
& 1))
335 /* Decide whether this is a function with a ``flat register window''
336 frame. For such functions, the frame pointer is actually in %i7. */
337 fi
->extra_info
->flat
= 0;
338 fi
->extra_info
->in_prologue
= 0;
339 if (find_pc_partial_function (fi
->pc
, &name
, &prologue_start
, &prologue_end
))
341 /* See if the function starts with an add (which will be of a
342 negative number if a flat frame) to the sp. FIXME: Does not
343 handle large frames which will need more than one instruction
345 insn
= fetch_instruction (prologue_start
);
346 if (X_OP (insn
) == 2 && X_RD (insn
) == 14 && X_OP3 (insn
) == 0
347 && X_I (insn
) && X_SIMM13 (insn
) < 0)
349 int offset
= X_SIMM13 (insn
);
351 /* Then look for a save of %i7 into the frame. */
352 insn
= fetch_instruction (prologue_start
+ 4);
356 && X_RS1 (insn
) == 14)
360 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
362 /* We definitely have a flat frame now. */
363 fi
->extra_info
->flat
= 1;
365 fi
->extra_info
->sp_offset
= offset
;
367 /* Overwrite the frame's address with the value in %i7. */
368 get_saved_register (buf
, 0, 0, fi
, I7_REGNUM
, 0);
369 fi
->frame
= extract_address (buf
, REGISTER_RAW_SIZE (I7_REGNUM
));
371 if (GDB_TARGET_IS_SPARC64
&& (fi
->frame
& 1))
374 /* Record where the fp got saved. */
375 fi
->extra_info
->fp_addr
=
376 fi
->frame
+ fi
->extra_info
->sp_offset
+ X_SIMM13 (insn
);
378 /* Also try to collect where the pc got saved to. */
379 fi
->extra_info
->pc_addr
= 0;
380 insn
= fetch_instruction (prologue_start
+ 12);
384 && X_RS1 (insn
) == 14)
385 fi
->extra_info
->pc_addr
=
386 fi
->frame
+ fi
->extra_info
->sp_offset
+ X_SIMM13 (insn
);
391 /* Check if the PC is in the function prologue before a SAVE
392 instruction has been executed yet. If so, set the frame
393 to the current value of the stack pointer and set
394 the in_prologue flag. */
396 struct symtab_and_line sal
;
398 sal
= find_pc_line (prologue_start
, 0);
399 if (sal
.line
== 0) /* no line info, use PC */
400 prologue_end
= fi
->pc
;
401 else if (sal
.end
< prologue_end
)
402 prologue_end
= sal
.end
;
403 if (fi
->pc
< prologue_end
)
405 for (addr
= prologue_start
; addr
< fi
->pc
; addr
+= 4)
407 insn
= read_memory_integer (addr
, 4);
408 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 0x3c)
409 break; /* SAVE seen, stop searching */
413 fi
->extra_info
->in_prologue
= 1;
414 fi
->frame
= read_register (SP_REGNUM
);
419 if (fi
->next
&& fi
->frame
== 0)
421 /* Kludge to cause init_prev_frame_info to destroy the new frame. */
422 fi
->frame
= fi
->next
->frame
;
423 fi
->pc
= fi
->next
->pc
;
428 sparc_frame_chain (struct frame_info
*frame
)
430 /* Value that will cause FRAME_CHAIN_VALID to not worry about the chain
431 value. If it really is zero, we detect it later in
432 sparc_init_prev_frame. */
433 return (CORE_ADDR
) 1;
437 sparc_extract_struct_value_address (char *regbuf
)
439 return extract_address (regbuf
+ REGISTER_BYTE (O0_REGNUM
),
440 REGISTER_RAW_SIZE (O0_REGNUM
));
443 /* Find the pc saved in frame FRAME. */
446 sparc_frame_saved_pc (struct frame_info
*frame
)
451 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
452 if (frame
->signal_handler_caller
)
454 /* This is the signal trampoline frame.
455 Get the saved PC from the sigcontext structure. */
457 #ifndef SIGCONTEXT_PC_OFFSET
458 #define SIGCONTEXT_PC_OFFSET 12
461 CORE_ADDR sigcontext_addr
;
463 int saved_pc_offset
= SIGCONTEXT_PC_OFFSET
;
466 scbuf
= alloca (TARGET_PTR_BIT
/ HOST_CHAR_BIT
);
468 /* Solaris2 ucbsigvechandler passes a pointer to a sigcontext
469 as the third parameter. The offset to the saved pc is 12. */
470 find_pc_partial_function (frame
->pc
, &name
,
471 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
472 if (name
&& STREQ (name
, "ucbsigvechandler"))
473 saved_pc_offset
= 12;
475 /* The sigcontext address is contained in register O2. */
476 get_saved_register (buf
, (int *) NULL
, (CORE_ADDR
*) NULL
,
477 frame
, O0_REGNUM
+ 2, (enum lval_type
*) NULL
);
478 sigcontext_addr
= extract_address (buf
, REGISTER_RAW_SIZE (O0_REGNUM
+ 2));
480 /* Don't cause a memory_error when accessing sigcontext in case the
481 stack layout has changed or the stack is corrupt. */
482 target_read_memory (sigcontext_addr
+ saved_pc_offset
,
483 scbuf
, sizeof (scbuf
));
484 return extract_address (scbuf
, sizeof (scbuf
));
486 else if (frame
->extra_info
->in_prologue
||
487 (frame
->next
!= NULL
&&
488 (frame
->next
->signal_handler_caller
||
489 frame_in_dummy (frame
->next
)) &&
490 frameless_look_for_prologue (frame
)))
492 /* A frameless function interrupted by a signal did not save
493 the PC, it is still in %o7. */
494 get_saved_register (buf
, (int *) NULL
, (CORE_ADDR
*) NULL
,
495 frame
, O7_REGNUM
, (enum lval_type
*) NULL
);
496 return PC_ADJUST (extract_address (buf
, SPARC_INTREG_SIZE
));
498 if (frame
->extra_info
->flat
)
499 addr
= frame
->extra_info
->pc_addr
;
501 addr
= frame
->extra_info
->bottom
+ FRAME_SAVED_I0
+
502 SPARC_INTREG_SIZE
* (I7_REGNUM
- I0_REGNUM
);
505 /* A flat frame leaf function might not save the PC anywhere,
506 just leave it in %o7. */
507 return PC_ADJUST (read_register (O7_REGNUM
));
509 read_memory (addr
, buf
, SPARC_INTREG_SIZE
);
510 return PC_ADJUST (extract_address (buf
, SPARC_INTREG_SIZE
));
513 /* Since an individual frame in the frame cache is defined by two
514 arguments (a frame pointer and a stack pointer), we need two
515 arguments to get info for an arbitrary stack frame. This routine
516 takes two arguments and makes the cached frames look as if these
517 two arguments defined a frame on the cache. This allows the rest
518 of info frame to extract the important arguments without
522 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
524 struct frame_info
*frame
;
527 error ("Sparc frame specifications require two arguments: fp and sp");
529 frame
= create_new_frame (argv
[0], 0);
532 internal_error (__FILE__
, __LINE__
,
533 "create_new_frame returned invalid frame");
535 frame
->extra_info
->bottom
= argv
[1];
536 frame
->pc
= FRAME_SAVED_PC (frame
);
540 /* Given a pc value, skip it forward past the function prologue by
541 disassembling instructions that appear to be a prologue.
543 If FRAMELESS_P is set, we are only testing to see if the function
544 is frameless. This allows a quicker answer.
546 This routine should be more specific in its actions; making sure
547 that it uses the same register in the initial prologue section. */
549 static CORE_ADDR
examine_prologue (CORE_ADDR
, int, struct frame_info
*,
553 examine_prologue (CORE_ADDR start_pc
, int frameless_p
, struct frame_info
*fi
,
554 CORE_ADDR
*saved_regs
)
558 CORE_ADDR pc
= start_pc
;
561 insn
= fetch_instruction (pc
);
563 /* Recognize the `sethi' insn and record its destination. */
564 if (X_OP (insn
) == 0 && X_OP2 (insn
) == 4)
568 insn
= fetch_instruction (pc
);
571 /* Recognize an add immediate value to register to either %g1 or
572 the destination register recorded above. Actually, this might
573 well recognize several different arithmetic operations.
574 It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1"
575 followed by "save %sp, %g1, %sp" is a valid prologue (Not that
576 I imagine any compiler really does that, however). */
579 && (X_RD (insn
) == 1 || X_RD (insn
) == dest
))
582 insn
= fetch_instruction (pc
);
585 /* Recognize any SAVE insn. */
586 if (X_OP (insn
) == 2 && X_OP3 (insn
) == 60)
589 if (frameless_p
) /* If the save is all we care about, */
590 return pc
; /* return before doing more work */
591 insn
= fetch_instruction (pc
);
593 /* Recognize add to %sp. */
594 else if (X_OP (insn
) == 2 && X_RD (insn
) == 14 && X_OP3 (insn
) == 0)
597 if (frameless_p
) /* If the add is all we care about, */
598 return pc
; /* return before doing more work */
600 insn
= fetch_instruction (pc
);
601 /* Recognize store of frame pointer (i7). */
605 && X_RS1 (insn
) == 14)
608 insn
= fetch_instruction (pc
);
610 /* Recognize sub %sp, <anything>, %i7. */
613 && X_RS1 (insn
) == 14
614 && X_RD (insn
) == 31)
617 insn
= fetch_instruction (pc
);
626 /* Without a save or add instruction, it's not a prologue. */
631 /* Recognize stores into the frame from the input registers.
632 This recognizes all non alternate stores of an input register,
633 into a location offset from the frame pointer between
636 /* The above will fail for arguments that are promoted
637 (eg. shorts to ints or floats to doubles), because the compiler
638 will pass them in positive-offset frame space, but the prologue
639 will save them (after conversion) in negative frame space at an
640 unpredictable offset. Therefore I am going to remove the
641 restriction on the target-address of the save, on the theory
642 that any unbroken sequence of saves from input registers must
643 be part of the prologue. In un-optimized code (at least), I'm
644 fairly sure that the compiler would emit SOME other instruction
645 (eg. a move or add) before emitting another save that is actually
646 a part of the function body.
648 Besides, the reserved stack space is different for SPARC64 anyway.
653 && (X_OP3 (insn
) & 0x3c) == 4 /* Store, non-alternate. */
654 && (X_RD (insn
) & 0x18) == 0x18 /* Input register. */
655 && X_I (insn
) /* Immediate mode. */
656 && X_RS1 (insn
) == 30) /* Off of frame pointer. */
657 ; /* empty statement -- fall thru to end of loop */
658 else if (GDB_TARGET_IS_SPARC64
660 && (X_OP3 (insn
) & 0x3c) == 12 /* store, extended (64-bit) */
661 && (X_RD (insn
) & 0x18) == 0x18 /* input register */
662 && X_I (insn
) /* immediate mode */
663 && X_RS1 (insn
) == 30) /* off of frame pointer */
664 ; /* empty statement -- fall thru to end of loop */
665 else if (X_OP (insn
) == 3
666 && (X_OP3 (insn
) & 0x3c) == 36 /* store, floating-point */
667 && X_I (insn
) /* immediate mode */
668 && X_RS1 (insn
) == 30) /* off of frame pointer */
669 ; /* empty statement -- fall thru to end of loop */
672 && X_OP3 (insn
) == 4 /* store? */
673 && X_RS1 (insn
) == 14) /* off of frame pointer */
675 if (saved_regs
&& X_I (insn
))
676 saved_regs
[X_RD (insn
)] =
677 fi
->frame
+ fi
->extra_info
->sp_offset
+ X_SIMM13 (insn
);
682 insn
= fetch_instruction (pc
);
688 /* Advance PC across any function entry prologue instructions to reach
692 sparc_skip_prologue (CORE_ADDR start_pc
)
694 struct symtab_and_line sal
;
695 CORE_ADDR func_start
, func_end
;
697 /* This is the preferred method, find the end of the prologue by
698 using the debugging information. */
699 if (find_pc_partial_function (start_pc
, NULL
, &func_start
, &func_end
))
701 sal
= find_pc_line (func_start
, 0);
703 if (sal
.end
< func_end
704 && start_pc
<= sal
.end
)
708 /* Oh well, examine the code by hand. */
709 return examine_prologue (start_pc
, 0, NULL
, NULL
);
712 /* Is the prologue at IP frameless? */
715 sparc_prologue_frameless_p (CORE_ADDR ip
)
717 return ip
== examine_prologue (ip
, 1, NULL
, NULL
);
720 /* Check instruction at ADDR to see if it is a branch.
721 All non-annulled instructions will go to NPC or will trap.
722 Set *TARGET if we find a candidate branch; set to zero if not.
724 This isn't static as it's used by remote-sa.sparc.c. */
727 isbranch (long instruction
, CORE_ADDR addr
, CORE_ADDR
*target
)
729 branch_type val
= not_branch
;
730 long int offset
= 0; /* Must be signed for sign-extend. */
734 if (X_OP (instruction
) == 0
735 && (X_OP2 (instruction
) == 2
736 || X_OP2 (instruction
) == 6
737 || X_OP2 (instruction
) == 1
738 || X_OP2 (instruction
) == 3
739 || X_OP2 (instruction
) == 5
740 || (GDB_TARGET_IS_SPARC64
&& X_OP2 (instruction
) == 7)))
742 if (X_COND (instruction
) == 8)
743 val
= X_A (instruction
) ? baa
: ba
;
745 val
= X_A (instruction
) ? bicca
: bicc
;
746 switch (X_OP2 (instruction
))
749 if (!GDB_TARGET_IS_SPARC64
)
754 offset
= 4 * X_DISP22 (instruction
);
758 offset
= 4 * X_DISP19 (instruction
);
761 offset
= 4 * X_DISP16 (instruction
);
764 *target
= addr
+ offset
;
766 else if (GDB_TARGET_IS_SPARC64
767 && X_OP (instruction
) == 2
768 && X_OP3 (instruction
) == 62)
770 if (X_FCN (instruction
) == 0)
773 *target
= read_register (TNPC_REGNUM
);
776 else if (X_FCN (instruction
) == 1)
779 *target
= read_register (TPC_REGNUM
);
787 /* Find register number REGNUM relative to FRAME and put its
788 (raw) contents in *RAW_BUFFER. Set *OPTIMIZED if the variable
789 was optimized out (and thus can't be fetched). If the variable
790 was fetched from memory, set *ADDRP to where it was fetched from,
791 otherwise it was fetched from a register.
793 The argument RAW_BUFFER must point to aligned memory. */
796 sparc_get_saved_register (char *raw_buffer
, int *optimized
, CORE_ADDR
*addrp
,
797 struct frame_info
*frame
, int regnum
,
798 enum lval_type
*lval
)
800 struct frame_info
*frame1
;
803 if (!target_has_registers
)
804 error ("No registers.");
811 /* FIXME This code extracted from infcmd.c; should put elsewhere! */
814 /* error ("No selected frame."); */
815 if (!target_has_registers
)
816 error ("The program has no registers now.");
817 if (selected_frame
== NULL
)
818 error ("No selected frame.");
819 /* Try to use selected frame */
820 frame
= get_prev_frame (selected_frame
);
822 error ("Cmd not meaningful in the outermost frame.");
826 frame1
= frame
->next
;
828 /* Get saved PC from the frame info if not in innermost frame. */
829 if (regnum
== PC_REGNUM
&& frame1
!= NULL
)
833 if (raw_buffer
!= NULL
)
835 /* Put it back in target format. */
836 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), frame
->pc
);
843 while (frame1
!= NULL
)
845 /* FIXME MVS: wrong test for dummy frame at entry. */
847 if (frame1
->pc
>= (frame1
->extra_info
->bottom
?
848 frame1
->extra_info
->bottom
: read_sp ())
849 && frame1
->pc
<= FRAME_FP (frame1
))
851 /* Dummy frame. All but the window regs are in there somewhere.
852 The window registers are saved on the stack, just like in a
854 if (regnum
>= G1_REGNUM
&& regnum
< G1_REGNUM
+ 7)
855 addr
= frame1
->frame
+ (regnum
- G0_REGNUM
) * SPARC_INTREG_SIZE
856 - (FP_REGISTER_BYTES
+ 8 * SPARC_INTREG_SIZE
);
857 else if (regnum
>= I0_REGNUM
&& regnum
< I0_REGNUM
+ 8)
858 /* NOTE: cagney/2002-05-04: The call to get_prev_frame()
859 is safe/cheap - there will always be a prev frame.
860 This is because frame1 is initialized to frame->next
861 (frame1->prev == frame) and is then advanced towards
862 the innermost (next) frame. */
863 addr
= (get_prev_frame (frame1
)->extra_info
->bottom
864 + (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
866 else if (regnum
>= L0_REGNUM
&& regnum
< L0_REGNUM
+ 8)
867 /* NOTE: cagney/2002-05-04: The call to get_prev_frame()
868 is safe/cheap - there will always be a prev frame.
869 This is because frame1 is initialized to frame->next
870 (frame1->prev == frame) and is then advanced towards
871 the innermost (next) frame. */
872 addr
= (get_prev_frame (frame1
)->extra_info
->bottom
873 + (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
875 else if (regnum
>= O0_REGNUM
&& regnum
< O0_REGNUM
+ 8)
876 addr
= frame1
->frame
+ (regnum
- O0_REGNUM
) * SPARC_INTREG_SIZE
877 - (FP_REGISTER_BYTES
+ 16 * SPARC_INTREG_SIZE
);
878 else if (SPARC_HAS_FPU
&&
879 regnum
>= FP0_REGNUM
&& regnum
< FP0_REGNUM
+ 32)
880 addr
= frame1
->frame
+ (regnum
- FP0_REGNUM
) * 4
881 - (FP_REGISTER_BYTES
);
882 else if (GDB_TARGET_IS_SPARC64
&& SPARC_HAS_FPU
&&
883 regnum
>= FP0_REGNUM
+ 32 && regnum
< FP_MAX_REGNUM
)
884 addr
= frame1
->frame
+ 32 * 4 + (regnum
- FP0_REGNUM
- 32) * 8
885 - (FP_REGISTER_BYTES
);
886 else if (regnum
>= Y_REGNUM
&& regnum
< NUM_REGS
)
887 addr
= frame1
->frame
+ (regnum
- Y_REGNUM
) * SPARC_INTREG_SIZE
888 - (FP_REGISTER_BYTES
+ 24 * SPARC_INTREG_SIZE
);
890 else if (frame1
->extra_info
->flat
)
893 if (regnum
== RP_REGNUM
)
894 addr
= frame1
->extra_info
->pc_addr
;
895 else if (regnum
== I7_REGNUM
)
896 addr
= frame1
->extra_info
->fp_addr
;
899 CORE_ADDR func_start
;
902 regs
= alloca (NUM_REGS
* sizeof (CORE_ADDR
));
903 memset (regs
, 0, NUM_REGS
* sizeof (CORE_ADDR
));
905 find_pc_partial_function (frame1
->pc
, NULL
, &func_start
, NULL
);
906 examine_prologue (func_start
, 0, frame1
, regs
);
912 /* Normal frame. Local and In registers are saved on stack. */
913 if (regnum
>= I0_REGNUM
&& regnum
< I0_REGNUM
+ 8)
914 addr
= (get_prev_frame (frame1
)->extra_info
->bottom
915 + (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
917 else if (regnum
>= L0_REGNUM
&& regnum
< L0_REGNUM
+ 8)
918 addr
= (get_prev_frame (frame1
)->extra_info
->bottom
919 + (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
921 else if (regnum
>= O0_REGNUM
&& regnum
< O0_REGNUM
+ 8)
923 /* Outs become ins. */
924 get_saved_register (raw_buffer
, optimized
, addrp
, frame1
,
925 (regnum
- O0_REGNUM
+ I0_REGNUM
), lval
);
931 frame1
= frame1
->next
;
937 if (regnum
== SP_REGNUM
)
939 if (raw_buffer
!= NULL
)
941 /* Put it back in target format. */
942 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), addr
);
948 if (raw_buffer
!= NULL
)
949 read_memory (addr
, raw_buffer
, REGISTER_RAW_SIZE (regnum
));
954 *lval
= lval_register
;
955 addr
= REGISTER_BYTE (regnum
);
956 if (raw_buffer
!= NULL
)
957 read_register_gen (regnum
, raw_buffer
);
963 /* Push an empty stack frame, and record in it the current PC, regs, etc.
965 We save the non-windowed registers and the ins. The locals and outs
966 are new; they don't need to be saved. The i's and l's of
967 the last frame were already saved on the stack. */
969 /* Definitely see tm-sparc.h for more doc of the frame format here. */
971 /* See tm-sparc.h for how this is calculated. */
973 #define DUMMY_STACK_REG_BUF_SIZE \
974 (((8+8+8) * SPARC_INTREG_SIZE) + FP_REGISTER_BYTES)
975 #define DUMMY_STACK_SIZE \
976 (DUMMY_STACK_REG_BUF_SIZE + DUMMY_REG_SAVE_OFFSET)
979 sparc_push_dummy_frame (void)
981 CORE_ADDR sp
, old_sp
;
984 register_temp
= alloca (DUMMY_STACK_SIZE
);
986 old_sp
= sp
= read_sp ();
988 if (GDB_TARGET_IS_SPARC64
)
990 /* PC, NPC, CCR, FSR, FPRS, Y, ASI */
991 read_register_bytes (REGISTER_BYTE (PC_REGNUM
), ®ister_temp
[0],
992 REGISTER_RAW_SIZE (PC_REGNUM
) * 7);
993 read_register_bytes (REGISTER_BYTE (PSTATE_REGNUM
),
994 ®ister_temp
[7 * SPARC_INTREG_SIZE
],
995 REGISTER_RAW_SIZE (PSTATE_REGNUM
));
996 /* FIXME: not sure what needs to be saved here. */
1000 /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */
1001 read_register_bytes (REGISTER_BYTE (Y_REGNUM
), ®ister_temp
[0],
1002 REGISTER_RAW_SIZE (Y_REGNUM
) * 8);
1005 read_register_bytes (REGISTER_BYTE (O0_REGNUM
),
1006 ®ister_temp
[8 * SPARC_INTREG_SIZE
],
1007 SPARC_INTREG_SIZE
* 8);
1009 read_register_bytes (REGISTER_BYTE (G0_REGNUM
),
1010 ®ister_temp
[16 * SPARC_INTREG_SIZE
],
1011 SPARC_INTREG_SIZE
* 8);
1014 read_register_bytes (REGISTER_BYTE (FP0_REGNUM
),
1015 ®ister_temp
[24 * SPARC_INTREG_SIZE
],
1018 sp
-= DUMMY_STACK_SIZE
;
1022 write_memory (sp
+ DUMMY_REG_SAVE_OFFSET
, ®ister_temp
[0],
1023 DUMMY_STACK_REG_BUF_SIZE
);
1025 if (strcmp (target_shortname
, "sim") != 0)
1027 /* NOTE: cagney/2002-04-04: The code below originally contained
1028 GDB's _only_ call to write_fp(). That call was eliminated by
1029 inlining the corresponding code. For the 64 bit case, the
1030 old function (sparc64_write_fp) did the below although I'm
1031 not clear why. The same goes for why this is only done when
1032 the underlying target is a simulator. */
1033 if (GDB_TARGET_IS_SPARC64
)
1035 /* Target is a 64 bit SPARC. */
1036 CORE_ADDR oldfp
= read_register (FP_REGNUM
);
1038 write_register (FP_REGNUM
, old_sp
- 2047);
1040 write_register (FP_REGNUM
, old_sp
);
1044 /* Target is a 32 bit SPARC. */
1045 write_register (FP_REGNUM
, old_sp
);
1047 /* Set return address register for the call dummy to the current PC. */
1048 write_register (I7_REGNUM
, read_pc () - 8);
1052 /* The call dummy will write this value to FP before executing
1053 the 'save'. This ensures that register window flushes work
1054 correctly in the simulator. */
1055 write_register (G0_REGNUM
+ 1, read_register (FP_REGNUM
));
1057 /* The call dummy will write this value to FP after executing
1059 write_register (G0_REGNUM
+ 2, old_sp
);
1061 /* The call dummy will write this value to the return address (%i7) after
1062 executing the 'save'. */
1063 write_register (G0_REGNUM
+ 3, read_pc () - 8);
1065 /* Set the FP that the call dummy will be using after the 'save'.
1066 This makes backtraces from an inferior function call work properly. */
1067 write_register (FP_REGNUM
, old_sp
);
1071 /* sparc_frame_find_saved_regs (). This function is here only because
1072 pop_frame uses it. Note there is an interesting corner case which
1073 I think few ports of GDB get right--if you are popping a frame
1074 which does not save some register that *is* saved by a more inner
1075 frame (such a frame will never be a dummy frame because dummy
1076 frames save all registers). Rewriting pop_frame to use
1077 get_saved_register would solve this problem and also get rid of the
1078 ugly duplication between sparc_frame_find_saved_regs and
1081 Stores, into an array of CORE_ADDR,
1082 the addresses of the saved registers of frame described by FRAME_INFO.
1083 This includes special registers such as pc and fp saved in special
1084 ways in the stack frame. sp is even more special:
1085 the address we return for it IS the sp for the next frame.
1087 Note that on register window machines, we are currently making the
1088 assumption that window registers are being saved somewhere in the
1089 frame in which they are being used. If they are stored in an
1090 inferior frame, find_saved_register will break.
1092 On the Sun 4, the only time all registers are saved is when
1093 a dummy frame is involved. Otherwise, the only saved registers
1094 are the LOCAL and IN registers which are saved as a result
1095 of the "save/restore" opcodes. This condition is determined
1096 by address rather than by value.
1098 The "pc" is not stored in a frame on the SPARC. (What is stored
1099 is a return address minus 8.) sparc_pop_frame knows how to
1100 deal with that. Other routines might or might not.
1102 See tm-sparc.h (PUSH_DUMMY_FRAME and friends) for CRITICAL information
1103 about how this works. */
1105 static void sparc_frame_find_saved_regs (struct frame_info
*, CORE_ADDR
*);
1108 sparc_frame_find_saved_regs (struct frame_info
*fi
, CORE_ADDR
*saved_regs_addr
)
1110 register int regnum
;
1111 CORE_ADDR frame_addr
= FRAME_FP (fi
);
1114 internal_error (__FILE__
, __LINE__
,
1115 "Bad frame info struct in FRAME_FIND_SAVED_REGS");
1117 memset (saved_regs_addr
, 0, NUM_REGS
* sizeof (CORE_ADDR
));
1119 if (fi
->pc
>= (fi
->extra_info
->bottom
?
1120 fi
->extra_info
->bottom
: read_sp ())
1121 && fi
->pc
<= FRAME_FP (fi
))
1123 /* Dummy frame. All but the window regs are in there somewhere. */
1124 for (regnum
= G1_REGNUM
; regnum
< G1_REGNUM
+ 7; regnum
++)
1125 saved_regs_addr
[regnum
] =
1126 frame_addr
+ (regnum
- G0_REGNUM
) * SPARC_INTREG_SIZE
1127 - DUMMY_STACK_REG_BUF_SIZE
+ 16 * SPARC_INTREG_SIZE
;
1129 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+ 8; regnum
++)
1130 saved_regs_addr
[regnum
] =
1131 frame_addr
+ (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
1132 - DUMMY_STACK_REG_BUF_SIZE
+ 8 * SPARC_INTREG_SIZE
;
1135 for (regnum
= FP0_REGNUM
; regnum
< FP_MAX_REGNUM
; regnum
++)
1136 saved_regs_addr
[regnum
] = frame_addr
+ (regnum
- FP0_REGNUM
) * 4
1137 - DUMMY_STACK_REG_BUF_SIZE
+ 24 * SPARC_INTREG_SIZE
;
1139 if (GDB_TARGET_IS_SPARC64
)
1141 for (regnum
= PC_REGNUM
; regnum
< PC_REGNUM
+ 7; regnum
++)
1143 saved_regs_addr
[regnum
] =
1144 frame_addr
+ (regnum
- PC_REGNUM
) * SPARC_INTREG_SIZE
1145 - DUMMY_STACK_REG_BUF_SIZE
;
1147 saved_regs_addr
[PSTATE_REGNUM
] =
1148 frame_addr
+ 8 * SPARC_INTREG_SIZE
- DUMMY_STACK_REG_BUF_SIZE
;
1151 for (regnum
= Y_REGNUM
; regnum
< NUM_REGS
; regnum
++)
1152 saved_regs_addr
[regnum
] =
1153 frame_addr
+ (regnum
- Y_REGNUM
) * SPARC_INTREG_SIZE
1154 - DUMMY_STACK_REG_BUF_SIZE
;
1156 frame_addr
= fi
->extra_info
->bottom
?
1157 fi
->extra_info
->bottom
: read_sp ();
1159 else if (fi
->extra_info
->flat
)
1161 CORE_ADDR func_start
;
1162 find_pc_partial_function (fi
->pc
, NULL
, &func_start
, NULL
);
1163 examine_prologue (func_start
, 0, fi
, saved_regs_addr
);
1165 /* Flat register window frame. */
1166 saved_regs_addr
[RP_REGNUM
] = fi
->extra_info
->pc_addr
;
1167 saved_regs_addr
[I7_REGNUM
] = fi
->extra_info
->fp_addr
;
1171 /* Normal frame. Just Local and In registers */
1172 frame_addr
= fi
->extra_info
->bottom
?
1173 fi
->extra_info
->bottom
: read_sp ();
1174 for (regnum
= L0_REGNUM
; regnum
< L0_REGNUM
+ 8; regnum
++)
1175 saved_regs_addr
[regnum
] =
1176 (frame_addr
+ (regnum
- L0_REGNUM
) * SPARC_INTREG_SIZE
1178 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+ 8; regnum
++)
1179 saved_regs_addr
[regnum
] =
1180 (frame_addr
+ (regnum
- I0_REGNUM
) * SPARC_INTREG_SIZE
1185 if (fi
->extra_info
->flat
)
1187 saved_regs_addr
[O7_REGNUM
] = fi
->extra_info
->pc_addr
;
1191 /* Pull off either the next frame pointer or the stack pointer */
1192 CORE_ADDR next_next_frame_addr
=
1193 (fi
->next
->extra_info
->bottom
?
1194 fi
->next
->extra_info
->bottom
: read_sp ());
1195 for (regnum
= O0_REGNUM
; regnum
< O0_REGNUM
+ 8; regnum
++)
1196 saved_regs_addr
[regnum
] =
1197 (next_next_frame_addr
1198 + (regnum
- O0_REGNUM
) * SPARC_INTREG_SIZE
1202 /* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */
1203 /* FIXME -- should this adjust for the sparc64 offset? */
1204 saved_regs_addr
[SP_REGNUM
] = FRAME_FP (fi
);
1207 /* Discard from the stack the innermost frame, restoring all saved registers.
1209 Note that the values stored in fsr by get_frame_saved_regs are *in
1210 the context of the called frame*. What this means is that the i
1211 regs of fsr must be restored into the o regs of the (calling) frame that
1212 we pop into. We don't care about the output regs of the calling frame,
1213 since unless it's a dummy frame, it won't have any output regs in it.
1215 We never have to bother with %l (local) regs, since the called routine's
1216 locals get tossed, and the calling routine's locals are already saved
1219 /* Definitely see tm-sparc.h for more doc of the frame format here. */
1222 sparc_pop_frame (void)
1224 register struct frame_info
*frame
= get_current_frame ();
1225 register CORE_ADDR pc
;
1230 fsr
= alloca (NUM_REGS
* sizeof (CORE_ADDR
));
1231 raw_buffer
= alloca (REGISTER_BYTES
);
1232 sparc_frame_find_saved_regs (frame
, &fsr
[0]);
1235 if (fsr
[FP0_REGNUM
])
1237 read_memory (fsr
[FP0_REGNUM
], raw_buffer
, FP_REGISTER_BYTES
);
1238 write_register_bytes (REGISTER_BYTE (FP0_REGNUM
),
1239 raw_buffer
, FP_REGISTER_BYTES
);
1241 if (!(GDB_TARGET_IS_SPARC64
))
1243 if (fsr
[FPS_REGNUM
])
1245 read_memory (fsr
[FPS_REGNUM
], raw_buffer
, SPARC_INTREG_SIZE
);
1246 write_register_gen (FPS_REGNUM
, raw_buffer
);
1248 if (fsr
[CPS_REGNUM
])
1250 read_memory (fsr
[CPS_REGNUM
], raw_buffer
, SPARC_INTREG_SIZE
);
1251 write_register_gen (CPS_REGNUM
, raw_buffer
);
1257 read_memory (fsr
[G1_REGNUM
], raw_buffer
, 7 * SPARC_INTREG_SIZE
);
1258 write_register_bytes (REGISTER_BYTE (G1_REGNUM
), raw_buffer
,
1259 7 * SPARC_INTREG_SIZE
);
1262 if (frame
->extra_info
->flat
)
1264 /* Each register might or might not have been saved, need to test
1266 for (regnum
= L0_REGNUM
; regnum
< L0_REGNUM
+ 8; ++regnum
)
1268 write_register (regnum
, read_memory_integer (fsr
[regnum
],
1269 SPARC_INTREG_SIZE
));
1270 for (regnum
= I0_REGNUM
; regnum
< I0_REGNUM
+ 8; ++regnum
)
1272 write_register (regnum
, read_memory_integer (fsr
[regnum
],
1273 SPARC_INTREG_SIZE
));
1275 /* Handle all outs except stack pointer (o0-o5; o7). */
1276 for (regnum
= O0_REGNUM
; regnum
< O0_REGNUM
+ 6; ++regnum
)
1278 write_register (regnum
, read_memory_integer (fsr
[regnum
],
1279 SPARC_INTREG_SIZE
));
1280 if (fsr
[O0_REGNUM
+ 7])
1281 write_register (O0_REGNUM
+ 7,
1282 read_memory_integer (fsr
[O0_REGNUM
+ 7],
1283 SPARC_INTREG_SIZE
));
1285 write_sp (frame
->frame
);
1287 else if (fsr
[I0_REGNUM
])
1293 reg_temp
= alloca (SPARC_INTREG_SIZE
* 16);
1295 read_memory (fsr
[I0_REGNUM
], raw_buffer
, 8 * SPARC_INTREG_SIZE
);
1297 /* Get the ins and locals which we are about to restore. Just
1298 moving the stack pointer is all that is really needed, except
1299 store_inferior_registers is then going to write the ins and
1300 locals from the registers array, so we need to muck with the
1302 sp
= fsr
[SP_REGNUM
];
1304 if (GDB_TARGET_IS_SPARC64
&& (sp
& 1))
1307 read_memory (sp
, reg_temp
, SPARC_INTREG_SIZE
* 16);
1309 /* Restore the out registers.
1310 Among other things this writes the new stack pointer. */
1311 write_register_bytes (REGISTER_BYTE (O0_REGNUM
), raw_buffer
,
1312 SPARC_INTREG_SIZE
* 8);
1314 write_register_bytes (REGISTER_BYTE (L0_REGNUM
), reg_temp
,
1315 SPARC_INTREG_SIZE
* 16);
1318 if (!(GDB_TARGET_IS_SPARC64
))
1320 write_register (PS_REGNUM
,
1321 read_memory_integer (fsr
[PS_REGNUM
],
1322 REGISTER_RAW_SIZE (PS_REGNUM
)));
1325 write_register (Y_REGNUM
,
1326 read_memory_integer (fsr
[Y_REGNUM
],
1327 REGISTER_RAW_SIZE (Y_REGNUM
)));
1330 /* Explicitly specified PC (and maybe NPC) -- just restore them. */
1331 write_register (PC_REGNUM
,
1332 read_memory_integer (fsr
[PC_REGNUM
],
1333 REGISTER_RAW_SIZE (PC_REGNUM
)));
1334 if (fsr
[NPC_REGNUM
])
1335 write_register (NPC_REGNUM
,
1336 read_memory_integer (fsr
[NPC_REGNUM
],
1337 REGISTER_RAW_SIZE (NPC_REGNUM
)));
1339 else if (frame
->extra_info
->flat
)
1341 if (frame
->extra_info
->pc_addr
)
1342 pc
= PC_ADJUST ((CORE_ADDR
)
1343 read_memory_integer (frame
->extra_info
->pc_addr
,
1344 REGISTER_RAW_SIZE (PC_REGNUM
)));
1347 /* I think this happens only in the innermost frame, if so then
1348 it is a complicated way of saying
1349 "pc = read_register (O7_REGNUM);". */
1352 buf
= alloca (MAX_REGISTER_RAW_SIZE
);
1353 get_saved_register (buf
, 0, 0, frame
, O7_REGNUM
, 0);
1354 pc
= PC_ADJUST (extract_address
1355 (buf
, REGISTER_RAW_SIZE (O7_REGNUM
)));
1358 write_register (PC_REGNUM
, pc
);
1359 write_register (NPC_REGNUM
, pc
+ 4);
1361 else if (fsr
[I7_REGNUM
])
1363 /* Return address in %i7 -- adjust it, then restore PC and NPC from it */
1364 pc
= PC_ADJUST ((CORE_ADDR
) read_memory_integer (fsr
[I7_REGNUM
],
1365 SPARC_INTREG_SIZE
));
1366 write_register (PC_REGNUM
, pc
);
1367 write_register (NPC_REGNUM
, pc
+ 4);
1369 flush_cached_frames ();
1372 /* On the Sun 4 under SunOS, the compile will leave a fake insn which
1373 encodes the structure size being returned. If we detect such
1374 a fake insn, step past it. */
1377 sparc_pc_adjust (CORE_ADDR pc
)
1383 err
= target_read_memory (pc
+ 8, buf
, 4);
1384 insn
= extract_unsigned_integer (buf
, 4);
1385 if ((err
== 0) && (insn
& 0xffc00000) == 0)
1391 /* If pc is in a shared library trampoline, return its target.
1392 The SunOs 4.x linker rewrites the jump table entries for PIC
1393 compiled modules in the main executable to bypass the dynamic linker
1394 with jumps of the form
1397 and removes the corresponding jump table relocation entry in the
1398 dynamic relocations.
1399 find_solib_trampoline_target relies on the presence of the jump
1400 table relocation entry, so we have to detect these jump instructions
1404 sunos4_skip_trampoline_code (CORE_ADDR pc
)
1406 unsigned long insn1
;
1410 err
= target_read_memory (pc
, buf
, 4);
1411 insn1
= extract_unsigned_integer (buf
, 4);
1412 if (err
== 0 && (insn1
& 0xffc00000) == 0x03000000)
1414 unsigned long insn2
;
1416 err
= target_read_memory (pc
+ 4, buf
, 4);
1417 insn2
= extract_unsigned_integer (buf
, 4);
1418 if (err
== 0 && (insn2
& 0xffffe000) == 0x81c06000)
1420 CORE_ADDR target_pc
= (insn1
& 0x3fffff) << 10;
1421 int delta
= insn2
& 0x1fff;
1423 /* Sign extend the displacement. */
1426 return target_pc
+ delta
;
1429 return find_solib_trampoline_target (pc
);
1432 #ifdef USE_PROC_FS /* Target dependent support for /proc */
1434 /* The /proc interface divides the target machine's register set up into
1435 two different sets, the general register set (gregset) and the floating
1436 point register set (fpregset). For each set, there is an ioctl to get
1437 the current register set and another ioctl to set the current values.
1439 The actual structure passed through the ioctl interface is, of course,
1440 naturally machine dependent, and is different for each set of registers.
1441 For the sparc for example, the general register set is typically defined
1444 typedef int gregset_t[38];
1450 and the floating point set by:
1452 typedef struct prfpregset {
1455 double pr_dregs[16];
1460 u_char pr_q_entrysize;
1465 These routines provide the packing and unpacking of gregset_t and
1466 fpregset_t formatted data.
1471 /* Given a pointer to a general register set in /proc format (gregset_t *),
1472 unpack the register contents and supply them as gdb's idea of the current
1476 supply_gregset (gdb_gregset_t
*gregsetp
)
1478 prgreg_t
*regp
= (prgreg_t
*) gregsetp
;
1479 int regi
, offset
= 0;
1481 /* If the host is 64-bit sparc, but the target is 32-bit sparc,
1482 then the gregset may contain 64-bit ints while supply_register
1483 is expecting 32-bit ints. Compensate. */
1484 if (sizeof (regp
[0]) == 8 && SPARC_INTREG_SIZE
== 4)
1487 /* GDB register numbers for Gn, On, Ln, In all match /proc reg numbers. */
1488 /* FIXME MVS: assumes the order of the first 32 elements... */
1489 for (regi
= G0_REGNUM
; regi
<= I7_REGNUM
; regi
++)
1491 supply_register (regi
, ((char *) (regp
+ regi
)) + offset
);
1494 /* These require a bit more care. */
1495 supply_register (PC_REGNUM
, ((char *) (regp
+ R_PC
)) + offset
);
1496 supply_register (NPC_REGNUM
, ((char *) (regp
+ R_nPC
)) + offset
);
1497 supply_register (Y_REGNUM
, ((char *) (regp
+ R_Y
)) + offset
);
1499 if (GDB_TARGET_IS_SPARC64
)
1502 supply_register (CCR_REGNUM
, ((char *) (regp
+ R_CCR
)) + offset
);
1504 supply_register (CCR_REGNUM
, NULL
);
1507 supply_register (FPRS_REGNUM
, ((char *) (regp
+ R_FPRS
)) + offset
);
1509 supply_register (FPRS_REGNUM
, NULL
);
1512 supply_register (ASI_REGNUM
, ((char *) (regp
+ R_ASI
)) + offset
);
1514 supply_register (ASI_REGNUM
, NULL
);
1520 supply_register (PS_REGNUM
, ((char *) (regp
+ R_PS
)) + offset
);
1522 supply_register (PS_REGNUM
, NULL
);
1525 /* For 64-bit hosts, R_WIM and R_TBR may not be defined.
1526 Steal R_ASI and R_FPRS, and hope for the best! */
1528 #if !defined (R_WIM) && defined (R_ASI)
1532 #if !defined (R_TBR) && defined (R_FPRS)
1533 #define R_TBR R_FPRS
1537 supply_register (WIM_REGNUM
, ((char *) (regp
+ R_WIM
)) + offset
);
1539 supply_register (WIM_REGNUM
, NULL
);
1543 supply_register (TBR_REGNUM
, ((char *) (regp
+ R_TBR
)) + offset
);
1545 supply_register (TBR_REGNUM
, NULL
);
1549 /* Fill inaccessible registers with zero. */
1550 if (GDB_TARGET_IS_SPARC64
)
1553 * don't know how to get value of any of the following:
1555 supply_register (VER_REGNUM
, NULL
);
1556 supply_register (TICK_REGNUM
, NULL
);
1557 supply_register (PIL_REGNUM
, NULL
);
1558 supply_register (PSTATE_REGNUM
, NULL
);
1559 supply_register (TSTATE_REGNUM
, NULL
);
1560 supply_register (TBA_REGNUM
, NULL
);
1561 supply_register (TL_REGNUM
, NULL
);
1562 supply_register (TT_REGNUM
, NULL
);
1563 supply_register (TPC_REGNUM
, NULL
);
1564 supply_register (TNPC_REGNUM
, NULL
);
1565 supply_register (WSTATE_REGNUM
, NULL
);
1566 supply_register (CWP_REGNUM
, NULL
);
1567 supply_register (CANSAVE_REGNUM
, NULL
);
1568 supply_register (CANRESTORE_REGNUM
, NULL
);
1569 supply_register (CLEANWIN_REGNUM
, NULL
);
1570 supply_register (OTHERWIN_REGNUM
, NULL
);
1571 supply_register (ASR16_REGNUM
, NULL
);
1572 supply_register (ASR17_REGNUM
, NULL
);
1573 supply_register (ASR18_REGNUM
, NULL
);
1574 supply_register (ASR19_REGNUM
, NULL
);
1575 supply_register (ASR20_REGNUM
, NULL
);
1576 supply_register (ASR21_REGNUM
, NULL
);
1577 supply_register (ASR22_REGNUM
, NULL
);
1578 supply_register (ASR23_REGNUM
, NULL
);
1579 supply_register (ASR24_REGNUM
, NULL
);
1580 supply_register (ASR25_REGNUM
, NULL
);
1581 supply_register (ASR26_REGNUM
, NULL
);
1582 supply_register (ASR27_REGNUM
, NULL
);
1583 supply_register (ASR28_REGNUM
, NULL
);
1584 supply_register (ASR29_REGNUM
, NULL
);
1585 supply_register (ASR30_REGNUM
, NULL
);
1586 supply_register (ASR31_REGNUM
, NULL
);
1587 supply_register (ICC_REGNUM
, NULL
);
1588 supply_register (XCC_REGNUM
, NULL
);
1592 supply_register (CPS_REGNUM
, NULL
);
1597 fill_gregset (gdb_gregset_t
*gregsetp
, int regno
)
1599 prgreg_t
*regp
= (prgreg_t
*) gregsetp
;
1600 int regi
, offset
= 0;
1602 /* If the host is 64-bit sparc, but the target is 32-bit sparc,
1603 then the gregset may contain 64-bit ints while supply_register
1604 is expecting 32-bit ints. Compensate. */
1605 if (sizeof (regp
[0]) == 8 && SPARC_INTREG_SIZE
== 4)
1608 for (regi
= 0; regi
<= R_I7
; regi
++)
1609 if ((regno
== -1) || (regno
== regi
))
1610 read_register_gen (regi
, (char *) (regp
+ regi
) + offset
);
1612 if ((regno
== -1) || (regno
== PC_REGNUM
))
1613 read_register_gen (PC_REGNUM
, (char *) (regp
+ R_PC
) + offset
);
1615 if ((regno
== -1) || (regno
== NPC_REGNUM
))
1616 read_register_gen (NPC_REGNUM
, (char *) (regp
+ R_nPC
) + offset
);
1618 if ((regno
== -1) || (regno
== Y_REGNUM
))
1619 read_register_gen (Y_REGNUM
, (char *) (regp
+ R_Y
) + offset
);
1621 if (GDB_TARGET_IS_SPARC64
)
1624 if (regno
== -1 || regno
== CCR_REGNUM
)
1625 read_register_gen (CCR_REGNUM
, ((char *) (regp
+ R_CCR
)) + offset
);
1628 if (regno
== -1 || regno
== FPRS_REGNUM
)
1629 read_register_gen (FPRS_REGNUM
, ((char *) (regp
+ R_FPRS
)) + offset
);
1632 if (regno
== -1 || regno
== ASI_REGNUM
)
1633 read_register_gen (ASI_REGNUM
, ((char *) (regp
+ R_ASI
)) + offset
);
1639 if (regno
== -1 || regno
== PS_REGNUM
)
1640 read_register_gen (PS_REGNUM
, ((char *) (regp
+ R_PS
)) + offset
);
1643 /* For 64-bit hosts, R_WIM and R_TBR may not be defined.
1644 Steal R_ASI and R_FPRS, and hope for the best! */
1646 #if !defined (R_WIM) && defined (R_ASI)
1650 #if !defined (R_TBR) && defined (R_FPRS)
1651 #define R_TBR R_FPRS
1655 if (regno
== -1 || regno
== WIM_REGNUM
)
1656 read_register_gen (WIM_REGNUM
, ((char *) (regp
+ R_WIM
)) + offset
);
1658 if (regno
== -1 || regno
== WIM_REGNUM
)
1659 read_register_gen (WIM_REGNUM
, NULL
);
1663 if (regno
== -1 || regno
== TBR_REGNUM
)
1664 read_register_gen (TBR_REGNUM
, ((char *) (regp
+ R_TBR
)) + offset
);
1666 if (regno
== -1 || regno
== TBR_REGNUM
)
1667 read_register_gen (TBR_REGNUM
, NULL
);
1672 /* Given a pointer to a floating point register set in /proc format
1673 (fpregset_t *), unpack the register contents and supply them as gdb's
1674 idea of the current floating point register values. */
1677 supply_fpregset (gdb_fpregset_t
*fpregsetp
)
1685 for (regi
= FP0_REGNUM
; regi
< FP_MAX_REGNUM
; regi
++)
1687 from
= (char *) &fpregsetp
->pr_fr
.pr_regs
[regi
- FP0_REGNUM
];
1688 supply_register (regi
, from
);
1691 if (GDB_TARGET_IS_SPARC64
)
1694 * don't know how to get value of the following.
1696 supply_register (FSR_REGNUM
, NULL
); /* zero it out for now */
1697 supply_register (FCC0_REGNUM
, NULL
);
1698 supply_register (FCC1_REGNUM
, NULL
); /* don't know how to get value */
1699 supply_register (FCC2_REGNUM
, NULL
); /* don't know how to get value */
1700 supply_register (FCC3_REGNUM
, NULL
); /* don't know how to get value */
1704 supply_register (FPS_REGNUM
, (char *) &(fpregsetp
->pr_fsr
));
1708 /* Given a pointer to a floating point register set in /proc format
1709 (fpregset_t *), update the register specified by REGNO from gdb's idea
1710 of the current floating point register set. If REGNO is -1, update
1712 /* This will probably need some changes for sparc64. */
1715 fill_fpregset (gdb_fpregset_t
*fpregsetp
, int regno
)
1724 for (regi
= FP0_REGNUM
; regi
< FP_MAX_REGNUM
; regi
++)
1726 if ((regno
== -1) || (regno
== regi
))
1728 from
= (char *) ®isters
[REGISTER_BYTE (regi
)];
1729 to
= (char *) &fpregsetp
->pr_fr
.pr_regs
[regi
- FP0_REGNUM
];
1730 memcpy (to
, from
, REGISTER_RAW_SIZE (regi
));
1734 if (!(GDB_TARGET_IS_SPARC64
)) /* FIXME: does Sparc64 have this register? */
1735 if ((regno
== -1) || (regno
== FPS_REGNUM
))
1737 from
= (char *)®isters
[REGISTER_BYTE (FPS_REGNUM
)];
1738 to
= (char *) &fpregsetp
->pr_fsr
;
1739 memcpy (to
, from
, REGISTER_RAW_SIZE (FPS_REGNUM
));
1743 #endif /* USE_PROC_FS */
1745 /* Because of Multi-arch, GET_LONGJMP_TARGET is always defined. So test
1746 for a definition of JB_PC. */
1749 /* Figure out where the longjmp will land. We expect that we have just entered
1750 longjmp and haven't yet setup the stack frame, so the args are still in the
1751 output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we
1752 extract the pc (JB_PC) that we will land at. The pc is copied into ADDR.
1753 This routine returns true on success */
1756 get_longjmp_target (CORE_ADDR
*pc
)
1759 #define LONGJMP_TARGET_SIZE 4
1760 char buf
[LONGJMP_TARGET_SIZE
];
1762 jb_addr
= read_register (O0_REGNUM
);
1764 if (target_read_memory (jb_addr
+ JB_PC
* JB_ELEMENT_SIZE
, buf
,
1765 LONGJMP_TARGET_SIZE
))
1768 *pc
= extract_address (buf
, LONGJMP_TARGET_SIZE
);
1772 #endif /* GET_LONGJMP_TARGET */
1774 #ifdef STATIC_TRANSFORM_NAME
1775 /* SunPRO (3.0 at least), encodes the static variables. This is not
1776 related to C++ mangling, it is done for C too. */
1779 sunpro_static_transform_name (char *name
)
1784 /* For file-local statics there will be a dollar sign, a bunch
1785 of junk (the contents of which match a string given in the
1786 N_OPT), a period and the name. For function-local statics
1787 there will be a bunch of junk (which seems to change the
1788 second character from 'A' to 'B'), a period, the name of the
1789 function, and the name. So just skip everything before the
1791 p
= strrchr (name
, '.');
1797 #endif /* STATIC_TRANSFORM_NAME */
1800 /* Utilities for printing registers.
1801 Page numbers refer to the SPARC Architecture Manual. */
1803 static void dump_ccreg (char *, int);
1806 dump_ccreg (char *reg
, int val
)
1809 printf_unfiltered ("%s:%s,%s,%s,%s", reg
,
1810 val
& 8 ? "N" : "NN",
1811 val
& 4 ? "Z" : "NZ",
1812 val
& 2 ? "O" : "NO",
1813 val
& 1 ? "C" : "NC");
1817 decode_asi (int val
)
1823 return "ASI_NUCLEUS";
1825 return "ASI_NUCLEUS_LITTLE";
1827 return "ASI_AS_IF_USER_PRIMARY";
1829 return "ASI_AS_IF_USER_SECONDARY";
1831 return "ASI_AS_IF_USER_PRIMARY_LITTLE";
1833 return "ASI_AS_IF_USER_SECONDARY_LITTLE";
1835 return "ASI_PRIMARY";
1837 return "ASI_SECONDARY";
1839 return "ASI_PRIMARY_NOFAULT";
1841 return "ASI_SECONDARY_NOFAULT";
1843 return "ASI_PRIMARY_LITTLE";
1845 return "ASI_SECONDARY_LITTLE";
1847 return "ASI_PRIMARY_NOFAULT_LITTLE";
1849 return "ASI_SECONDARY_NOFAULT_LITTLE";
1855 /* PRINT_REGISTER_HOOK routine.
1856 Pretty print various registers. */
1857 /* FIXME: Would be nice if this did some fancy things for 32 bit sparc. */
1860 sparc_print_register_hook (int regno
)
1864 /* Handle double/quad versions of lower 32 fp regs. */
1865 if (regno
>= FP0_REGNUM
&& regno
< FP0_REGNUM
+ 32
1866 && (regno
& 1) == 0)
1870 if (frame_register_read (selected_frame
, regno
, value
)
1871 && frame_register_read (selected_frame
, regno
+ 1, value
+ 4))
1873 printf_unfiltered ("\t");
1874 print_floating (value
, builtin_type_double
, gdb_stdout
);
1876 #if 0 /* FIXME: gdb doesn't handle long doubles */
1877 if ((regno
& 3) == 0)
1879 if (frame_register_read (selected_frame
, regno
+ 2, value
+ 8)
1880 && frame_register_read (selected_frame
, regno
+ 3, value
+ 12))
1882 printf_unfiltered ("\t");
1883 print_floating (value
, builtin_type_long_double
, gdb_stdout
);
1890 #if 0 /* FIXME: gdb doesn't handle long doubles */
1891 /* Print upper fp regs as long double if appropriate. */
1892 if (regno
>= FP0_REGNUM
+ 32 && regno
< FP_MAX_REGNUM
1893 /* We test for even numbered regs and not a multiple of 4 because
1894 the upper fp regs are recorded as doubles. */
1895 && (regno
& 1) == 0)
1899 if (frame_register_read (selected_frame
, regno
, value
)
1900 && frame_register_read (selected_frame
, regno
+ 1, value
+ 8))
1902 printf_unfiltered ("\t");
1903 print_floating (value
, builtin_type_long_double
, gdb_stdout
);
1909 /* FIXME: Some of these are priviledged registers.
1910 Not sure how they should be handled. */
1912 #define BITS(n, mask) ((int) (((val) >> (n)) & (mask)))
1914 val
= read_register (regno
);
1917 if (GDB_TARGET_IS_SPARC64
)
1921 printf_unfiltered ("\t");
1922 dump_ccreg ("xcc", val
>> 4);
1923 printf_unfiltered (", ");
1924 dump_ccreg ("icc", val
& 15);
1927 printf ("\tfef:%d, du:%d, dl:%d",
1928 BITS (2, 1), BITS (1, 1), BITS (0, 1));
1932 static char *fcc
[4] =
1933 {"=", "<", ">", "?"};
1934 static char *rd
[4] =
1935 {"N", "0", "+", "-"};
1936 /* Long, but I'd rather leave it as is and use a wide screen. */
1937 printf_filtered ("\t0:%s, 1:%s, 2:%s, 3:%s, rd:%s, tem:%d, ",
1938 fcc
[BITS (10, 3)], fcc
[BITS (32, 3)],
1939 fcc
[BITS (34, 3)], fcc
[BITS (36, 3)],
1940 rd
[BITS (30, 3)], BITS (23, 31));
1941 printf_filtered ("ns:%d, ver:%d, ftt:%d, qne:%d, aexc:%d, cexc:%d",
1942 BITS (22, 1), BITS (17, 7), BITS (14, 7),
1943 BITS (13, 1), BITS (5, 31), BITS (0, 31));
1948 char *asi
= decode_asi (val
);
1950 printf ("\t%s", asi
);
1954 printf ("\tmanuf:%d, impl:%d, mask:%d, maxtl:%d, maxwin:%d",
1955 BITS (48, 0xffff), BITS (32, 0xffff),
1956 BITS (24, 0xff), BITS (8, 0xff), BITS (0, 31));
1960 static char *mm
[4] =
1961 {"tso", "pso", "rso", "?"};
1962 printf_filtered ("\tcle:%d, tle:%d, mm:%s, red:%d, ",
1963 BITS (9, 1), BITS (8, 1),
1964 mm
[BITS (6, 3)], BITS (5, 1));
1965 printf_filtered ("pef:%d, am:%d, priv:%d, ie:%d, ag:%d",
1966 BITS (4, 1), BITS (3, 1), BITS (2, 1),
1967 BITS (1, 1), BITS (0, 1));
1971 /* FIXME: print all 4? */
1974 /* FIXME: print all 4? */
1977 /* FIXME: print all 4? */
1980 /* FIXME: print all 4? */
1983 printf ("\tother:%d, normal:%d", BITS (3, 7), BITS (0, 7));
1986 printf ("\t%d", BITS (0, 31));
1988 case CANSAVE_REGNUM
:
1989 printf ("\t%-2d before spill", BITS (0, 31));
1991 case CANRESTORE_REGNUM
:
1992 printf ("\t%-2d before fill", BITS (0, 31));
1994 case CLEANWIN_REGNUM
:
1995 printf ("\t%-2d before clean", BITS (0, 31));
1997 case OTHERWIN_REGNUM
:
1998 printf ("\t%d", BITS (0, 31));
2005 printf ("\ticc:%c%c%c%c, pil:%d, s:%d, ps:%d, et:%d, cwp:%d",
2006 BITS (23, 1) ? 'N' : '-', BITS (22, 1) ? 'Z' : '-',
2007 BITS (21, 1) ? 'V' : '-', BITS (20, 1) ? 'C' : '-',
2008 BITS (8, 15), BITS (7, 1), BITS (6, 1), BITS (5, 1),
2013 static char *fcc
[4] =
2014 {"=", "<", ">", "?"};
2015 static char *rd
[4] =
2016 {"N", "0", "+", "-"};
2017 /* Long, but I'd rather leave it as is and use a wide screen. */
2018 printf ("\trd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, "
2019 "fcc:%s, aexc:%d, cexc:%d",
2020 rd
[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7),
2021 BITS (14, 7), BITS (13, 1), fcc
[BITS (10, 3)], BITS (5, 31),
2031 gdb_print_insn_sparc (bfd_vma memaddr
, disassemble_info
*info
)
2033 /* It's necessary to override mach again because print_insn messes it up. */
2034 info
->mach
= TARGET_ARCHITECTURE
->mach
;
2035 return print_insn_sparc (memaddr
, info
);
2038 /* The SPARC passes the arguments on the stack; arguments smaller
2039 than an int are promoted to an int. The first 6 words worth of
2040 args are also passed in registers o0 - o5. */
2043 sparc32_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
2044 int struct_return
, CORE_ADDR struct_addr
)
2047 int accumulate_size
= 0;
2054 struct sparc_arg
*sparc_args
=
2055 (struct sparc_arg
*) alloca (nargs
* sizeof (struct sparc_arg
));
2056 struct sparc_arg
*m_arg
;
2058 /* Promote arguments if necessary, and calculate their stack offsets
2060 for (i
= 0, m_arg
= sparc_args
; i
< nargs
; i
++, m_arg
++)
2062 struct value
*arg
= args
[i
];
2063 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2064 /* Cast argument to long if necessary as the compiler does it too. */
2065 switch (TYPE_CODE (arg_type
))
2068 case TYPE_CODE_BOOL
:
2069 case TYPE_CODE_CHAR
:
2070 case TYPE_CODE_RANGE
:
2071 case TYPE_CODE_ENUM
:
2072 if (TYPE_LENGTH (arg_type
) < TYPE_LENGTH (builtin_type_long
))
2074 arg_type
= builtin_type_long
;
2075 arg
= value_cast (arg_type
, arg
);
2081 m_arg
->len
= TYPE_LENGTH (arg_type
);
2082 m_arg
->offset
= accumulate_size
;
2083 accumulate_size
= (accumulate_size
+ m_arg
->len
+ 3) & ~3;
2084 m_arg
->contents
= VALUE_CONTENTS (arg
);
2087 /* Make room for the arguments on the stack. */
2088 accumulate_size
+= CALL_DUMMY_STACK_ADJUST
;
2089 sp
= ((sp
- accumulate_size
) & ~7) + CALL_DUMMY_STACK_ADJUST
;
2091 /* `Push' arguments on the stack. */
2092 for (i
= 0, oregnum
= 0, m_arg
= sparc_args
;
2096 write_memory (sp
+ m_arg
->offset
, m_arg
->contents
, m_arg
->len
);
2098 j
< m_arg
->len
&& oregnum
< 6;
2099 j
+= SPARC_INTREG_SIZE
, oregnum
++)
2100 write_register_gen (O0_REGNUM
+ oregnum
, m_arg
->contents
+ j
);
2107 /* Extract from an array REGBUF containing the (raw) register state
2108 a function return value of type TYPE, and copy that, in virtual format,
2112 sparc32_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2114 int typelen
= TYPE_LENGTH (type
);
2115 int regsize
= REGISTER_RAW_SIZE (O0_REGNUM
);
2117 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2118 memcpy (valbuf
, ®buf
[REGISTER_BYTE (FP0_REGNUM
)], typelen
);
2121 ®buf
[O0_REGNUM
* regsize
+
2123 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
? 0
2124 : regsize
- typelen
)],
2129 /* Write into appropriate registers a function return value
2130 of type TYPE, given in virtual format. On SPARCs with FPUs,
2131 float values are returned in %f0 (and %f1). In all other cases,
2132 values are returned in register %o0. */
2135 sparc_store_return_value (struct type
*type
, char *valbuf
)
2140 buffer
= alloca (MAX_REGISTER_RAW_SIZE
);
2142 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2143 /* Floating-point values are returned in the register pair */
2144 /* formed by %f0 and %f1 (doubles are, anyway). */
2147 /* Other values are returned in register %o0. */
2150 /* Add leading zeros to the value. */
2151 if (TYPE_LENGTH (type
) < REGISTER_RAW_SIZE (regno
))
2153 memset (buffer
, 0, REGISTER_RAW_SIZE (regno
));
2154 memcpy (buffer
+ REGISTER_RAW_SIZE (regno
) - TYPE_LENGTH (type
), valbuf
,
2155 TYPE_LENGTH (type
));
2156 write_register_gen (regno
, buffer
);
2159 write_register_bytes (REGISTER_BYTE (regno
), valbuf
, TYPE_LENGTH (type
));
2163 sparclet_store_return_value (struct type
*type
, char *valbuf
)
2165 /* Other values are returned in register %o0. */
2166 write_register_bytes (REGISTER_BYTE (O0_REGNUM
), valbuf
,
2167 TYPE_LENGTH (type
));
2171 #ifndef CALL_DUMMY_CALL_OFFSET
2172 #define CALL_DUMMY_CALL_OFFSET \
2173 (gdbarch_tdep (current_gdbarch)->call_dummy_call_offset)
2174 #endif /* CALL_DUMMY_CALL_OFFSET */
2176 /* Insert the function address into a call dummy instruction sequence
2179 For structs and unions, if the function was compiled with Sun cc,
2180 it expects 'unimp' after the call. But gcc doesn't use that
2181 (twisted) convention. So leave a nop there for gcc (FIX_CALL_DUMMY
2182 can assume it is operating on a pristine CALL_DUMMY, not one that
2183 has already been customized for a different function). */
2186 sparc_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
,
2187 struct type
*value_type
, int using_gcc
)
2191 /* Store the relative adddress of the target function into the
2192 'call' instruction. */
2193 store_unsigned_integer (dummy
+ CALL_DUMMY_CALL_OFFSET
, 4,
2195 | (((fun
- (pc
+ CALL_DUMMY_CALL_OFFSET
)) >> 2)
2198 /* If the called function returns an aggregate value, fill in the UNIMP
2199 instruction containing the size of the returned aggregate return value,
2200 which follows the call instruction.
2201 For details see the SPARC Architecture Manual Version 8, Appendix D.3.
2203 Adjust the call_dummy_breakpoint_offset for the bp_call_dummy breakpoint
2204 to the proper address in the call dummy, so that `finish' after a stop
2205 in a call dummy works.
2206 Tweeking current_gdbarch is not an optimal solution, but the call to
2207 sparc_fix_call_dummy is immediately followed by a call to run_stack_dummy,
2208 which is the only function where dummy_breakpoint_offset is actually
2209 used, if it is non-zero. */
2210 if (TYPE_CODE (value_type
) == TYPE_CODE_STRUCT
2211 || TYPE_CODE (value_type
) == TYPE_CODE_UNION
)
2213 store_unsigned_integer (dummy
+ CALL_DUMMY_CALL_OFFSET
+ 8, 4,
2214 TYPE_LENGTH (value_type
) & 0x1fff);
2215 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch
, 0x30);
2218 set_gdbarch_call_dummy_breakpoint_offset (current_gdbarch
, 0x2c);
2220 if (!(GDB_TARGET_IS_SPARC64
))
2222 /* If this is not a simulator target, change the first four
2223 instructions of the call dummy to NOPs. Those instructions
2224 include a 'save' instruction and are designed to work around
2225 problems with register window flushing in the simulator. */
2227 if (strcmp (target_shortname
, "sim") != 0)
2229 for (i
= 0; i
< 4; i
++)
2230 store_unsigned_integer (dummy
+ (i
* 4), 4, 0x01000000);
2234 /* If this is a bi-endian target, GDB has written the call dummy
2235 in little-endian order. We must byte-swap it back to big-endian. */
2238 for (i
= 0; i
< CALL_DUMMY_LENGTH
; i
+= 4)
2240 char tmp
= dummy
[i
];
2241 dummy
[i
] = dummy
[i
+ 3];
2244 dummy
[i
+ 1] = dummy
[i
+ 2];
2251 /* Set target byte order based on machine type. */
2254 sparc_target_architecture_hook (const bfd_arch_info_type
*ap
)
2258 if (ap
->mach
== bfd_mach_sparc_sparclite_le
)
2260 target_byte_order
= BFD_ENDIAN_LITTLE
;
2270 * Module "constructor" function.
2273 static struct gdbarch
* sparc_gdbarch_init (struct gdbarch_info info
,
2274 struct gdbarch_list
*arches
);
2277 _initialize_sparc_tdep (void)
2279 /* Hook us into the gdbarch mechanism. */
2280 register_gdbarch_init (bfd_arch_sparc
, sparc_gdbarch_init
);
2282 tm_print_insn
= gdb_print_insn_sparc
;
2283 tm_print_insn_info
.mach
= TM_PRINT_INSN_MACH
; /* Selects sparc/sparclite */
2284 target_architecture_hook
= sparc_target_architecture_hook
;
2287 /* Compensate for stack bias. Note that we currently don't handle
2288 mixed 32/64 bit code. */
2291 sparc64_read_sp (void)
2293 CORE_ADDR sp
= read_register (SP_REGNUM
);
2301 sparc64_read_fp (void)
2303 CORE_ADDR fp
= read_register (FP_REGNUM
);
2311 sparc64_write_sp (CORE_ADDR val
)
2313 CORE_ADDR oldsp
= read_register (SP_REGNUM
);
2315 write_register (SP_REGNUM
, val
- 2047);
2317 write_register (SP_REGNUM
, val
);
2320 /* The SPARC 64 ABI passes floating-point arguments in FP0 to FP31,
2321 and all other arguments in O0 to O5. They are also copied onto
2322 the stack in the correct places. Apparently (empirically),
2323 structs of less than 16 bytes are passed member-by-member in
2324 separate registers, but I am unable to figure out the algorithm.
2325 Some members go in floating point regs, but I don't know which.
2327 FIXME: Handle small structs (less than 16 bytes containing floats).
2329 The counting regimen for using both integer and FP registers
2330 for argument passing is rather odd -- a single counter is used
2331 for both; this means that if the arguments alternate between
2332 int and float, we will waste every other register of both types. */
2335 sparc64_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
2336 int struct_return
, CORE_ADDR struct_retaddr
)
2338 int i
, j
, register_counter
= 0;
2340 struct type
*sparc_intreg_type
=
2341 TYPE_LENGTH (builtin_type_long
) == SPARC_INTREG_SIZE
?
2342 builtin_type_long
: builtin_type_long_long
;
2344 sp
= (sp
& ~(((unsigned long) SPARC_INTREG_SIZE
) - 1UL));
2346 /* Figure out how much space we'll need. */
2347 for (i
= nargs
- 1; i
>= 0; i
--)
2349 int len
= TYPE_LENGTH (check_typedef (VALUE_TYPE (args
[i
])));
2350 struct value
*copyarg
= args
[i
];
2353 if (copylen
< SPARC_INTREG_SIZE
)
2355 copyarg
= value_cast (sparc_intreg_type
, copyarg
);
2356 copylen
= SPARC_INTREG_SIZE
;
2365 /* if STRUCT_RETURN, then first argument is the struct return location. */
2367 write_register (O0_REGNUM
+ register_counter
++, struct_retaddr
);
2369 /* Now write the arguments onto the stack, while writing FP
2370 arguments into the FP registers, and other arguments into the
2371 first six 'O' registers. */
2373 for (i
= 0; i
< nargs
; i
++)
2375 int len
= TYPE_LENGTH (check_typedef (VALUE_TYPE (args
[i
])));
2376 struct value
*copyarg
= args
[i
];
2377 enum type_code typecode
= TYPE_CODE (VALUE_TYPE (args
[i
]));
2380 if (typecode
== TYPE_CODE_INT
||
2381 typecode
== TYPE_CODE_BOOL
||
2382 typecode
== TYPE_CODE_CHAR
||
2383 typecode
== TYPE_CODE_RANGE
||
2384 typecode
== TYPE_CODE_ENUM
)
2385 if (len
< SPARC_INTREG_SIZE
)
2387 /* Small ints will all take up the size of one intreg on
2389 copyarg
= value_cast (sparc_intreg_type
, copyarg
);
2390 copylen
= SPARC_INTREG_SIZE
;
2393 write_memory (tempsp
, VALUE_CONTENTS (copyarg
), copylen
);
2396 /* Corner case: Structs consisting of a single float member are floats.
2397 * FIXME! I don't know about structs containing multiple floats!
2398 * Structs containing mixed floats and ints are even more weird.
2403 /* Separate float args from all other args. */
2404 if (typecode
== TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2406 if (register_counter
< 16)
2408 /* This arg gets copied into a FP register. */
2412 case 4: /* Single-precision (float) */
2413 fpreg
= FP0_REGNUM
+ 2 * register_counter
+ 1;
2414 register_counter
+= 1;
2416 case 8: /* Double-precision (double) */
2417 fpreg
= FP0_REGNUM
+ 2 * register_counter
;
2418 register_counter
+= 1;
2420 case 16: /* Quad-precision (long double) */
2421 fpreg
= FP0_REGNUM
+ 2 * register_counter
;
2422 register_counter
+= 2;
2425 internal_error (__FILE__
, __LINE__
, "bad switch");
2427 write_register_bytes (REGISTER_BYTE (fpreg
),
2428 VALUE_CONTENTS (args
[i
]),
2432 else /* all other args go into the first six 'o' registers */
2435 j
< len
&& register_counter
< 6;
2436 j
+= SPARC_INTREG_SIZE
)
2438 int oreg
= O0_REGNUM
+ register_counter
;
2440 write_register_gen (oreg
, VALUE_CONTENTS (copyarg
) + j
);
2441 register_counter
+= 1;
2448 /* Values <= 32 bytes are returned in o0-o3 (floating-point values are
2449 returned in f0-f3). */
2452 sp64_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
,
2455 int typelen
= TYPE_LENGTH (type
);
2456 int regsize
= REGISTER_RAW_SIZE (O0_REGNUM
);
2458 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2460 memcpy (valbuf
, ®buf
[REGISTER_BYTE (FP0_REGNUM
)], typelen
);
2464 if (TYPE_CODE (type
) != TYPE_CODE_STRUCT
2465 || (TYPE_LENGTH (type
) > 32))
2468 ®buf
[O0_REGNUM
* regsize
+
2469 (typelen
>= regsize
? 0 : regsize
- typelen
)],
2475 char *o0
= ®buf
[O0_REGNUM
* regsize
];
2476 char *f0
= ®buf
[FP0_REGNUM
* regsize
];
2479 for (x
= 0; x
< TYPE_NFIELDS (type
); x
++)
2481 struct field
*f
= &TYPE_FIELDS (type
)[x
];
2482 /* FIXME: We may need to handle static fields here. */
2483 int whichreg
= (f
->loc
.bitpos
+ bitoffset
) / 32;
2484 int remainder
= ((f
->loc
.bitpos
+ bitoffset
) % 32) / 8;
2485 int where
= (f
->loc
.bitpos
+ bitoffset
) / 8;
2486 int size
= TYPE_LENGTH (f
->type
);
2487 int typecode
= TYPE_CODE (f
->type
);
2489 if (typecode
== TYPE_CODE_STRUCT
)
2491 sp64_extract_return_value (f
->type
,
2494 bitoffset
+ f
->loc
.bitpos
);
2496 else if (typecode
== TYPE_CODE_FLT
&& SPARC_HAS_FPU
)
2498 memcpy (valbuf
+ where
, &f0
[whichreg
* 4] + remainder
, size
);
2502 memcpy (valbuf
+ where
, &o0
[whichreg
* 4] + remainder
, size
);
2509 sparc64_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2511 sp64_extract_return_value (type
, regbuf
, valbuf
, 0);
2515 sparclet_extract_return_value (struct type
*type
,
2519 regbuf
+= REGISTER_RAW_SIZE (O0_REGNUM
) * 8;
2520 if (TYPE_LENGTH (type
) < REGISTER_RAW_SIZE (O0_REGNUM
))
2521 regbuf
+= REGISTER_RAW_SIZE (O0_REGNUM
) - TYPE_LENGTH (type
);
2523 memcpy ((void *) valbuf
, regbuf
, TYPE_LENGTH (type
));
2528 sparc32_stack_align (CORE_ADDR addr
)
2530 return ((addr
+ 7) & -8);
2534 sparc64_stack_align (CORE_ADDR addr
)
2536 return ((addr
+ 15) & -16);
2540 sparc_print_extra_frame_info (struct frame_info
*fi
)
2542 if (fi
&& fi
->extra_info
&& fi
->extra_info
->flat
)
2543 printf_filtered (" flat, pc saved at 0x%s, fp saved at 0x%s\n",
2544 paddr_nz (fi
->extra_info
->pc_addr
),
2545 paddr_nz (fi
->extra_info
->fp_addr
));
2548 /* MULTI_ARCH support */
2551 sparc32_register_name (int regno
)
2553 static char *register_names
[] =
2554 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2555 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2556 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2557 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2559 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2560 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2561 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2562 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
2564 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
2568 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2571 return register_names
[regno
];
2575 sparc64_register_name (int regno
)
2577 static char *register_names
[] =
2578 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2579 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2580 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2581 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2583 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2584 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2585 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2586 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
2587 "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
2588 "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
2590 "pc", "npc", "ccr", "fsr", "fprs", "y", "asi", "ver",
2591 "tick", "pil", "pstate", "tstate", "tba", "tl", "tt", "tpc",
2592 "tnpc", "wstate", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
2593 "asr16", "asr17", "asr18", "asr19", "asr20", "asr21", "asr22", "asr23",
2594 "asr24", "asr25", "asr26", "asr27", "asr28", "asr29", "asr30", "asr31",
2595 /* These are here at the end to simplify removing them if we have to. */
2596 "icc", "xcc", "fcc0", "fcc1", "fcc2", "fcc3"
2600 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2603 return register_names
[regno
];
2607 sparclite_register_name (int regno
)
2609 static char *register_names
[] =
2610 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2611 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2612 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2613 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2615 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2616 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2617 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2618 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
2620 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr",
2621 "dia1", "dia2", "dda1", "dda2", "ddv1", "ddv2", "dcr", "dsr"
2625 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2628 return register_names
[regno
];
2632 sparclet_register_name (int regno
)
2634 static char *register_names
[] =
2635 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2636 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2637 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2638 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2640 "", "", "", "", "", "", "", "", /* no floating point registers */
2641 "", "", "", "", "", "", "", "",
2642 "", "", "", "", "", "", "", "",
2643 "", "", "", "", "", "", "", "",
2645 "y", "psr", "wim", "tbr", "pc", "npc", "", "", /* no FPSR or CPSR */
2646 "ccsr", "ccpr", "cccrcr", "ccor", "ccobr", "ccibr", "ccir", "",
2648 /* ASR15 ASR19 (don't display them) */
2649 "asr1", "", "asr17", "asr18", "", "asr20", "asr21", "asr22"
2650 /* None of the rest get displayed */
2652 "awr0", "awr1", "awr2", "awr3", "awr4", "awr5", "awr6", "awr7",
2653 "awr8", "awr9", "awr10", "awr11", "awr12", "awr13", "awr14", "awr15",
2654 "awr16", "awr17", "awr18", "awr19", "awr20", "awr21", "awr22", "awr23",
2655 "awr24", "awr25", "awr26", "awr27", "awr28", "awr29", "awr30", "awr31",
2661 regno
>= (sizeof (register_names
) / sizeof (register_names
[0])))
2664 return register_names
[regno
];
2668 sparc_push_return_address (CORE_ADDR pc_unused
, CORE_ADDR sp
)
2670 if (CALL_DUMMY_LOCATION
== AT_ENTRY_POINT
)
2672 /* The return PC of the dummy_frame is the former 'current' PC
2673 (where we were before we made the target function call).
2674 This is saved in %i7 by push_dummy_frame.
2676 We will save the 'call dummy location' (ie. the address
2677 to which the target function will return) in %o7.
2678 This address will actually be the program's entry point.
2679 There will be a special call_dummy breakpoint there. */
2681 write_register (O7_REGNUM
,
2682 CALL_DUMMY_ADDRESS () - 8);
2688 /* Should call_function allocate stack space for a struct return? */
2691 sparc64_use_struct_convention (int gcc_p
, struct type
*type
)
2693 return (TYPE_LENGTH (type
) > 32);
2696 /* Store the address of the place in which to copy the structure the
2697 subroutine will return. This is called from call_function_by_hand.
2698 The ultimate mystery is, tho, what is the value "16"?
2700 MVS: That's the offset from where the sp is now, to where the
2701 subroutine is gonna expect to find the struct return address. */
2704 sparc32_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
2709 val
= alloca (SPARC_INTREG_SIZE
);
2710 store_unsigned_integer (val
, SPARC_INTREG_SIZE
, addr
);
2711 write_memory (sp
+ (16 * SPARC_INTREG_SIZE
), val
, SPARC_INTREG_SIZE
);
2713 if (CALL_DUMMY_LOCATION
== AT_ENTRY_POINT
)
2715 /* Now adjust the value of the link register, which was previously
2716 stored by push_return_address. Functions that return structs are
2717 peculiar in that they return to link register + 12, rather than
2718 link register + 8. */
2720 o7
= read_register (O7_REGNUM
);
2721 write_register (O7_REGNUM
, o7
- 4);
2726 sparc64_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
2728 /* FIXME: V9 uses %o0 for this. */
2729 /* FIXME MVS: Only for small enough structs!!! */
2731 target_write_memory (sp
+ (16 * SPARC_INTREG_SIZE
),
2732 (char *) &addr
, SPARC_INTREG_SIZE
);
2734 if (CALL_DUMMY_LOCATION
== AT_ENTRY_POINT
)
2736 /* Now adjust the value of the link register, which was previously
2737 stored by push_return_address. Functions that return structs are
2738 peculiar in that they return to link register + 12, rather than
2739 link register + 8. */
2741 write_register (O7_REGNUM
, read_register (O7_REGNUM
) - 4);
2746 /* Default target data type for register REGNO. */
2748 static struct type
*
2749 sparc32_register_virtual_type (int regno
)
2751 if (regno
== PC_REGNUM
||
2752 regno
== FP_REGNUM
||
2754 return builtin_type_unsigned_int
;
2756 return builtin_type_int
;
2758 return builtin_type_float
;
2759 return builtin_type_int
;
2762 static struct type
*
2763 sparc64_register_virtual_type (int regno
)
2765 if (regno
== PC_REGNUM
||
2766 regno
== FP_REGNUM
||
2768 return builtin_type_unsigned_long_long
;
2770 return builtin_type_long_long
;
2772 return builtin_type_float
;
2774 return builtin_type_double
;
2775 return builtin_type_long_long
;
2778 /* Number of bytes of storage in the actual machine representation for
2782 sparc32_register_size (int regno
)
2788 sparc64_register_size (int regno
)
2790 return (regno
< 32 ? 8 : regno
< 64 ? 4 : 8);
2793 /* Index within the `registers' buffer of the first byte of the space
2794 for register REGNO. */
2797 sparc32_register_byte (int regno
)
2803 sparc64_register_byte (int regno
)
2807 else if (regno
< 64)
2808 return 32 * 8 + (regno
- 32) * 4;
2809 else if (regno
< 80)
2810 return 32 * 8 + 32 * 4 + (regno
- 64) * 8;
2812 return 64 * 8 + (regno
- 80) * 8;
2815 /* Immediately after a function call, return the saved pc.
2816 Can't go through the frames for this because on some machines
2817 the new frame is not set up until the new function executes
2818 some instructions. */
2821 sparc_saved_pc_after_call (struct frame_info
*fi
)
2823 return sparc_pc_adjust (read_register (RP_REGNUM
));
2826 /* Convert registers between 'raw' and 'virtual' formats.
2827 They are the same on sparc, so there's nothing to do. */
2830 sparc_convert_to_virtual (int regnum
, struct type
*type
, char *from
, char *to
)
2831 { /* do nothing (should never be called) */
2835 sparc_convert_to_raw (struct type
*type
, int regnum
, char *from
, char *to
)
2836 { /* do nothing (should never be called) */
2839 /* Init saved regs: nothing to do, just a place-holder function. */
2842 sparc_frame_init_saved_regs (struct frame_info
*fi_ignored
)
2846 /* gdbarch fix call dummy:
2847 All this function does is rearrange the arguments before calling
2848 sparc_fix_call_dummy (which does the real work). */
2851 sparc_gdbarch_fix_call_dummy (char *dummy
,
2855 struct value
**args
,
2859 if (CALL_DUMMY_LOCATION
== ON_STACK
)
2860 sparc_fix_call_dummy (dummy
, pc
, fun
, type
, gcc_p
);
2863 /* Coerce float to double: a no-op. */
2866 sparc_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
2871 /* CALL_DUMMY_ADDRESS: fetch the breakpoint address for a call dummy. */
2874 sparc_call_dummy_address (void)
2876 return (CALL_DUMMY_START_OFFSET
) + CALL_DUMMY_BREAKPOINT_OFFSET
;
2879 /* Supply the Y register number to those that need it. */
2882 sparc_y_regnum (void)
2884 return gdbarch_tdep (current_gdbarch
)->y_regnum
;
2888 sparc_reg_struct_has_addr (int gcc_p
, struct type
*type
)
2890 if (GDB_TARGET_IS_SPARC64
)
2891 return (TYPE_LENGTH (type
) > 32);
2893 return (gcc_p
!= 1);
2897 sparc_intreg_size (void)
2899 return SPARC_INTREG_SIZE
;
2903 sparc_return_value_on_stack (struct type
*type
)
2905 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&&
2906 TYPE_LENGTH (type
) > 8)
2913 * Gdbarch "constructor" function.
2916 #define SPARC32_CALL_DUMMY_ON_STACK
2918 #define SPARC_SP_REGNUM 14
2919 #define SPARC_FP_REGNUM 30
2920 #define SPARC_FP0_REGNUM 32
2921 #define SPARC32_NPC_REGNUM 69
2922 #define SPARC32_PC_REGNUM 68
2923 #define SPARC32_Y_REGNUM 64
2924 #define SPARC64_PC_REGNUM 80
2925 #define SPARC64_NPC_REGNUM 81
2926 #define SPARC64_Y_REGNUM 85
2928 static struct gdbarch
*
2929 sparc_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2931 struct gdbarch
*gdbarch
;
2932 struct gdbarch_tdep
*tdep
;
2934 static LONGEST call_dummy_32
[] =
2935 { 0xbc100001, 0x9de38000, 0xbc100002, 0xbe100003,
2936 0xda03a058, 0xd803a054, 0xd603a050, 0xd403a04c,
2937 0xd203a048, 0x40000000, 0xd003a044, 0x01000000,
2938 0x91d02001, 0x01000000
2940 static LONGEST call_dummy_64
[] =
2941 { 0x9de3bec0fd3fa7f7LL
, 0xf93fa7eff53fa7e7LL
,
2942 0xf13fa7dfed3fa7d7LL
, 0xe93fa7cfe53fa7c7LL
,
2943 0xe13fa7bfdd3fa7b7LL
, 0xd93fa7afd53fa7a7LL
,
2944 0xd13fa79fcd3fa797LL
, 0xc93fa78fc53fa787LL
,
2945 0xc13fa77fcc3fa777LL
, 0xc83fa76fc43fa767LL
,
2946 0xc03fa75ffc3fa757LL
, 0xf83fa74ff43fa747LL
,
2947 0xf03fa73f01000000LL
, 0x0100000001000000LL
,
2948 0x0100000091580000LL
, 0xd027a72b93500000LL
,
2949 0xd027a72791480000LL
, 0xd027a72391400000LL
,
2950 0xd027a71fda5ba8a7LL
, 0xd85ba89fd65ba897LL
,
2951 0xd45ba88fd25ba887LL
, 0x9fc02000d05ba87fLL
,
2952 0x0100000091d02001LL
, 0x0100000001000000LL
2954 static LONGEST call_dummy_nil
[] = {0};
2956 /* First see if there is already a gdbarch that can satisfy the request. */
2957 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2959 return arches
->gdbarch
;
2961 /* None found: is the request for a sparc architecture? */
2962 if (info
.bfd_arch_info
->arch
!= bfd_arch_sparc
)
2963 return NULL
; /* No; then it's not for us. */
2965 /* Yes: create a new gdbarch for the specified machine type. */
2966 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
2967 gdbarch
= gdbarch_alloc (&info
, tdep
);
2969 /* First set settings that are common for all sparc architectures. */
2970 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2971 set_gdbarch_breakpoint_from_pc (gdbarch
, memory_breakpoint_from_pc
);
2972 set_gdbarch_coerce_float_to_double (gdbarch
,
2973 sparc_coerce_float_to_double
);
2974 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
2975 set_gdbarch_call_dummy_p (gdbarch
, 1);
2976 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 1);
2977 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
2978 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2979 set_gdbarch_extract_struct_value_address (gdbarch
,
2980 sparc_extract_struct_value_address
);
2981 set_gdbarch_fix_call_dummy (gdbarch
, sparc_gdbarch_fix_call_dummy
);
2982 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2983 set_gdbarch_fp_regnum (gdbarch
, SPARC_FP_REGNUM
);
2984 set_gdbarch_fp0_regnum (gdbarch
, SPARC_FP0_REGNUM
);
2985 set_gdbarch_frame_args_address (gdbarch
, default_frame_address
);
2986 set_gdbarch_frame_chain (gdbarch
, sparc_frame_chain
);
2987 set_gdbarch_frame_init_saved_regs (gdbarch
, sparc_frame_init_saved_regs
);
2988 set_gdbarch_frame_locals_address (gdbarch
, default_frame_address
);
2989 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
2990 set_gdbarch_frame_saved_pc (gdbarch
, sparc_frame_saved_pc
);
2991 set_gdbarch_frameless_function_invocation (gdbarch
,
2992 frameless_look_for_prologue
);
2993 set_gdbarch_get_saved_register (gdbarch
, sparc_get_saved_register
);
2994 set_gdbarch_init_extra_frame_info (gdbarch
, sparc_init_extra_frame_info
);
2995 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2996 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2997 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
2998 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2999 set_gdbarch_max_register_raw_size (gdbarch
, 8);
3000 set_gdbarch_max_register_virtual_size (gdbarch
, 8);
3001 set_gdbarch_pop_frame (gdbarch
, sparc_pop_frame
);
3002 set_gdbarch_push_return_address (gdbarch
, sparc_push_return_address
);
3003 set_gdbarch_push_dummy_frame (gdbarch
, sparc_push_dummy_frame
);
3004 set_gdbarch_read_pc (gdbarch
, generic_target_read_pc
);
3005 set_gdbarch_register_convert_to_raw (gdbarch
, sparc_convert_to_raw
);
3006 set_gdbarch_register_convert_to_virtual (gdbarch
,
3007 sparc_convert_to_virtual
);
3008 set_gdbarch_register_convertible (gdbarch
,
3009 generic_register_convertible_not
);
3010 set_gdbarch_reg_struct_has_addr (gdbarch
, sparc_reg_struct_has_addr
);
3011 set_gdbarch_return_value_on_stack (gdbarch
, sparc_return_value_on_stack
);
3012 set_gdbarch_saved_pc_after_call (gdbarch
, sparc_saved_pc_after_call
);
3013 set_gdbarch_prologue_frameless_p (gdbarch
, sparc_prologue_frameless_p
);
3014 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
3015 set_gdbarch_skip_prologue (gdbarch
, sparc_skip_prologue
);
3016 set_gdbarch_sp_regnum (gdbarch
, SPARC_SP_REGNUM
);
3017 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
3018 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
3021 * Settings that depend only on 32/64 bit word size
3024 switch (info
.bfd_arch_info
->mach
)
3026 case bfd_mach_sparc
:
3027 case bfd_mach_sparc_sparclet
:
3028 case bfd_mach_sparc_sparclite
:
3029 case bfd_mach_sparc_v8plus
:
3030 case bfd_mach_sparc_v8plusa
:
3031 case bfd_mach_sparc_sparclite_le
:
3032 /* 32-bit machine types: */
3034 #ifdef SPARC32_CALL_DUMMY_ON_STACK
3035 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_on_stack
);
3036 set_gdbarch_call_dummy_address (gdbarch
, sparc_call_dummy_address
);
3037 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0x30);
3038 set_gdbarch_call_dummy_length (gdbarch
, 0x38);
3040 /* NOTE: cagney/2002-04-26: Based from info posted by Peter
3041 Schauer around Oct '99. Briefly, due to aspects of the SPARC
3042 ABI, it isn't possible to use ON_STACK with a strictly
3045 Peter Schauer writes ...
3047 No, any call from GDB to a user function returning a
3048 struct/union will fail miserably. Try this:
3067 for (i = 0; i < 4; i++)
3073 Set a breakpoint at the gx = sret () statement, run to it and
3074 issue a `print sret()'. It will not succed with your
3075 approach, and I doubt that continuing the program will work
3078 For details of the ABI see the Sparc Architecture Manual. I
3079 have Version 8 (Prentice Hall ISBN 0-13-825001-4) and the
3080 calling conventions for functions returning aggregate values
3081 are explained in Appendix D.3. */
3083 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
3084 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_32
);
3086 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
3087 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
3088 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
3089 set_gdbarch_call_dummy_length (gdbarch
, 0);
3090 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
3091 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_nil
);
3093 set_gdbarch_call_dummy_stack_adjust (gdbarch
, 68);
3094 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
3095 set_gdbarch_frame_args_skip (gdbarch
, 68);
3096 set_gdbarch_function_start_offset (gdbarch
, 0);
3097 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3098 set_gdbarch_npc_regnum (gdbarch
, SPARC32_NPC_REGNUM
);
3099 set_gdbarch_pc_regnum (gdbarch
, SPARC32_PC_REGNUM
);
3100 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3101 set_gdbarch_push_arguments (gdbarch
, sparc32_push_arguments
);
3102 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
3103 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
3105 set_gdbarch_register_byte (gdbarch
, sparc32_register_byte
);
3106 set_gdbarch_register_raw_size (gdbarch
, sparc32_register_size
);
3107 set_gdbarch_register_size (gdbarch
, 4);
3108 set_gdbarch_register_virtual_size (gdbarch
, sparc32_register_size
);
3109 set_gdbarch_register_virtual_type (gdbarch
,
3110 sparc32_register_virtual_type
);
3111 #ifdef SPARC32_CALL_DUMMY_ON_STACK
3112 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (call_dummy_32
));
3114 set_gdbarch_sizeof_call_dummy_words (gdbarch
, 0);
3116 set_gdbarch_stack_align (gdbarch
, sparc32_stack_align
);
3117 set_gdbarch_store_struct_return (gdbarch
, sparc32_store_struct_return
);
3118 set_gdbarch_use_struct_convention (gdbarch
,
3119 generic_use_struct_convention
);
3120 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
3121 tdep
->y_regnum
= SPARC32_Y_REGNUM
;
3122 tdep
->fp_max_regnum
= SPARC_FP0_REGNUM
+ 32;
3123 tdep
->intreg_size
= 4;
3124 tdep
->reg_save_offset
= 0x60;
3125 tdep
->call_dummy_call_offset
= 0x24;
3128 case bfd_mach_sparc_v9
:
3129 case bfd_mach_sparc_v9a
:
3130 /* 64-bit machine types: */
3131 default: /* Any new machine type is likely to be 64-bit. */
3133 #ifdef SPARC64_CALL_DUMMY_ON_STACK
3134 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_on_stack
);
3135 set_gdbarch_call_dummy_address (gdbarch
, sparc_call_dummy_address
);
3136 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 8 * 4);
3137 set_gdbarch_call_dummy_length (gdbarch
, 192);
3138 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
3139 set_gdbarch_call_dummy_start_offset (gdbarch
, 148);
3140 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_64
);
3142 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
3143 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
3144 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
3145 set_gdbarch_call_dummy_length (gdbarch
, 0);
3146 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
3147 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
3148 set_gdbarch_call_dummy_words (gdbarch
, call_dummy_nil
);
3150 set_gdbarch_call_dummy_stack_adjust (gdbarch
, 128);
3151 set_gdbarch_frame_args_skip (gdbarch
, 136);
3152 set_gdbarch_function_start_offset (gdbarch
, 0);
3153 set_gdbarch_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3154 set_gdbarch_npc_regnum (gdbarch
, SPARC64_NPC_REGNUM
);
3155 set_gdbarch_pc_regnum (gdbarch
, SPARC64_PC_REGNUM
);
3156 set_gdbarch_ptr_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3157 set_gdbarch_push_arguments (gdbarch
, sparc64_push_arguments
);
3158 /* NOTE different for at_entry */
3159 set_gdbarch_read_fp (gdbarch
, sparc64_read_fp
);
3160 set_gdbarch_read_sp (gdbarch
, sparc64_read_sp
);
3161 /* Some of the registers aren't 64 bits, but it's a lot simpler just
3162 to assume they all are (since most of them are). */
3163 set_gdbarch_register_byte (gdbarch
, sparc64_register_byte
);
3164 set_gdbarch_register_raw_size (gdbarch
, sparc64_register_size
);
3165 set_gdbarch_register_size (gdbarch
, 8);
3166 set_gdbarch_register_virtual_size (gdbarch
, sparc64_register_size
);
3167 set_gdbarch_register_virtual_type (gdbarch
,
3168 sparc64_register_virtual_type
);
3169 #ifdef SPARC64_CALL_DUMMY_ON_STACK
3170 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (call_dummy_64
));
3172 set_gdbarch_sizeof_call_dummy_words (gdbarch
, 0);
3174 set_gdbarch_stack_align (gdbarch
, sparc64_stack_align
);
3175 set_gdbarch_store_struct_return (gdbarch
, sparc64_store_struct_return
);
3176 set_gdbarch_use_struct_convention (gdbarch
,
3177 sparc64_use_struct_convention
);
3178 set_gdbarch_write_sp (gdbarch
, sparc64_write_sp
);
3179 tdep
->y_regnum
= SPARC64_Y_REGNUM
;
3180 tdep
->fp_max_regnum
= SPARC_FP0_REGNUM
+ 48;
3181 tdep
->intreg_size
= 8;
3182 tdep
->reg_save_offset
= 0x90;
3183 tdep
->call_dummy_call_offset
= 148 + 4 * 5;
3188 * Settings that vary per-architecture:
3191 switch (info
.bfd_arch_info
->mach
)
3193 case bfd_mach_sparc
:
3194 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3195 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3196 set_gdbarch_num_regs (gdbarch
, 72);
3197 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4);
3198 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
3199 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3200 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3201 tdep
->fp_register_bytes
= 32 * 4;
3202 tdep
->print_insn_mach
= bfd_mach_sparc
;
3204 case bfd_mach_sparc_sparclet
:
3205 set_gdbarch_extract_return_value (gdbarch
,
3206 sparclet_extract_return_value
);
3207 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3208 set_gdbarch_num_regs (gdbarch
, 32 + 32 + 8 + 8 + 8);
3209 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4 + 8*4 + 8*4);
3210 set_gdbarch_register_name (gdbarch
, sparclet_register_name
);
3211 set_gdbarch_store_return_value (gdbarch
, sparclet_store_return_value
);
3212 tdep
->has_fpu
= 0; /* (all but sparclet and sparclite) */
3213 tdep
->fp_register_bytes
= 0;
3214 tdep
->print_insn_mach
= bfd_mach_sparc_sparclet
;
3216 case bfd_mach_sparc_sparclite
:
3217 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3218 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
3219 set_gdbarch_num_regs (gdbarch
, 80);
3220 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4 + 8*4);
3221 set_gdbarch_register_name (gdbarch
, sparclite_register_name
);
3222 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3223 tdep
->has_fpu
= 0; /* (all but sparclet and sparclite) */
3224 tdep
->fp_register_bytes
= 0;
3225 tdep
->print_insn_mach
= bfd_mach_sparc_sparclite
;
3227 case bfd_mach_sparc_v8plus
:
3228 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3229 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3230 set_gdbarch_num_regs (gdbarch
, 72);
3231 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4);
3232 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
3233 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3234 tdep
->print_insn_mach
= bfd_mach_sparc
;
3235 tdep
->fp_register_bytes
= 32 * 4;
3236 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3238 case bfd_mach_sparc_v8plusa
:
3239 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3240 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3241 set_gdbarch_num_regs (gdbarch
, 72);
3242 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4);
3243 set_gdbarch_register_name (gdbarch
, sparc32_register_name
);
3244 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3245 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3246 tdep
->fp_register_bytes
= 32 * 4;
3247 tdep
->print_insn_mach
= bfd_mach_sparc
;
3249 case bfd_mach_sparc_sparclite_le
:
3250 set_gdbarch_extract_return_value (gdbarch
, sparc32_extract_return_value
);
3251 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
3252 set_gdbarch_num_regs (gdbarch
, 80);
3253 set_gdbarch_register_bytes (gdbarch
, 32*4 + 32*4 + 8*4 + 8*4);
3254 set_gdbarch_register_name (gdbarch
, sparclite_register_name
);
3255 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3256 tdep
->has_fpu
= 0; /* (all but sparclet and sparclite) */
3257 tdep
->fp_register_bytes
= 0;
3258 tdep
->print_insn_mach
= bfd_mach_sparc_sparclite
;
3260 case bfd_mach_sparc_v9
:
3261 set_gdbarch_extract_return_value (gdbarch
, sparc64_extract_return_value
);
3262 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3263 set_gdbarch_num_regs (gdbarch
, 125);
3264 set_gdbarch_register_bytes (gdbarch
, 32*8 + 32*8 + 45*8);
3265 set_gdbarch_register_name (gdbarch
, sparc64_register_name
);
3266 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3267 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3268 tdep
->fp_register_bytes
= 64 * 4;
3269 tdep
->print_insn_mach
= bfd_mach_sparc_v9a
;
3271 case bfd_mach_sparc_v9a
:
3272 set_gdbarch_extract_return_value (gdbarch
, sparc64_extract_return_value
);
3273 set_gdbarch_frame_chain_valid (gdbarch
, file_frame_chain_valid
);
3274 set_gdbarch_num_regs (gdbarch
, 125);
3275 set_gdbarch_register_bytes (gdbarch
, 32*8 + 32*8 + 45*8);
3276 set_gdbarch_register_name (gdbarch
, sparc64_register_name
);
3277 set_gdbarch_store_return_value (gdbarch
, sparc_store_return_value
);
3278 tdep
->has_fpu
= 1; /* (all but sparclet and sparclite) */
3279 tdep
->fp_register_bytes
= 64 * 4;
3280 tdep
->print_insn_mach
= bfd_mach_sparc_v9a
;