* configure.ac: Switch license to GPLv3.
[deliverable/binutils-gdb.git] / gdb / sparc-tdep.c
1 /* Target-dependent code for SPARC.
2
3 Copyright (C) 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
21
22 #include "defs.h"
23 #include "arch-utils.h"
24 #include "dis-asm.h"
25 #include "dwarf2-frame.h"
26 #include "floatformat.h"
27 #include "frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
30 #include "gdbcore.h"
31 #include "gdbtypes.h"
32 #include "inferior.h"
33 #include "symtab.h"
34 #include "objfiles.h"
35 #include "osabi.h"
36 #include "regcache.h"
37 #include "target.h"
38 #include "value.h"
39
40 #include "gdb_assert.h"
41 #include "gdb_string.h"
42
43 #include "sparc-tdep.h"
44
45 struct regset;
46
47 /* This file implements the SPARC 32-bit ABI as defined by the section
48 "Low-Level System Information" of the SPARC Compliance Definition
49 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
50 lists changes with respect to the original 32-bit psABI as defined
51 in the "System V ABI, SPARC Processor Supplement".
52
53 Note that if we talk about SunOS, we mean SunOS 4.x, which was
54 BSD-based, which is sometimes (retroactively?) referred to as
55 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
56 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
57 suffering from severe version number inflation). Solaris 2.x is
58 also known as SunOS 5.x, since that's what uname(1) says. Solaris
59 2.x is SVR4-based. */
60
61 /* Please use the sparc32_-prefix for 32-bit specific code, the
62 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
63 code that can handle both. The 64-bit specific code lives in
64 sparc64-tdep.c; don't add any here. */
65
66 /* The SPARC Floating-Point Quad-Precision format is similar to
67 big-endian IA-64 Quad-recision format. */
68 #define floatformats_sparc_quad floatformats_ia64_quad
69
70 /* The stack pointer is offset from the stack frame by a BIAS of 2047
71 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
72 hosts, so undefine it first. */
73 #undef BIAS
74 #define BIAS 2047
75
76 /* Macros to extract fields from SPARC instructions. */
77 #define X_OP(i) (((i) >> 30) & 0x3)
78 #define X_RD(i) (((i) >> 25) & 0x1f)
79 #define X_A(i) (((i) >> 29) & 1)
80 #define X_COND(i) (((i) >> 25) & 0xf)
81 #define X_OP2(i) (((i) >> 22) & 0x7)
82 #define X_IMM22(i) ((i) & 0x3fffff)
83 #define X_OP3(i) (((i) >> 19) & 0x3f)
84 #define X_RS1(i) (((i) >> 14) & 0x1f)
85 #define X_RS2(i) ((i) & 0x1f)
86 #define X_I(i) (((i) >> 13) & 1)
87 /* Sign extension macros. */
88 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
89 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
90 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
91
92 /* Fetch the instruction at PC. Instructions are always big-endian
93 even if the processor operates in little-endian mode. */
94
95 unsigned long
96 sparc_fetch_instruction (CORE_ADDR pc)
97 {
98 gdb_byte buf[4];
99 unsigned long insn;
100 int i;
101
102 /* If we can't read the instruction at PC, return zero. */
103 if (read_memory_nobpt (pc, buf, sizeof (buf)))
104 return 0;
105
106 insn = 0;
107 for (i = 0; i < sizeof (buf); i++)
108 insn = (insn << 8) | buf[i];
109 return insn;
110 }
111 \f
112
113 /* Return non-zero if the instruction corresponding to PC is an "unimp"
114 instruction. */
115
116 static int
117 sparc_is_unimp_insn (CORE_ADDR pc)
118 {
119 const unsigned long insn = sparc_fetch_instruction (pc);
120
121 return ((insn & 0xc1c00000) == 0);
122 }
123
124 /* OpenBSD/sparc includes StackGhost, which according to the author's
125 website http://stackghost.cerias.purdue.edu "... transparently and
126 automatically protects applications' stack frames; more
127 specifically, it guards the return pointers. The protection
128 mechanisms require no application source or binary modification and
129 imposes only a negligible performance penalty."
130
131 The same website provides the following description of how
132 StackGhost works:
133
134 "StackGhost interfaces with the kernel trap handler that would
135 normally write out registers to the stack and the handler that
136 would read them back in. By XORing a cookie into the
137 return-address saved in the user stack when it is actually written
138 to the stack, and then XOR it out when the return-address is pulled
139 from the stack, StackGhost can cause attacker corrupted return
140 pointers to behave in a manner the attacker cannot predict.
141 StackGhost can also use several unused bits in the return pointer
142 to detect a smashed return pointer and abort the process."
143
144 For GDB this means that whenever we're reading %i7 from a stack
145 frame's window save area, we'll have to XOR the cookie.
146
147 More information on StackGuard can be found on in:
148
149 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
150 Stack Protection." 2001. Published in USENIX Security Symposium
151 '01. */
152
153 /* Fetch StackGhost Per-Process XOR cookie. */
154
155 ULONGEST
156 sparc_fetch_wcookie (void)
157 {
158 struct target_ops *ops = &current_target;
159 gdb_byte buf[8];
160 int len;
161
162 len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8);
163 if (len == -1)
164 return 0;
165
166 /* We should have either an 32-bit or an 64-bit cookie. */
167 gdb_assert (len == 4 || len == 8);
168
169 return extract_unsigned_integer (buf, len);
170 }
171 \f
172
173 /* The functions on this page are intended to be used to classify
174 function arguments. */
175
176 /* Check whether TYPE is "Integral or Pointer". */
177
178 static int
179 sparc_integral_or_pointer_p (const struct type *type)
180 {
181 int len = TYPE_LENGTH (type);
182
183 switch (TYPE_CODE (type))
184 {
185 case TYPE_CODE_INT:
186 case TYPE_CODE_BOOL:
187 case TYPE_CODE_CHAR:
188 case TYPE_CODE_ENUM:
189 case TYPE_CODE_RANGE:
190 /* We have byte, half-word, word and extended-word/doubleword
191 integral types. The doubleword is an extension to the
192 original 32-bit ABI by the SCD 2.4.x. */
193 return (len == 1 || len == 2 || len == 4 || len == 8);
194 case TYPE_CODE_PTR:
195 case TYPE_CODE_REF:
196 /* Allow either 32-bit or 64-bit pointers. */
197 return (len == 4 || len == 8);
198 default:
199 break;
200 }
201
202 return 0;
203 }
204
205 /* Check whether TYPE is "Floating". */
206
207 static int
208 sparc_floating_p (const struct type *type)
209 {
210 switch (TYPE_CODE (type))
211 {
212 case TYPE_CODE_FLT:
213 {
214 int len = TYPE_LENGTH (type);
215 return (len == 4 || len == 8 || len == 16);
216 }
217 default:
218 break;
219 }
220
221 return 0;
222 }
223
224 /* Check whether TYPE is "Structure or Union". */
225
226 static int
227 sparc_structure_or_union_p (const struct type *type)
228 {
229 switch (TYPE_CODE (type))
230 {
231 case TYPE_CODE_STRUCT:
232 case TYPE_CODE_UNION:
233 return 1;
234 default:
235 break;
236 }
237
238 return 0;
239 }
240
241 /* Register information. */
242
243 static const char *sparc32_register_names[] =
244 {
245 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
246 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
247 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
248 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
249
250 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
251 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
252 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
253 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
254
255 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
256 };
257
258 /* Total number of registers. */
259 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
260
261 /* We provide the aliases %d0..%d30 for the floating registers as
262 "psuedo" registers. */
263
264 static const char *sparc32_pseudo_register_names[] =
265 {
266 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
267 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
268 };
269
270 /* Total number of pseudo registers. */
271 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
272
273 /* Return the name of register REGNUM. */
274
275 static const char *
276 sparc32_register_name (int regnum)
277 {
278 if (regnum >= 0 && regnum < SPARC32_NUM_REGS)
279 return sparc32_register_names[regnum];
280
281 if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS)
282 return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS];
283
284 return NULL;
285 }
286 \f
287
288 /* Type for %psr. */
289 struct type *sparc_psr_type;
290
291 /* Type for %fsr. */
292 struct type *sparc_fsr_type;
293
294 /* Construct types for ISA-specific registers. */
295
296 static void
297 sparc_init_types (void)
298 {
299 struct type *type;
300
301 type = init_flags_type ("builtin_type_sparc_psr", 4);
302 append_flags_type_flag (type, 5, "ET");
303 append_flags_type_flag (type, 6, "PS");
304 append_flags_type_flag (type, 7, "S");
305 append_flags_type_flag (type, 12, "EF");
306 append_flags_type_flag (type, 13, "EC");
307 sparc_psr_type = type;
308
309 type = init_flags_type ("builtin_type_sparc_fsr", 4);
310 append_flags_type_flag (type, 0, "NXA");
311 append_flags_type_flag (type, 1, "DZA");
312 append_flags_type_flag (type, 2, "UFA");
313 append_flags_type_flag (type, 3, "OFA");
314 append_flags_type_flag (type, 4, "NVA");
315 append_flags_type_flag (type, 5, "NXC");
316 append_flags_type_flag (type, 6, "DZC");
317 append_flags_type_flag (type, 7, "UFC");
318 append_flags_type_flag (type, 8, "OFC");
319 append_flags_type_flag (type, 9, "NVC");
320 append_flags_type_flag (type, 22, "NS");
321 append_flags_type_flag (type, 23, "NXM");
322 append_flags_type_flag (type, 24, "DZM");
323 append_flags_type_flag (type, 25, "UFM");
324 append_flags_type_flag (type, 26, "OFM");
325 append_flags_type_flag (type, 27, "NVM");
326 sparc_fsr_type = type;
327 }
328
329 /* Return the GDB type object for the "standard" data type of data in
330 register REGNUM. */
331
332 static struct type *
333 sparc32_register_type (struct gdbarch *gdbarch, int regnum)
334 {
335 if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM)
336 return builtin_type_float;
337
338 if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM)
339 return builtin_type_double;
340
341 if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM)
342 return builtin_type_void_data_ptr;
343
344 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
345 return builtin_type_void_func_ptr;
346
347 if (regnum == SPARC32_PSR_REGNUM)
348 return sparc_psr_type;
349
350 if (regnum == SPARC32_FSR_REGNUM)
351 return sparc_fsr_type;
352
353 return builtin_type_int32;
354 }
355
356 static void
357 sparc32_pseudo_register_read (struct gdbarch *gdbarch,
358 struct regcache *regcache,
359 int regnum, gdb_byte *buf)
360 {
361 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
362
363 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
364 regcache_raw_read (regcache, regnum, buf);
365 regcache_raw_read (regcache, regnum + 1, buf + 4);
366 }
367
368 static void
369 sparc32_pseudo_register_write (struct gdbarch *gdbarch,
370 struct regcache *regcache,
371 int regnum, const gdb_byte *buf)
372 {
373 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
374
375 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
376 regcache_raw_write (regcache, regnum, buf);
377 regcache_raw_write (regcache, regnum + 1, buf + 4);
378 }
379 \f
380
381 static CORE_ADDR
382 sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
383 CORE_ADDR funcaddr, int using_gcc,
384 struct value **args, int nargs,
385 struct type *value_type,
386 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
387 struct regcache *regcache)
388 {
389 *bp_addr = sp - 4;
390 *real_pc = funcaddr;
391
392 if (using_struct_return (value_type, using_gcc))
393 {
394 gdb_byte buf[4];
395
396 /* This is an UNIMP instruction. */
397 store_unsigned_integer (buf, 4, TYPE_LENGTH (value_type) & 0x1fff);
398 write_memory (sp - 8, buf, 4);
399 return sp - 8;
400 }
401
402 return sp - 4;
403 }
404
405 static CORE_ADDR
406 sparc32_store_arguments (struct regcache *regcache, int nargs,
407 struct value **args, CORE_ADDR sp,
408 int struct_return, CORE_ADDR struct_addr)
409 {
410 /* Number of words in the "parameter array". */
411 int num_elements = 0;
412 int element = 0;
413 int i;
414
415 for (i = 0; i < nargs; i++)
416 {
417 struct type *type = value_type (args[i]);
418 int len = TYPE_LENGTH (type);
419
420 if (sparc_structure_or_union_p (type)
421 || (sparc_floating_p (type) && len == 16))
422 {
423 /* Structure, Union and Quad-Precision Arguments. */
424 sp -= len;
425
426 /* Use doubleword alignment for these values. That's always
427 correct, and wasting a few bytes shouldn't be a problem. */
428 sp &= ~0x7;
429
430 write_memory (sp, value_contents (args[i]), len);
431 args[i] = value_from_pointer (lookup_pointer_type (type), sp);
432 num_elements++;
433 }
434 else if (sparc_floating_p (type))
435 {
436 /* Floating arguments. */
437 gdb_assert (len == 4 || len == 8);
438 num_elements += (len / 4);
439 }
440 else
441 {
442 /* Integral and pointer arguments. */
443 gdb_assert (sparc_integral_or_pointer_p (type));
444
445 if (len < 4)
446 args[i] = value_cast (builtin_type_int32, args[i]);
447 num_elements += ((len + 3) / 4);
448 }
449 }
450
451 /* Always allocate at least six words. */
452 sp -= max (6, num_elements) * 4;
453
454 /* The psABI says that "Software convention requires space for the
455 struct/union return value pointer, even if the word is unused." */
456 sp -= 4;
457
458 /* The psABI says that "Although software convention and the
459 operating system require every stack frame to be doubleword
460 aligned." */
461 sp &= ~0x7;
462
463 for (i = 0; i < nargs; i++)
464 {
465 const bfd_byte *valbuf = value_contents (args[i]);
466 struct type *type = value_type (args[i]);
467 int len = TYPE_LENGTH (type);
468
469 gdb_assert (len == 4 || len == 8);
470
471 if (element < 6)
472 {
473 int regnum = SPARC_O0_REGNUM + element;
474
475 regcache_cooked_write (regcache, regnum, valbuf);
476 if (len > 4 && element < 5)
477 regcache_cooked_write (regcache, regnum + 1, valbuf + 4);
478 }
479
480 /* Always store the argument in memory. */
481 write_memory (sp + 4 + element * 4, valbuf, len);
482 element += len / 4;
483 }
484
485 gdb_assert (element == num_elements);
486
487 if (struct_return)
488 {
489 gdb_byte buf[4];
490
491 store_unsigned_integer (buf, 4, struct_addr);
492 write_memory (sp, buf, 4);
493 }
494
495 return sp;
496 }
497
498 static CORE_ADDR
499 sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
500 struct regcache *regcache, CORE_ADDR bp_addr,
501 int nargs, struct value **args, CORE_ADDR sp,
502 int struct_return, CORE_ADDR struct_addr)
503 {
504 CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8));
505
506 /* Set return address. */
507 regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc);
508
509 /* Set up function arguments. */
510 sp = sparc32_store_arguments (regcache, nargs, args, sp,
511 struct_return, struct_addr);
512
513 /* Allocate the 16-word window save area. */
514 sp -= 16 * 4;
515
516 /* Stack should be doubleword aligned at this point. */
517 gdb_assert (sp % 8 == 0);
518
519 /* Finally, update the stack pointer. */
520 regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp);
521
522 return sp;
523 }
524 \f
525
526 /* Use the program counter to determine the contents and size of a
527 breakpoint instruction. Return a pointer to a string of bytes that
528 encode a breakpoint instruction, store the length of the string in
529 *LEN and optionally adjust *PC to point to the correct memory
530 location for inserting the breakpoint. */
531
532 static const gdb_byte *
533 sparc_breakpoint_from_pc (CORE_ADDR *pc, int *len)
534 {
535 static const gdb_byte break_insn[] = { 0x91, 0xd0, 0x20, 0x01 };
536
537 *len = sizeof (break_insn);
538 return break_insn;
539 }
540 \f
541
542 /* Allocate and initialize a frame cache. */
543
544 static struct sparc_frame_cache *
545 sparc_alloc_frame_cache (void)
546 {
547 struct sparc_frame_cache *cache;
548 int i;
549
550 cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache);
551
552 /* Base address. */
553 cache->base = 0;
554 cache->pc = 0;
555
556 /* Frameless until proven otherwise. */
557 cache->frameless_p = 1;
558
559 cache->struct_return_p = 0;
560
561 return cache;
562 }
563
564 /* GCC generates several well-known sequences of instructions at the begining
565 of each function prologue when compiling with -fstack-check. If one of
566 such sequences starts at START_PC, then return the address of the
567 instruction immediately past this sequence. Otherwise, return START_PC. */
568
569 static CORE_ADDR
570 sparc_skip_stack_check (const CORE_ADDR start_pc)
571 {
572 CORE_ADDR pc = start_pc;
573 unsigned long insn;
574 int offset_stack_checking_sequence = 0;
575
576 /* With GCC, all stack checking sequences begin with the same two
577 instructions. */
578
579 /* sethi <some immediate>,%g1 */
580 insn = sparc_fetch_instruction (pc);
581 pc = pc + 4;
582 if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1))
583 return start_pc;
584
585 /* sub %sp, %g1, %g1 */
586 insn = sparc_fetch_instruction (pc);
587 pc = pc + 4;
588 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn)
589 && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1))
590 return start_pc;
591
592 insn = sparc_fetch_instruction (pc);
593 pc = pc + 4;
594
595 /* First possible sequence:
596 [first two instructions above]
597 clr [%g1 - some immediate] */
598
599 /* clr [%g1 - some immediate] */
600 if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
601 && X_RS1 (insn) == 1 && X_RD (insn) == 0)
602 {
603 /* Valid stack-check sequence, return the new PC. */
604 return pc;
605 }
606
607 /* Second possible sequence: A small number of probes.
608 [first two instructions above]
609 clr [%g1]
610 add %g1, -<some immediate>, %g1
611 clr [%g1]
612 [repeat the two instructions above any (small) number of times]
613 clr [%g1 - some immediate] */
614
615 /* clr [%g1] */
616 else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
617 && X_RS1 (insn) == 1 && X_RD (insn) == 0)
618 {
619 while (1)
620 {
621 /* add %g1, -<some immediate>, %g1 */
622 insn = sparc_fetch_instruction (pc);
623 pc = pc + 4;
624 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn)
625 && X_RS1 (insn) == 1 && X_RD (insn) == 1))
626 break;
627
628 /* clr [%g1] */
629 insn = sparc_fetch_instruction (pc);
630 pc = pc + 4;
631 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
632 && X_RD (insn) == 0 && X_RS1 (insn) == 1))
633 return start_pc;
634 }
635
636 /* clr [%g1 - some immediate] */
637 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
638 && X_RS1 (insn) == 1 && X_RD (insn) == 0))
639 return start_pc;
640
641 /* We found a valid stack-check sequence, return the new PC. */
642 return pc;
643 }
644
645 /* Third sequence: A probing loop.
646 [first two instructions above]
647 sethi <some immediate>, %g4
648 sub %g1, %g4, %g4
649 cmp %g1, %g4
650 be <disp>
651 add %g1, -<some immediate>, %g1
652 ba <disp>
653 clr [%g1]
654 clr [%g4 - some immediate] */
655
656 /* sethi <some immediate>, %g4 */
657 else if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4)
658 {
659 /* sub %g1, %g4, %g4 */
660 insn = sparc_fetch_instruction (pc);
661 pc = pc + 4;
662 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn)
663 && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4))
664 return start_pc;
665
666 /* cmp %g1, %g4 */
667 insn = sparc_fetch_instruction (pc);
668 pc = pc + 4;
669 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn)
670 && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4))
671 return start_pc;
672
673 /* be <disp> */
674 insn = sparc_fetch_instruction (pc);
675 pc = pc + 4;
676 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1))
677 return start_pc;
678
679 /* add %g1, -<some immediate>, %g1 */
680 insn = sparc_fetch_instruction (pc);
681 pc = pc + 4;
682 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn)
683 && X_RS1 (insn) == 1 && X_RD (insn) == 1))
684 return start_pc;
685
686 /* ba <disp> */
687 insn = sparc_fetch_instruction (pc);
688 pc = pc + 4;
689 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8))
690 return start_pc;
691
692 /* clr [%g1] */
693 insn = sparc_fetch_instruction (pc);
694 pc = pc + 4;
695 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
696 && X_RD (insn) == 0 && X_RS1 (insn) == 1))
697 return start_pc;
698
699 /* clr [%g4 - some immediate] */
700 insn = sparc_fetch_instruction (pc);
701 pc = pc + 4;
702 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
703 && X_RS1 (insn) == 4 && X_RD (insn) == 0))
704 return start_pc;
705
706 /* We found a valid stack-check sequence, return the new PC. */
707 return pc;
708 }
709
710 /* No stack check code in our prologue, return the start_pc. */
711 return start_pc;
712 }
713
714 CORE_ADDR
715 sparc_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
716 struct sparc_frame_cache *cache)
717 {
718 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
719 unsigned long insn;
720 int offset = 0;
721 int dest = -1;
722
723 pc = sparc_skip_stack_check (pc);
724
725 if (current_pc <= pc)
726 return current_pc;
727
728 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
729 SPARC the linker usually defines a symbol (typically
730 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
731 This symbol makes us end up here with PC pointing at the start of
732 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
733 would do our normal prologue analysis, we would probably conclude
734 that we've got a frame when in reality we don't, since the
735 dynamic linker patches up the first PLT with some code that
736 starts with a SAVE instruction. Patch up PC such that it points
737 at the start of our PLT entry. */
738 if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL))
739 pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size);
740
741 insn = sparc_fetch_instruction (pc);
742
743 /* Recognize a SETHI insn and record its destination. */
744 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04)
745 {
746 dest = X_RD (insn);
747 offset += 4;
748
749 insn = sparc_fetch_instruction (pc + 4);
750 }
751
752 /* Allow for an arithmetic operation on DEST or %g1. */
753 if (X_OP (insn) == 2 && X_I (insn)
754 && (X_RD (insn) == 1 || X_RD (insn) == dest))
755 {
756 offset += 4;
757
758 insn = sparc_fetch_instruction (pc + 8);
759 }
760
761 /* Check for the SAVE instruction that sets up the frame. */
762 if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c)
763 {
764 cache->frameless_p = 0;
765 return pc + offset + 4;
766 }
767
768 return pc;
769 }
770
771 static CORE_ADDR
772 sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
773 {
774 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
775 return frame_unwind_register_unsigned (next_frame, tdep->pc_regnum);
776 }
777
778 /* Return PC of first real instruction of the function starting at
779 START_PC. */
780
781 static CORE_ADDR
782 sparc32_skip_prologue (CORE_ADDR start_pc)
783 {
784 struct symtab_and_line sal;
785 CORE_ADDR func_start, func_end;
786 struct sparc_frame_cache cache;
787
788 /* This is the preferred method, find the end of the prologue by
789 using the debugging information. */
790 if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end))
791 {
792 sal = find_pc_line (func_start, 0);
793
794 if (sal.end < func_end
795 && start_pc <= sal.end)
796 return sal.end;
797 }
798
799 start_pc = sparc_analyze_prologue (start_pc, 0xffffffffUL, &cache);
800
801 /* The psABI says that "Although the first 6 words of arguments
802 reside in registers, the standard stack frame reserves space for
803 them.". It also suggests that a function may use that space to
804 "write incoming arguments 0 to 5" into that space, and that's
805 indeed what GCC seems to be doing. In that case GCC will
806 generate debug information that points to the stack slots instead
807 of the registers, so we should consider the instructions that
808 write out these incoming arguments onto the stack. Of course we
809 only need to do this if we have a stack frame. */
810
811 while (!cache.frameless_p)
812 {
813 unsigned long insn = sparc_fetch_instruction (start_pc);
814
815 /* Recognize instructions that store incoming arguments in
816 %i0...%i5 into the corresponding stack slot. */
817 if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 && X_I (insn)
818 && (X_RD (insn) >= 24 && X_RD (insn) <= 29) && X_RS1 (insn) == 30
819 && X_SIMM13 (insn) == 68 + (X_RD (insn) - 24) * 4)
820 {
821 start_pc += 4;
822 continue;
823 }
824
825 break;
826 }
827
828 return start_pc;
829 }
830
831 /* Normal frames. */
832
833 struct sparc_frame_cache *
834 sparc_frame_cache (struct frame_info *next_frame, void **this_cache)
835 {
836 struct sparc_frame_cache *cache;
837
838 if (*this_cache)
839 return *this_cache;
840
841 cache = sparc_alloc_frame_cache ();
842 *this_cache = cache;
843
844 cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME);
845 if (cache->pc != 0)
846 sparc_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache);
847
848 if (cache->frameless_p)
849 {
850 /* This function is frameless, so %fp (%i6) holds the frame
851 pointer for our calling frame. Use %sp (%o6) as this frame's
852 base address. */
853 cache->base =
854 frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM);
855 }
856 else
857 {
858 /* For normal frames, %fp (%i6) holds the frame pointer, the
859 base address for the current stack frame. */
860 cache->base =
861 frame_unwind_register_unsigned (next_frame, SPARC_FP_REGNUM);
862 }
863
864 if (cache->base & 1)
865 cache->base += BIAS;
866
867 return cache;
868 }
869
870 static int
871 sparc32_struct_return_from_sym (struct symbol *sym)
872 {
873 struct type *type = check_typedef (SYMBOL_TYPE (sym));
874 enum type_code code = TYPE_CODE (type);
875
876 if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD)
877 {
878 type = check_typedef (TYPE_TARGET_TYPE (type));
879 if (sparc_structure_or_union_p (type)
880 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
881 return 1;
882 }
883
884 return 0;
885 }
886
887 struct sparc_frame_cache *
888 sparc32_frame_cache (struct frame_info *next_frame, void **this_cache)
889 {
890 struct sparc_frame_cache *cache;
891 struct symbol *sym;
892
893 if (*this_cache)
894 return *this_cache;
895
896 cache = sparc_frame_cache (next_frame, this_cache);
897
898 sym = find_pc_function (cache->pc);
899 if (sym)
900 {
901 cache->struct_return_p = sparc32_struct_return_from_sym (sym);
902 }
903 else
904 {
905 /* There is no debugging information for this function to
906 help us determine whether this function returns a struct
907 or not. So we rely on another heuristic which is to check
908 the instruction at the return address and see if this is
909 an "unimp" instruction. If it is, then it is a struct-return
910 function. */
911 CORE_ADDR pc;
912 int regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM;
913
914 pc = frame_unwind_register_unsigned (next_frame, regnum) + 8;
915 if (sparc_is_unimp_insn (pc))
916 cache->struct_return_p = 1;
917 }
918
919 return cache;
920 }
921
922 static void
923 sparc32_frame_this_id (struct frame_info *next_frame, void **this_cache,
924 struct frame_id *this_id)
925 {
926 struct sparc_frame_cache *cache =
927 sparc32_frame_cache (next_frame, this_cache);
928
929 /* This marks the outermost frame. */
930 if (cache->base == 0)
931 return;
932
933 (*this_id) = frame_id_build (cache->base, cache->pc);
934 }
935
936 static void
937 sparc32_frame_prev_register (struct frame_info *next_frame, void **this_cache,
938 int regnum, int *optimizedp,
939 enum lval_type *lvalp, CORE_ADDR *addrp,
940 int *realnump, gdb_byte *valuep)
941 {
942 struct sparc_frame_cache *cache =
943 sparc32_frame_cache (next_frame, this_cache);
944
945 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
946 {
947 *optimizedp = 0;
948 *lvalp = not_lval;
949 *addrp = 0;
950 *realnump = -1;
951 if (valuep)
952 {
953 CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0;
954
955 /* If this functions has a Structure, Union or
956 Quad-Precision return value, we have to skip the UNIMP
957 instruction that encodes the size of the structure. */
958 if (cache->struct_return_p)
959 pc += 4;
960
961 regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM;
962 pc += frame_unwind_register_unsigned (next_frame, regnum) + 8;
963 store_unsigned_integer (valuep, 4, pc);
964 }
965 return;
966 }
967
968 /* Handle StackGhost. */
969 {
970 ULONGEST wcookie = sparc_fetch_wcookie ();
971
972 if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM)
973 {
974 *optimizedp = 0;
975 *lvalp = not_lval;
976 *addrp = 0;
977 *realnump = -1;
978 if (valuep)
979 {
980 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
981 ULONGEST i7;
982
983 /* Read the value in from memory. */
984 i7 = get_frame_memory_unsigned (next_frame, addr, 4);
985 store_unsigned_integer (valuep, 4, i7 ^ wcookie);
986 }
987 return;
988 }
989 }
990
991 /* The previous frame's `local' and `in' registers have been saved
992 in the register save area. */
993 if (!cache->frameless_p
994 && regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM)
995 {
996 *optimizedp = 0;
997 *lvalp = lval_memory;
998 *addrp = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
999 *realnump = -1;
1000 if (valuep)
1001 {
1002 struct gdbarch *gdbarch = get_frame_arch (next_frame);
1003
1004 /* Read the value in from memory. */
1005 read_memory (*addrp, valuep, register_size (gdbarch, regnum));
1006 }
1007 return;
1008 }
1009
1010 /* The previous frame's `out' registers are accessable as the
1011 current frame's `in' registers. */
1012 if (!cache->frameless_p
1013 && regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM)
1014 regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM);
1015
1016 *optimizedp = 0;
1017 *lvalp = lval_register;
1018 *addrp = 0;
1019 *realnump = regnum;
1020 if (valuep)
1021 frame_unwind_register (next_frame, (*realnump), valuep);
1022 }
1023
1024 static const struct frame_unwind sparc32_frame_unwind =
1025 {
1026 NORMAL_FRAME,
1027 sparc32_frame_this_id,
1028 sparc32_frame_prev_register
1029 };
1030
1031 static const struct frame_unwind *
1032 sparc32_frame_sniffer (struct frame_info *next_frame)
1033 {
1034 return &sparc32_frame_unwind;
1035 }
1036 \f
1037
1038 static CORE_ADDR
1039 sparc32_frame_base_address (struct frame_info *next_frame, void **this_cache)
1040 {
1041 struct sparc_frame_cache *cache =
1042 sparc32_frame_cache (next_frame, this_cache);
1043
1044 return cache->base;
1045 }
1046
1047 static const struct frame_base sparc32_frame_base =
1048 {
1049 &sparc32_frame_unwind,
1050 sparc32_frame_base_address,
1051 sparc32_frame_base_address,
1052 sparc32_frame_base_address
1053 };
1054
1055 static struct frame_id
1056 sparc_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1057 {
1058 CORE_ADDR sp;
1059
1060 sp = frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM);
1061 if (sp & 1)
1062 sp += BIAS;
1063 return frame_id_build (sp, frame_pc_unwind (next_frame));
1064 }
1065 \f
1066
1067 /* Extract from an array REGBUF containing the (raw) register state, a
1068 function return value of TYPE, and copy that into VALBUF. */
1069
1070 static void
1071 sparc32_extract_return_value (struct type *type, struct regcache *regcache,
1072 gdb_byte *valbuf)
1073 {
1074 int len = TYPE_LENGTH (type);
1075 gdb_byte buf[8];
1076
1077 gdb_assert (!sparc_structure_or_union_p (type));
1078 gdb_assert (!(sparc_floating_p (type) && len == 16));
1079
1080 if (sparc_floating_p (type))
1081 {
1082 /* Floating return values. */
1083 regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf);
1084 if (len > 4)
1085 regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4);
1086 memcpy (valbuf, buf, len);
1087 }
1088 else
1089 {
1090 /* Integral and pointer return values. */
1091 gdb_assert (sparc_integral_or_pointer_p (type));
1092
1093 regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf);
1094 if (len > 4)
1095 {
1096 regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4);
1097 gdb_assert (len == 8);
1098 memcpy (valbuf, buf, 8);
1099 }
1100 else
1101 {
1102 /* Just stripping off any unused bytes should preserve the
1103 signed-ness just fine. */
1104 memcpy (valbuf, buf + 4 - len, len);
1105 }
1106 }
1107 }
1108
1109 /* Write into the appropriate registers a function return value stored
1110 in VALBUF of type TYPE. */
1111
1112 static void
1113 sparc32_store_return_value (struct type *type, struct regcache *regcache,
1114 const gdb_byte *valbuf)
1115 {
1116 int len = TYPE_LENGTH (type);
1117 gdb_byte buf[8];
1118
1119 gdb_assert (!sparc_structure_or_union_p (type));
1120 gdb_assert (!(sparc_floating_p (type) && len == 16));
1121
1122 if (sparc_floating_p (type))
1123 {
1124 /* Floating return values. */
1125 memcpy (buf, valbuf, len);
1126 regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf);
1127 if (len > 4)
1128 regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4);
1129 }
1130 else
1131 {
1132 /* Integral and pointer return values. */
1133 gdb_assert (sparc_integral_or_pointer_p (type));
1134
1135 if (len > 4)
1136 {
1137 gdb_assert (len == 8);
1138 memcpy (buf, valbuf, 8);
1139 regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4);
1140 }
1141 else
1142 {
1143 /* ??? Do we need to do any sign-extension here? */
1144 memcpy (buf + 4 - len, valbuf, len);
1145 }
1146 regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf);
1147 }
1148 }
1149
1150 static enum return_value_convention
1151 sparc32_return_value (struct gdbarch *gdbarch, struct type *type,
1152 struct regcache *regcache, gdb_byte *readbuf,
1153 const gdb_byte *writebuf)
1154 {
1155 /* The psABI says that "...every stack frame reserves the word at
1156 %fp+64. If a function returns a structure, union, or
1157 quad-precision value, this word should hold the address of the
1158 object into which the return value should be copied." This
1159 guarantees that we can always find the return value, not just
1160 before the function returns. */
1161
1162 if (sparc_structure_or_union_p (type)
1163 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
1164 {
1165 if (readbuf)
1166 {
1167 ULONGEST sp;
1168 CORE_ADDR addr;
1169
1170 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1171 addr = read_memory_unsigned_integer (sp + 64, 4);
1172 read_memory (addr, readbuf, TYPE_LENGTH (type));
1173 }
1174
1175 return RETURN_VALUE_ABI_PRESERVES_ADDRESS;
1176 }
1177
1178 if (readbuf)
1179 sparc32_extract_return_value (type, regcache, readbuf);
1180 if (writebuf)
1181 sparc32_store_return_value (type, regcache, writebuf);
1182
1183 return RETURN_VALUE_REGISTER_CONVENTION;
1184 }
1185
1186 static int
1187 sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
1188 {
1189 return (sparc_structure_or_union_p (type)
1190 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16));
1191 }
1192
1193 static int
1194 sparc32_dwarf2_struct_return_p (struct frame_info *next_frame)
1195 {
1196 CORE_ADDR pc = frame_unwind_address_in_block (next_frame, NORMAL_FRAME);
1197 struct symbol *sym = find_pc_function (pc);
1198
1199 if (sym)
1200 return sparc32_struct_return_from_sym (sym);
1201 return 0;
1202 }
1203
1204 static void
1205 sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1206 struct dwarf2_frame_state_reg *reg,
1207 struct frame_info *next_frame)
1208 {
1209 int off;
1210
1211 switch (regnum)
1212 {
1213 case SPARC_G0_REGNUM:
1214 /* Since %g0 is always zero, there is no point in saving it, and
1215 people will be inclined omit it from the CFI. Make sure we
1216 don't warn about that. */
1217 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
1218 break;
1219 case SPARC_SP_REGNUM:
1220 reg->how = DWARF2_FRAME_REG_CFA;
1221 break;
1222 case SPARC32_PC_REGNUM:
1223 case SPARC32_NPC_REGNUM:
1224 reg->how = DWARF2_FRAME_REG_RA_OFFSET;
1225 off = 8;
1226 if (sparc32_dwarf2_struct_return_p (next_frame))
1227 off += 4;
1228 if (regnum == SPARC32_NPC_REGNUM)
1229 off += 4;
1230 reg->loc.offset = off;
1231 break;
1232 }
1233 }
1234
1235 \f
1236 /* The SPARC Architecture doesn't have hardware single-step support,
1237 and most operating systems don't implement it either, so we provide
1238 software single-step mechanism. */
1239
1240 static CORE_ADDR
1241 sparc_analyze_control_transfer (struct frame_info *frame,
1242 CORE_ADDR pc, CORE_ADDR *npc)
1243 {
1244 unsigned long insn = sparc_fetch_instruction (pc);
1245 int conditional_p = X_COND (insn) & 0x7;
1246 int branch_p = 0;
1247 long offset = 0; /* Must be signed for sign-extend. */
1248
1249 if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0)
1250 {
1251 /* Branch on Integer Register with Prediction (BPr). */
1252 branch_p = 1;
1253 conditional_p = 1;
1254 }
1255 else if (X_OP (insn) == 0 && X_OP2 (insn) == 6)
1256 {
1257 /* Branch on Floating-Point Condition Codes (FBfcc). */
1258 branch_p = 1;
1259 offset = 4 * X_DISP22 (insn);
1260 }
1261 else if (X_OP (insn) == 0 && X_OP2 (insn) == 5)
1262 {
1263 /* Branch on Floating-Point Condition Codes with Prediction
1264 (FBPfcc). */
1265 branch_p = 1;
1266 offset = 4 * X_DISP19 (insn);
1267 }
1268 else if (X_OP (insn) == 0 && X_OP2 (insn) == 2)
1269 {
1270 /* Branch on Integer Condition Codes (Bicc). */
1271 branch_p = 1;
1272 offset = 4 * X_DISP22 (insn);
1273 }
1274 else if (X_OP (insn) == 0 && X_OP2 (insn) == 1)
1275 {
1276 /* Branch on Integer Condition Codes with Prediction (BPcc). */
1277 branch_p = 1;
1278 offset = 4 * X_DISP19 (insn);
1279 }
1280 else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a)
1281 {
1282 /* Trap instruction (TRAP). */
1283 return gdbarch_tdep (get_frame_arch (frame))->step_trap (frame, insn);
1284 }
1285
1286 /* FIXME: Handle DONE and RETRY instructions. */
1287
1288 if (branch_p)
1289 {
1290 if (conditional_p)
1291 {
1292 /* For conditional branches, return nPC + 4 iff the annul
1293 bit is 1. */
1294 return (X_A (insn) ? *npc + 4 : 0);
1295 }
1296 else
1297 {
1298 /* For unconditional branches, return the target if its
1299 specified condition is "always" and return nPC + 4 if the
1300 condition is "never". If the annul bit is 1, set *NPC to
1301 zero. */
1302 if (X_COND (insn) == 0x0)
1303 pc = *npc, offset = 4;
1304 if (X_A (insn))
1305 *npc = 0;
1306
1307 gdb_assert (offset != 0);
1308 return pc + offset;
1309 }
1310 }
1311
1312 return 0;
1313 }
1314
1315 static CORE_ADDR
1316 sparc_step_trap (struct frame_info *frame, unsigned long insn)
1317 {
1318 return 0;
1319 }
1320
1321 int
1322 sparc_software_single_step (struct frame_info *frame)
1323 {
1324 struct gdbarch *arch = get_frame_arch (frame);
1325 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1326 CORE_ADDR npc, nnpc;
1327
1328 CORE_ADDR pc, orig_npc;
1329
1330 pc = get_frame_register_unsigned (frame, tdep->pc_regnum);
1331 orig_npc = npc = get_frame_register_unsigned (frame, tdep->npc_regnum);
1332
1333 /* Analyze the instruction at PC. */
1334 nnpc = sparc_analyze_control_transfer (frame, pc, &npc);
1335 if (npc != 0)
1336 insert_single_step_breakpoint (npc);
1337
1338 if (nnpc != 0)
1339 insert_single_step_breakpoint (nnpc);
1340
1341 /* Assert that we have set at least one breakpoint, and that
1342 they're not set at the same spot - unless we're going
1343 from here straight to NULL, i.e. a call or jump to 0. */
1344 gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0);
1345 gdb_assert (nnpc != npc || orig_npc == 0);
1346
1347 return 1;
1348 }
1349
1350 static void
1351 sparc_write_pc (struct regcache *regcache, CORE_ADDR pc)
1352 {
1353 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
1354
1355 regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc);
1356 regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4);
1357 }
1358 \f
1359 /* Unglobalize NAME. */
1360
1361 char *
1362 sparc_stabs_unglobalize_name (char *name)
1363 {
1364 /* The Sun compilers (Sun ONE Studio, Forte Developer, Sun WorkShop,
1365 SunPRO) convert file static variables into global values, a
1366 process known as globalization. In order to do this, the
1367 compiler will create a unique prefix and prepend it to each file
1368 static variable. For static variables within a function, this
1369 globalization prefix is followed by the function name (nested
1370 static variables within a function are supposed to generate a
1371 warning message, and are left alone). The procedure is
1372 documented in the Stabs Interface Manual, which is distrubuted
1373 with the compilers, although version 4.0 of the manual seems to
1374 be incorrect in some places, at least for SPARC. The
1375 globalization prefix is encoded into an N_OPT stab, with the form
1376 "G=<prefix>". The globalization prefix always seems to start
1377 with a dollar sign '$'; a dot '.' is used as a seperator. So we
1378 simply strip everything up until the last dot. */
1379
1380 if (name[0] == '$')
1381 {
1382 char *p = strrchr (name, '.');
1383 if (p)
1384 return p + 1;
1385 }
1386
1387 return name;
1388 }
1389 \f
1390
1391 /* Return the appropriate register set for the core section identified
1392 by SECT_NAME and SECT_SIZE. */
1393
1394 const struct regset *
1395 sparc_regset_from_core_section (struct gdbarch *gdbarch,
1396 const char *sect_name, size_t sect_size)
1397 {
1398 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1399
1400 if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset)
1401 return tdep->gregset;
1402
1403 if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset)
1404 return tdep->fpregset;
1405
1406 return NULL;
1407 }
1408 \f
1409
1410 static struct gdbarch *
1411 sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1412 {
1413 struct gdbarch_tdep *tdep;
1414 struct gdbarch *gdbarch;
1415
1416 /* If there is already a candidate, use it. */
1417 arches = gdbarch_list_lookup_by_info (arches, &info);
1418 if (arches != NULL)
1419 return arches->gdbarch;
1420
1421 /* Allocate space for the new architecture. */
1422 tdep = XMALLOC (struct gdbarch_tdep);
1423 gdbarch = gdbarch_alloc (&info, tdep);
1424
1425 tdep->pc_regnum = SPARC32_PC_REGNUM;
1426 tdep->npc_regnum = SPARC32_NPC_REGNUM;
1427 tdep->gregset = NULL;
1428 tdep->sizeof_gregset = 0;
1429 tdep->fpregset = NULL;
1430 tdep->sizeof_fpregset = 0;
1431 tdep->plt_entry_size = 0;
1432 tdep->step_trap = sparc_step_trap;
1433
1434 set_gdbarch_long_double_bit (gdbarch, 128);
1435 set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad);
1436
1437 set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS);
1438 set_gdbarch_register_name (gdbarch, sparc32_register_name);
1439 set_gdbarch_register_type (gdbarch, sparc32_register_type);
1440 set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS);
1441 set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read);
1442 set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write);
1443
1444 /* Register numbers of various important registers. */
1445 set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */
1446 set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */
1447 set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */
1448
1449 /* Call dummy code. */
1450 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
1451 set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code);
1452 set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call);
1453
1454 set_gdbarch_return_value (gdbarch, sparc32_return_value);
1455 set_gdbarch_stabs_argument_has_addr
1456 (gdbarch, sparc32_stabs_argument_has_addr);
1457
1458 set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue);
1459
1460 /* Stack grows downward. */
1461 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1462
1463 set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc);
1464
1465 set_gdbarch_frame_args_skip (gdbarch, 8);
1466
1467 set_gdbarch_print_insn (gdbarch, print_insn_sparc);
1468
1469 set_gdbarch_software_single_step (gdbarch, sparc_software_single_step);
1470 set_gdbarch_write_pc (gdbarch, sparc_write_pc);
1471
1472 set_gdbarch_unwind_dummy_id (gdbarch, sparc_unwind_dummy_id);
1473
1474 set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc);
1475
1476 frame_base_set_default (gdbarch, &sparc32_frame_base);
1477
1478 /* Hook in the DWARF CFI frame unwinder. */
1479 dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg);
1480 /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1481 StackGhost issues have been resolved. */
1482
1483 /* Hook in ABI-specific overrides, if they have been registered. */
1484 gdbarch_init_osabi (info, gdbarch);
1485
1486 frame_unwind_append_sniffer (gdbarch, sparc32_frame_sniffer);
1487
1488 /* If we have register sets, enable the generic core file support. */
1489 if (tdep->gregset)
1490 set_gdbarch_regset_from_core_section (gdbarch,
1491 sparc_regset_from_core_section);
1492
1493 return gdbarch;
1494 }
1495 \f
1496 /* Helper functions for dealing with register windows. */
1497
1498 void
1499 sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum)
1500 {
1501 int offset = 0;
1502 gdb_byte buf[8];
1503 int i;
1504
1505 if (sp & 1)
1506 {
1507 /* Registers are 64-bit. */
1508 sp += BIAS;
1509
1510 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1511 {
1512 if (regnum == i || regnum == -1)
1513 {
1514 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1515
1516 /* Handle StackGhost. */
1517 if (i == SPARC_I7_REGNUM)
1518 {
1519 ULONGEST wcookie = sparc_fetch_wcookie ();
1520 ULONGEST i7 = extract_unsigned_integer (buf + offset, 8);
1521
1522 store_unsigned_integer (buf + offset, 8, i7 ^ wcookie);
1523 }
1524
1525 regcache_raw_supply (regcache, i, buf);
1526 }
1527 }
1528 }
1529 else
1530 {
1531 /* Registers are 32-bit. Toss any sign-extension of the stack
1532 pointer. */
1533 sp &= 0xffffffffUL;
1534
1535 /* Clear out the top half of the temporary buffer, and put the
1536 register value in the bottom half if we're in 64-bit mode. */
1537 if (gdbarch_ptr_bit (current_gdbarch) == 64)
1538 {
1539 memset (buf, 0, 4);
1540 offset = 4;
1541 }
1542
1543 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1544 {
1545 if (regnum == i || regnum == -1)
1546 {
1547 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1548 buf + offset, 4);
1549
1550 /* Handle StackGhost. */
1551 if (i == SPARC_I7_REGNUM)
1552 {
1553 ULONGEST wcookie = sparc_fetch_wcookie ();
1554 ULONGEST i7 = extract_unsigned_integer (buf + offset, 4);
1555
1556 store_unsigned_integer (buf + offset, 4, i7 ^ wcookie);
1557 }
1558
1559 regcache_raw_supply (regcache, i, buf);
1560 }
1561 }
1562 }
1563 }
1564
1565 void
1566 sparc_collect_rwindow (const struct regcache *regcache,
1567 CORE_ADDR sp, int regnum)
1568 {
1569 int offset = 0;
1570 gdb_byte buf[8];
1571 int i;
1572
1573 if (sp & 1)
1574 {
1575 /* Registers are 64-bit. */
1576 sp += BIAS;
1577
1578 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1579 {
1580 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1581 {
1582 regcache_raw_collect (regcache, i, buf);
1583
1584 /* Handle StackGhost. */
1585 if (i == SPARC_I7_REGNUM)
1586 {
1587 ULONGEST wcookie = sparc_fetch_wcookie ();
1588 ULONGEST i7 = extract_unsigned_integer (buf + offset, 8);
1589
1590 store_unsigned_integer (buf, 8, i7 ^ wcookie);
1591 }
1592
1593 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1594 }
1595 }
1596 }
1597 else
1598 {
1599 /* Registers are 32-bit. Toss any sign-extension of the stack
1600 pointer. */
1601 sp &= 0xffffffffUL;
1602
1603 /* Only use the bottom half if we're in 64-bit mode. */
1604 if (gdbarch_ptr_bit (current_gdbarch) == 64)
1605 offset = 4;
1606
1607 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1608 {
1609 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1610 {
1611 regcache_raw_collect (regcache, i, buf);
1612
1613 /* Handle StackGhost. */
1614 if (i == SPARC_I7_REGNUM)
1615 {
1616 ULONGEST wcookie = sparc_fetch_wcookie ();
1617 ULONGEST i7 = extract_unsigned_integer (buf + offset, 4);
1618
1619 store_unsigned_integer (buf + offset, 4, i7 ^ wcookie);
1620 }
1621
1622 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1623 buf + offset, 4);
1624 }
1625 }
1626 }
1627 }
1628
1629 /* Helper functions for dealing with register sets. */
1630
1631 void
1632 sparc32_supply_gregset (const struct sparc_gregset *gregset,
1633 struct regcache *regcache,
1634 int regnum, const void *gregs)
1635 {
1636 const gdb_byte *regs = gregs;
1637 int i;
1638
1639 if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1640 regcache_raw_supply (regcache, SPARC32_PSR_REGNUM,
1641 regs + gregset->r_psr_offset);
1642
1643 if (regnum == SPARC32_PC_REGNUM || regnum == -1)
1644 regcache_raw_supply (regcache, SPARC32_PC_REGNUM,
1645 regs + gregset->r_pc_offset);
1646
1647 if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
1648 regcache_raw_supply (regcache, SPARC32_NPC_REGNUM,
1649 regs + gregset->r_npc_offset);
1650
1651 if (regnum == SPARC32_Y_REGNUM || regnum == -1)
1652 regcache_raw_supply (regcache, SPARC32_Y_REGNUM,
1653 regs + gregset->r_y_offset);
1654
1655 if (regnum == SPARC_G0_REGNUM || regnum == -1)
1656 regcache_raw_supply (regcache, SPARC_G0_REGNUM, NULL);
1657
1658 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
1659 {
1660 int offset = gregset->r_g1_offset;
1661
1662 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
1663 {
1664 if (regnum == i || regnum == -1)
1665 regcache_raw_supply (regcache, i, regs + offset);
1666 offset += 4;
1667 }
1668 }
1669
1670 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
1671 {
1672 /* Not all of the register set variants include Locals and
1673 Inputs. For those that don't, we read them off the stack. */
1674 if (gregset->r_l0_offset == -1)
1675 {
1676 ULONGEST sp;
1677
1678 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1679 sparc_supply_rwindow (regcache, sp, regnum);
1680 }
1681 else
1682 {
1683 int offset = gregset->r_l0_offset;
1684
1685 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1686 {
1687 if (regnum == i || regnum == -1)
1688 regcache_raw_supply (regcache, i, regs + offset);
1689 offset += 4;
1690 }
1691 }
1692 }
1693 }
1694
1695 void
1696 sparc32_collect_gregset (const struct sparc_gregset *gregset,
1697 const struct regcache *regcache,
1698 int regnum, void *gregs)
1699 {
1700 gdb_byte *regs = gregs;
1701 int i;
1702
1703 if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1704 regcache_raw_collect (regcache, SPARC32_PSR_REGNUM,
1705 regs + gregset->r_psr_offset);
1706
1707 if (regnum == SPARC32_PC_REGNUM || regnum == -1)
1708 regcache_raw_collect (regcache, SPARC32_PC_REGNUM,
1709 regs + gregset->r_pc_offset);
1710
1711 if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
1712 regcache_raw_collect (regcache, SPARC32_NPC_REGNUM,
1713 regs + gregset->r_npc_offset);
1714
1715 if (regnum == SPARC32_Y_REGNUM || regnum == -1)
1716 regcache_raw_collect (regcache, SPARC32_Y_REGNUM,
1717 regs + gregset->r_y_offset);
1718
1719 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
1720 {
1721 int offset = gregset->r_g1_offset;
1722
1723 /* %g0 is always zero. */
1724 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
1725 {
1726 if (regnum == i || regnum == -1)
1727 regcache_raw_collect (regcache, i, regs + offset);
1728 offset += 4;
1729 }
1730 }
1731
1732 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
1733 {
1734 /* Not all of the register set variants include Locals and
1735 Inputs. For those that don't, we read them off the stack. */
1736 if (gregset->r_l0_offset != -1)
1737 {
1738 int offset = gregset->r_l0_offset;
1739
1740 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1741 {
1742 if (regnum == i || regnum == -1)
1743 regcache_raw_collect (regcache, i, regs + offset);
1744 offset += 4;
1745 }
1746 }
1747 }
1748 }
1749
1750 void
1751 sparc32_supply_fpregset (struct regcache *regcache,
1752 int regnum, const void *fpregs)
1753 {
1754 const gdb_byte *regs = fpregs;
1755 int i;
1756
1757 for (i = 0; i < 32; i++)
1758 {
1759 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
1760 regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, regs + (i * 4));
1761 }
1762
1763 if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
1764 regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4);
1765 }
1766
1767 void
1768 sparc32_collect_fpregset (const struct regcache *regcache,
1769 int regnum, void *fpregs)
1770 {
1771 gdb_byte *regs = fpregs;
1772 int i;
1773
1774 for (i = 0; i < 32; i++)
1775 {
1776 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
1777 regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, regs + (i * 4));
1778 }
1779
1780 if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
1781 regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4);
1782 }
1783 \f
1784
1785 /* SunOS 4. */
1786
1787 /* From <machine/reg.h>. */
1788 const struct sparc_gregset sparc32_sunos4_gregset =
1789 {
1790 0 * 4, /* %psr */
1791 1 * 4, /* %pc */
1792 2 * 4, /* %npc */
1793 3 * 4, /* %y */
1794 -1, /* %wim */
1795 -1, /* %tbr */
1796 4 * 4, /* %g1 */
1797 -1 /* %l0 */
1798 };
1799 \f
1800
1801 /* Provide a prototype to silence -Wmissing-prototypes. */
1802 void _initialize_sparc_tdep (void);
1803
1804 void
1805 _initialize_sparc_tdep (void)
1806 {
1807 register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init);
1808
1809 /* Initialize the SPARC-specific register types. */
1810 sparc_init_types();
1811 }
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