1 /* SPU target-dependent code for GDB, the GNU debugger.
2 Copyright (C) 2006, 2007, 2008 Free Software Foundation, Inc.
4 Contributed by Ulrich Weigand <uweigand@de.ibm.com>.
5 Based on a port by Sid Manning <sid@us.ibm.com>.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "arch-utils.h"
27 #include "gdb_string.h"
28 #include "gdb_assert.h"
30 #include "frame-unwind.h"
31 #include "frame-base.h"
32 #include "trad-frame.h"
41 #include "reggroups.h"
42 #include "floatformat.h"
48 /* The tdep structure. */
51 /* SPU-specific vector type. */
52 struct type
*spu_builtin_type_vec128
;
56 /* SPU-specific vector type. */
58 spu_builtin_type_vec128 (struct gdbarch
*gdbarch
)
60 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
62 if (!tdep
->spu_builtin_type_vec128
)
66 t
= init_composite_type ("__spu_builtin_type_vec128", TYPE_CODE_UNION
);
67 append_composite_type_field (t
, "uint128", builtin_type_int128
);
68 append_composite_type_field (t
, "v2_int64",
69 init_vector_type (builtin_type_int64
, 2));
70 append_composite_type_field (t
, "v4_int32",
71 init_vector_type (builtin_type_int32
, 4));
72 append_composite_type_field (t
, "v8_int16",
73 init_vector_type (builtin_type_int16
, 8));
74 append_composite_type_field (t
, "v16_int8",
75 init_vector_type (builtin_type_int8
, 16));
76 append_composite_type_field (t
, "v2_double",
77 init_vector_type (builtin_type_double
, 2));
78 append_composite_type_field (t
, "v4_float",
79 init_vector_type (builtin_type_float
, 4));
82 TYPE_NAME (t
) = "spu_builtin_type_vec128";
84 tdep
->spu_builtin_type_vec128
= t
;
87 return tdep
->spu_builtin_type_vec128
;
91 /* The list of available "info spu " commands. */
92 static struct cmd_list_element
*infospucmdlist
= NULL
;
97 spu_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
99 static char *register_names
[] =
101 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
102 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
103 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
104 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
105 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
106 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
107 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
108 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
109 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
110 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
111 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
112 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
113 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
114 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
115 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
116 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
117 "id", "pc", "sp", "fpscr", "srr0", "lslr", "decr", "decr_status"
122 if (reg_nr
>= sizeof register_names
/ sizeof *register_names
)
125 return register_names
[reg_nr
];
129 spu_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
131 if (reg_nr
< SPU_NUM_GPRS
)
132 return spu_builtin_type_vec128 (gdbarch
);
137 return builtin_type_uint32
;
140 return builtin_type_void_func_ptr
;
143 return builtin_type_void_data_ptr
;
145 case SPU_FPSCR_REGNUM
:
146 return builtin_type_uint128
;
148 case SPU_SRR0_REGNUM
:
149 return builtin_type_uint32
;
151 case SPU_LSLR_REGNUM
:
152 return builtin_type_uint32
;
154 case SPU_DECR_REGNUM
:
155 return builtin_type_uint32
;
157 case SPU_DECR_STATUS_REGNUM
:
158 return builtin_type_uint32
;
161 internal_error (__FILE__
, __LINE__
, "invalid regnum");
165 /* Pseudo registers for preferred slots - stack pointer. */
168 spu_pseudo_register_read_spu (struct regcache
*regcache
, const char *regname
,
175 regcache_raw_read_unsigned (regcache
, SPU_ID_REGNUM
, &id
);
176 xsnprintf (annex
, sizeof annex
, "%d/%s", (int) id
, regname
);
177 memset (reg
, 0, sizeof reg
);
178 target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
181 store_unsigned_integer (buf
, 4, strtoulst (reg
, NULL
, 16));
185 spu_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
186 int regnum
, gdb_byte
*buf
)
195 regcache_raw_read (regcache
, SPU_RAW_SP_REGNUM
, reg
);
196 memcpy (buf
, reg
, 4);
199 case SPU_FPSCR_REGNUM
:
200 regcache_raw_read_unsigned (regcache
, SPU_ID_REGNUM
, &id
);
201 xsnprintf (annex
, sizeof annex
, "%d/fpcr", (int) id
);
202 target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
, buf
, 0, 16);
205 case SPU_SRR0_REGNUM
:
206 spu_pseudo_register_read_spu (regcache
, "srr0", buf
);
209 case SPU_LSLR_REGNUM
:
210 spu_pseudo_register_read_spu (regcache
, "lslr", buf
);
213 case SPU_DECR_REGNUM
:
214 spu_pseudo_register_read_spu (regcache
, "decr", buf
);
217 case SPU_DECR_STATUS_REGNUM
:
218 spu_pseudo_register_read_spu (regcache
, "decr_status", buf
);
222 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
227 spu_pseudo_register_write_spu (struct regcache
*regcache
, const char *regname
,
234 regcache_raw_read_unsigned (regcache
, SPU_ID_REGNUM
, &id
);
235 xsnprintf (annex
, sizeof annex
, "%d/%s", (int) id
, regname
);
236 xsnprintf (reg
, sizeof reg
, "0x%s",
237 phex_nz (extract_unsigned_integer (buf
, 4), 4));
238 target_write (¤t_target
, TARGET_OBJECT_SPU
, annex
,
239 reg
, 0, strlen (reg
));
243 spu_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
244 int regnum
, const gdb_byte
*buf
)
253 regcache_raw_read (regcache
, SPU_RAW_SP_REGNUM
, reg
);
254 memcpy (reg
, buf
, 4);
255 regcache_raw_write (regcache
, SPU_RAW_SP_REGNUM
, reg
);
258 case SPU_FPSCR_REGNUM
:
259 regcache_raw_read_unsigned (regcache
, SPU_ID_REGNUM
, &id
);
260 xsnprintf (annex
, sizeof annex
, "%d/fpcr", (int) id
);
261 target_write (¤t_target
, TARGET_OBJECT_SPU
, annex
, buf
, 0, 16);
264 case SPU_SRR0_REGNUM
:
265 spu_pseudo_register_write_spu (regcache
, "srr0", buf
);
268 case SPU_LSLR_REGNUM
:
269 spu_pseudo_register_write_spu (regcache
, "lslr", buf
);
272 case SPU_DECR_REGNUM
:
273 spu_pseudo_register_write_spu (regcache
, "decr", buf
);
276 case SPU_DECR_STATUS_REGNUM
:
277 spu_pseudo_register_write_spu (regcache
, "decr_status", buf
);
281 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
285 /* Value conversion -- access scalar values at the preferred slot. */
287 static struct value
*
288 spu_value_from_register (struct type
*type
, int regnum
,
289 struct frame_info
*frame
)
291 struct value
*value
= default_value_from_register (type
, regnum
, frame
);
292 int len
= TYPE_LENGTH (type
);
294 if (regnum
< SPU_NUM_GPRS
&& len
< 16)
296 int preferred_slot
= len
< 4 ? 4 - len
: 0;
297 set_value_offset (value
, preferred_slot
);
303 /* Register groups. */
306 spu_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
307 struct reggroup
*group
)
309 /* Registers displayed via 'info regs'. */
310 if (group
== general_reggroup
)
313 /* Registers displayed via 'info float'. */
314 if (group
== float_reggroup
)
317 /* Registers that need to be saved/restored in order to
318 push or pop frames. */
319 if (group
== save_reggroup
|| group
== restore_reggroup
)
322 return default_register_reggroup_p (gdbarch
, regnum
, group
);
325 /* Address conversion. */
328 spu_pointer_to_address (struct type
*type
, const gdb_byte
*buf
)
330 ULONGEST addr
= extract_unsigned_integer (buf
, TYPE_LENGTH (type
));
331 ULONGEST lslr
= SPU_LS_SIZE
- 1; /* Hard-wired LS size. */
333 if (target_has_registers
&& target_has_stack
&& target_has_memory
)
334 lslr
= get_frame_register_unsigned (get_selected_frame (NULL
),
341 spu_integer_to_address (struct gdbarch
*gdbarch
,
342 struct type
*type
, const gdb_byte
*buf
)
344 ULONGEST addr
= unpack_long (type
, buf
);
345 ULONGEST lslr
= SPU_LS_SIZE
- 1; /* Hard-wired LS size. */
347 if (target_has_registers
&& target_has_stack
&& target_has_memory
)
348 lslr
= get_frame_register_unsigned (get_selected_frame (NULL
),
355 /* Decoding SPU instructions. */
392 is_rr (unsigned int insn
, int op
, int *rt
, int *ra
, int *rb
)
394 if ((insn
>> 21) == op
)
397 *ra
= (insn
>> 7) & 127;
398 *rb
= (insn
>> 14) & 127;
406 is_rrr (unsigned int insn
, int op
, int *rt
, int *ra
, int *rb
, int *rc
)
408 if ((insn
>> 28) == op
)
410 *rt
= (insn
>> 21) & 127;
411 *ra
= (insn
>> 7) & 127;
412 *rb
= (insn
>> 14) & 127;
421 is_ri7 (unsigned int insn
, int op
, int *rt
, int *ra
, int *i7
)
423 if ((insn
>> 21) == op
)
426 *ra
= (insn
>> 7) & 127;
427 *i7
= (((insn
>> 14) & 127) ^ 0x40) - 0x40;
435 is_ri10 (unsigned int insn
, int op
, int *rt
, int *ra
, int *i10
)
437 if ((insn
>> 24) == op
)
440 *ra
= (insn
>> 7) & 127;
441 *i10
= (((insn
>> 14) & 0x3ff) ^ 0x200) - 0x200;
449 is_ri16 (unsigned int insn
, int op
, int *rt
, int *i16
)
451 if ((insn
>> 23) == op
)
454 *i16
= (((insn
>> 7) & 0xffff) ^ 0x8000) - 0x8000;
462 is_ri18 (unsigned int insn
, int op
, int *rt
, int *i18
)
464 if ((insn
>> 25) == op
)
467 *i18
= (((insn
>> 7) & 0x3ffff) ^ 0x20000) - 0x20000;
475 is_branch (unsigned int insn
, int *offset
, int *reg
)
479 if (is_ri16 (insn
, op_br
, &rt
, &i16
)
480 || is_ri16 (insn
, op_brsl
, &rt
, &i16
)
481 || is_ri16 (insn
, op_brnz
, &rt
, &i16
)
482 || is_ri16 (insn
, op_brz
, &rt
, &i16
)
483 || is_ri16 (insn
, op_brhnz
, &rt
, &i16
)
484 || is_ri16 (insn
, op_brhz
, &rt
, &i16
))
486 *reg
= SPU_PC_REGNUM
;
491 if (is_ri16 (insn
, op_bra
, &rt
, &i16
)
492 || is_ri16 (insn
, op_brasl
, &rt
, &i16
))
499 if (is_ri7 (insn
, op_bi
, &rt
, reg
, &i7
)
500 || is_ri7 (insn
, op_bisl
, &rt
, reg
, &i7
)
501 || is_ri7 (insn
, op_biz
, &rt
, reg
, &i7
)
502 || is_ri7 (insn
, op_binz
, &rt
, reg
, &i7
)
503 || is_ri7 (insn
, op_bihz
, &rt
, reg
, &i7
)
504 || is_ri7 (insn
, op_bihnz
, &rt
, reg
, &i7
))
514 /* Prolog parsing. */
516 struct spu_prologue_data
518 /* Stack frame size. -1 if analysis was unsuccessful. */
521 /* How to find the CFA. The CFA is equal to SP at function entry. */
525 /* Offset relative to CFA where a register is saved. -1 if invalid. */
526 int reg_offset
[SPU_NUM_GPRS
];
530 spu_analyze_prologue (CORE_ADDR start_pc
, CORE_ADDR end_pc
,
531 struct spu_prologue_data
*data
)
536 int reg_immed
[SPU_NUM_GPRS
];
538 CORE_ADDR prolog_pc
= start_pc
;
543 /* Initialize DATA to default values. */
546 data
->cfa_reg
= SPU_RAW_SP_REGNUM
;
547 data
->cfa_offset
= 0;
549 for (i
= 0; i
< SPU_NUM_GPRS
; i
++)
550 data
->reg_offset
[i
] = -1;
552 /* Set up REG_IMMED array. This is non-zero for a register if we know its
553 preferred slot currently holds this immediate value. */
554 for (i
= 0; i
< SPU_NUM_GPRS
; i
++)
557 /* Scan instructions until the first branch.
559 The following instructions are important prolog components:
561 - The first instruction to set up the stack pointer.
562 - The first instruction to set up the frame pointer.
563 - The first instruction to save the link register.
565 We return the instruction after the latest of these three,
566 or the incoming PC if none is found. The first instruction
567 to set up the stack pointer also defines the frame size.
569 Note that instructions saving incoming arguments to their stack
570 slots are not counted as important, because they are hard to
571 identify with certainty. This should not matter much, because
572 arguments are relevant only in code compiled with debug data,
573 and in such code the GDB core will advance until the first source
574 line anyway, using SAL data.
576 For purposes of stack unwinding, we analyze the following types
577 of instructions in addition:
579 - Any instruction adding to the current frame pointer.
580 - Any instruction loading an immediate constant into a register.
581 - Any instruction storing a register onto the stack.
583 These are used to compute the CFA and REG_OFFSET output. */
585 for (pc
= start_pc
; pc
< end_pc
; pc
+= 4)
588 int rt
, ra
, rb
, rc
, immed
;
590 if (target_read_memory (pc
, buf
, 4))
592 insn
= extract_unsigned_integer (buf
, 4);
594 /* AI is the typical instruction to set up a stack frame.
595 It is also used to initialize the frame pointer. */
596 if (is_ri10 (insn
, op_ai
, &rt
, &ra
, &immed
))
598 if (rt
== data
->cfa_reg
&& ra
== data
->cfa_reg
)
599 data
->cfa_offset
-= immed
;
601 if (rt
== SPU_RAW_SP_REGNUM
&& ra
== SPU_RAW_SP_REGNUM
609 else if (rt
== SPU_FP_REGNUM
&& ra
== SPU_RAW_SP_REGNUM
615 data
->cfa_reg
= SPU_FP_REGNUM
;
616 data
->cfa_offset
-= immed
;
620 /* A is used to set up stack frames of size >= 512 bytes.
621 If we have tracked the contents of the addend register,
622 we can handle this as well. */
623 else if (is_rr (insn
, op_a
, &rt
, &ra
, &rb
))
625 if (rt
== data
->cfa_reg
&& ra
== data
->cfa_reg
)
627 if (reg_immed
[rb
] != 0)
628 data
->cfa_offset
-= reg_immed
[rb
];
630 data
->cfa_reg
= -1; /* We don't know the CFA any more. */
633 if (rt
== SPU_RAW_SP_REGNUM
&& ra
== SPU_RAW_SP_REGNUM
639 if (reg_immed
[rb
] != 0)
640 data
->size
= -reg_immed
[rb
];
644 /* We need to track IL and ILA used to load immediate constants
645 in case they are later used as input to an A instruction. */
646 else if (is_ri16 (insn
, op_il
, &rt
, &immed
))
648 reg_immed
[rt
] = immed
;
650 if (rt
== SPU_RAW_SP_REGNUM
&& !found_sp
)
654 else if (is_ri18 (insn
, op_ila
, &rt
, &immed
))
656 reg_immed
[rt
] = immed
& 0x3ffff;
658 if (rt
== SPU_RAW_SP_REGNUM
&& !found_sp
)
662 /* STQD is used to save registers to the stack. */
663 else if (is_ri10 (insn
, op_stqd
, &rt
, &ra
, &immed
))
665 if (ra
== data
->cfa_reg
)
666 data
->reg_offset
[rt
] = data
->cfa_offset
- (immed
<< 4);
668 if (ra
== data
->cfa_reg
&& rt
== SPU_LR_REGNUM
676 /* _start uses SELB to set up the stack pointer. */
677 else if (is_rrr (insn
, op_selb
, &rt
, &ra
, &rb
, &rc
))
679 if (rt
== SPU_RAW_SP_REGNUM
&& !found_sp
)
683 /* We terminate if we find a branch. */
684 else if (is_branch (insn
, &immed
, &ra
))
689 /* If we successfully parsed until here, and didn't find any instruction
690 modifying SP, we assume we have a frameless function. */
694 /* Return cooked instead of raw SP. */
695 if (data
->cfa_reg
== SPU_RAW_SP_REGNUM
)
696 data
->cfa_reg
= SPU_SP_REGNUM
;
701 /* Return the first instruction after the prologue starting at PC. */
703 spu_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
705 struct spu_prologue_data data
;
706 return spu_analyze_prologue (pc
, (CORE_ADDR
)-1, &data
);
709 /* Return the frame pointer in use at address PC. */
711 spu_virtual_frame_pointer (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
712 int *reg
, LONGEST
*offset
)
714 struct spu_prologue_data data
;
715 spu_analyze_prologue (pc
, (CORE_ADDR
)-1, &data
);
717 if (data
.size
!= -1 && data
.cfa_reg
!= -1)
719 /* The 'frame pointer' address is CFA minus frame size. */
721 *offset
= data
.cfa_offset
- data
.size
;
725 /* ??? We don't really know ... */
726 *reg
= SPU_SP_REGNUM
;
731 /* Return true if we are in the function's epilogue, i.e. after the
732 instruction that destroyed the function's stack frame.
734 1) scan forward from the point of execution:
735 a) If you find an instruction that modifies the stack pointer
736 or transfers control (except a return), execution is not in
738 b) Stop scanning if you find a return instruction or reach the
739 end of the function or reach the hard limit for the size of
741 2) scan backward from the point of execution:
742 a) If you find an instruction that modifies the stack pointer,
743 execution *is* in an epilogue, return.
744 b) Stop scanning if you reach an instruction that transfers
745 control or the beginning of the function or reach the hard
746 limit for the size of an epilogue. */
749 spu_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
751 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
754 int rt
, ra
, rb
, rc
, immed
;
756 /* Find the search limits based on function boundaries and hard limit.
757 We assume the epilogue can be up to 64 instructions long. */
759 const int spu_max_epilogue_size
= 64 * 4;
761 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
764 if (pc
- func_start
< spu_max_epilogue_size
)
765 epilogue_start
= func_start
;
767 epilogue_start
= pc
- spu_max_epilogue_size
;
769 if (func_end
- pc
< spu_max_epilogue_size
)
770 epilogue_end
= func_end
;
772 epilogue_end
= pc
+ spu_max_epilogue_size
;
774 /* Scan forward until next 'bi $0'. */
776 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= 4)
778 if (target_read_memory (scan_pc
, buf
, 4))
780 insn
= extract_unsigned_integer (buf
, 4);
782 if (is_branch (insn
, &immed
, &ra
))
784 if (immed
== 0 && ra
== SPU_LR_REGNUM
)
790 if (is_ri10 (insn
, op_ai
, &rt
, &ra
, &immed
)
791 || is_rr (insn
, op_a
, &rt
, &ra
, &rb
)
792 || is_ri10 (insn
, op_lqd
, &rt
, &ra
, &immed
))
794 if (rt
== SPU_RAW_SP_REGNUM
)
799 if (scan_pc
>= epilogue_end
)
802 /* Scan backward until adjustment to stack pointer (R1). */
804 for (scan_pc
= pc
- 4; scan_pc
>= epilogue_start
; scan_pc
-= 4)
806 if (target_read_memory (scan_pc
, buf
, 4))
808 insn
= extract_unsigned_integer (buf
, 4);
810 if (is_branch (insn
, &immed
, &ra
))
813 if (is_ri10 (insn
, op_ai
, &rt
, &ra
, &immed
)
814 || is_rr (insn
, op_a
, &rt
, &ra
, &rb
)
815 || is_ri10 (insn
, op_lqd
, &rt
, &ra
, &immed
))
817 if (rt
== SPU_RAW_SP_REGNUM
)
826 /* Normal stack frames. */
828 struct spu_unwind_cache
831 CORE_ADDR frame_base
;
832 CORE_ADDR local_base
;
834 struct trad_frame_saved_reg
*saved_regs
;
837 static struct spu_unwind_cache
*
838 spu_frame_unwind_cache (struct frame_info
*this_frame
,
839 void **this_prologue_cache
)
841 struct spu_unwind_cache
*info
;
842 struct spu_prologue_data data
;
845 if (*this_prologue_cache
)
846 return *this_prologue_cache
;
848 info
= FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache
);
849 *this_prologue_cache
= info
;
850 info
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
851 info
->frame_base
= 0;
852 info
->local_base
= 0;
854 /* Find the start of the current function, and analyze its prologue. */
855 info
->func
= get_frame_func (this_frame
);
858 /* Fall back to using the current PC as frame ID. */
859 info
->func
= get_frame_pc (this_frame
);
863 spu_analyze_prologue (info
->func
, get_frame_pc (this_frame
), &data
);
866 /* If successful, use prologue analysis data. */
867 if (data
.size
!= -1 && data
.cfa_reg
!= -1)
872 /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */
873 get_frame_register (this_frame
, data
.cfa_reg
, buf
);
874 cfa
= extract_unsigned_integer (buf
, 4) + data
.cfa_offset
;
876 /* Call-saved register slots. */
877 for (i
= 0; i
< SPU_NUM_GPRS
; i
++)
878 if (i
== SPU_LR_REGNUM
879 || (i
>= SPU_SAVED1_REGNUM
&& i
<= SPU_SAVEDN_REGNUM
))
880 if (data
.reg_offset
[i
] != -1)
881 info
->saved_regs
[i
].addr
= cfa
- data
.reg_offset
[i
];
884 info
->frame_base
= cfa
;
885 info
->local_base
= cfa
- data
.size
;
888 /* Otherwise, fall back to reading the backchain link. */
895 /* Get the backchain. */
896 reg
= get_frame_register_unsigned (this_frame
, SPU_SP_REGNUM
);
897 status
= safe_read_memory_integer (reg
, 4, &backchain
);
899 /* A zero backchain terminates the frame chain. Also, sanity
900 check against the local store size limit. */
901 if (status
&& backchain
> 0 && backchain
< SPU_LS_SIZE
)
903 /* Assume the link register is saved into its slot. */
904 if (backchain
+ 16 < SPU_LS_SIZE
)
905 info
->saved_regs
[SPU_LR_REGNUM
].addr
= backchain
+ 16;
908 info
->frame_base
= backchain
;
909 info
->local_base
= reg
;
913 /* If we didn't find a frame, we cannot determine SP / return address. */
914 if (info
->frame_base
== 0)
917 /* The previous SP is equal to the CFA. */
918 trad_frame_set_value (info
->saved_regs
, SPU_SP_REGNUM
, info
->frame_base
);
920 /* Read full contents of the unwound link register in order to
921 be able to determine the return address. */
922 if (trad_frame_addr_p (info
->saved_regs
, SPU_LR_REGNUM
))
923 target_read_memory (info
->saved_regs
[SPU_LR_REGNUM
].addr
, buf
, 16);
925 get_frame_register (this_frame
, SPU_LR_REGNUM
, buf
);
927 /* Normally, the return address is contained in the slot 0 of the
928 link register, and slots 1-3 are zero. For an overlay return,
929 slot 0 contains the address of the overlay manager return stub,
930 slot 1 contains the partition number of the overlay section to
931 be returned to, and slot 2 contains the return address within
932 that section. Return the latter address in that case. */
933 if (extract_unsigned_integer (buf
+ 8, 4) != 0)
934 trad_frame_set_value (info
->saved_regs
, SPU_PC_REGNUM
,
935 extract_unsigned_integer (buf
+ 8, 4));
937 trad_frame_set_value (info
->saved_regs
, SPU_PC_REGNUM
,
938 extract_unsigned_integer (buf
, 4));
944 spu_frame_this_id (struct frame_info
*this_frame
,
945 void **this_prologue_cache
, struct frame_id
*this_id
)
947 struct spu_unwind_cache
*info
=
948 spu_frame_unwind_cache (this_frame
, this_prologue_cache
);
950 if (info
->frame_base
== 0)
953 *this_id
= frame_id_build (info
->frame_base
, info
->func
);
956 static struct value
*
957 spu_frame_prev_register (struct frame_info
*this_frame
,
958 void **this_prologue_cache
, int regnum
)
960 struct spu_unwind_cache
*info
961 = spu_frame_unwind_cache (this_frame
, this_prologue_cache
);
963 /* Special-case the stack pointer. */
964 if (regnum
== SPU_RAW_SP_REGNUM
)
965 regnum
= SPU_SP_REGNUM
;
967 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
970 static const struct frame_unwind spu_frame_unwind
= {
973 spu_frame_prev_register
,
975 default_frame_sniffer
979 spu_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
981 struct spu_unwind_cache
*info
982 = spu_frame_unwind_cache (this_frame
, this_cache
);
983 return info
->local_base
;
986 static const struct frame_base spu_frame_base
= {
988 spu_frame_base_address
,
989 spu_frame_base_address
,
990 spu_frame_base_address
994 spu_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
996 CORE_ADDR pc
= frame_unwind_register_unsigned (next_frame
, SPU_PC_REGNUM
);
997 /* Mask off interrupt enable bit. */
1002 spu_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1004 return frame_unwind_register_unsigned (next_frame
, SPU_SP_REGNUM
);
1008 spu_read_pc (struct regcache
*regcache
)
1011 regcache_cooked_read_unsigned (regcache
, SPU_PC_REGNUM
, &pc
);
1012 /* Mask off interrupt enable bit. */
1017 spu_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1019 /* Keep interrupt enabled state unchanged. */
1021 regcache_cooked_read_unsigned (regcache
, SPU_PC_REGNUM
, &old_pc
);
1022 regcache_cooked_write_unsigned (regcache
, SPU_PC_REGNUM
,
1023 (pc
& -4) | (old_pc
& 3));
1027 /* Function calling convention. */
1030 spu_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1036 spu_scalar_value_p (struct type
*type
)
1038 switch (TYPE_CODE (type
))
1041 case TYPE_CODE_ENUM
:
1042 case TYPE_CODE_RANGE
:
1043 case TYPE_CODE_CHAR
:
1044 case TYPE_CODE_BOOL
:
1047 return TYPE_LENGTH (type
) <= 16;
1055 spu_value_to_regcache (struct regcache
*regcache
, int regnum
,
1056 struct type
*type
, const gdb_byte
*in
)
1058 int len
= TYPE_LENGTH (type
);
1060 if (spu_scalar_value_p (type
))
1062 int preferred_slot
= len
< 4 ? 4 - len
: 0;
1063 regcache_cooked_write_part (regcache
, regnum
, preferred_slot
, len
, in
);
1069 regcache_cooked_write (regcache
, regnum
++, in
);
1075 regcache_cooked_write_part (regcache
, regnum
, 0, len
, in
);
1080 spu_regcache_to_value (struct regcache
*regcache
, int regnum
,
1081 struct type
*type
, gdb_byte
*out
)
1083 int len
= TYPE_LENGTH (type
);
1085 if (spu_scalar_value_p (type
))
1087 int preferred_slot
= len
< 4 ? 4 - len
: 0;
1088 regcache_cooked_read_part (regcache
, regnum
, preferred_slot
, len
, out
);
1094 regcache_cooked_read (regcache
, regnum
++, out
);
1100 regcache_cooked_read_part (regcache
, regnum
, 0, len
, out
);
1105 spu_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1106 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1107 int nargs
, struct value
**args
, CORE_ADDR sp
,
1108 int struct_return
, CORE_ADDR struct_addr
)
1112 int regnum
= SPU_ARG1_REGNUM
;
1116 /* Set the return address. */
1117 memset (buf
, 0, sizeof buf
);
1118 store_unsigned_integer (buf
, 4, bp_addr
);
1119 regcache_cooked_write (regcache
, SPU_LR_REGNUM
, buf
);
1121 /* If STRUCT_RETURN is true, then the struct return address (in
1122 STRUCT_ADDR) will consume the first argument-passing register.
1123 Both adjust the register count and store that value. */
1126 memset (buf
, 0, sizeof buf
);
1127 store_unsigned_integer (buf
, 4, struct_addr
);
1128 regcache_cooked_write (regcache
, regnum
++, buf
);
1131 /* Fill in argument registers. */
1132 for (i
= 0; i
< nargs
; i
++)
1134 struct value
*arg
= args
[i
];
1135 struct type
*type
= check_typedef (value_type (arg
));
1136 const gdb_byte
*contents
= value_contents (arg
);
1137 int len
= TYPE_LENGTH (type
);
1138 int n_regs
= align_up (len
, 16) / 16;
1140 /* If the argument doesn't wholly fit into registers, it and
1141 all subsequent arguments go to the stack. */
1142 if (regnum
+ n_regs
- 1 > SPU_ARGN_REGNUM
)
1148 spu_value_to_regcache (regcache
, regnum
, type
, contents
);
1152 /* Overflow arguments go to the stack. */
1153 if (stack_arg
!= -1)
1157 /* Allocate all required stack size. */
1158 for (i
= stack_arg
; i
< nargs
; i
++)
1160 struct type
*type
= check_typedef (value_type (args
[i
]));
1161 sp
-= align_up (TYPE_LENGTH (type
), 16);
1164 /* Fill in stack arguments. */
1166 for (i
= stack_arg
; i
< nargs
; i
++)
1168 struct value
*arg
= args
[i
];
1169 struct type
*type
= check_typedef (value_type (arg
));
1170 int len
= TYPE_LENGTH (type
);
1173 if (spu_scalar_value_p (type
))
1174 preferred_slot
= len
< 4 ? 4 - len
: 0;
1178 target_write_memory (ap
+ preferred_slot
, value_contents (arg
), len
);
1179 ap
+= align_up (TYPE_LENGTH (type
), 16);
1183 /* Allocate stack frame header. */
1186 /* Store stack back chain. */
1187 regcache_cooked_read (regcache
, SPU_RAW_SP_REGNUM
, buf
);
1188 target_write_memory (sp
, buf
, 16);
1190 /* Finally, update all slots of the SP register. */
1191 sp_delta
= sp
- extract_unsigned_integer (buf
, 4);
1192 for (i
= 0; i
< 4; i
++)
1194 CORE_ADDR sp_slot
= extract_unsigned_integer (buf
+ 4*i
, 4);
1195 store_unsigned_integer (buf
+ 4*i
, 4, sp_slot
+ sp_delta
);
1197 regcache_cooked_write (regcache
, SPU_RAW_SP_REGNUM
, buf
);
1202 static struct frame_id
1203 spu_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1205 CORE_ADDR pc
= get_frame_register_unsigned (this_frame
, SPU_PC_REGNUM
);
1206 CORE_ADDR sp
= get_frame_register_unsigned (this_frame
, SPU_SP_REGNUM
);
1207 return frame_id_build (sp
, pc
& -4);
1210 /* Function return value access. */
1212 static enum return_value_convention
1213 spu_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
1214 struct type
*type
, struct regcache
*regcache
,
1215 gdb_byte
*out
, const gdb_byte
*in
)
1217 enum return_value_convention rvc
;
1219 if (TYPE_LENGTH (type
) <= (SPU_ARGN_REGNUM
- SPU_ARG1_REGNUM
+ 1) * 16)
1220 rvc
= RETURN_VALUE_REGISTER_CONVENTION
;
1222 rvc
= RETURN_VALUE_STRUCT_CONVENTION
;
1228 case RETURN_VALUE_REGISTER_CONVENTION
:
1229 spu_value_to_regcache (regcache
, SPU_ARG1_REGNUM
, type
, in
);
1232 case RETURN_VALUE_STRUCT_CONVENTION
:
1233 error ("Cannot set function return value.");
1241 case RETURN_VALUE_REGISTER_CONVENTION
:
1242 spu_regcache_to_value (regcache
, SPU_ARG1_REGNUM
, type
, out
);
1245 case RETURN_VALUE_STRUCT_CONVENTION
:
1246 error ("Function return value unknown.");
1257 static const gdb_byte
*
1258 spu_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
* pcptr
, int *lenptr
)
1260 static const gdb_byte breakpoint
[] = { 0x00, 0x00, 0x3f, 0xff };
1262 *lenptr
= sizeof breakpoint
;
1267 /* Software single-stepping support. */
1270 spu_software_single_step (struct frame_info
*frame
)
1272 CORE_ADDR pc
, next_pc
;
1277 pc
= get_frame_pc (frame
);
1279 if (target_read_memory (pc
, buf
, 4))
1281 insn
= extract_unsigned_integer (buf
, 4);
1283 /* Next sequential instruction is at PC + 4, except if the current
1284 instruction is a PPE-assisted call, in which case it is at PC + 8.
1285 Wrap around LS limit to be on the safe side. */
1286 if ((insn
& 0xffffff00) == 0x00002100)
1287 next_pc
= (pc
+ 8) & (SPU_LS_SIZE
- 1);
1289 next_pc
= (pc
+ 4) & (SPU_LS_SIZE
- 1);
1291 insert_single_step_breakpoint (next_pc
);
1293 if (is_branch (insn
, &offset
, ®
))
1295 CORE_ADDR target
= offset
;
1297 if (reg
== SPU_PC_REGNUM
)
1301 get_frame_register_bytes (frame
, reg
, 0, 4, buf
);
1302 target
+= extract_unsigned_integer (buf
, 4) & -4;
1305 target
= target
& (SPU_LS_SIZE
- 1);
1306 if (target
!= next_pc
)
1307 insert_single_step_breakpoint (target
);
1313 /* Target overlays for the SPU overlay manager.
1315 See the documentation of simple_overlay_update for how the
1316 interface is supposed to work.
1318 Data structures used by the overlay manager:
1326 } _ovly_table[]; -- one entry per overlay section
1328 struct ovly_buf_table
1331 } _ovly_buf_table[]; -- one entry per overlay buffer
1333 _ovly_table should never change.
1335 Both tables are aligned to a 16-byte boundary, the symbols _ovly_table
1336 and _ovly_buf_table are of type STT_OBJECT and their size set to the size
1337 of the respective array. buf in _ovly_table is an index into _ovly_buf_table.
1339 mapped is an index into _ovly_table. Both the mapped and buf indices start
1340 from one to reference the first entry in their respective tables. */
1342 /* Using the per-objfile private data mechanism, we store for each
1343 objfile an array of "struct spu_overlay_table" structures, one
1344 for each obj_section of the objfile. This structure holds two
1345 fields, MAPPED_PTR and MAPPED_VAL. If MAPPED_PTR is zero, this
1346 is *not* an overlay section. If it is non-zero, it represents
1347 a target address. The overlay section is mapped iff the target
1348 integer at this location equals MAPPED_VAL. */
1350 static const struct objfile_data
*spu_overlay_data
;
1352 struct spu_overlay_table
1354 CORE_ADDR mapped_ptr
;
1355 CORE_ADDR mapped_val
;
1358 /* Retrieve the overlay table for OBJFILE. If not already cached, read
1359 the _ovly_table data structure from the target and initialize the
1360 spu_overlay_table data structure from it. */
1361 static struct spu_overlay_table
*
1362 spu_get_overlay_table (struct objfile
*objfile
)
1364 struct minimal_symbol
*ovly_table_msym
, *ovly_buf_table_msym
;
1365 CORE_ADDR ovly_table_base
, ovly_buf_table_base
;
1366 unsigned ovly_table_size
, ovly_buf_table_size
;
1367 struct spu_overlay_table
*tbl
;
1368 struct obj_section
*osect
;
1372 tbl
= objfile_data (objfile
, spu_overlay_data
);
1376 ovly_table_msym
= lookup_minimal_symbol ("_ovly_table", NULL
, objfile
);
1377 if (!ovly_table_msym
)
1380 ovly_buf_table_msym
= lookup_minimal_symbol ("_ovly_buf_table", NULL
, objfile
);
1381 if (!ovly_buf_table_msym
)
1384 ovly_table_base
= SYMBOL_VALUE_ADDRESS (ovly_table_msym
);
1385 ovly_table_size
= MSYMBOL_SIZE (ovly_table_msym
);
1387 ovly_buf_table_base
= SYMBOL_VALUE_ADDRESS (ovly_buf_table_msym
);
1388 ovly_buf_table_size
= MSYMBOL_SIZE (ovly_buf_table_msym
);
1390 ovly_table
= xmalloc (ovly_table_size
);
1391 read_memory (ovly_table_base
, ovly_table
, ovly_table_size
);
1393 tbl
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
1394 objfile
->sections_end
- objfile
->sections
,
1395 struct spu_overlay_table
);
1397 for (i
= 0; i
< ovly_table_size
/ 16; i
++)
1399 CORE_ADDR vma
= extract_unsigned_integer (ovly_table
+ 16*i
+ 0, 4);
1400 CORE_ADDR size
= extract_unsigned_integer (ovly_table
+ 16*i
+ 4, 4);
1401 CORE_ADDR pos
= extract_unsigned_integer (ovly_table
+ 16*i
+ 8, 4);
1402 CORE_ADDR buf
= extract_unsigned_integer (ovly_table
+ 16*i
+ 12, 4);
1404 if (buf
== 0 || (buf
- 1) * 4 >= ovly_buf_table_size
)
1407 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
1408 if (vma
== bfd_section_vma (objfile
->obfd
, osect
->the_bfd_section
)
1409 && pos
== osect
->the_bfd_section
->filepos
)
1411 int ndx
= osect
- objfile
->sections
;
1412 tbl
[ndx
].mapped_ptr
= ovly_buf_table_base
+ (buf
- 1) * 4;
1413 tbl
[ndx
].mapped_val
= i
+ 1;
1419 set_objfile_data (objfile
, spu_overlay_data
, tbl
);
1423 /* Read _ovly_buf_table entry from the target to dermine whether
1424 OSECT is currently mapped, and update the mapped state. */
1426 spu_overlay_update_osect (struct obj_section
*osect
)
1428 struct spu_overlay_table
*ovly_table
;
1431 ovly_table
= spu_get_overlay_table (osect
->objfile
);
1435 ovly_table
+= osect
- osect
->objfile
->sections
;
1436 if (ovly_table
->mapped_ptr
== 0)
1439 val
= read_memory_unsigned_integer (ovly_table
->mapped_ptr
, 4);
1440 osect
->ovly_mapped
= (val
== ovly_table
->mapped_val
);
1443 /* If OSECT is NULL, then update all sections' mapped state.
1444 If OSECT is non-NULL, then update only OSECT's mapped state. */
1446 spu_overlay_update (struct obj_section
*osect
)
1448 /* Just one section. */
1450 spu_overlay_update_osect (osect
);
1455 struct objfile
*objfile
;
1457 ALL_OBJSECTIONS (objfile
, osect
)
1458 if (section_is_overlay (osect
))
1459 spu_overlay_update_osect (osect
);
1463 /* Whenever a new objfile is loaded, read the target's _ovly_table.
1464 If there is one, go through all sections and make sure for non-
1465 overlay sections LMA equals VMA, while for overlay sections LMA
1466 is larger than local store size. */
1468 spu_overlay_new_objfile (struct objfile
*objfile
)
1470 struct spu_overlay_table
*ovly_table
;
1471 struct obj_section
*osect
;
1473 /* If we've already touched this file, do nothing. */
1474 if (!objfile
|| objfile_data (objfile
, spu_overlay_data
) != NULL
)
1477 /* Consider only SPU objfiles. */
1478 if (bfd_get_arch (objfile
->obfd
) != bfd_arch_spu
)
1481 /* Check if this objfile has overlays. */
1482 ovly_table
= spu_get_overlay_table (objfile
);
1486 /* Now go and fiddle with all the LMAs. */
1487 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
1489 bfd
*obfd
= objfile
->obfd
;
1490 asection
*bsect
= osect
->the_bfd_section
;
1491 int ndx
= osect
- objfile
->sections
;
1493 if (ovly_table
[ndx
].mapped_ptr
== 0)
1494 bfd_section_lma (obfd
, bsect
) = bfd_section_vma (obfd
, bsect
);
1496 bfd_section_lma (obfd
, bsect
) = bsect
->filepos
+ SPU_LS_SIZE
;
1501 /* "info spu" commands. */
1504 info_spu_event_command (char *args
, int from_tty
)
1506 struct frame_info
*frame
= get_selected_frame (NULL
);
1507 ULONGEST event_status
= 0;
1508 ULONGEST event_mask
= 0;
1509 struct cleanup
*chain
;
1515 if (gdbarch_bfd_arch_info (get_frame_arch (frame
))->arch
!= bfd_arch_spu
)
1516 error (_("\"info spu\" is only supported on the SPU architecture."));
1518 id
= get_frame_register_unsigned (frame
, SPU_ID_REGNUM
);
1520 xsnprintf (annex
, sizeof annex
, "%d/event_status", id
);
1521 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1522 buf
, 0, (sizeof (buf
) - 1));
1524 error (_("Could not read event_status."));
1526 event_status
= strtoulst (buf
, NULL
, 16);
1528 xsnprintf (annex
, sizeof annex
, "%d/event_mask", id
);
1529 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1530 buf
, 0, (sizeof (buf
) - 1));
1532 error (_("Could not read event_mask."));
1534 event_mask
= strtoulst (buf
, NULL
, 16);
1536 chain
= make_cleanup_ui_out_tuple_begin_end (uiout
, "SPUInfoEvent");
1538 if (ui_out_is_mi_like_p (uiout
))
1540 ui_out_field_fmt (uiout
, "event_status",
1541 "0x%s", phex_nz (event_status
, 4));
1542 ui_out_field_fmt (uiout
, "event_mask",
1543 "0x%s", phex_nz (event_mask
, 4));
1547 printf_filtered (_("Event Status 0x%s\n"), phex (event_status
, 4));
1548 printf_filtered (_("Event Mask 0x%s\n"), phex (event_mask
, 4));
1551 do_cleanups (chain
);
1555 info_spu_signal_command (char *args
, int from_tty
)
1557 struct frame_info
*frame
= get_selected_frame (NULL
);
1558 ULONGEST signal1
= 0;
1559 ULONGEST signal1_type
= 0;
1560 int signal1_pending
= 0;
1561 ULONGEST signal2
= 0;
1562 ULONGEST signal2_type
= 0;
1563 int signal2_pending
= 0;
1564 struct cleanup
*chain
;
1570 if (gdbarch_bfd_arch_info (get_frame_arch (frame
))->arch
!= bfd_arch_spu
)
1571 error (_("\"info spu\" is only supported on the SPU architecture."));
1573 id
= get_frame_register_unsigned (frame
, SPU_ID_REGNUM
);
1575 xsnprintf (annex
, sizeof annex
, "%d/signal1", id
);
1576 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
, buf
, 0, 4);
1578 error (_("Could not read signal1."));
1581 signal1
= extract_unsigned_integer (buf
, 4);
1582 signal1_pending
= 1;
1585 xsnprintf (annex
, sizeof annex
, "%d/signal1_type", id
);
1586 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1587 buf
, 0, (sizeof (buf
) - 1));
1589 error (_("Could not read signal1_type."));
1591 signal1_type
= strtoulst (buf
, NULL
, 16);
1593 xsnprintf (annex
, sizeof annex
, "%d/signal2", id
);
1594 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
, buf
, 0, 4);
1596 error (_("Could not read signal2."));
1599 signal2
= extract_unsigned_integer (buf
, 4);
1600 signal2_pending
= 1;
1603 xsnprintf (annex
, sizeof annex
, "%d/signal2_type", id
);
1604 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1605 buf
, 0, (sizeof (buf
) - 1));
1607 error (_("Could not read signal2_type."));
1609 signal2_type
= strtoulst (buf
, NULL
, 16);
1611 chain
= make_cleanup_ui_out_tuple_begin_end (uiout
, "SPUInfoSignal");
1613 if (ui_out_is_mi_like_p (uiout
))
1615 ui_out_field_int (uiout
, "signal1_pending", signal1_pending
);
1616 ui_out_field_fmt (uiout
, "signal1", "0x%s", phex_nz (signal1
, 4));
1617 ui_out_field_int (uiout
, "signal1_type", signal1_type
);
1618 ui_out_field_int (uiout
, "signal2_pending", signal2_pending
);
1619 ui_out_field_fmt (uiout
, "signal2", "0x%s", phex_nz (signal2
, 4));
1620 ui_out_field_int (uiout
, "signal2_type", signal2_type
);
1624 if (signal1_pending
)
1625 printf_filtered (_("Signal 1 control word 0x%s "), phex (signal1
, 4));
1627 printf_filtered (_("Signal 1 not pending "));
1630 printf_filtered (_("(Type Or)\n"));
1632 printf_filtered (_("(Type Overwrite)\n"));
1634 if (signal2_pending
)
1635 printf_filtered (_("Signal 2 control word 0x%s "), phex (signal2
, 4));
1637 printf_filtered (_("Signal 2 not pending "));
1640 printf_filtered (_("(Type Or)\n"));
1642 printf_filtered (_("(Type Overwrite)\n"));
1645 do_cleanups (chain
);
1649 info_spu_mailbox_list (gdb_byte
*buf
, int nr
,
1650 const char *field
, const char *msg
)
1652 struct cleanup
*chain
;
1658 chain
= make_cleanup_ui_out_table_begin_end (uiout
, 1, nr
, "mbox");
1660 ui_out_table_header (uiout
, 32, ui_left
, field
, msg
);
1661 ui_out_table_body (uiout
);
1663 for (i
= 0; i
< nr
; i
++)
1665 struct cleanup
*val_chain
;
1667 val_chain
= make_cleanup_ui_out_tuple_begin_end (uiout
, "mbox");
1668 val
= extract_unsigned_integer (buf
+ 4*i
, 4);
1669 ui_out_field_fmt (uiout
, field
, "0x%s", phex (val
, 4));
1670 do_cleanups (val_chain
);
1672 if (!ui_out_is_mi_like_p (uiout
))
1673 printf_filtered ("\n");
1676 do_cleanups (chain
);
1680 info_spu_mailbox_command (char *args
, int from_tty
)
1682 struct frame_info
*frame
= get_selected_frame (NULL
);
1683 struct cleanup
*chain
;
1689 if (gdbarch_bfd_arch_info (get_frame_arch (frame
))->arch
!= bfd_arch_spu
)
1690 error (_("\"info spu\" is only supported on the SPU architecture."));
1692 id
= get_frame_register_unsigned (frame
, SPU_ID_REGNUM
);
1694 chain
= make_cleanup_ui_out_tuple_begin_end (uiout
, "SPUInfoMailbox");
1696 xsnprintf (annex
, sizeof annex
, "%d/mbox_info", id
);
1697 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1698 buf
, 0, sizeof buf
);
1700 error (_("Could not read mbox_info."));
1702 info_spu_mailbox_list (buf
, len
/ 4, "mbox", "SPU Outbound Mailbox");
1704 xsnprintf (annex
, sizeof annex
, "%d/ibox_info", id
);
1705 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1706 buf
, 0, sizeof buf
);
1708 error (_("Could not read ibox_info."));
1710 info_spu_mailbox_list (buf
, len
/ 4, "ibox", "SPU Outbound Interrupt Mailbox");
1712 xsnprintf (annex
, sizeof annex
, "%d/wbox_info", id
);
1713 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1714 buf
, 0, sizeof buf
);
1716 error (_("Could not read wbox_info."));
1718 info_spu_mailbox_list (buf
, len
/ 4, "wbox", "SPU Inbound Mailbox");
1720 do_cleanups (chain
);
1724 spu_mfc_get_bitfield (ULONGEST word
, int first
, int last
)
1726 ULONGEST mask
= ~(~(ULONGEST
)0 << (last
- first
+ 1));
1727 return (word
>> (63 - last
)) & mask
;
1731 info_spu_dma_cmdlist (gdb_byte
*buf
, int nr
)
1733 static char *spu_mfc_opcode
[256] =
1735 /* 00 */ NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1736 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1737 /* 10 */ NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1738 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1739 /* 20 */ "put", "putb", "putf", NULL
, "putl", "putlb", "putlf", NULL
,
1740 "puts", "putbs", "putfs", NULL
, NULL
, NULL
, NULL
, NULL
,
1741 /* 30 */ "putr", "putrb", "putrf", NULL
, "putrl", "putrlb", "putrlf", NULL
,
1742 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1743 /* 40 */ "get", "getb", "getf", NULL
, "getl", "getlb", "getlf", NULL
,
1744 "gets", "getbs", "getfs", NULL
, NULL
, NULL
, NULL
, NULL
,
1745 /* 50 */ NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1746 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1747 /* 60 */ NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1748 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1749 /* 70 */ NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1750 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1751 /* 80 */ "sdcrt", "sdcrtst", NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1752 NULL
, "sdcrz", NULL
, NULL
, NULL
, "sdcrst", NULL
, "sdcrf",
1753 /* 90 */ NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1754 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1755 /* a0 */ "sndsig", "sndsigb", "sndsigf", NULL
, NULL
, NULL
, NULL
, NULL
,
1756 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1757 /* b0 */ "putlluc", NULL
, NULL
, NULL
, "putllc", NULL
, NULL
, NULL
,
1758 "putqlluc", NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1759 /* c0 */ "barrier", NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1760 "mfceieio", NULL
, NULL
, NULL
, "mfcsync", NULL
, NULL
, NULL
,
1761 /* d0 */ "getllar", NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1762 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1763 /* e0 */ NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1764 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1765 /* f0 */ NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1766 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1769 int *seq
= alloca (nr
* sizeof (int));
1771 struct cleanup
*chain
;
1775 /* Determine sequence in which to display (valid) entries. */
1776 for (i
= 0; i
< nr
; i
++)
1778 /* Search for the first valid entry all of whose
1779 dependencies are met. */
1780 for (j
= 0; j
< nr
; j
++)
1782 ULONGEST mfc_cq_dw3
;
1783 ULONGEST dependencies
;
1785 if (done
& (1 << (nr
- 1 - j
)))
1788 mfc_cq_dw3
= extract_unsigned_integer (buf
+ 32*j
+ 24, 8);
1789 if (!spu_mfc_get_bitfield (mfc_cq_dw3
, 16, 16))
1792 dependencies
= spu_mfc_get_bitfield (mfc_cq_dw3
, 0, nr
- 1);
1793 if ((dependencies
& done
) != dependencies
)
1797 done
|= 1 << (nr
- 1 - j
);
1808 chain
= make_cleanup_ui_out_table_begin_end (uiout
, 10, nr
, "dma_cmd");
1810 ui_out_table_header (uiout
, 7, ui_left
, "opcode", "Opcode");
1811 ui_out_table_header (uiout
, 3, ui_left
, "tag", "Tag");
1812 ui_out_table_header (uiout
, 3, ui_left
, "tid", "TId");
1813 ui_out_table_header (uiout
, 3, ui_left
, "rid", "RId");
1814 ui_out_table_header (uiout
, 18, ui_left
, "ea", "EA");
1815 ui_out_table_header (uiout
, 7, ui_left
, "lsa", "LSA");
1816 ui_out_table_header (uiout
, 7, ui_left
, "size", "Size");
1817 ui_out_table_header (uiout
, 7, ui_left
, "lstaddr", "LstAddr");
1818 ui_out_table_header (uiout
, 7, ui_left
, "lstsize", "LstSize");
1819 ui_out_table_header (uiout
, 1, ui_left
, "error_p", "E");
1821 ui_out_table_body (uiout
);
1823 for (i
= 0; i
< nr
; i
++)
1825 struct cleanup
*cmd_chain
;
1826 ULONGEST mfc_cq_dw0
;
1827 ULONGEST mfc_cq_dw1
;
1828 ULONGEST mfc_cq_dw2
;
1829 int mfc_cmd_opcode
, mfc_cmd_tag
, rclass_id
, tclass_id
;
1830 int lsa
, size
, list_lsa
, list_size
, mfc_lsa
, mfc_size
;
1832 int list_valid_p
, noop_valid_p
, qw_valid_p
, ea_valid_p
, cmd_error_p
;
1834 /* Decode contents of MFC Command Queue Context Save/Restore Registers.
1835 See "Cell Broadband Engine Registers V1.3", section 3.3.2.1. */
1837 mfc_cq_dw0
= extract_unsigned_integer (buf
+ 32*seq
[i
], 8);
1838 mfc_cq_dw1
= extract_unsigned_integer (buf
+ 32*seq
[i
] + 8, 8);
1839 mfc_cq_dw2
= extract_unsigned_integer (buf
+ 32*seq
[i
] + 16, 8);
1841 list_lsa
= spu_mfc_get_bitfield (mfc_cq_dw0
, 0, 14);
1842 list_size
= spu_mfc_get_bitfield (mfc_cq_dw0
, 15, 26);
1843 mfc_cmd_opcode
= spu_mfc_get_bitfield (mfc_cq_dw0
, 27, 34);
1844 mfc_cmd_tag
= spu_mfc_get_bitfield (mfc_cq_dw0
, 35, 39);
1845 list_valid_p
= spu_mfc_get_bitfield (mfc_cq_dw0
, 40, 40);
1846 rclass_id
= spu_mfc_get_bitfield (mfc_cq_dw0
, 41, 43);
1847 tclass_id
= spu_mfc_get_bitfield (mfc_cq_dw0
, 44, 46);
1849 mfc_ea
= spu_mfc_get_bitfield (mfc_cq_dw1
, 0, 51) << 12
1850 | spu_mfc_get_bitfield (mfc_cq_dw2
, 25, 36);
1852 mfc_lsa
= spu_mfc_get_bitfield (mfc_cq_dw2
, 0, 13);
1853 mfc_size
= spu_mfc_get_bitfield (mfc_cq_dw2
, 14, 24);
1854 noop_valid_p
= spu_mfc_get_bitfield (mfc_cq_dw2
, 37, 37);
1855 qw_valid_p
= spu_mfc_get_bitfield (mfc_cq_dw2
, 38, 38);
1856 ea_valid_p
= spu_mfc_get_bitfield (mfc_cq_dw2
, 39, 39);
1857 cmd_error_p
= spu_mfc_get_bitfield (mfc_cq_dw2
, 40, 40);
1859 cmd_chain
= make_cleanup_ui_out_tuple_begin_end (uiout
, "cmd");
1861 if (spu_mfc_opcode
[mfc_cmd_opcode
])
1862 ui_out_field_string (uiout
, "opcode", spu_mfc_opcode
[mfc_cmd_opcode
]);
1864 ui_out_field_int (uiout
, "opcode", mfc_cmd_opcode
);
1866 ui_out_field_int (uiout
, "tag", mfc_cmd_tag
);
1867 ui_out_field_int (uiout
, "tid", tclass_id
);
1868 ui_out_field_int (uiout
, "rid", rclass_id
);
1871 ui_out_field_fmt (uiout
, "ea", "0x%s", phex (mfc_ea
, 8));
1873 ui_out_field_skip (uiout
, "ea");
1875 ui_out_field_fmt (uiout
, "lsa", "0x%05x", mfc_lsa
<< 4);
1877 ui_out_field_fmt (uiout
, "size", "0x%05x", mfc_size
<< 4);
1879 ui_out_field_fmt (uiout
, "size", "0x%05x", mfc_size
);
1883 ui_out_field_fmt (uiout
, "lstaddr", "0x%05x", list_lsa
<< 3);
1884 ui_out_field_fmt (uiout
, "lstsize", "0x%05x", list_size
<< 3);
1888 ui_out_field_skip (uiout
, "lstaddr");
1889 ui_out_field_skip (uiout
, "lstsize");
1893 ui_out_field_string (uiout
, "error_p", "*");
1895 ui_out_field_skip (uiout
, "error_p");
1897 do_cleanups (cmd_chain
);
1899 if (!ui_out_is_mi_like_p (uiout
))
1900 printf_filtered ("\n");
1903 do_cleanups (chain
);
1907 info_spu_dma_command (char *args
, int from_tty
)
1909 struct frame_info
*frame
= get_selected_frame (NULL
);
1910 ULONGEST dma_info_type
;
1911 ULONGEST dma_info_mask
;
1912 ULONGEST dma_info_status
;
1913 ULONGEST dma_info_stall_and_notify
;
1914 ULONGEST dma_info_atomic_command_status
;
1915 struct cleanup
*chain
;
1921 if (gdbarch_bfd_arch_info (get_frame_arch (frame
))->arch
!= bfd_arch_spu
)
1922 error (_("\"info spu\" is only supported on the SPU architecture."));
1924 id
= get_frame_register_unsigned (frame
, SPU_ID_REGNUM
);
1926 xsnprintf (annex
, sizeof annex
, "%d/dma_info", id
);
1927 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1928 buf
, 0, 40 + 16 * 32);
1930 error (_("Could not read dma_info."));
1932 dma_info_type
= extract_unsigned_integer (buf
, 8);
1933 dma_info_mask
= extract_unsigned_integer (buf
+ 8, 8);
1934 dma_info_status
= extract_unsigned_integer (buf
+ 16, 8);
1935 dma_info_stall_and_notify
= extract_unsigned_integer (buf
+ 24, 8);
1936 dma_info_atomic_command_status
= extract_unsigned_integer (buf
+ 32, 8);
1938 chain
= make_cleanup_ui_out_tuple_begin_end (uiout
, "SPUInfoDMA");
1940 if (ui_out_is_mi_like_p (uiout
))
1942 ui_out_field_fmt (uiout
, "dma_info_type", "0x%s",
1943 phex_nz (dma_info_type
, 4));
1944 ui_out_field_fmt (uiout
, "dma_info_mask", "0x%s",
1945 phex_nz (dma_info_mask
, 4));
1946 ui_out_field_fmt (uiout
, "dma_info_status", "0x%s",
1947 phex_nz (dma_info_status
, 4));
1948 ui_out_field_fmt (uiout
, "dma_info_stall_and_notify", "0x%s",
1949 phex_nz (dma_info_stall_and_notify
, 4));
1950 ui_out_field_fmt (uiout
, "dma_info_atomic_command_status", "0x%s",
1951 phex_nz (dma_info_atomic_command_status
, 4));
1955 const char *query_msg
= _("no query pending");
1957 if (dma_info_type
& 4)
1958 switch (dma_info_type
& 3)
1960 case 1: query_msg
= _("'any' query pending"); break;
1961 case 2: query_msg
= _("'all' query pending"); break;
1962 default: query_msg
= _("undefined query type"); break;
1965 printf_filtered (_("Tag-Group Status 0x%s\n"),
1966 phex (dma_info_status
, 4));
1967 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
1968 phex (dma_info_mask
, 4), query_msg
);
1969 printf_filtered (_("Stall-and-Notify 0x%s\n"),
1970 phex (dma_info_stall_and_notify
, 4));
1971 printf_filtered (_("Atomic Cmd Status 0x%s\n"),
1972 phex (dma_info_atomic_command_status
, 4));
1973 printf_filtered ("\n");
1976 info_spu_dma_cmdlist (buf
+ 40, 16);
1977 do_cleanups (chain
);
1981 info_spu_proxydma_command (char *args
, int from_tty
)
1983 struct frame_info
*frame
= get_selected_frame (NULL
);
1984 ULONGEST dma_info_type
;
1985 ULONGEST dma_info_mask
;
1986 ULONGEST dma_info_status
;
1987 struct cleanup
*chain
;
1993 if (gdbarch_bfd_arch_info (get_frame_arch (frame
))->arch
!= bfd_arch_spu
)
1994 error (_("\"info spu\" is only supported on the SPU architecture."));
1996 id
= get_frame_register_unsigned (frame
, SPU_ID_REGNUM
);
1998 xsnprintf (annex
, sizeof annex
, "%d/proxydma_info", id
);
1999 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
2000 buf
, 0, 24 + 8 * 32);
2002 error (_("Could not read proxydma_info."));
2004 dma_info_type
= extract_unsigned_integer (buf
, 8);
2005 dma_info_mask
= extract_unsigned_integer (buf
+ 8, 8);
2006 dma_info_status
= extract_unsigned_integer (buf
+ 16, 8);
2008 chain
= make_cleanup_ui_out_tuple_begin_end (uiout
, "SPUInfoProxyDMA");
2010 if (ui_out_is_mi_like_p (uiout
))
2012 ui_out_field_fmt (uiout
, "proxydma_info_type", "0x%s",
2013 phex_nz (dma_info_type
, 4));
2014 ui_out_field_fmt (uiout
, "proxydma_info_mask", "0x%s",
2015 phex_nz (dma_info_mask
, 4));
2016 ui_out_field_fmt (uiout
, "proxydma_info_status", "0x%s",
2017 phex_nz (dma_info_status
, 4));
2021 const char *query_msg
;
2023 switch (dma_info_type
& 3)
2025 case 0: query_msg
= _("no query pending"); break;
2026 case 1: query_msg
= _("'any' query pending"); break;
2027 case 2: query_msg
= _("'all' query pending"); break;
2028 default: query_msg
= _("undefined query type"); break;
2031 printf_filtered (_("Tag-Group Status 0x%s\n"),
2032 phex (dma_info_status
, 4));
2033 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
2034 phex (dma_info_mask
, 4), query_msg
);
2035 printf_filtered ("\n");
2038 info_spu_dma_cmdlist (buf
+ 24, 8);
2039 do_cleanups (chain
);
2043 info_spu_command (char *args
, int from_tty
)
2045 printf_unfiltered (_("\"info spu\" must be followed by the name of an SPU facility.\n"));
2046 help_list (infospucmdlist
, "info spu ", -1, gdb_stdout
);
2050 /* Set up gdbarch struct. */
2052 static struct gdbarch
*
2053 spu_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2055 struct gdbarch
*gdbarch
;
2056 struct gdbarch_tdep
*tdep
;
2058 /* Find a candidate among the list of pre-declared architectures. */
2059 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2061 return arches
->gdbarch
;
2064 if (info
.bfd_arch_info
->mach
!= bfd_mach_spu
)
2067 /* Yes, create a new architecture. */
2068 tdep
= XCALLOC (1, struct gdbarch_tdep
);
2069 gdbarch
= gdbarch_alloc (&info
, tdep
);
2072 set_gdbarch_print_insn (gdbarch
, print_insn_spu
);
2075 set_gdbarch_num_regs (gdbarch
, SPU_NUM_REGS
);
2076 set_gdbarch_num_pseudo_regs (gdbarch
, SPU_NUM_PSEUDO_REGS
);
2077 set_gdbarch_sp_regnum (gdbarch
, SPU_SP_REGNUM
);
2078 set_gdbarch_pc_regnum (gdbarch
, SPU_PC_REGNUM
);
2079 set_gdbarch_read_pc (gdbarch
, spu_read_pc
);
2080 set_gdbarch_write_pc (gdbarch
, spu_write_pc
);
2081 set_gdbarch_register_name (gdbarch
, spu_register_name
);
2082 set_gdbarch_register_type (gdbarch
, spu_register_type
);
2083 set_gdbarch_pseudo_register_read (gdbarch
, spu_pseudo_register_read
);
2084 set_gdbarch_pseudo_register_write (gdbarch
, spu_pseudo_register_write
);
2085 set_gdbarch_value_from_register (gdbarch
, spu_value_from_register
);
2086 set_gdbarch_register_reggroup_p (gdbarch
, spu_register_reggroup_p
);
2089 set_gdbarch_char_signed (gdbarch
, 0);
2090 set_gdbarch_ptr_bit (gdbarch
, 32);
2091 set_gdbarch_addr_bit (gdbarch
, 32);
2092 set_gdbarch_short_bit (gdbarch
, 16);
2093 set_gdbarch_int_bit (gdbarch
, 32);
2094 set_gdbarch_long_bit (gdbarch
, 32);
2095 set_gdbarch_long_long_bit (gdbarch
, 64);
2096 set_gdbarch_float_bit (gdbarch
, 32);
2097 set_gdbarch_double_bit (gdbarch
, 64);
2098 set_gdbarch_long_double_bit (gdbarch
, 64);
2099 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
2100 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
2101 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
2103 /* Address conversion. */
2104 set_gdbarch_pointer_to_address (gdbarch
, spu_pointer_to_address
);
2105 set_gdbarch_integer_to_address (gdbarch
, spu_integer_to_address
);
2107 /* Inferior function calls. */
2108 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
2109 set_gdbarch_frame_align (gdbarch
, spu_frame_align
);
2110 set_gdbarch_frame_red_zone_size (gdbarch
, 2000);
2111 set_gdbarch_push_dummy_call (gdbarch
, spu_push_dummy_call
);
2112 set_gdbarch_dummy_id (gdbarch
, spu_dummy_id
);
2113 set_gdbarch_return_value (gdbarch
, spu_return_value
);
2115 /* Frame handling. */
2116 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2117 frame_unwind_append_unwinder (gdbarch
, &spu_frame_unwind
);
2118 frame_base_set_default (gdbarch
, &spu_frame_base
);
2119 set_gdbarch_unwind_pc (gdbarch
, spu_unwind_pc
);
2120 set_gdbarch_unwind_sp (gdbarch
, spu_unwind_sp
);
2121 set_gdbarch_virtual_frame_pointer (gdbarch
, spu_virtual_frame_pointer
);
2122 set_gdbarch_frame_args_skip (gdbarch
, 0);
2123 set_gdbarch_skip_prologue (gdbarch
, spu_skip_prologue
);
2124 set_gdbarch_in_function_epilogue_p (gdbarch
, spu_in_function_epilogue_p
);
2127 set_gdbarch_decr_pc_after_break (gdbarch
, 4);
2128 set_gdbarch_breakpoint_from_pc (gdbarch
, spu_breakpoint_from_pc
);
2129 set_gdbarch_cannot_step_breakpoint (gdbarch
, 1);
2130 set_gdbarch_software_single_step (gdbarch
, spu_software_single_step
);
2133 set_gdbarch_overlay_update (gdbarch
, spu_overlay_update
);
2139 _initialize_spu_tdep (void)
2141 register_gdbarch_init (bfd_arch_spu
, spu_gdbarch_init
);
2143 /* Add ourselves to objfile event chain. */
2144 observer_attach_new_objfile (spu_overlay_new_objfile
);
2145 spu_overlay_data
= register_objfile_data ();
2147 /* Add root prefix command for all "info spu" commands. */
2148 add_prefix_cmd ("spu", class_info
, info_spu_command
,
2149 _("Various SPU specific commands."),
2150 &infospucmdlist
, "info spu ", 0, &infolist
);
2152 /* Add various "info spu" commands. */
2153 add_cmd ("event", class_info
, info_spu_event_command
,
2154 _("Display SPU event facility status.\n"),
2156 add_cmd ("signal", class_info
, info_spu_signal_command
,
2157 _("Display SPU signal notification facility status.\n"),
2159 add_cmd ("mailbox", class_info
, info_spu_mailbox_command
,
2160 _("Display SPU mailbox facility status.\n"),
2162 add_cmd ("dma", class_info
, info_spu_dma_command
,
2163 _("Display MFC DMA status.\n"),
2165 add_cmd ("proxydma", class_info
, info_spu_proxydma_command
,
2166 _("Display MFC Proxy-DMA status.\n"),