1 /* SPU target-dependent code for GDB, the GNU debugger.
2 Copyright (C) 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Ulrich Weigand <uweigand@de.ibm.com>.
5 Based on a port by Sid Manning <sid@us.ibm.com>.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "arch-utils.h"
27 #include "gdb_string.h"
28 #include "gdb_assert.h"
30 #include "frame-unwind.h"
31 #include "frame-base.h"
32 #include "trad-frame.h"
41 #include "reggroups.h"
42 #include "floatformat.h"
48 /* The tdep structure. */
51 /* SPU-specific vector type. */
52 struct type
*spu_builtin_type_vec128
;
56 /* SPU-specific vector type. */
58 spu_builtin_type_vec128 (struct gdbarch
*gdbarch
)
60 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
62 if (!tdep
->spu_builtin_type_vec128
)
66 t
= init_composite_type ("__spu_builtin_type_vec128", TYPE_CODE_UNION
);
67 append_composite_type_field (t
, "uint128", builtin_type_int128
);
68 append_composite_type_field (t
, "v2_int64",
69 init_vector_type (builtin_type_int64
, 2));
70 append_composite_type_field (t
, "v4_int32",
71 init_vector_type (builtin_type_int32
, 4));
72 append_composite_type_field (t
, "v8_int16",
73 init_vector_type (builtin_type_int16
, 8));
74 append_composite_type_field (t
, "v16_int8",
75 init_vector_type (builtin_type_int8
, 16));
76 append_composite_type_field (t
, "v2_double",
77 init_vector_type (builtin_type_double
, 2));
78 append_composite_type_field (t
, "v4_float",
79 init_vector_type (builtin_type_float
, 4));
81 TYPE_FLAGS (t
) |= TYPE_FLAG_VECTOR
;
82 TYPE_NAME (t
) = "spu_builtin_type_vec128";
84 tdep
->spu_builtin_type_vec128
= t
;
87 return tdep
->spu_builtin_type_vec128
;
91 /* The list of available "info spu " commands. */
92 static struct cmd_list_element
*infospucmdlist
= NULL
;
97 spu_register_name (int reg_nr
)
99 static char *register_names
[] =
101 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
102 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
103 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
104 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
105 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
106 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
107 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
108 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
109 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
110 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
111 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
112 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
113 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
114 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
115 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
116 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
117 "id", "pc", "sp", "fpscr", "srr0", "lslr", "decr", "decr_status"
122 if (reg_nr
>= sizeof register_names
/ sizeof *register_names
)
125 return register_names
[reg_nr
];
129 spu_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
131 if (reg_nr
< SPU_NUM_GPRS
)
132 return spu_builtin_type_vec128 (gdbarch
);
137 return builtin_type_uint32
;
140 return builtin_type_void_func_ptr
;
143 return builtin_type_void_data_ptr
;
145 case SPU_FPSCR_REGNUM
:
146 return builtin_type_uint128
;
148 case SPU_SRR0_REGNUM
:
149 return builtin_type_uint32
;
151 case SPU_LSLR_REGNUM
:
152 return builtin_type_uint32
;
154 case SPU_DECR_REGNUM
:
155 return builtin_type_uint32
;
157 case SPU_DECR_STATUS_REGNUM
:
158 return builtin_type_uint32
;
161 internal_error (__FILE__
, __LINE__
, "invalid regnum");
165 /* Pseudo registers for preferred slots - stack pointer. */
168 spu_pseudo_register_read_spu (struct regcache
*regcache
, const char *regname
,
175 regcache_raw_read_unsigned (regcache
, SPU_ID_REGNUM
, &id
);
176 xsnprintf (annex
, sizeof annex
, "%d/%s", (int) id
, regname
);
177 memset (reg
, 0, sizeof reg
);
178 target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
181 store_unsigned_integer (buf
, 4, strtoulst (reg
, NULL
, 16));
185 spu_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
186 int regnum
, gdb_byte
*buf
)
195 regcache_raw_read (regcache
, SPU_RAW_SP_REGNUM
, reg
);
196 memcpy (buf
, reg
, 4);
199 case SPU_FPSCR_REGNUM
:
200 regcache_raw_read_unsigned (regcache
, SPU_ID_REGNUM
, &id
);
201 xsnprintf (annex
, sizeof annex
, "%d/fpcr", (int) id
);
202 target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
, buf
, 0, 16);
205 case SPU_SRR0_REGNUM
:
206 spu_pseudo_register_read_spu (regcache
, "srr0", buf
);
209 case SPU_LSLR_REGNUM
:
210 spu_pseudo_register_read_spu (regcache
, "lslr", buf
);
213 case SPU_DECR_REGNUM
:
214 spu_pseudo_register_read_spu (regcache
, "decr", buf
);
217 case SPU_DECR_STATUS_REGNUM
:
218 spu_pseudo_register_read_spu (regcache
, "decr_status", buf
);
222 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
227 spu_pseudo_register_write_spu (struct regcache
*regcache
, const char *regname
,
234 regcache_raw_read_unsigned (regcache
, SPU_ID_REGNUM
, &id
);
235 xsnprintf (annex
, sizeof annex
, "%d/%s", (int) id
, regname
);
236 xsnprintf (reg
, sizeof reg
, "0x%s",
237 phex_nz (extract_unsigned_integer (buf
, 4), 4));
238 target_write (¤t_target
, TARGET_OBJECT_SPU
, annex
,
239 reg
, 0, strlen (reg
));
243 spu_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
244 int regnum
, const gdb_byte
*buf
)
253 regcache_raw_read (regcache
, SPU_RAW_SP_REGNUM
, reg
);
254 memcpy (reg
, buf
, 4);
255 regcache_raw_write (regcache
, SPU_RAW_SP_REGNUM
, reg
);
258 case SPU_FPSCR_REGNUM
:
259 regcache_raw_read_unsigned (regcache
, SPU_ID_REGNUM
, &id
);
260 xsnprintf (annex
, sizeof annex
, "%d/fpcr", (int) id
);
261 target_write (¤t_target
, TARGET_OBJECT_SPU
, annex
, buf
, 0, 16);
264 case SPU_SRR0_REGNUM
:
265 spu_pseudo_register_write_spu (regcache
, "srr0", buf
);
268 case SPU_LSLR_REGNUM
:
269 spu_pseudo_register_write_spu (regcache
, "lslr", buf
);
272 case SPU_DECR_REGNUM
:
273 spu_pseudo_register_write_spu (regcache
, "decr", buf
);
276 case SPU_DECR_STATUS_REGNUM
:
277 spu_pseudo_register_write_spu (regcache
, "decr_status", buf
);
281 internal_error (__FILE__
, __LINE__
, _("invalid regnum"));
285 /* Value conversion -- access scalar values at the preferred slot. */
287 static struct value
*
288 spu_value_from_register (struct type
*type
, int regnum
,
289 struct frame_info
*frame
)
291 struct value
*value
= default_value_from_register (type
, regnum
, frame
);
292 int len
= TYPE_LENGTH (type
);
294 if (regnum
< SPU_NUM_GPRS
&& len
< 16)
296 int preferred_slot
= len
< 4 ? 4 - len
: 0;
297 set_value_offset (value
, preferred_slot
);
303 /* Register groups. */
306 spu_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
307 struct reggroup
*group
)
309 /* Registers displayed via 'info regs'. */
310 if (group
== general_reggroup
)
313 /* Registers displayed via 'info float'. */
314 if (group
== float_reggroup
)
317 /* Registers that need to be saved/restored in order to
318 push or pop frames. */
319 if (group
== save_reggroup
|| group
== restore_reggroup
)
322 return default_register_reggroup_p (gdbarch
, regnum
, group
);
326 /* Decoding SPU instructions. */
363 is_rr (unsigned int insn
, int op
, int *rt
, int *ra
, int *rb
)
365 if ((insn
>> 21) == op
)
368 *ra
= (insn
>> 7) & 127;
369 *rb
= (insn
>> 14) & 127;
377 is_rrr (unsigned int insn
, int op
, int *rt
, int *ra
, int *rb
, int *rc
)
379 if ((insn
>> 28) == op
)
381 *rt
= (insn
>> 21) & 127;
382 *ra
= (insn
>> 7) & 127;
383 *rb
= (insn
>> 14) & 127;
392 is_ri7 (unsigned int insn
, int op
, int *rt
, int *ra
, int *i7
)
394 if ((insn
>> 21) == op
)
397 *ra
= (insn
>> 7) & 127;
398 *i7
= (((insn
>> 14) & 127) ^ 0x40) - 0x40;
406 is_ri10 (unsigned int insn
, int op
, int *rt
, int *ra
, int *i10
)
408 if ((insn
>> 24) == op
)
411 *ra
= (insn
>> 7) & 127;
412 *i10
= (((insn
>> 14) & 0x3ff) ^ 0x200) - 0x200;
420 is_ri16 (unsigned int insn
, int op
, int *rt
, int *i16
)
422 if ((insn
>> 23) == op
)
425 *i16
= (((insn
>> 7) & 0xffff) ^ 0x8000) - 0x8000;
433 is_ri18 (unsigned int insn
, int op
, int *rt
, int *i18
)
435 if ((insn
>> 25) == op
)
438 *i18
= (((insn
>> 7) & 0x3ffff) ^ 0x20000) - 0x20000;
446 is_branch (unsigned int insn
, int *offset
, int *reg
)
450 if (is_ri16 (insn
, op_br
, &rt
, &i16
)
451 || is_ri16 (insn
, op_brsl
, &rt
, &i16
)
452 || is_ri16 (insn
, op_brnz
, &rt
, &i16
)
453 || is_ri16 (insn
, op_brz
, &rt
, &i16
)
454 || is_ri16 (insn
, op_brhnz
, &rt
, &i16
)
455 || is_ri16 (insn
, op_brhz
, &rt
, &i16
))
457 *reg
= SPU_PC_REGNUM
;
462 if (is_ri16 (insn
, op_bra
, &rt
, &i16
)
463 || is_ri16 (insn
, op_brasl
, &rt
, &i16
))
470 if (is_ri7 (insn
, op_bi
, &rt
, reg
, &i7
)
471 || is_ri7 (insn
, op_bisl
, &rt
, reg
, &i7
)
472 || is_ri7 (insn
, op_biz
, &rt
, reg
, &i7
)
473 || is_ri7 (insn
, op_binz
, &rt
, reg
, &i7
)
474 || is_ri7 (insn
, op_bihz
, &rt
, reg
, &i7
)
475 || is_ri7 (insn
, op_bihnz
, &rt
, reg
, &i7
))
485 /* Prolog parsing. */
487 struct spu_prologue_data
489 /* Stack frame size. -1 if analysis was unsuccessful. */
492 /* How to find the CFA. The CFA is equal to SP at function entry. */
496 /* Offset relative to CFA where a register is saved. -1 if invalid. */
497 int reg_offset
[SPU_NUM_GPRS
];
501 spu_analyze_prologue (CORE_ADDR start_pc
, CORE_ADDR end_pc
,
502 struct spu_prologue_data
*data
)
507 int reg_immed
[SPU_NUM_GPRS
];
509 CORE_ADDR prolog_pc
= start_pc
;
514 /* Initialize DATA to default values. */
517 data
->cfa_reg
= SPU_RAW_SP_REGNUM
;
518 data
->cfa_offset
= 0;
520 for (i
= 0; i
< SPU_NUM_GPRS
; i
++)
521 data
->reg_offset
[i
] = -1;
523 /* Set up REG_IMMED array. This is non-zero for a register if we know its
524 preferred slot currently holds this immediate value. */
525 for (i
= 0; i
< SPU_NUM_GPRS
; i
++)
528 /* Scan instructions until the first branch.
530 The following instructions are important prolog components:
532 - The first instruction to set up the stack pointer.
533 - The first instruction to set up the frame pointer.
534 - The first instruction to save the link register.
536 We return the instruction after the latest of these three,
537 or the incoming PC if none is found. The first instruction
538 to set up the stack pointer also defines the frame size.
540 Note that instructions saving incoming arguments to their stack
541 slots are not counted as important, because they are hard to
542 identify with certainty. This should not matter much, because
543 arguments are relevant only in code compiled with debug data,
544 and in such code the GDB core will advance until the first source
545 line anyway, using SAL data.
547 For purposes of stack unwinding, we analyze the following types
548 of instructions in addition:
550 - Any instruction adding to the current frame pointer.
551 - Any instruction loading an immediate constant into a register.
552 - Any instruction storing a register onto the stack.
554 These are used to compute the CFA and REG_OFFSET output. */
556 for (pc
= start_pc
; pc
< end_pc
; pc
+= 4)
559 int rt
, ra
, rb
, rc
, immed
;
561 if (target_read_memory (pc
, buf
, 4))
563 insn
= extract_unsigned_integer (buf
, 4);
565 /* AI is the typical instruction to set up a stack frame.
566 It is also used to initialize the frame pointer. */
567 if (is_ri10 (insn
, op_ai
, &rt
, &ra
, &immed
))
569 if (rt
== data
->cfa_reg
&& ra
== data
->cfa_reg
)
570 data
->cfa_offset
-= immed
;
572 if (rt
== SPU_RAW_SP_REGNUM
&& ra
== SPU_RAW_SP_REGNUM
580 else if (rt
== SPU_FP_REGNUM
&& ra
== SPU_RAW_SP_REGNUM
586 data
->cfa_reg
= SPU_FP_REGNUM
;
587 data
->cfa_offset
-= immed
;
591 /* A is used to set up stack frames of size >= 512 bytes.
592 If we have tracked the contents of the addend register,
593 we can handle this as well. */
594 else if (is_rr (insn
, op_a
, &rt
, &ra
, &rb
))
596 if (rt
== data
->cfa_reg
&& ra
== data
->cfa_reg
)
598 if (reg_immed
[rb
] != 0)
599 data
->cfa_offset
-= reg_immed
[rb
];
601 data
->cfa_reg
= -1; /* We don't know the CFA any more. */
604 if (rt
== SPU_RAW_SP_REGNUM
&& ra
== SPU_RAW_SP_REGNUM
610 if (reg_immed
[rb
] != 0)
611 data
->size
= -reg_immed
[rb
];
615 /* We need to track IL and ILA used to load immediate constants
616 in case they are later used as input to an A instruction. */
617 else if (is_ri16 (insn
, op_il
, &rt
, &immed
))
619 reg_immed
[rt
] = immed
;
621 if (rt
== SPU_RAW_SP_REGNUM
&& !found_sp
)
625 else if (is_ri18 (insn
, op_ila
, &rt
, &immed
))
627 reg_immed
[rt
] = immed
& 0x3ffff;
629 if (rt
== SPU_RAW_SP_REGNUM
&& !found_sp
)
633 /* STQD is used to save registers to the stack. */
634 else if (is_ri10 (insn
, op_stqd
, &rt
, &ra
, &immed
))
636 if (ra
== data
->cfa_reg
)
637 data
->reg_offset
[rt
] = data
->cfa_offset
- (immed
<< 4);
639 if (ra
== data
->cfa_reg
&& rt
== SPU_LR_REGNUM
647 /* _start uses SELB to set up the stack pointer. */
648 else if (is_rrr (insn
, op_selb
, &rt
, &ra
, &rb
, &rc
))
650 if (rt
== SPU_RAW_SP_REGNUM
&& !found_sp
)
654 /* We terminate if we find a branch. */
655 else if (is_branch (insn
, &immed
, &ra
))
660 /* If we successfully parsed until here, and didn't find any instruction
661 modifying SP, we assume we have a frameless function. */
665 /* Return cooked instead of raw SP. */
666 if (data
->cfa_reg
== SPU_RAW_SP_REGNUM
)
667 data
->cfa_reg
= SPU_SP_REGNUM
;
672 /* Return the first instruction after the prologue starting at PC. */
674 spu_skip_prologue (CORE_ADDR pc
)
676 struct spu_prologue_data data
;
677 return spu_analyze_prologue (pc
, (CORE_ADDR
)-1, &data
);
680 /* Return the frame pointer in use at address PC. */
682 spu_virtual_frame_pointer (CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
684 struct spu_prologue_data data
;
685 spu_analyze_prologue (pc
, (CORE_ADDR
)-1, &data
);
687 if (data
.size
!= -1 && data
.cfa_reg
!= -1)
689 /* The 'frame pointer' address is CFA minus frame size. */
691 *offset
= data
.cfa_offset
- data
.size
;
695 /* ??? We don't really know ... */
696 *reg
= SPU_SP_REGNUM
;
701 /* Return true if we are in the function's epilogue, i.e. after the
702 instruction that destroyed the function's stack frame.
704 1) scan forward from the point of execution:
705 a) If you find an instruction that modifies the stack pointer
706 or transfers control (except a return), execution is not in
708 b) Stop scanning if you find a return instruction or reach the
709 end of the function or reach the hard limit for the size of
711 2) scan backward from the point of execution:
712 a) If you find an instruction that modifies the stack pointer,
713 execution *is* in an epilogue, return.
714 b) Stop scanning if you reach an instruction that transfers
715 control or the beginning of the function or reach the hard
716 limit for the size of an epilogue. */
719 spu_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
721 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
724 int rt
, ra
, rb
, rc
, immed
;
726 /* Find the search limits based on function boundaries and hard limit.
727 We assume the epilogue can be up to 64 instructions long. */
729 const int spu_max_epilogue_size
= 64 * 4;
731 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
734 if (pc
- func_start
< spu_max_epilogue_size
)
735 epilogue_start
= func_start
;
737 epilogue_start
= pc
- spu_max_epilogue_size
;
739 if (func_end
- pc
< spu_max_epilogue_size
)
740 epilogue_end
= func_end
;
742 epilogue_end
= pc
+ spu_max_epilogue_size
;
744 /* Scan forward until next 'bi $0'. */
746 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= 4)
748 if (target_read_memory (scan_pc
, buf
, 4))
750 insn
= extract_unsigned_integer (buf
, 4);
752 if (is_branch (insn
, &immed
, &ra
))
754 if (immed
== 0 && ra
== SPU_LR_REGNUM
)
760 if (is_ri10 (insn
, op_ai
, &rt
, &ra
, &immed
)
761 || is_rr (insn
, op_a
, &rt
, &ra
, &rb
)
762 || is_ri10 (insn
, op_lqd
, &rt
, &ra
, &immed
))
764 if (rt
== SPU_RAW_SP_REGNUM
)
769 if (scan_pc
>= epilogue_end
)
772 /* Scan backward until adjustment to stack pointer (R1). */
774 for (scan_pc
= pc
- 4; scan_pc
>= epilogue_start
; scan_pc
-= 4)
776 if (target_read_memory (scan_pc
, buf
, 4))
778 insn
= extract_unsigned_integer (buf
, 4);
780 if (is_branch (insn
, &immed
, &ra
))
783 if (is_ri10 (insn
, op_ai
, &rt
, &ra
, &immed
)
784 || is_rr (insn
, op_a
, &rt
, &ra
, &rb
)
785 || is_ri10 (insn
, op_lqd
, &rt
, &ra
, &immed
))
787 if (rt
== SPU_RAW_SP_REGNUM
)
796 /* Normal stack frames. */
798 struct spu_unwind_cache
801 CORE_ADDR frame_base
;
802 CORE_ADDR local_base
;
804 struct trad_frame_saved_reg
*saved_regs
;
807 static struct spu_unwind_cache
*
808 spu_frame_unwind_cache (struct frame_info
*next_frame
,
809 void **this_prologue_cache
)
811 struct spu_unwind_cache
*info
;
812 struct spu_prologue_data data
;
815 if (*this_prologue_cache
)
816 return *this_prologue_cache
;
818 info
= FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache
);
819 *this_prologue_cache
= info
;
820 info
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
821 info
->frame_base
= 0;
822 info
->local_base
= 0;
824 /* Find the start of the current function, and analyze its prologue. */
825 info
->func
= frame_func_unwind (next_frame
, NORMAL_FRAME
);
828 /* Fall back to using the current PC as frame ID. */
829 info
->func
= frame_pc_unwind (next_frame
);
833 spu_analyze_prologue (info
->func
, frame_pc_unwind (next_frame
), &data
);
836 /* If successful, use prologue analysis data. */
837 if (data
.size
!= -1 && data
.cfa_reg
!= -1)
842 /* Determine CFA via unwound CFA_REG plus CFA_OFFSET. */
843 frame_unwind_register (next_frame
, data
.cfa_reg
, buf
);
844 cfa
= extract_unsigned_integer (buf
, 4) + data
.cfa_offset
;
846 /* Call-saved register slots. */
847 for (i
= 0; i
< SPU_NUM_GPRS
; i
++)
848 if (i
== SPU_LR_REGNUM
849 || (i
>= SPU_SAVED1_REGNUM
&& i
<= SPU_SAVEDN_REGNUM
))
850 if (data
.reg_offset
[i
] != -1)
851 info
->saved_regs
[i
].addr
= cfa
- data
.reg_offset
[i
];
854 info
->frame_base
= cfa
;
855 info
->local_base
= cfa
- data
.size
;
858 /* Otherwise, fall back to reading the backchain link. */
861 CORE_ADDR reg
, backchain
;
863 /* Get the backchain. */
864 reg
= frame_unwind_register_unsigned (next_frame
, SPU_SP_REGNUM
);
865 backchain
= read_memory_unsigned_integer (reg
, 4);
867 /* A zero backchain terminates the frame chain. Also, sanity
868 check against the local store size limit. */
869 if (backchain
!= 0 && backchain
< SPU_LS_SIZE
)
871 /* Assume the link register is saved into its slot. */
872 if (backchain
+ 16 < SPU_LS_SIZE
)
873 info
->saved_regs
[SPU_LR_REGNUM
].addr
= backchain
+ 16;
876 info
->frame_base
= backchain
;
877 info
->local_base
= reg
;
881 /* The previous SP is equal to the CFA. */
882 trad_frame_set_value (info
->saved_regs
, SPU_SP_REGNUM
, info
->frame_base
);
884 /* Read full contents of the unwound link register in order to
885 be able to determine the return address. */
886 if (trad_frame_addr_p (info
->saved_regs
, SPU_LR_REGNUM
))
887 target_read_memory (info
->saved_regs
[SPU_LR_REGNUM
].addr
, buf
, 16);
889 frame_unwind_register (next_frame
, SPU_LR_REGNUM
, buf
);
891 /* Normally, the return address is contained in the slot 0 of the
892 link register, and slots 1-3 are zero. For an overlay return,
893 slot 0 contains the address of the overlay manager return stub,
894 slot 1 contains the partition number of the overlay section to
895 be returned to, and slot 2 contains the return address within
896 that section. Return the latter address in that case. */
897 if (extract_unsigned_integer (buf
+ 8, 4) != 0)
898 trad_frame_set_value (info
->saved_regs
, SPU_PC_REGNUM
,
899 extract_unsigned_integer (buf
+ 8, 4));
901 trad_frame_set_value (info
->saved_regs
, SPU_PC_REGNUM
,
902 extract_unsigned_integer (buf
, 4));
908 spu_frame_this_id (struct frame_info
*next_frame
,
909 void **this_prologue_cache
, struct frame_id
*this_id
)
911 struct spu_unwind_cache
*info
=
912 spu_frame_unwind_cache (next_frame
, this_prologue_cache
);
914 if (info
->frame_base
== 0)
917 *this_id
= frame_id_build (info
->frame_base
, info
->func
);
921 spu_frame_prev_register (struct frame_info
*next_frame
,
922 void **this_prologue_cache
,
923 int regnum
, int *optimizedp
,
924 enum lval_type
*lvalp
, CORE_ADDR
* addrp
,
925 int *realnump
, gdb_byte
*bufferp
)
927 struct spu_unwind_cache
*info
928 = spu_frame_unwind_cache (next_frame
, this_prologue_cache
);
930 /* Special-case the stack pointer. */
931 if (regnum
== SPU_RAW_SP_REGNUM
)
932 regnum
= SPU_SP_REGNUM
;
934 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
935 optimizedp
, lvalp
, addrp
, realnump
, bufferp
);
938 static const struct frame_unwind spu_frame_unwind
= {
941 spu_frame_prev_register
944 const struct frame_unwind
*
945 spu_frame_sniffer (struct frame_info
*next_frame
)
947 return &spu_frame_unwind
;
951 spu_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
953 struct spu_unwind_cache
*info
954 = spu_frame_unwind_cache (next_frame
, this_cache
);
955 return info
->local_base
;
958 static const struct frame_base spu_frame_base
= {
960 spu_frame_base_address
,
961 spu_frame_base_address
,
962 spu_frame_base_address
966 spu_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
968 CORE_ADDR pc
= frame_unwind_register_unsigned (next_frame
, SPU_PC_REGNUM
);
969 /* Mask off interrupt enable bit. */
974 spu_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
976 return frame_unwind_register_unsigned (next_frame
, SPU_SP_REGNUM
);
980 spu_read_pc (struct regcache
*regcache
)
983 regcache_cooked_read_unsigned (regcache
, SPU_PC_REGNUM
, &pc
);
984 /* Mask off interrupt enable bit. */
989 spu_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
991 /* Keep interrupt enabled state unchanged. */
993 regcache_cooked_read_unsigned (regcache
, SPU_PC_REGNUM
, &old_pc
);
994 regcache_cooked_write_unsigned (regcache
, SPU_PC_REGNUM
,
995 (pc
& -4) | (old_pc
& 3));
999 /* Function calling convention. */
1002 spu_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1008 spu_scalar_value_p (struct type
*type
)
1010 switch (TYPE_CODE (type
))
1013 case TYPE_CODE_ENUM
:
1014 case TYPE_CODE_RANGE
:
1015 case TYPE_CODE_CHAR
:
1016 case TYPE_CODE_BOOL
:
1019 return TYPE_LENGTH (type
) <= 16;
1027 spu_value_to_regcache (struct regcache
*regcache
, int regnum
,
1028 struct type
*type
, const gdb_byte
*in
)
1030 int len
= TYPE_LENGTH (type
);
1032 if (spu_scalar_value_p (type
))
1034 int preferred_slot
= len
< 4 ? 4 - len
: 0;
1035 regcache_cooked_write_part (regcache
, regnum
, preferred_slot
, len
, in
);
1041 regcache_cooked_write (regcache
, regnum
++, in
);
1047 regcache_cooked_write_part (regcache
, regnum
, 0, len
, in
);
1052 spu_regcache_to_value (struct regcache
*regcache
, int regnum
,
1053 struct type
*type
, gdb_byte
*out
)
1055 int len
= TYPE_LENGTH (type
);
1057 if (spu_scalar_value_p (type
))
1059 int preferred_slot
= len
< 4 ? 4 - len
: 0;
1060 regcache_cooked_read_part (regcache
, regnum
, preferred_slot
, len
, out
);
1066 regcache_cooked_read (regcache
, regnum
++, out
);
1072 regcache_cooked_read_part (regcache
, regnum
, 0, len
, out
);
1077 spu_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1078 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1079 int nargs
, struct value
**args
, CORE_ADDR sp
,
1080 int struct_return
, CORE_ADDR struct_addr
)
1083 int regnum
= SPU_ARG1_REGNUM
;
1087 /* Set the return address. */
1088 memset (buf
, 0, sizeof buf
);
1089 store_unsigned_integer (buf
, 4, bp_addr
);
1090 regcache_cooked_write (regcache
, SPU_LR_REGNUM
, buf
);
1092 /* If STRUCT_RETURN is true, then the struct return address (in
1093 STRUCT_ADDR) will consume the first argument-passing register.
1094 Both adjust the register count and store that value. */
1097 memset (buf
, 0, sizeof buf
);
1098 store_unsigned_integer (buf
, 4, struct_addr
);
1099 regcache_cooked_write (regcache
, regnum
++, buf
);
1102 /* Fill in argument registers. */
1103 for (i
= 0; i
< nargs
; i
++)
1105 struct value
*arg
= args
[i
];
1106 struct type
*type
= check_typedef (value_type (arg
));
1107 const gdb_byte
*contents
= value_contents (arg
);
1108 int len
= TYPE_LENGTH (type
);
1109 int n_regs
= align_up (len
, 16) / 16;
1111 /* If the argument doesn't wholly fit into registers, it and
1112 all subsequent arguments go to the stack. */
1113 if (regnum
+ n_regs
- 1 > SPU_ARGN_REGNUM
)
1119 spu_value_to_regcache (regcache
, regnum
, type
, contents
);
1123 /* Overflow arguments go to the stack. */
1124 if (stack_arg
!= -1)
1128 /* Allocate all required stack size. */
1129 for (i
= stack_arg
; i
< nargs
; i
++)
1131 struct type
*type
= check_typedef (value_type (args
[i
]));
1132 sp
-= align_up (TYPE_LENGTH (type
), 16);
1135 /* Fill in stack arguments. */
1137 for (i
= stack_arg
; i
< nargs
; i
++)
1139 struct value
*arg
= args
[i
];
1140 struct type
*type
= check_typedef (value_type (arg
));
1141 int len
= TYPE_LENGTH (type
);
1144 if (spu_scalar_value_p (type
))
1145 preferred_slot
= len
< 4 ? 4 - len
: 0;
1149 target_write_memory (ap
+ preferred_slot
, value_contents (arg
), len
);
1150 ap
+= align_up (TYPE_LENGTH (type
), 16);
1154 /* Allocate stack frame header. */
1157 /* Store stack back chain. */
1158 regcache_cooked_read (regcache
, SPU_RAW_SP_REGNUM
, buf
);
1159 target_write_memory (sp
, buf
, 16);
1161 /* Finally, update the SP register. */
1162 regcache_cooked_write_unsigned (regcache
, SPU_SP_REGNUM
, sp
);
1167 static struct frame_id
1168 spu_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1170 return frame_id_build (spu_unwind_sp (gdbarch
, next_frame
),
1171 spu_unwind_pc (gdbarch
, next_frame
));
1174 /* Function return value access. */
1176 static enum return_value_convention
1177 spu_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
1178 struct regcache
*regcache
, gdb_byte
*out
, const gdb_byte
*in
)
1180 enum return_value_convention rvc
;
1182 if (TYPE_LENGTH (type
) <= (SPU_ARGN_REGNUM
- SPU_ARG1_REGNUM
+ 1) * 16)
1183 rvc
= RETURN_VALUE_REGISTER_CONVENTION
;
1185 rvc
= RETURN_VALUE_STRUCT_CONVENTION
;
1191 case RETURN_VALUE_REGISTER_CONVENTION
:
1192 spu_value_to_regcache (regcache
, SPU_ARG1_REGNUM
, type
, in
);
1195 case RETURN_VALUE_STRUCT_CONVENTION
:
1196 error ("Cannot set function return value.");
1204 case RETURN_VALUE_REGISTER_CONVENTION
:
1205 spu_regcache_to_value (regcache
, SPU_ARG1_REGNUM
, type
, out
);
1208 case RETURN_VALUE_STRUCT_CONVENTION
:
1209 error ("Function return value unknown.");
1220 static const gdb_byte
*
1221 spu_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
1223 static const gdb_byte breakpoint
[] = { 0x00, 0x00, 0x3f, 0xff };
1225 *lenptr
= sizeof breakpoint
;
1230 /* Software single-stepping support. */
1233 spu_software_single_step (struct frame_info
*frame
)
1235 CORE_ADDR pc
, next_pc
;
1240 pc
= get_frame_pc (frame
);
1242 if (target_read_memory (pc
, buf
, 4))
1244 insn
= extract_unsigned_integer (buf
, 4);
1246 /* Next sequential instruction is at PC + 4, except if the current
1247 instruction is a PPE-assisted call, in which case it is at PC + 8.
1248 Wrap around LS limit to be on the safe side. */
1249 if ((insn
& 0xffffff00) == 0x00002100)
1250 next_pc
= (pc
+ 8) & (SPU_LS_SIZE
- 1);
1252 next_pc
= (pc
+ 4) & (SPU_LS_SIZE
- 1);
1254 insert_single_step_breakpoint (next_pc
);
1256 if (is_branch (insn
, &offset
, ®
))
1258 CORE_ADDR target
= offset
;
1260 if (reg
== SPU_PC_REGNUM
)
1264 get_frame_register_bytes (frame
, reg
, 0, 4, buf
);
1265 target
+= extract_unsigned_integer (buf
, 4) & -4;
1268 target
= target
& (SPU_LS_SIZE
- 1);
1269 if (target
!= next_pc
)
1270 insert_single_step_breakpoint (target
);
1276 /* Target overlays for the SPU overlay manager.
1278 See the documentation of simple_overlay_update for how the
1279 interface is supposed to work.
1281 Data structures used by the overlay manager:
1289 } _ovly_table[]; -- one entry per overlay section
1291 struct ovly_buf_table
1294 } _ovly_buf_table[]; -- one entry per overlay buffer
1296 _ovly_table should never change.
1298 Both tables are aligned to a 16-byte boundary, the symbols _ovly_table
1299 and _ovly_buf_table are of type STT_OBJECT and their size set to the size
1300 of the respective array. buf in _ovly_table is an index into _ovly_buf_table.
1302 mapped is an index into _ovly_table. Both the mapped and buf indices start
1303 from one to reference the first entry in their respective tables. */
1305 /* Using the per-objfile private data mechanism, we store for each
1306 objfile an array of "struct spu_overlay_table" structures, one
1307 for each obj_section of the objfile. This structure holds two
1308 fields, MAPPED_PTR and MAPPED_VAL. If MAPPED_PTR is zero, this
1309 is *not* an overlay section. If it is non-zero, it represents
1310 a target address. The overlay section is mapped iff the target
1311 integer at this location equals MAPPED_VAL. */
1313 static const struct objfile_data
*spu_overlay_data
;
1315 struct spu_overlay_table
1317 CORE_ADDR mapped_ptr
;
1318 CORE_ADDR mapped_val
;
1321 /* Retrieve the overlay table for OBJFILE. If not already cached, read
1322 the _ovly_table data structure from the target and initialize the
1323 spu_overlay_table data structure from it. */
1324 static struct spu_overlay_table
*
1325 spu_get_overlay_table (struct objfile
*objfile
)
1327 struct minimal_symbol
*ovly_table_msym
, *ovly_buf_table_msym
;
1328 CORE_ADDR ovly_table_base
, ovly_buf_table_base
;
1329 unsigned ovly_table_size
, ovly_buf_table_size
;
1330 struct spu_overlay_table
*tbl
;
1331 struct obj_section
*osect
;
1335 tbl
= objfile_data (objfile
, spu_overlay_data
);
1339 ovly_table_msym
= lookup_minimal_symbol ("_ovly_table", NULL
, objfile
);
1340 if (!ovly_table_msym
)
1343 ovly_buf_table_msym
= lookup_minimal_symbol ("_ovly_buf_table", NULL
, objfile
);
1344 if (!ovly_buf_table_msym
)
1347 ovly_table_base
= SYMBOL_VALUE_ADDRESS (ovly_table_msym
);
1348 ovly_table_size
= MSYMBOL_SIZE (ovly_table_msym
);
1350 ovly_buf_table_base
= SYMBOL_VALUE_ADDRESS (ovly_buf_table_msym
);
1351 ovly_buf_table_size
= MSYMBOL_SIZE (ovly_buf_table_msym
);
1353 ovly_table
= xmalloc (ovly_table_size
);
1354 read_memory (ovly_table_base
, ovly_table
, ovly_table_size
);
1356 tbl
= OBSTACK_CALLOC (&objfile
->objfile_obstack
,
1357 objfile
->sections_end
- objfile
->sections
,
1358 struct spu_overlay_table
);
1360 for (i
= 0; i
< ovly_table_size
/ 16; i
++)
1362 CORE_ADDR vma
= extract_unsigned_integer (ovly_table
+ 16*i
+ 0, 4);
1363 CORE_ADDR size
= extract_unsigned_integer (ovly_table
+ 16*i
+ 4, 4);
1364 CORE_ADDR pos
= extract_unsigned_integer (ovly_table
+ 16*i
+ 8, 4);
1365 CORE_ADDR buf
= extract_unsigned_integer (ovly_table
+ 16*i
+ 12, 4);
1367 if (buf
== 0 || (buf
- 1) * 4 >= ovly_buf_table_size
)
1370 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
1371 if (vma
== bfd_section_vma (objfile
->obfd
, osect
->the_bfd_section
)
1372 && pos
== osect
->the_bfd_section
->filepos
)
1374 int ndx
= osect
- objfile
->sections
;
1375 tbl
[ndx
].mapped_ptr
= ovly_buf_table_base
+ (buf
- 1) * 4;
1376 tbl
[ndx
].mapped_val
= i
+ 1;
1382 set_objfile_data (objfile
, spu_overlay_data
, tbl
);
1386 /* Read _ovly_buf_table entry from the target to dermine whether
1387 OSECT is currently mapped, and update the mapped state. */
1389 spu_overlay_update_osect (struct obj_section
*osect
)
1391 struct spu_overlay_table
*ovly_table
;
1394 ovly_table
= spu_get_overlay_table (osect
->objfile
);
1398 ovly_table
+= osect
- osect
->objfile
->sections
;
1399 if (ovly_table
->mapped_ptr
== 0)
1402 val
= read_memory_unsigned_integer (ovly_table
->mapped_ptr
, 4);
1403 osect
->ovly_mapped
= (val
== ovly_table
->mapped_val
);
1406 /* If OSECT is NULL, then update all sections' mapped state.
1407 If OSECT is non-NULL, then update only OSECT's mapped state. */
1409 spu_overlay_update (struct obj_section
*osect
)
1411 /* Just one section. */
1413 spu_overlay_update_osect (osect
);
1418 struct objfile
*objfile
;
1420 ALL_OBJSECTIONS (objfile
, osect
)
1421 if (section_is_overlay (osect
->the_bfd_section
))
1422 spu_overlay_update_osect (osect
);
1426 /* Whenever a new objfile is loaded, read the target's _ovly_table.
1427 If there is one, go through all sections and make sure for non-
1428 overlay sections LMA equals VMA, while for overlay sections LMA
1429 is larger than local store size. */
1431 spu_overlay_new_objfile (struct objfile
*objfile
)
1433 struct spu_overlay_table
*ovly_table
;
1434 struct obj_section
*osect
;
1436 /* If we've already touched this file, do nothing. */
1437 if (!objfile
|| objfile_data (objfile
, spu_overlay_data
) != NULL
)
1440 /* Check if this objfile has overlays. */
1441 ovly_table
= spu_get_overlay_table (objfile
);
1445 /* Now go and fiddle with all the LMAs. */
1446 ALL_OBJFILE_OSECTIONS (objfile
, osect
)
1448 bfd
*obfd
= objfile
->obfd
;
1449 asection
*bsect
= osect
->the_bfd_section
;
1450 int ndx
= osect
- objfile
->sections
;
1452 if (ovly_table
[ndx
].mapped_ptr
== 0)
1453 bfd_section_lma (obfd
, bsect
) = bfd_section_vma (obfd
, bsect
);
1455 bfd_section_lma (obfd
, bsect
) = bsect
->filepos
+ SPU_LS_SIZE
;
1460 /* "info spu" commands. */
1463 info_spu_event_command (char *args
, int from_tty
)
1465 struct frame_info
*frame
= get_selected_frame (NULL
);
1466 ULONGEST event_status
= 0;
1467 ULONGEST event_mask
= 0;
1468 struct cleanup
*chain
;
1474 id
= get_frame_register_unsigned (frame
, SPU_ID_REGNUM
);
1476 xsnprintf (annex
, sizeof annex
, "%d/event_status", id
);
1477 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1478 buf
, 0, sizeof buf
);
1480 error (_("Could not read event_status."));
1481 event_status
= strtoulst (buf
, NULL
, 16);
1483 xsnprintf (annex
, sizeof annex
, "%d/event_mask", id
);
1484 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1485 buf
, 0, sizeof buf
);
1487 error (_("Could not read event_mask."));
1488 event_mask
= strtoulst (buf
, NULL
, 16);
1490 chain
= make_cleanup_ui_out_tuple_begin_end (uiout
, "SPUInfoEvent");
1492 if (ui_out_is_mi_like_p (uiout
))
1494 ui_out_field_fmt (uiout
, "event_status",
1495 "0x%s", phex_nz (event_status
, 4));
1496 ui_out_field_fmt (uiout
, "event_mask",
1497 "0x%s", phex_nz (event_mask
, 4));
1501 printf_filtered (_("Event Status 0x%s\n"), phex (event_status
, 4));
1502 printf_filtered (_("Event Mask 0x%s\n"), phex (event_mask
, 4));
1505 do_cleanups (chain
);
1509 info_spu_signal_command (char *args
, int from_tty
)
1511 struct frame_info
*frame
= get_selected_frame (NULL
);
1512 ULONGEST signal1
= 0;
1513 ULONGEST signal1_type
= 0;
1514 int signal1_pending
= 0;
1515 ULONGEST signal2
= 0;
1516 ULONGEST signal2_type
= 0;
1517 int signal2_pending
= 0;
1518 struct cleanup
*chain
;
1524 id
= get_frame_register_unsigned (frame
, SPU_ID_REGNUM
);
1526 xsnprintf (annex
, sizeof annex
, "%d/signal1", id
);
1527 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
, buf
, 0, 4);
1529 error (_("Could not read signal1."));
1532 signal1
= extract_unsigned_integer (buf
, 4);
1533 signal1_pending
= 1;
1536 xsnprintf (annex
, sizeof annex
, "%d/signal1_type", id
);
1537 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1538 buf
, 0, sizeof buf
);
1540 error (_("Could not read signal1_type."));
1541 signal1_type
= strtoulst (buf
, NULL
, 16);
1543 xsnprintf (annex
, sizeof annex
, "%d/signal2", id
);
1544 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
, buf
, 0, 4);
1546 error (_("Could not read signal2."));
1549 signal2
= extract_unsigned_integer (buf
, 4);
1550 signal2_pending
= 1;
1553 xsnprintf (annex
, sizeof annex
, "%d/signal2_type", id
);
1554 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1555 buf
, 0, sizeof buf
);
1557 error (_("Could not read signal2_type."));
1558 signal2_type
= strtoulst (buf
, NULL
, 16);
1560 chain
= make_cleanup_ui_out_tuple_begin_end (uiout
, "SPUInfoSignal");
1562 if (ui_out_is_mi_like_p (uiout
))
1564 ui_out_field_int (uiout
, "signal1_pending", signal1_pending
);
1565 ui_out_field_fmt (uiout
, "signal1", "0x%s", phex_nz (signal1
, 4));
1566 ui_out_field_int (uiout
, "signal1_type", signal1_type
);
1567 ui_out_field_int (uiout
, "signal2_pending", signal2_pending
);
1568 ui_out_field_fmt (uiout
, "signal2", "0x%s", phex_nz (signal2
, 4));
1569 ui_out_field_int (uiout
, "signal2_type", signal2_type
);
1573 if (signal1_pending
)
1574 printf_filtered (_("Signal 1 control word 0x%s "), phex (signal1
, 4));
1576 printf_filtered (_("Signal 1 not pending "));
1579 printf_filtered (_("(Type Overwrite)\n"));
1581 printf_filtered (_("(Type Or)\n"));
1583 if (signal2_pending
)
1584 printf_filtered (_("Signal 2 control word 0x%s "), phex (signal2
, 4));
1586 printf_filtered (_("Signal 2 not pending "));
1589 printf_filtered (_("(Type Overwrite)\n"));
1591 printf_filtered (_("(Type Or)\n"));
1594 do_cleanups (chain
);
1598 info_spu_mailbox_list (gdb_byte
*buf
, int nr
,
1599 const char *field
, const char *msg
)
1601 struct cleanup
*chain
;
1607 chain
= make_cleanup_ui_out_table_begin_end (uiout
, 1, nr
, "mbox");
1609 ui_out_table_header (uiout
, 32, ui_left
, field
, msg
);
1610 ui_out_table_body (uiout
);
1612 for (i
= 0; i
< nr
; i
++)
1614 struct cleanup
*val_chain
;
1616 val_chain
= make_cleanup_ui_out_tuple_begin_end (uiout
, "mbox");
1617 val
= extract_unsigned_integer (buf
+ 4*i
, 4);
1618 ui_out_field_fmt (uiout
, field
, "0x%s", phex (val
, 4));
1619 do_cleanups (val_chain
);
1621 if (!ui_out_is_mi_like_p (uiout
))
1622 printf_filtered ("\n");
1625 do_cleanups (chain
);
1629 info_spu_mailbox_command (char *args
, int from_tty
)
1631 struct frame_info
*frame
= get_selected_frame (NULL
);
1632 struct cleanup
*chain
;
1638 id
= get_frame_register_unsigned (frame
, SPU_ID_REGNUM
);
1640 chain
= make_cleanup_ui_out_tuple_begin_end (uiout
, "SPUInfoMailbox");
1642 xsnprintf (annex
, sizeof annex
, "%d/mbox_info", id
);
1643 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1644 buf
, 0, sizeof buf
);
1646 error (_("Could not read mbox_info."));
1648 info_spu_mailbox_list (buf
, len
/ 4, "mbox", "SPU Outbound Mailbox");
1650 xsnprintf (annex
, sizeof annex
, "%d/ibox_info", id
);
1651 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1652 buf
, 0, sizeof buf
);
1654 error (_("Could not read ibox_info."));
1656 info_spu_mailbox_list (buf
, len
/ 4, "ibox", "SPU Outbound Interrupt Mailbox");
1658 xsnprintf (annex
, sizeof annex
, "%d/wbox_info", id
);
1659 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1660 buf
, 0, sizeof buf
);
1662 error (_("Could not read wbox_info."));
1664 info_spu_mailbox_list (buf
, len
/ 4, "wbox", "SPU Inbound Mailbox");
1666 do_cleanups (chain
);
1670 spu_mfc_get_bitfield (ULONGEST word
, int first
, int last
)
1672 ULONGEST mask
= ~(~(ULONGEST
)0 << (last
- first
+ 1));
1673 return (word
>> (63 - last
)) & mask
;
1677 info_spu_dma_cmdlist (gdb_byte
*buf
, int nr
)
1679 static char *spu_mfc_opcode
[256] =
1681 /* 00 */ NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1682 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1683 /* 10 */ NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1684 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1685 /* 20 */ "put", "putb", "putf", NULL
, "putl", "putlb", "putlf", NULL
,
1686 "puts", "putbs", "putfs", NULL
, NULL
, NULL
, NULL
, NULL
,
1687 /* 30 */ "putr", "putrb", "putrf", NULL
, "putrl", "putrlb", "putrlf", NULL
,
1688 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1689 /* 40 */ "get", "getb", "getf", NULL
, "getl", "getlb", "getlf", NULL
,
1690 "gets", "getbs", "getfs", NULL
, NULL
, NULL
, NULL
, NULL
,
1691 /* 50 */ NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1692 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1693 /* 60 */ NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1694 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1695 /* 70 */ NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1696 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1697 /* 80 */ "sdcrt", "sdcrtst", NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1698 NULL
, "sdcrz", NULL
, NULL
, NULL
, "sdcrst", NULL
, "sdcrf",
1699 /* 90 */ NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1700 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1701 /* a0 */ "sndsig", "sndsigb", "sndsigf", NULL
, NULL
, NULL
, NULL
, NULL
,
1702 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1703 /* b0 */ "putlluc", NULL
, NULL
, NULL
, "putllc", NULL
, NULL
, NULL
,
1704 "putqlluc", NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1705 /* c0 */ "barrier", NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1706 "mfceieio", NULL
, NULL
, NULL
, "mfcsync", NULL
, NULL
, NULL
,
1707 /* d0 */ "getllar", NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1708 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1709 /* e0 */ NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1710 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1711 /* f0 */ NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1712 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
1715 struct cleanup
*chain
;
1718 chain
= make_cleanup_ui_out_table_begin_end (uiout
, 10, nr
, "dma_cmd");
1720 ui_out_table_header (uiout
, 7, ui_left
, "opcode", "Opcode");
1721 ui_out_table_header (uiout
, 3, ui_left
, "tag", "Tag");
1722 ui_out_table_header (uiout
, 3, ui_left
, "tid", "TId");
1723 ui_out_table_header (uiout
, 3, ui_left
, "rid", "RId");
1724 ui_out_table_header (uiout
, 18, ui_left
, "ea", "EA");
1725 ui_out_table_header (uiout
, 7, ui_left
, "lsa", "LSA");
1726 ui_out_table_header (uiout
, 7, ui_left
, "size", "Size");
1727 ui_out_table_header (uiout
, 7, ui_left
, "lstaddr", "LstAddr");
1728 ui_out_table_header (uiout
, 7, ui_left
, "lstsize", "LstSize");
1729 ui_out_table_header (uiout
, 1, ui_left
, "error_p", "E");
1731 ui_out_table_body (uiout
);
1733 for (i
= 0; i
< nr
; i
++)
1735 struct cleanup
*cmd_chain
;
1736 ULONGEST mfc_cq_dw0
;
1737 ULONGEST mfc_cq_dw1
;
1738 ULONGEST mfc_cq_dw2
;
1739 ULONGEST mfc_cq_dw3
;
1740 int mfc_cmd_opcode
, mfc_cmd_tag
, rclass_id
, tclass_id
;
1741 int lsa
, size
, list_lsa
, list_size
, mfc_lsa
, mfc_size
;
1743 int list_valid_p
, noop_valid_p
, qw_valid_p
, ea_valid_p
, cmd_error_p
;
1745 /* Decode contents of MFC Command Queue Context Save/Restore Registers.
1746 See "Cell Broadband Engine Registers V1.3", section 3.3.2.1. */
1748 mfc_cq_dw0
= extract_unsigned_integer (buf
+ 32*i
, 8);
1749 mfc_cq_dw1
= extract_unsigned_integer (buf
+ 32*i
+ 8, 8);
1750 mfc_cq_dw2
= extract_unsigned_integer (buf
+ 32*i
+ 16, 8);
1751 mfc_cq_dw3
= extract_unsigned_integer (buf
+ 32*i
+ 24, 8);
1753 list_lsa
= spu_mfc_get_bitfield (mfc_cq_dw0
, 0, 14);
1754 list_size
= spu_mfc_get_bitfield (mfc_cq_dw0
, 15, 26);
1755 mfc_cmd_opcode
= spu_mfc_get_bitfield (mfc_cq_dw0
, 27, 34);
1756 mfc_cmd_tag
= spu_mfc_get_bitfield (mfc_cq_dw0
, 35, 39);
1757 list_valid_p
= spu_mfc_get_bitfield (mfc_cq_dw0
, 40, 40);
1758 rclass_id
= spu_mfc_get_bitfield (mfc_cq_dw0
, 41, 43);
1759 tclass_id
= spu_mfc_get_bitfield (mfc_cq_dw0
, 44, 46);
1761 mfc_ea
= spu_mfc_get_bitfield (mfc_cq_dw1
, 0, 51) << 12
1762 | spu_mfc_get_bitfield (mfc_cq_dw2
, 25, 36);
1764 mfc_lsa
= spu_mfc_get_bitfield (mfc_cq_dw2
, 0, 13);
1765 mfc_size
= spu_mfc_get_bitfield (mfc_cq_dw2
, 14, 24);
1766 noop_valid_p
= spu_mfc_get_bitfield (mfc_cq_dw2
, 37, 37);
1767 qw_valid_p
= spu_mfc_get_bitfield (mfc_cq_dw2
, 38, 38);
1768 ea_valid_p
= spu_mfc_get_bitfield (mfc_cq_dw2
, 39, 39);
1769 cmd_error_p
= spu_mfc_get_bitfield (mfc_cq_dw2
, 40, 40);
1771 cmd_chain
= make_cleanup_ui_out_tuple_begin_end (uiout
, "cmd");
1773 if (spu_mfc_opcode
[mfc_cmd_opcode
])
1774 ui_out_field_string (uiout
, "opcode", spu_mfc_opcode
[mfc_cmd_opcode
]);
1776 ui_out_field_int (uiout
, "opcode", mfc_cmd_opcode
);
1778 ui_out_field_int (uiout
, "tag", mfc_cmd_tag
);
1779 ui_out_field_int (uiout
, "tid", tclass_id
);
1780 ui_out_field_int (uiout
, "rid", rclass_id
);
1783 ui_out_field_fmt (uiout
, "ea", "0x%s", phex (mfc_ea
, 8));
1785 ui_out_field_skip (uiout
, "ea");
1787 ui_out_field_fmt (uiout
, "lsa", "0x%05x", mfc_lsa
<< 4);
1789 ui_out_field_fmt (uiout
, "size", "0x%05x", mfc_size
<< 4);
1791 ui_out_field_fmt (uiout
, "size", "0x%05x", mfc_size
);
1795 ui_out_field_fmt (uiout
, "lstaddr", "0x%05x", list_lsa
<< 3);
1796 ui_out_field_fmt (uiout
, "lstsize", "0x%05x", list_size
<< 3);
1800 ui_out_field_skip (uiout
, "lstaddr");
1801 ui_out_field_skip (uiout
, "lstsize");
1805 ui_out_field_string (uiout
, "error_p", "*");
1807 ui_out_field_skip (uiout
, "error_p");
1809 do_cleanups (cmd_chain
);
1811 if (!ui_out_is_mi_like_p (uiout
))
1812 printf_filtered ("\n");
1815 do_cleanups (chain
);
1819 info_spu_dma_command (char *args
, int from_tty
)
1821 struct frame_info
*frame
= get_selected_frame (NULL
);
1822 ULONGEST dma_info_type
;
1823 ULONGEST dma_info_mask
;
1824 ULONGEST dma_info_status
;
1825 ULONGEST dma_info_stall_and_notify
;
1826 ULONGEST dma_info_atomic_command_status
;
1827 struct cleanup
*chain
;
1833 id
= get_frame_register_unsigned (frame
, SPU_ID_REGNUM
);
1835 xsnprintf (annex
, sizeof annex
, "%d/dma_info", id
);
1836 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1837 buf
, 0, 40 + 16 * 32);
1839 error (_("Could not read dma_info."));
1841 dma_info_type
= extract_unsigned_integer (buf
, 8);
1842 dma_info_mask
= extract_unsigned_integer (buf
+ 8, 8);
1843 dma_info_status
= extract_unsigned_integer (buf
+ 16, 8);
1844 dma_info_stall_and_notify
= extract_unsigned_integer (buf
+ 24, 8);
1845 dma_info_atomic_command_status
= extract_unsigned_integer (buf
+ 32, 8);
1847 chain
= make_cleanup_ui_out_tuple_begin_end (uiout
, "SPUInfoDMA");
1849 if (ui_out_is_mi_like_p (uiout
))
1851 ui_out_field_fmt (uiout
, "dma_info_type", "0x%s",
1852 phex_nz (dma_info_type
, 4));
1853 ui_out_field_fmt (uiout
, "dma_info_mask", "0x%s",
1854 phex_nz (dma_info_mask
, 4));
1855 ui_out_field_fmt (uiout
, "dma_info_status", "0x%s",
1856 phex_nz (dma_info_status
, 4));
1857 ui_out_field_fmt (uiout
, "dma_info_stall_and_notify", "0x%s",
1858 phex_nz (dma_info_stall_and_notify
, 4));
1859 ui_out_field_fmt (uiout
, "dma_info_atomic_command_status", "0x%s",
1860 phex_nz (dma_info_atomic_command_status
, 4));
1864 const char *query_msg
;
1866 switch (dma_info_type
)
1868 case 0: query_msg
= _("no query pending"); break;
1869 case 1: query_msg
= _("'any' query pending"); break;
1870 case 2: query_msg
= _("'all' query pending"); break;
1871 default: query_msg
= _("undefined query type"); break;
1874 printf_filtered (_("Tag-Group Status 0x%s\n"),
1875 phex (dma_info_status
, 4));
1876 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
1877 phex (dma_info_mask
, 4), query_msg
);
1878 printf_filtered (_("Stall-and-Notify 0x%s\n"),
1879 phex (dma_info_stall_and_notify
, 4));
1880 printf_filtered (_("Atomic Cmd Status 0x%s\n"),
1881 phex (dma_info_atomic_command_status
, 4));
1882 printf_filtered ("\n");
1885 info_spu_dma_cmdlist (buf
+ 40, 16);
1886 do_cleanups (chain
);
1890 info_spu_proxydma_command (char *args
, int from_tty
)
1892 struct frame_info
*frame
= get_selected_frame (NULL
);
1893 ULONGEST dma_info_type
;
1894 ULONGEST dma_info_mask
;
1895 ULONGEST dma_info_status
;
1896 struct cleanup
*chain
;
1902 id
= get_frame_register_unsigned (frame
, SPU_ID_REGNUM
);
1904 xsnprintf (annex
, sizeof annex
, "%d/proxydma_info", id
);
1905 len
= target_read (¤t_target
, TARGET_OBJECT_SPU
, annex
,
1906 buf
, 0, 24 + 8 * 32);
1908 error (_("Could not read proxydma_info."));
1910 dma_info_type
= extract_unsigned_integer (buf
, 8);
1911 dma_info_mask
= extract_unsigned_integer (buf
+ 8, 8);
1912 dma_info_status
= extract_unsigned_integer (buf
+ 16, 8);
1914 chain
= make_cleanup_ui_out_tuple_begin_end (uiout
, "SPUInfoProxyDMA");
1916 if (ui_out_is_mi_like_p (uiout
))
1918 ui_out_field_fmt (uiout
, "proxydma_info_type", "0x%s",
1919 phex_nz (dma_info_type
, 4));
1920 ui_out_field_fmt (uiout
, "proxydma_info_mask", "0x%s",
1921 phex_nz (dma_info_mask
, 4));
1922 ui_out_field_fmt (uiout
, "proxydma_info_status", "0x%s",
1923 phex_nz (dma_info_status
, 4));
1927 const char *query_msg
;
1929 switch (dma_info_type
)
1931 case 0: query_msg
= _("no query pending"); break;
1932 case 1: query_msg
= _("'any' query pending"); break;
1933 case 2: query_msg
= _("'all' query pending"); break;
1934 default: query_msg
= _("undefined query type"); break;
1937 printf_filtered (_("Tag-Group Status 0x%s\n"),
1938 phex (dma_info_status
, 4));
1939 printf_filtered (_("Tag-Group Mask 0x%s (%s)\n"),
1940 phex (dma_info_mask
, 4), query_msg
);
1941 printf_filtered ("\n");
1944 info_spu_dma_cmdlist (buf
+ 24, 8);
1945 do_cleanups (chain
);
1949 info_spu_command (char *args
, int from_tty
)
1951 printf_unfiltered (_("\"info spu\" must be followed by the name of an SPU facility.\n"));
1952 help_list (infospucmdlist
, "info spu ", -1, gdb_stdout
);
1956 /* Set up gdbarch struct. */
1958 static struct gdbarch
*
1959 spu_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1961 struct gdbarch
*gdbarch
;
1962 struct gdbarch_tdep
*tdep
;
1964 /* Find a candidate among the list of pre-declared architectures. */
1965 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1967 return arches
->gdbarch
;
1970 if (info
.bfd_arch_info
->mach
!= bfd_mach_spu
)
1973 /* Yes, create a new architecture. */
1974 tdep
= XCALLOC (1, struct gdbarch_tdep
);
1975 gdbarch
= gdbarch_alloc (&info
, tdep
);
1978 set_gdbarch_print_insn (gdbarch
, print_insn_spu
);
1981 set_gdbarch_num_regs (gdbarch
, SPU_NUM_REGS
);
1982 set_gdbarch_num_pseudo_regs (gdbarch
, SPU_NUM_PSEUDO_REGS
);
1983 set_gdbarch_sp_regnum (gdbarch
, SPU_SP_REGNUM
);
1984 set_gdbarch_pc_regnum (gdbarch
, SPU_PC_REGNUM
);
1985 set_gdbarch_read_pc (gdbarch
, spu_read_pc
);
1986 set_gdbarch_write_pc (gdbarch
, spu_write_pc
);
1987 set_gdbarch_register_name (gdbarch
, spu_register_name
);
1988 set_gdbarch_register_type (gdbarch
, spu_register_type
);
1989 set_gdbarch_pseudo_register_read (gdbarch
, spu_pseudo_register_read
);
1990 set_gdbarch_pseudo_register_write (gdbarch
, spu_pseudo_register_write
);
1991 set_gdbarch_value_from_register (gdbarch
, spu_value_from_register
);
1992 set_gdbarch_register_reggroup_p (gdbarch
, spu_register_reggroup_p
);
1995 set_gdbarch_char_signed (gdbarch
, 0);
1996 set_gdbarch_ptr_bit (gdbarch
, 32);
1997 set_gdbarch_addr_bit (gdbarch
, 32);
1998 set_gdbarch_short_bit (gdbarch
, 16);
1999 set_gdbarch_int_bit (gdbarch
, 32);
2000 set_gdbarch_long_bit (gdbarch
, 32);
2001 set_gdbarch_long_long_bit (gdbarch
, 64);
2002 set_gdbarch_float_bit (gdbarch
, 32);
2003 set_gdbarch_double_bit (gdbarch
, 64);
2004 set_gdbarch_long_double_bit (gdbarch
, 64);
2005 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
2006 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
2007 set_gdbarch_long_double_format (gdbarch
, floatformats_ieee_double
);
2009 /* Inferior function calls. */
2010 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
2011 set_gdbarch_frame_align (gdbarch
, spu_frame_align
);
2012 set_gdbarch_push_dummy_call (gdbarch
, spu_push_dummy_call
);
2013 set_gdbarch_unwind_dummy_id (gdbarch
, spu_unwind_dummy_id
);
2014 set_gdbarch_return_value (gdbarch
, spu_return_value
);
2016 /* Frame handling. */
2017 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2018 frame_unwind_append_sniffer (gdbarch
, spu_frame_sniffer
);
2019 frame_base_set_default (gdbarch
, &spu_frame_base
);
2020 set_gdbarch_unwind_pc (gdbarch
, spu_unwind_pc
);
2021 set_gdbarch_unwind_sp (gdbarch
, spu_unwind_sp
);
2022 set_gdbarch_virtual_frame_pointer (gdbarch
, spu_virtual_frame_pointer
);
2023 set_gdbarch_frame_args_skip (gdbarch
, 0);
2024 set_gdbarch_skip_prologue (gdbarch
, spu_skip_prologue
);
2025 set_gdbarch_in_function_epilogue_p (gdbarch
, spu_in_function_epilogue_p
);
2028 set_gdbarch_decr_pc_after_break (gdbarch
, 4);
2029 set_gdbarch_breakpoint_from_pc (gdbarch
, spu_breakpoint_from_pc
);
2030 set_gdbarch_cannot_step_breakpoint (gdbarch
, 1);
2031 set_gdbarch_software_single_step (gdbarch
, spu_software_single_step
);
2034 set_gdbarch_overlay_update (gdbarch
, spu_overlay_update
);
2040 _initialize_spu_tdep (void)
2042 register_gdbarch_init (bfd_arch_spu
, spu_gdbarch_init
);
2044 /* Add ourselves to objfile event chain. */
2045 observer_attach_new_objfile (spu_overlay_new_objfile
);
2046 spu_overlay_data
= register_objfile_data ();
2048 /* Add root prefix command for all "info spu" commands. */
2049 add_prefix_cmd ("spu", class_info
, info_spu_command
,
2050 _("Various SPU specific commands."),
2051 &infospucmdlist
, "info spu ", 0, &infolist
);
2053 /* Add various "info spu" commands. */
2054 add_cmd ("event", class_info
, info_spu_event_command
,
2055 _("Display SPU event facility status.\n"),
2057 add_cmd ("signal", class_info
, info_spu_signal_command
,
2058 _("Display SPU signal notification facility status.\n"),
2060 add_cmd ("mailbox", class_info
, info_spu_mailbox_command
,
2061 _("Display SPU mailbox facility status.\n"),
2063 add_cmd ("dma", class_info
, info_spu_dma_command
,
2064 _("Display MFC DMA status.\n"),
2066 add_cmd ("proxydma", class_info
, info_spu_proxydma_command
,
2067 _("Display MFC Proxy-DMA status.\n"),