gdb/spu-tdep.c

   1 /* SPU target-dependent code for GDB, the GNU debugger.
   2    Copyright (C) 2006-2014 Free Software Foundation, Inc.
   3
   4    Contributed by Ulrich Weigand <uweigand@de.ibm.com>.
   5    Based on a port by Sid Manning <sid@us.ibm.com>.
   6
   7    This file is part of GDB.
   8
   9    This program is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3 of the License, or
  12    (at your option) any later version.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  21
  22 #include "defs.h"
  23 #include "arch-utils.h"
  24 #include "gdbtypes.h"
  25 #include "gdbcmd.h"
  26 #include "gdbcore.h"
  27 #include "frame.h"
  28 #include "frame-unwind.h"
  29 #include "frame-base.h"
  30 #include "trad-frame.h"
  31 #include "symtab.h"
  32 #include "symfile.h"
  33 #include "value.h"
  34 #include "inferior.h"
  35 #include "dis-asm.h"
  36 #include "objfiles.h"
  37 #include "language.h"
  38 #include "regcache.h"
  39 #include "reggroups.h"
  40 #include "floatformat.h"
  41 #include "block.h"
  42 #include "observer.h"
  43 #include "infcall.h"
  44 #include "dwarf2.h"
  45 #include "dwarf2-frame.h"
  46 #include "ax.h"
  47 #include "exceptions.h"
  48 #include "spu-tdep.h"
  49
  50
  51 /* The list of available "set spu " and "show spu " commands.  */
  52 static struct cmd_list_element *setspucmdlist = NULL;
  53 static struct cmd_list_element *showspucmdlist = NULL;
  54
  55 /* Whether to stop for new SPE contexts.  */
  56 static int spu_stop_on_load_p = 0;
  57 /* Whether to automatically flush the SW-managed cache.  */
  58 static int spu_auto_flush_cache_p = 1;
  59
  60
  61 /* The tdep structure.  */
  62 struct gdbarch_tdep
  63 {
  64   /* The spufs ID identifying our address space.  */
  65   int id;
  66
  67   /* SPU-specific vector type.  */
  68   struct type *spu_builtin_type_vec128;
  69 };
  70
  71
  72 /* SPU-specific vector type.  */
  73 static struct type *
  74 spu_builtin_type_vec128 (struct gdbarch *gdbarch)
  75 {
  76   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
  77
  78   if (!tdep->spu_builtin_type_vec128)
  79     {
  80       const struct builtin_type *bt = builtin_type (gdbarch);
  81       struct type *t;
  82
  83       t = arch_composite_type (gdbarch,
  84                                "__spu_builtin_type_vec128", TYPE_CODE_UNION);
  85       append_composite_type_field (t, "uint128", bt->builtin_int128);
  86       append_composite_type_field (t, "v2_int64",
  87                                    init_vector_type (bt->builtin_int64, 2));
  88       append_composite_type_field (t, "v4_int32",
  89                                    init_vector_type (bt->builtin_int32, 4));
  90       append_composite_type_field (t, "v8_int16",
  91                                    init_vector_type (bt->builtin_int16, 8));
  92       append_composite_type_field (t, "v16_int8",
  93                                    init_vector_type (bt->builtin_int8, 16));
  94       append_composite_type_field (t, "v2_double",
  95                                    init_vector_type (bt->builtin_double, 2));
  96       append_composite_type_field (t, "v4_float",
  97                                    init_vector_type (bt->builtin_float, 4));
  98
  99       TYPE_VECTOR (t) = 1;
 100       TYPE_NAME (t) = "spu_builtin_type_vec128";
 101
 102       tdep->spu_builtin_type_vec128 = t;
 103     }
 104
 105   return tdep->spu_builtin_type_vec128;
 106 }
 107
 108
 109 /* The list of available "info spu " commands.  */
 110 static struct cmd_list_element *infospucmdlist = NULL;
 111
 112 /* Registers.  */
 113
 114 static const char *
 115 spu_register_name (struct gdbarch *gdbarch, int reg_nr)
 116 {
 117   static char *register_names[] =
 118     {
 119       "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 120       "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 121       "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
 122       "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
 123       "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
 124       "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
 125       "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
 126       "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
 127       "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
 128       "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
 129       "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
 130       "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
 131       "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
 132       "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
 133       "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
 134       "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
 135       "id", "pc", "sp", "fpscr", "srr0", "lslr", "decr", "decr_status"
 136     };
 137
 138   if (reg_nr < 0)
 139     return NULL;
 140   if (reg_nr >= sizeof register_names / sizeof *register_names)
 141     return NULL;
 142
 143   return register_names[reg_nr];
 144 }
 145
 146 static struct type *
 147 spu_register_type (struct gdbarch *gdbarch, int reg_nr)
 148 {
 149   if (reg_nr < SPU_NUM_GPRS)
 150     return spu_builtin_type_vec128 (gdbarch);
 151
 152   switch (reg_nr)
 153     {
 154     case SPU_ID_REGNUM:
 155       return builtin_type (gdbarch)->builtin_uint32;
 156
 157     case SPU_PC_REGNUM:
 158       return builtin_type (gdbarch)->builtin_func_ptr;
 159
 160     case SPU_SP_REGNUM:
 161       return builtin_type (gdbarch)->builtin_data_ptr;
 162
 163     case SPU_FPSCR_REGNUM:
 164       return builtin_type (gdbarch)->builtin_uint128;
 165
 166     case SPU_SRR0_REGNUM:
 167       return builtin_type (gdbarch)->builtin_uint32;
 168
 169     case SPU_LSLR_REGNUM:
 170       return builtin_type (gdbarch)->builtin_uint32;
 171
 172     case SPU_DECR_REGNUM:
 173       return builtin_type (gdbarch)->builtin_uint32;
 174
 175     case SPU_DECR_STATUS_REGNUM:
 176       return builtin_type (gdbarch)->builtin_uint32;
 177
 178     default:
 179       internal_error (__FILE__, __LINE__, _("invalid regnum"));
 180     }
 181 }
 182
 183 /* Pseudo registers for preferred slots - stack pointer.  */
 184
 185 static enum register_status
 186 spu_pseudo_register_read_spu (struct regcache *regcache, const char *regname,
 187                               gdb_byte *buf)
 188 {
 189   struct gdbarch *gdbarch = get_regcache_arch (regcache);
 190   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 191   enum register_status status;
 192   gdb_byte reg[32];
 193   char annex[32];
 194   ULONGEST id;
 195   ULONGEST ul;
 196
 197   status = regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
 198   if (status != REG_VALID)
 199     return status;
 200   xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
 201   memset (reg, 0, sizeof reg);
 202   target_read (&current_target, TARGET_OBJECT_SPU, annex,
 203                reg, 0, sizeof reg);
 204
 205   ul = strtoulst ((char *) reg, NULL, 16);
 206   store_unsigned_integer (buf, 4, byte_order, ul);
 207   return REG_VALID;
 208 }
 209
 210 static enum register_status
 211 spu_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
 212                           int regnum, gdb_byte *buf)
 213 {
 214   gdb_byte reg[16];
 215   char annex[32];
 216   ULONGEST id;
 217   enum register_status status;
 218
 219   switch (regnum)
 220     {
 221     case SPU_SP_REGNUM:
 222       status = regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
 223       if (status != REG_VALID)
 224         return status;
 225       memcpy (buf, reg, 4);
 226       return status;
 227
 228     case SPU_FPSCR_REGNUM:
 229       status = regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
 230       if (status != REG_VALID)
 231         return status;
 232       xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
 233       target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
 234       return status;
 235
 236     case SPU_SRR0_REGNUM:
 237       return spu_pseudo_register_read_spu (regcache, "srr0", buf);
 238
 239     case SPU_LSLR_REGNUM:
 240       return spu_pseudo_register_read_spu (regcache, "lslr", buf);
 241
 242     case SPU_DECR_REGNUM:
 243       return spu_pseudo_register_read_spu (regcache, "decr", buf);
 244
 245     case SPU_DECR_STATUS_REGNUM:
 246       return spu_pseudo_register_read_spu (regcache, "decr_status", buf);
 247
 248     default:
 249       internal_error (__FILE__, __LINE__, _("invalid regnum"));
 250     }
 251 }
 252
 253 static void
 254 spu_pseudo_register_write_spu (struct regcache *regcache, const char *regname,
 255                                const gdb_byte *buf)
 256 {
 257   struct gdbarch *gdbarch = get_regcache_arch (regcache);
 258   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 259   char reg[32];
 260   char annex[32];
 261   ULONGEST id;
 262
 263   regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
 264   xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
 265   xsnprintf (reg, sizeof reg, "0x%s",
 266              phex_nz (extract_unsigned_integer (buf, 4, byte_order), 4));
 267   target_write (&current_target, TARGET_OBJECT_SPU, annex,
 268                 (gdb_byte *) reg, 0, strlen (reg));
 269 }
 270
 271 static void
 272 spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
 273                            int regnum, const gdb_byte *buf)
 274 {
 275   gdb_byte reg[16];
 276   char annex[32];
 277   ULONGEST id;
 278
 279   switch (regnum)
 280     {
 281     case SPU_SP_REGNUM:
 282       regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
 283       memcpy (reg, buf, 4);
 284       regcache_raw_write (regcache, SPU_RAW_SP_REGNUM, reg);
 285       break;
 286
 287     case SPU_FPSCR_REGNUM:
 288       regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
 289       xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
 290       target_write (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
 291       break;
 292
 293     case SPU_SRR0_REGNUM:
 294       spu_pseudo_register_write_spu (regcache, "srr0", buf);
 295       break;
 296
 297     case SPU_LSLR_REGNUM:
 298       spu_pseudo_register_write_spu (regcache, "lslr", buf);
 299       break;
 300
 301     case SPU_DECR_REGNUM:
 302       spu_pseudo_register_write_spu (regcache, "decr", buf);
 303       break;
 304
 305     case SPU_DECR_STATUS_REGNUM:
 306       spu_pseudo_register_write_spu (regcache, "decr_status", buf);
 307       break;
 308
 309     default:
 310       internal_error (__FILE__, __LINE__, _("invalid regnum"));
 311     }
 312 }
 313
 314 static int
 315 spu_ax_pseudo_register_collect (struct gdbarch *gdbarch,
 316                                 struct agent_expr *ax, int regnum)
 317 {
 318   switch (regnum)
 319     {
 320     case SPU_SP_REGNUM:
 321       ax_reg_mask (ax, SPU_RAW_SP_REGNUM);
 322       return 0;
 323
 324     case SPU_FPSCR_REGNUM:
 325     case SPU_SRR0_REGNUM:
 326     case SPU_LSLR_REGNUM:
 327     case SPU_DECR_REGNUM:
 328     case SPU_DECR_STATUS_REGNUM:
 329       return -1;
 330
 331     default:
 332       internal_error (__FILE__, __LINE__, _("invalid regnum"));
 333     }
 334 }
 335
 336 static int
 337 spu_ax_pseudo_register_push_stack (struct gdbarch *gdbarch,
 338                                    struct agent_expr *ax, int regnum)
 339 {
 340   switch (regnum)
 341     {
 342     case SPU_SP_REGNUM:
 343       ax_reg (ax, SPU_RAW_SP_REGNUM);
 344       return 0;
 345
 346     case SPU_FPSCR_REGNUM:
 347     case SPU_SRR0_REGNUM:
 348     case SPU_LSLR_REGNUM:
 349     case SPU_DECR_REGNUM:
 350     case SPU_DECR_STATUS_REGNUM:
 351       return -1;
 352
 353     default:
 354       internal_error (__FILE__, __LINE__, _("invalid regnum"));
 355     }
 356 }
 357
 358
 359 /* Value conversion -- access scalar values at the preferred slot.  */
 360
 361 static struct value *
 362 spu_value_from_register (struct gdbarch *gdbarch, struct type *type,
 363                          int regnum, struct frame_id frame_id)
 364 {
 365   struct value *value = default_value_from_register (gdbarch, type,
 366                                                      regnum, frame_id);
 367   int len = TYPE_LENGTH (type);
 368
 369   if (regnum < SPU_NUM_GPRS && len < 16)
 370     {
 371       int preferred_slot = len < 4 ? 4 - len : 0;
 372       set_value_offset (value, preferred_slot);
 373     }
 374
 375   return value;
 376 }
 377
 378 /* Register groups.  */
 379
 380 static int
 381 spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
 382                          struct reggroup *group)
 383 {
 384   /* Registers displayed via 'info regs'.  */
 385   if (group == general_reggroup)
 386     return 1;
 387
 388   /* Registers displayed via 'info float'.  */
 389   if (group == float_reggroup)
 390     return 0;
 391
 392   /* Registers that need to be saved/restored in order to
 393      push or pop frames.  */
 394   if (group == save_reggroup || group == restore_reggroup)
 395     return 1;
 396
 397   return default_register_reggroup_p (gdbarch, regnum, group);
 398 }
 399
 400 /* DWARF-2 register numbers.  */
 401
 402 static int
 403 spu_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
 404 {
 405   /* Use cooked instead of raw SP.  */
 406   return (reg == SPU_RAW_SP_REGNUM)? SPU_SP_REGNUM : reg;
 407 }
 408
 409
 410 /* Address handling.  */
 411
 412 static int
 413 spu_gdbarch_id (struct gdbarch *gdbarch)
 414 {
 415   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
 416   int id = tdep->id;
 417
 418   /* The objfile architecture of a standalone SPU executable does not
 419      provide an SPU ID.  Retrieve it from the objfile's relocated
 420      address range in this special case.  */
 421   if (id == -1
 422       && symfile_objfile && symfile_objfile->obfd
 423       && bfd_get_arch (symfile_objfile->obfd) == bfd_arch_spu
 424       && symfile_objfile->sections != symfile_objfile->sections_end)
 425     id = SPUADDR_SPU (obj_section_addr (symfile_objfile->sections));
 426
 427   return id;
 428 }
 429
 430 static int
 431 spu_address_class_type_flags (int byte_size, int dwarf2_addr_class)
 432 {
 433   if (dwarf2_addr_class == 1)
 434     return TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1;
 435   else
 436     return 0;
 437 }
 438
 439 static const char *
 440 spu_address_class_type_flags_to_name (struct gdbarch *gdbarch, int type_flags)
 441 {
 442   if (type_flags & TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1)
 443     return "__ea";
 444   else
 445     return NULL;
 446 }
 447
 448 static int
 449 spu_address_class_name_to_type_flags (struct gdbarch *gdbarch,
 450                                       const char *name, int *type_flags_ptr)
 451 {
 452   if (strcmp (name, "__ea") == 0)
 453     {
 454       *type_flags_ptr = TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1;
 455       return 1;
 456     }
 457   else
 458    return 0;
 459 }
 460
 461 static void
 462 spu_address_to_pointer (struct gdbarch *gdbarch,
 463                         struct type *type, gdb_byte *buf, CORE_ADDR addr)
 464 {
 465   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 466   store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order,
 467                           SPUADDR_ADDR (addr));
 468 }
 469
 470 static CORE_ADDR
 471 spu_pointer_to_address (struct gdbarch *gdbarch,
 472                         struct type *type, const gdb_byte *buf)
 473 {
 474   int id = spu_gdbarch_id (gdbarch);
 475   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 476   ULONGEST addr
 477     = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);
 478
 479   /* Do not convert __ea pointers.  */
 480   if (TYPE_ADDRESS_CLASS_1 (type))
 481     return addr;
 482
 483   return addr? SPUADDR (id, addr) : 0;
 484 }
 485
 486 static CORE_ADDR
 487 spu_integer_to_address (struct gdbarch *gdbarch,
 488                         struct type *type, const gdb_byte *buf)
 489 {
 490   int id = spu_gdbarch_id (gdbarch);
 491   ULONGEST addr = unpack_long (type, buf);
 492
 493   return SPUADDR (id, addr);
 494 }
 495
 496
 497 /* Decoding SPU instructions.  */
 498
 499 enum
 500   {
 501     op_lqd   = 0x34,
 502     op_lqx   = 0x3c4,
 503     op_lqa   = 0x61,
 504     op_lqr   = 0x67,
 505     op_stqd  = 0x24,
 506     op_stqx  = 0x144,
 507     op_stqa  = 0x41,
 508     op_stqr  = 0x47,
 509
 510     op_il    = 0x081,
 511     op_ila   = 0x21,
 512     op_a     = 0x0c0,
 513     op_ai    = 0x1c,
 514
 515     op_selb  = 0x8,
 516
 517     op_br    = 0x64,
 518     op_bra   = 0x60,
 519     op_brsl  = 0x66,
 520     op_brasl = 0x62,
 521     op_brnz  = 0x42,
 522     op_brz   = 0x40,
 523     op_brhnz = 0x46,
 524     op_brhz  = 0x44,
 525     op_bi    = 0x1a8,
 526     op_bisl  = 0x1a9,
 527     op_biz   = 0x128,
 528     op_binz  = 0x129,
 529     op_bihz  = 0x12a,
 530     op_bihnz = 0x12b,
 531   };
 532
 533 static int
 534 is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb)
 535 {
 536   if ((insn >> 21) == op)
 537     {
 538       *rt = insn & 127;
 539       *ra = (insn >> 7) & 127;
 540       *rb = (insn >> 14) & 127;
 541       return 1;
 542     }
 543
 544   return 0;
 545 }
 546
 547 static int
 548 is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc)
 549 {
 550   if ((insn >> 28) == op)
 551     {
 552       *rt = (insn >> 21) & 127;
 553       *ra = (insn >> 7) & 127;
 554       *rb = (insn >> 14) & 127;
 555       *rc = insn & 127;
 556       return 1;
 557     }
 558
 559   return 0;
 560 }
 561
 562 static int
 563 is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7)
 564 {
 565   if ((insn >> 21) == op)
 566     {
 567       *rt = insn & 127;
 568       *ra = (insn >> 7) & 127;
 569       *i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40;
 570       return 1;
 571     }
 572
 573   return 0;
 574 }
 575
 576 static int
 577 is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10)
 578 {
 579   if ((insn >> 24) == op)
 580     {
 581       *rt = insn & 127;
 582       *ra = (insn >> 7) & 127;
 583       *i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200;
 584       return 1;
 585     }
 586
 587   return 0;
 588 }
 589
 590 static int
 591 is_ri16 (unsigned int insn, int op, int *rt, int *i16)
 592 {
 593   if ((insn >> 23) == op)
 594     {
 595       *rt = insn & 127;
 596       *i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000;
 597       return 1;
 598     }
 599
 600   return 0;
 601 }
 602
 603 static int
 604 is_ri18 (unsigned int insn, int op, int *rt, int *i18)
 605 {
 606   if ((insn >> 25) == op)
 607     {
 608       *rt = insn & 127;
 609       *i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000;
 610       return 1;
 611     }
 612
 613   return 0;
 614 }
 615
 616 static int
 617 is_branch (unsigned int insn, int *offset, int *reg)
 618 {
 619   int rt, i7, i16;
 620
 621   if (is_ri16 (insn, op_br, &rt, &i16)
 622       || is_ri16 (insn, op_brsl, &rt, &i16)
 623       || is_ri16 (insn, op_brnz, &rt, &i16)
 624       || is_ri16 (insn, op_brz, &rt, &i16)
 625       || is_ri16 (insn, op_brhnz, &rt, &i16)
 626       || is_ri16 (insn, op_brhz, &rt, &i16))
 627     {
 628       *reg = SPU_PC_REGNUM;
 629       *offset = i16 << 2;
 630       return 1;
 631     }
 632
 633   if (is_ri16 (insn, op_bra, &rt, &i16)
 634       || is_ri16 (insn, op_brasl, &rt, &i16))
 635     {
 636       *reg = -1;
 637       *offset = i16 << 2;
 638       return 1;
 639     }
 640
 641   if (is_ri7 (insn, op_bi, &rt, reg, &i7)
 642       || is_ri7 (insn, op_bisl, &rt, reg, &i7)
 643       || is_ri7 (insn, op_biz, &rt, reg, &i7)
 644       || is_ri7 (insn, op_binz, &rt, reg, &i7)
 645       || is_ri7 (insn, op_bihz, &rt, reg, &i7)
 646       || is_ri7 (insn, op_bihnz, &rt, reg, &i7))
 647     {
 648       *offset = 0;
 649       return 1;
 650     }
 651
 652   return 0;
 653 }
 654
 655
 656 /* Prolog parsing.  */
 657
 658 struct spu_prologue_data
 659   {
 660     /* Stack frame size.  -1 if analysis was unsuccessful.  */
 661     int size;
 662
 663     /* How to find the CFA.  The CFA is equal to SP at function entry.  */
 664     int cfa_reg;
 665     int cfa_offset;
 666
 667     /* Offset relative to CFA where a register is saved.  -1 if invalid.  */
 668     int reg_offset[SPU_NUM_GPRS];
 669   };
 670
 671 static CORE_ADDR
 672 spu_analyze_prologue (struct gdbarch *gdbarch,
 673                       CORE_ADDR start_pc, CORE_ADDR end_pc,
 674                       struct spu_prologue_data *data)
 675 {
 676   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 677   int found_sp = 0;
 678   int found_fp = 0;
 679   int found_lr = 0;
 680   int found_bc = 0;
 681   int reg_immed[SPU_NUM_GPRS];
 682   gdb_byte buf[16];
 683   CORE_ADDR prolog_pc = start_pc;
 684   CORE_ADDR pc;
 685   int i;
 686
 687
 688   /* Initialize DATA to default values.  */
 689   data->size = -1;
 690
 691   data->cfa_reg = SPU_RAW_SP_REGNUM;
 692   data->cfa_offset = 0;
 693
 694   for (i = 0; i < SPU_NUM_GPRS; i++)
 695     data->reg_offset[i] = -1;
 696
 697   /* Set up REG_IMMED array.  This is non-zero for a register if we know its
 698      preferred slot currently holds this immediate value.  */
 699   for (i = 0; i < SPU_NUM_GPRS; i++)
 700       reg_immed[i] = 0;
 701
 702   /* Scan instructions until the first branch.
 703
 704      The following instructions are important prolog components:
 705
 706         - The first instruction to set up the stack pointer.
 707         - The first instruction to set up the frame pointer.
 708         - The first instruction to save the link register.
 709         - The first instruction to save the backchain.
 710
 711      We return the instruction after the latest of these four,
 712      or the incoming PC if none is found.  The first instruction
 713      to set up the stack pointer also defines the frame size.
 714
 715      Note that instructions saving incoming arguments to their stack
 716      slots are not counted as important, because they are hard to
 717      identify with certainty.  This should not matter much, because
 718      arguments are relevant only in code compiled with debug data,
 719      and in such code the GDB core will advance until the first source
 720      line anyway, using SAL data.
 721
 722      For purposes of stack unwinding, we analyze the following types
 723      of instructions in addition:
 724
 725       - Any instruction adding to the current frame pointer.
 726       - Any instruction loading an immediate constant into a register.
 727       - Any instruction storing a register onto the stack.
 728
 729      These are used to compute the CFA and REG_OFFSET output.  */
 730
 731   for (pc = start_pc; pc < end_pc; pc += 4)
 732     {
 733       unsigned int insn;
 734       int rt, ra, rb, rc, immed;
 735
 736       if (target_read_memory (pc, buf, 4))
 737         break;
 738       insn = extract_unsigned_integer (buf, 4, byte_order);
 739
 740       /* AI is the typical instruction to set up a stack frame.
 741          It is also used to initialize the frame pointer.  */
 742       if (is_ri10 (insn, op_ai, &rt, &ra, &immed))
 743         {
 744           if (rt == data->cfa_reg && ra == data->cfa_reg)
 745             data->cfa_offset -= immed;
 746
 747           if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
 748               && !found_sp)
 749             {
 750               found_sp = 1;
 751               prolog_pc = pc + 4;
 752
 753               data->size = -immed;
 754             }
 755           else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM
 756                    && !found_fp)
 757             {
 758               found_fp = 1;
 759               prolog_pc = pc + 4;
 760
 761               data->cfa_reg = SPU_FP_REGNUM;
 762               data->cfa_offset -= immed;
 763             }
 764         }
 765
 766       /* A is used to set up stack frames of size >= 512 bytes.
 767          If we have tracked the contents of the addend register,
 768          we can handle this as well.  */
 769       else if (is_rr (insn, op_a, &rt, &ra, &rb))
 770         {
 771           if (rt == data->cfa_reg && ra == data->cfa_reg)
 772             {
 773               if (reg_immed[rb] != 0)
 774                 data->cfa_offset -= reg_immed[rb];
 775               else
 776                 data->cfa_reg = -1;  /* We don't know the CFA any more.  */
 777             }
 778
 779           if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
 780               && !found_sp)
 781             {
 782               found_sp = 1;
 783               prolog_pc = pc + 4;
 784
 785               if (reg_immed[rb] != 0)
 786                 data->size = -reg_immed[rb];
 787             }
 788         }
 789
 790       /* We need to track IL and ILA used to load immediate constants
 791          in case they are later used as input to an A instruction.  */
 792       else if (is_ri16 (insn, op_il, &rt, &immed))
 793         {
 794           reg_immed[rt] = immed;
 795
 796           if (rt == SPU_RAW_SP_REGNUM && !found_sp)
 797             found_sp = 1;
 798         }
 799
 800       else if (is_ri18 (insn, op_ila, &rt, &immed))
 801         {
 802           reg_immed[rt] = immed & 0x3ffff;
 803
 804           if (rt == SPU_RAW_SP_REGNUM && !found_sp)
 805             found_sp = 1;
 806         }
 807
 808       /* STQD is used to save registers to the stack.  */
 809       else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed))
 810         {
 811           if (ra == data->cfa_reg)
 812             data->reg_offset[rt] = data->cfa_offset - (immed << 4);
 813
 814           if (ra == data->cfa_reg && rt == SPU_LR_REGNUM
 815               && !found_lr)
 816             {
 817               found_lr = 1;
 818               prolog_pc = pc + 4;
 819             }
 820
 821           if (ra == SPU_RAW_SP_REGNUM
 822               && (found_sp? immed == 0 : rt == SPU_RAW_SP_REGNUM)
 823               && !found_bc)
 824             {
 825               found_bc = 1;
 826               prolog_pc = pc + 4;
 827             }
 828         }
 829
 830       /* _start uses SELB to set up the stack pointer.  */
 831       else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc))
 832         {
 833           if (rt == SPU_RAW_SP_REGNUM && !found_sp)
 834             found_sp = 1;
 835         }
 836
 837       /* We terminate if we find a branch.  */
 838       else if (is_branch (insn, &immed, &ra))
 839         break;
 840     }
 841
 842
 843   /* If we successfully parsed until here, and didn't find any instruction
 844      modifying SP, we assume we have a frameless function.  */
 845   if (!found_sp)
 846     data->size = 0;
 847
 848   /* Return cooked instead of raw SP.  */
 849   if (data->cfa_reg == SPU_RAW_SP_REGNUM)
 850     data->cfa_reg = SPU_SP_REGNUM;
 851
 852   return prolog_pc;
 853 }
 854
 855 /* Return the first instruction after the prologue starting at PC.  */
 856 static CORE_ADDR
 857 spu_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
 858 {
 859   struct spu_prologue_data data;
 860   return spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data);
 861 }
 862
 863 /* Return the frame pointer in use at address PC.  */
 864 static void
 865 spu_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc,
 866                            int *reg, LONGEST *offset)
 867 {
 868   struct spu_prologue_data data;
 869   spu_analyze_prologue (gdbarch, pc, (CORE_ADDR)-1, &data);
 870
 871   if (data.size != -1 && data.cfa_reg != -1)
 872     {
 873       /* The 'frame pointer' address is CFA minus frame size.  */
 874       *reg = data.cfa_reg;
 875       *offset = data.cfa_offset - data.size;
 876     }
 877   else
 878     {
 879       /* ??? We don't really know ...  */
 880       *reg = SPU_SP_REGNUM;
 881       *offset = 0;
 882     }
 883 }
 884
 885 /* Return true if we are in the function's epilogue, i.e. after the
 886    instruction that destroyed the function's stack frame.
 887
 888    1) scan forward from the point of execution:
 889        a) If you find an instruction that modifies the stack pointer
 890           or transfers control (except a return), execution is not in
 891           an epilogue, return.
 892        b) Stop scanning if you find a return instruction or reach the
 893           end of the function or reach the hard limit for the size of
 894           an epilogue.
 895    2) scan backward from the point of execution:
 896         a) If you find an instruction that modifies the stack pointer,
 897             execution *is* in an epilogue, return.
 898         b) Stop scanning if you reach an instruction that transfers
 899            control or the beginning of the function or reach the hard
 900            limit for the size of an epilogue.  */
 901
 902 static int
 903 spu_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
 904 {
 905   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 906   CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
 907   bfd_byte buf[4];
 908   unsigned int insn;
 909   int rt, ra, rb, immed;
 910
 911   /* Find the search limits based on function boundaries and hard limit.
 912      We assume the epilogue can be up to 64 instructions long.  */
 913
 914   const int spu_max_epilogue_size = 64 * 4;
 915
 916   if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
 917     return 0;
 918
 919   if (pc - func_start < spu_max_epilogue_size)
 920     epilogue_start = func_start;
 921   else
 922     epilogue_start = pc - spu_max_epilogue_size;
 923
 924   if (func_end - pc < spu_max_epilogue_size)
 925     epilogue_end = func_end;
 926   else
 927     epilogue_end = pc + spu_max_epilogue_size;
 928
 929   /* Scan forward until next 'bi $0'.  */
 930
 931   for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += 4)
 932     {
 933       if (target_read_memory (scan_pc, buf, 4))
 934         return 0;
 935       insn = extract_unsigned_integer (buf, 4, byte_order);
 936
 937       if (is_branch (insn, &immed, &ra))
 938         {
 939           if (immed == 0 && ra == SPU_LR_REGNUM)
 940             break;
 941
 942           return 0;
 943         }
 944
 945       if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
 946           || is_rr (insn, op_a, &rt, &ra, &rb)
 947           || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
 948         {
 949           if (rt == SPU_RAW_SP_REGNUM)
 950             return 0;
 951         }
 952     }
 953
 954   if (scan_pc >= epilogue_end)
 955     return 0;
 956
 957   /* Scan backward until adjustment to stack pointer (R1).  */
 958
 959   for (scan_pc = pc - 4; scan_pc >= epilogue_start; scan_pc -= 4)
 960     {
 961       if (target_read_memory (scan_pc, buf, 4))
 962         return 0;
 963       insn = extract_unsigned_integer (buf, 4, byte_order);
 964
 965       if (is_branch (insn, &immed, &ra))
 966         return 0;
 967
 968       if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
 969           || is_rr (insn, op_a, &rt, &ra, &rb)
 970           || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
 971         {
 972           if (rt == SPU_RAW_SP_REGNUM)
 973             return 1;
 974         }
 975     }
 976
 977   return 0;
 978 }
 979
 980
 981 /* Normal stack frames.  */
 982
 983 struct spu_unwind_cache
 984 {
 985   CORE_ADDR func;
 986   CORE_ADDR frame_base;
 987   CORE_ADDR local_base;
 988
 989   struct trad_frame_saved_reg *saved_regs;
 990 };
 991
 992 static struct spu_unwind_cache *
 993 spu_frame_unwind_cache (struct frame_info *this_frame,
 994                         void **this_prologue_cache)
 995 {
 996   struct gdbarch *gdbarch = get_frame_arch (this_frame);
 997   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
 998   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 999   struct spu_unwind_cache *info;
1000   struct spu_prologue_data data;
1001   CORE_ADDR id = tdep->id;
1002   gdb_byte buf[16];
1003
1004   if (*this_prologue_cache)
1005     return *this_prologue_cache;
1006
1007   info = FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache);
1008   *this_prologue_cache = info;
1009   info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1010   info->frame_base = 0;
1011   info->local_base = 0;
1012
1013   /* Find the start of the current function, and analyze its prologue.  */
1014   info->func = get_frame_func (this_frame);
1015   if (info->func == 0)
1016     {
1017       /* Fall back to using the current PC as frame ID.  */
1018       info->func = get_frame_pc (this_frame);
1019       data.size = -1;
1020     }
1021   else
1022     spu_analyze_prologue (gdbarch, info->func, get_frame_pc (this_frame),
1023                           &data);
1024
1025   /* If successful, use prologue analysis data.  */
1026   if (data.size != -1 && data.cfa_reg != -1)
1027     {
1028       CORE_ADDR cfa;
1029       int i;
1030
1031       /* Determine CFA via unwound CFA_REG plus CFA_OFFSET.  */
1032       get_frame_register (this_frame, data.cfa_reg, buf);
1033       cfa = extract_unsigned_integer (buf, 4, byte_order) + data.cfa_offset;
1034       cfa = SPUADDR (id, cfa);
1035
1036       /* Call-saved register slots.  */
1037       for (i = 0; i < SPU_NUM_GPRS; i++)
1038         if (i == SPU_LR_REGNUM
1039             || (i >= SPU_SAVED1_REGNUM && i <= SPU_SAVEDN_REGNUM))
1040           if (data.reg_offset[i] != -1)
1041             info->saved_regs[i].addr = cfa - data.reg_offset[i];
1042
1043       /* Frame bases.  */
1044       info->frame_base = cfa;
1045       info->local_base = cfa - data.size;
1046     }
1047
1048   /* Otherwise, fall back to reading the backchain link.  */
1049   else
1050     {
1051       CORE_ADDR reg;
1052       LONGEST backchain;
1053       ULONGEST lslr;
1054       int status;
1055
1056       /* Get local store limit.  */
1057       lslr = get_frame_register_unsigned (this_frame, SPU_LSLR_REGNUM);
1058       if (!lslr)
1059         lslr = (ULONGEST) -1;
1060
1061       /* Get the backchain.  */
1062       reg = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
1063       status = safe_read_memory_integer (SPUADDR (id, reg), 4, byte_order,
1064                                          &backchain);
1065
1066       /* A zero backchain terminates the frame chain.  Also, sanity
1067          check against the local store size limit.  */
1068       if (status && backchain > 0 && backchain <= lslr)
1069         {
1070           /* Assume the link register is saved into its slot.  */
1071           if (backchain + 16 <= lslr)
1072             info->saved_regs[SPU_LR_REGNUM].addr = SPUADDR (id,
1073                                                             backchain + 16);
1074
1075           /* Frame bases.  */
1076           info->frame_base = SPUADDR (id, backchain);
1077           info->local_base = SPUADDR (id, reg);
1078         }
1079     }
1080
1081   /* If we didn't find a frame, we cannot determine SP / return address.  */
1082   if (info->frame_base == 0)
1083     return info;
1084
1085   /* The previous SP is equal to the CFA.  */
1086   trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM,
1087                         SPUADDR_ADDR (info->frame_base));
1088
1089   /* Read full contents of the unwound link register in order to
1090      be able to determine the return address.  */
1091   if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM))
1092     target_read_memory (info->saved_regs[SPU_LR_REGNUM].addr, buf, 16);
1093   else
1094     get_frame_register (this_frame, SPU_LR_REGNUM, buf);
1095
1096   /* Normally, the return address is contained in the slot 0 of the
1097      link register, and slots 1-3 are zero.  For an overlay return,
1098      slot 0 contains the address of the overlay manager return stub,
1099      slot 1 contains the partition number of the overlay section to
1100      be returned to, and slot 2 contains the return address within
1101      that section.  Return the latter address in that case.  */
1102   if (extract_unsigned_integer (buf + 8, 4, byte_order) != 0)
1103     trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
1104                           extract_unsigned_integer (buf + 8, 4, byte_order));
1105   else
1106     trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
1107                           extract_unsigned_integer (buf, 4, byte_order));
1108
1109   return info;
1110 }
1111
1112 static void
1113 spu_frame_this_id (struct frame_info *this_frame,
1114                    void **this_prologue_cache, struct frame_id *this_id)
1115 {
1116   struct spu_unwind_cache *info =
1117     spu_frame_unwind_cache (this_frame, this_prologue_cache);
1118
1119   if (info->frame_base == 0)
1120     return;
1121
1122   *this_id = frame_id_build (info->frame_base, info->func);
1123 }
1124
1125 static struct value *
1126 spu_frame_prev_register (struct frame_info *this_frame,
1127                          void **this_prologue_cache, int regnum)
1128 {
1129   struct spu_unwind_cache *info
1130     = spu_frame_unwind_cache (this_frame, this_prologue_cache);
1131
1132   /* Special-case the stack pointer.  */
1133   if (regnum == SPU_RAW_SP_REGNUM)
1134     regnum = SPU_SP_REGNUM;
1135
1136   return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
1137 }
1138
1139 static const struct frame_unwind spu_frame_unwind = {
1140   NORMAL_FRAME,
1141   default_frame_unwind_stop_reason,
1142   spu_frame_this_id,
1143   spu_frame_prev_register,
1144   NULL,
1145   default_frame_sniffer
1146 };
1147
1148 static CORE_ADDR
1149 spu_frame_base_address (struct frame_info *this_frame, void **this_cache)
1150 {
1151   struct spu_unwind_cache *info
1152     = spu_frame_unwind_cache (this_frame, this_cache);
1153   return info->local_base;
1154 }
1155
1156 static const struct frame_base spu_frame_base = {
1157   &spu_frame_unwind,
1158   spu_frame_base_address,
1159   spu_frame_base_address,
1160   spu_frame_base_address
1161 };
1162
1163 static CORE_ADDR
1164 spu_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1165 {
1166   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1167   CORE_ADDR pc = frame_unwind_register_unsigned (next_frame, SPU_PC_REGNUM);
1168   /* Mask off interrupt enable bit.  */
1169   return SPUADDR (tdep->id, pc & -4);
1170 }
1171
1172 static CORE_ADDR
1173 spu_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1174 {
1175   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1176   CORE_ADDR sp = frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM);
1177   return SPUADDR (tdep->id, sp);
1178 }
1179
1180 static CORE_ADDR
1181 spu_read_pc (struct regcache *regcache)
1182 {
1183   struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
1184   ULONGEST pc;
1185   regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &pc);
1186   /* Mask off interrupt enable bit.  */
1187   return SPUADDR (tdep->id, pc & -4);
1188 }
1189
1190 static void
1191 spu_write_pc (struct regcache *regcache, CORE_ADDR pc)
1192 {
1193   /* Keep interrupt enabled state unchanged.  */
1194   ULONGEST old_pc;
1195
1196   regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &old_pc);
1197   regcache_cooked_write_unsigned (regcache, SPU_PC_REGNUM,
1198                                   (SPUADDR_ADDR (pc) & -4) | (old_pc & 3));
1199 }
1200
1201
1202 /* Cell/B.E. cross-architecture unwinder support.  */
1203
1204 struct spu2ppu_cache
1205 {
1206   struct frame_id frame_id;
1207   struct regcache *regcache;
1208 };
1209
1210 static struct gdbarch *
1211 spu2ppu_prev_arch (struct frame_info *this_frame, void **this_cache)
1212 {
1213   struct spu2ppu_cache *cache = *this_cache;
1214   return get_regcache_arch (cache->regcache);
1215 }
1216
1217 static void
1218 spu2ppu_this_id (struct frame_info *this_frame,
1219                  void **this_cache, struct frame_id *this_id)
1220 {
1221   struct spu2ppu_cache *cache = *this_cache;
1222   *this_id = cache->frame_id;
1223 }
1224
1225 static struct value *
1226 spu2ppu_prev_register (struct frame_info *this_frame,
1227                        void **this_cache, int regnum)
1228 {
1229   struct spu2ppu_cache *cache = *this_cache;
1230   struct gdbarch *gdbarch = get_regcache_arch (cache->regcache);
1231   gdb_byte *buf;
1232
1233   buf = alloca (register_size (gdbarch, regnum));
1234   regcache_cooked_read (cache->regcache, regnum, buf);
1235   return frame_unwind_got_bytes (this_frame, regnum, buf);
1236 }
1237
1238 static int
1239 spu2ppu_sniffer (const struct frame_unwind *self,
1240                  struct frame_info *this_frame, void **this_prologue_cache)
1241 {
1242   struct gdbarch *gdbarch = get_frame_arch (this_frame);
1243   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1244   CORE_ADDR base, func, backchain;
1245   gdb_byte buf[4];
1246
1247   if (gdbarch_bfd_arch_info (target_gdbarch ())->arch == bfd_arch_spu)
1248     return 0;
1249
1250   base = get_frame_sp (this_frame);
1251   func = get_frame_pc (this_frame);
1252   if (target_read_memory (base, buf, 4))
1253     return 0;
1254   backchain = extract_unsigned_integer (buf, 4, byte_order);
1255
1256   if (!backchain)
1257     {
1258       struct frame_info *fi;
1259
1260       struct spu2ppu_cache *cache
1261         = FRAME_OBSTACK_CALLOC (1, struct spu2ppu_cache);
1262
1263       cache->frame_id = frame_id_build (base + 16, func);
1264
1265       for (fi = get_next_frame (this_frame); fi; fi = get_next_frame (fi))
1266         if (gdbarch_bfd_arch_info (get_frame_arch (fi))->arch != bfd_arch_spu)
1267           break;
1268
1269       if (fi)
1270         {
1271           cache->regcache = frame_save_as_regcache (fi);
1272           *this_prologue_cache = cache;
1273           return 1;
1274         }
1275       else
1276         {
1277           struct regcache *regcache;
1278           regcache = get_thread_arch_regcache (inferior_ptid, target_gdbarch ());
1279           cache->regcache = regcache_dup (regcache);
1280           *this_prologue_cache = cache;
1281           return 1;
1282         }
1283     }
1284
1285   return 0;
1286 }
1287
1288 static void
1289 spu2ppu_dealloc_cache (struct frame_info *self, void *this_cache)
1290 {
1291   struct spu2ppu_cache *cache = this_cache;
1292   regcache_xfree (cache->regcache);
1293 }
1294
1295 static const struct frame_unwind spu2ppu_unwind = {
1296   ARCH_FRAME,
1297   default_frame_unwind_stop_reason,
1298   spu2ppu_this_id,
1299   spu2ppu_prev_register,
1300   NULL,
1301   spu2ppu_sniffer,
1302   spu2ppu_dealloc_cache,
1303   spu2ppu_prev_arch,
1304 };
1305
1306
1307 /* Function calling convention.  */
1308
1309 static CORE_ADDR
1310 spu_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1311 {
1312   return sp & ~15;
1313 }
1314
1315 static CORE_ADDR
1316 spu_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
1317                      struct value **args, int nargs, struct type *value_type,
1318                      CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
1319                      struct regcache *regcache)
1320 {
1321   /* Allocate space sufficient for a breakpoint, keeping the stack aligned.  */
1322   sp = (sp - 4) & ~15;
1323   /* Store the address of that breakpoint */
1324   *bp_addr = sp;
1325   /* The call starts at the callee's entry point.  */
1326   *real_pc = funaddr;
1327
1328   return sp;
1329 }
1330
1331 static int
1332 spu_scalar_value_p (struct type *type)
1333 {
1334   switch (TYPE_CODE (type))
1335     {
1336     case TYPE_CODE_INT:
1337     case TYPE_CODE_ENUM:
1338     case TYPE_CODE_RANGE:
1339     case TYPE_CODE_CHAR:
1340     case TYPE_CODE_BOOL:
1341     case TYPE_CODE_PTR:
1342     case TYPE_CODE_REF:
1343       return TYPE_LENGTH (type) <= 16;
1344
1345     default:
1346       return 0;
1347     }
1348 }
1349
1350 static void
1351 spu_value_to_regcache (struct regcache *regcache, int regnum,
1352                        struct type *type, const gdb_byte *in)
1353 {
1354   int len = TYPE_LENGTH (type);
1355
1356   if (spu_scalar_value_p (type))
1357     {
1358       int preferred_slot = len < 4 ? 4 - len : 0;
1359       regcache_cooked_write_part (regcache, regnum, preferred_slot, len, in);
1360     }
1361   else
1362     {
1363       while (len >= 16)
1364         {
1365           regcache_cooked_write (regcache, regnum++, in);
1366           in += 16;
1367           len -= 16;
1368         }
1369
1370       if (len > 0)
1371         regcache_cooked_write_part (regcache, regnum, 0, len, in);
1372     }
1373 }
1374
1375 static void
1376 spu_regcache_to_value (struct regcache *regcache, int regnum,
1377                        struct type *type, gdb_byte *out)
1378 {
1379   int len = TYPE_LENGTH (type);
1380
1381   if (spu_scalar_value_p (type))
1382     {
1383       int preferred_slot = len < 4 ? 4 - len : 0;
1384       regcache_cooked_read_part (regcache, regnum, preferred_slot, len, out);
1385     }
1386   else
1387     {
1388       while (len >= 16)
1389         {
1390           regcache_cooked_read (regcache, regnum++, out);
1391           out += 16;
1392           len -= 16;
1393         }
1394
1395       if (len > 0)
1396         regcache_cooked_read_part (regcache, regnum, 0, len, out);
1397     }
1398 }
1399
1400 static CORE_ADDR
1401 spu_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1402                      struct regcache *regcache, CORE_ADDR bp_addr,
1403                      int nargs, struct value **args, CORE_ADDR sp,
1404                      int struct_return, CORE_ADDR struct_addr)
1405 {
1406   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1407   CORE_ADDR sp_delta;
1408   int i;
1409   int regnum = SPU_ARG1_REGNUM;
1410   int stack_arg = -1;
1411   gdb_byte buf[16];
1412
1413   /* Set the return address.  */
1414   memset (buf, 0, sizeof buf);
1415   store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (bp_addr));
1416   regcache_cooked_write (regcache, SPU_LR_REGNUM, buf);
1417
1418   /* If STRUCT_RETURN is true, then the struct return address (in
1419      STRUCT_ADDR) will consume the first argument-passing register.
1420      Both adjust the register count and store that value.  */
1421   if (struct_return)
1422     {
1423       memset (buf, 0, sizeof buf);
1424       store_unsigned_integer (buf, 4, byte_order, SPUADDR_ADDR (struct_addr));
1425       regcache_cooked_write (regcache, regnum++, buf);
1426     }
1427
1428   /* Fill in argument registers.  */
1429   for (i = 0; i < nargs; i++)
1430     {
1431       struct value *arg = args[i];
1432       struct type *type = check_typedef (value_type (arg));
1433       const gdb_byte *contents = value_contents (arg);
1434       int n_regs = align_up (TYPE_LENGTH (type), 16) / 16;
1435
1436       /* If the argument doesn't wholly fit into registers, it and
1437          all subsequent arguments go to the stack.  */
1438       if (regnum + n_regs - 1 > SPU_ARGN_REGNUM)
1439         {
1440           stack_arg = i;
1441           break;
1442         }
1443
1444       spu_value_to_regcache (regcache, regnum, type, contents);
1445       regnum += n_regs;
1446     }
1447
1448   /* Overflow arguments go to the stack.  */
1449   if (stack_arg != -1)
1450     {
1451       CORE_ADDR ap;
1452
1453       /* Allocate all required stack size.  */
1454       for (i = stack_arg; i < nargs; i++)
1455         {
1456           struct type *type = check_typedef (value_type (args[i]));
1457           sp -= align_up (TYPE_LENGTH (type), 16);
1458         }
1459
1460       /* Fill in stack arguments.  */
1461       ap = sp;
1462       for (i = stack_arg; i < nargs; i++)
1463         {
1464           struct value *arg = args[i];
1465           struct type *type = check_typedef (value_type (arg));
1466           int len = TYPE_LENGTH (type);
1467           int preferred_slot;
1468
1469           if (spu_scalar_value_p (type))
1470             preferred_slot = len < 4 ? 4 - len : 0;
1471           else
1472             preferred_slot = 0;
1473
1474           target_write_memory (ap + preferred_slot, value_contents (arg), len);
1475           ap += align_up (TYPE_LENGTH (type), 16);
1476         }
1477     }
1478
1479   /* Allocate stack frame header.  */
1480   sp -= 32;
1481
1482   /* Store stack back chain.  */
1483   regcache_cooked_read (regcache, SPU_RAW_SP_REGNUM, buf);
1484   target_write_memory (sp, buf, 16);
1485
1486   /* Finally, update all slots of the SP register.  */
1487   sp_delta = sp - extract_unsigned_integer (buf, 4, byte_order);
1488   for (i = 0; i < 4; i++)
1489     {
1490       CORE_ADDR sp_slot = extract_unsigned_integer (buf + 4*i, 4, byte_order);
1491       store_unsigned_integer (buf + 4*i, 4, byte_order, sp_slot + sp_delta);
1492     }
1493   regcache_cooked_write (regcache, SPU_RAW_SP_REGNUM, buf);
1494
1495   return sp;
1496 }
1497
1498 static struct frame_id
1499 spu_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1500 {
1501   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1502   CORE_ADDR pc = get_frame_register_unsigned (this_frame, SPU_PC_REGNUM);
1503   CORE_ADDR sp = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
1504   return frame_id_build (SPUADDR (tdep->id, sp), SPUADDR (tdep->id, pc & -4));
1505 }
1506
1507 /* Function return value access.  */
1508
1509 static enum return_value_convention
1510 spu_return_value (struct gdbarch *gdbarch, struct value *function,
1511                   struct type *type, struct regcache *regcache,
1512                   gdb_byte *out, const gdb_byte *in)
1513 {
1514   struct type *func_type = function ? value_type (function) : NULL;
1515   enum return_value_convention rvc;
1516   int opencl_vector = 0;
1517
1518   if (func_type)
1519     {
1520       func_type = check_typedef (func_type);
1521
1522       if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
1523         func_type = check_typedef (TYPE_TARGET_TYPE (func_type));
1524
1525       if (TYPE_CODE (func_type) == TYPE_CODE_FUNC
1526           && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GDB_IBM_OpenCL
1527           && TYPE_CODE (type) == TYPE_CODE_ARRAY
1528           && TYPE_VECTOR (type))
1529         opencl_vector = 1;
1530     }
1531
1532   if (TYPE_LENGTH (type) <= (SPU_ARGN_REGNUM - SPU_ARG1_REGNUM + 1) * 16)
1533     rvc = RETURN_VALUE_REGISTER_CONVENTION;
1534   else
1535     rvc = RETURN_VALUE_STRUCT_CONVENTION;
1536
1537   if (in)
1538     {
1539       switch (rvc)
1540         {
1541         case RETURN_VALUE_REGISTER_CONVENTION:
1542           if (opencl_vector && TYPE_LENGTH (type) == 2)
1543             regcache_cooked_write_part (regcache, SPU_ARG1_REGNUM, 2, 2, in);
1544           else
1545             spu_value_to_regcache (regcache, SPU_ARG1_REGNUM, type, in);
1546           break;
1547
1548         case RETURN_VALUE_STRUCT_CONVENTION:
1549           error (_("Cannot set function return value."));
1550           break;
1551         }
1552     }
1553   else if (out)
1554     {
1555       switch (rvc)
1556         {
1557         case RETURN_VALUE_REGISTER_CONVENTION:
1558           if (opencl_vector && TYPE_LENGTH (type) == 2)
1559             regcache_cooked_read_part (regcache, SPU_ARG1_REGNUM, 2, 2, out);
1560           else
1561             spu_regcache_to_value (regcache, SPU_ARG1_REGNUM, type, out);
1562           break;
1563
1564         case RETURN_VALUE_STRUCT_CONVENTION:
1565           error (_("Function return value unknown."));
1566           break;
1567         }
1568     }
1569
1570   return rvc;
1571 }
1572
1573
1574 /* Breakpoints.  */
1575
1576 static const gdb_byte *
1577 spu_breakpoint_from_pc (struct gdbarch *gdbarch,
1578                         CORE_ADDR * pcptr, int *lenptr)
1579 {
1580   static const gdb_byte breakpoint[] = { 0x00, 0x00, 0x3f, 0xff };
1581
1582   *lenptr = sizeof breakpoint;
1583   return breakpoint;
1584 }
1585
1586 static int
1587 spu_memory_remove_breakpoint (struct gdbarch *gdbarch,
1588                               struct bp_target_info *bp_tgt)
1589 {
1590   /* We work around a problem in combined Cell/B.E. debugging here.  Consider
1591      that in a combined application, we have some breakpoints inserted in SPU
1592      code, and now the application forks (on the PPU side).  GDB common code
1593      will assume that the fork system call copied all breakpoints into the new
1594      process' address space, and that all those copies now need to be removed
1595      (see breakpoint.c:detach_breakpoints).
1596
1597      While this is certainly true for PPU side breakpoints, it is not true
1598      for SPU side breakpoints.  fork will clone the SPU context file
1599      descriptors, so that all the existing SPU contexts are in accessible
1600      in the new process.  However, the contents of the SPU contexts themselves
1601      are *not* cloned.  Therefore the effect of detach_breakpoints is to
1602      remove SPU breakpoints from the *original* SPU context's local store
1603      -- this is not the correct behaviour.
1604
1605      The workaround is to check whether the PID we are asked to remove this
1606      breakpoint from (i.e. ptid_get_pid (inferior_ptid)) is different from the
1607      PID of the current inferior (i.e. current_inferior ()->pid).  This is only
1608      true in the context of detach_breakpoints.  If so, we simply do nothing.
1609      [ Note that for the fork child process, it does not matter if breakpoints
1610      remain inserted, because those SPU contexts are not runnable anyway --
1611      the Linux kernel allows only the original process to invoke spu_run.  */
1612
1613   if (ptid_get_pid (inferior_ptid) != current_inferior ()->pid)
1614     return 0;
1615
1616   return default_memory_remove_breakpoint (gdbarch, bp_tgt);
1617 }
1618
1619
1620 /* Software single-stepping support.  */
1621
1622 static int
1623 spu_software_single_step (struct frame_info *frame)
1624 {
1625   struct gdbarch *gdbarch = get_frame_arch (frame);
1626   struct address_space *aspace = get_frame_address_space (frame);
1627   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1628   CORE_ADDR pc, next_pc;
1629   unsigned int insn;
1630   int offset, reg;
1631   gdb_byte buf[4];
1632   ULONGEST lslr;
1633
1634   pc = get_frame_pc (frame);
1635
1636   if (target_read_memory (pc, buf, 4))
1637     return 1;
1638   insn = extract_unsigned_integer (buf, 4, byte_order);
1639
1640   /* Get local store limit.  */
1641   lslr = get_frame_register_unsigned (frame, SPU_LSLR_REGNUM);
1642   if (!lslr)
1643     lslr = (ULONGEST) -1;
1644
1645   /* Next sequential instruction is at PC + 4, except if the current
1646      instruction is a PPE-assisted call, in which case it is at PC + 8.
1647      Wrap around LS limit to be on the safe side.  */
1648   if ((insn & 0xffffff00) == 0x00002100)
1649     next_pc = (SPUADDR_ADDR (pc) + 8) & lslr;
1650   else
1651     next_pc = (SPUADDR_ADDR (pc) + 4) & lslr;
1652
1653   insert_single_step_breakpoint (gdbarch,
1654                                  aspace, SPUADDR (SPUADDR_SPU (pc), next_pc));
1655
1656   if (is_branch (insn, &offset, &reg))
1657     {
1658       CORE_ADDR target = offset;
1659
1660       if (reg == SPU_PC_REGNUM)
1661         target += SPUADDR_ADDR (pc);
1662       else if (reg != -1)
1663         {
1664           int optim, unavail;
1665
1666           if (get_frame_register_bytes (frame, reg, 0, 4, buf,
1667                                          &optim, &unavail))
1668             target += extract_unsigned_integer (buf, 4, byte_order) & -4;
1669           else
1670             {
1671               if (optim)
1672                 throw_error (OPTIMIZED_OUT_ERROR,
1673                              _("Could not determine address of "
1674                                "single-step breakpoint."));
1675               if (unavail)
1676                 throw_error (NOT_AVAILABLE_ERROR,
1677                              _("Could not determine address of "
1678                                "single-step breakpoint."));
1679             }
1680         }
1681
1682       target = target & lslr;
1683       if (target != next_pc)
1684         insert_single_step_breakpoint (gdbarch, aspace,
1685                                        SPUADDR (SPUADDR_SPU (pc), target));
1686     }
1687
1688   return 1;
1689 }
1690
1691
1692 /* Longjmp support.  */
1693
1694 static int
1695 spu_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1696 {
1697   struct gdbarch *gdbarch = get_frame_arch (frame);
1698   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1699   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1700   gdb_byte buf[4];
1701   CORE_ADDR jb_addr;
1702   int optim, unavail;
1703
1704   /* Jump buffer is pointed to by the argument register $r3.  */
1705   if (!get_frame_register_bytes (frame, SPU_ARG1_REGNUM, 0, 4, buf,
1706                                  &optim, &unavail))
1707     return 0;
1708
1709   jb_addr = extract_unsigned_integer (buf, 4, byte_order);
1710   if (target_read_memory (SPUADDR (tdep->id, jb_addr), buf, 4))
1711     return 0;
1712
1713   *pc = extract_unsigned_integer (buf, 4, byte_order);
1714   *pc = SPUADDR (tdep->id, *pc);
1715   return 1;
1716 }
1717
1718
1719 /* Disassembler.  */
1720
1721 struct spu_dis_asm_data
1722 {
1723   struct gdbarch *gdbarch;
1724   int id;
1725 };
1726
1727 static void
1728 spu_dis_asm_print_address (bfd_vma addr, struct disassemble_info *info)
1729 {
1730   struct spu_dis_asm_data *data = info->application_data;
1731   print_address (data->gdbarch, SPUADDR (data->id, addr), info->stream);
1732 }
1733
1734 static int
1735 gdb_print_insn_spu (bfd_vma memaddr, struct disassemble_info *info)
1736 {
1737   /* The opcodes disassembler does 18-bit address arithmetic.  Make
1738      sure the SPU ID encoded in the high bits is added back when we
1739      call print_address.  */
1740   struct disassemble_info spu_info = *info;
1741   struct spu_dis_asm_data data;
1742   data.gdbarch = info->application_data;
1743   data.id = SPUADDR_SPU (memaddr);
1744
1745   spu_info.application_data = &data;
1746   spu_info.print_address_func = spu_dis_asm_print_address;
1747   return print_insn_spu (memaddr, &spu_info);
1748 }
1749
1750
1751 /* Target overlays for the SPU overlay manager.
1752
1753    See the documentation of simple_overlay_update for how the
1754    interface is supposed to work.
1755
1756    Data structures used by the overlay manager:
1757
1758    struct ovly_table
1759      {
1760         u32 vma;
1761         u32 size;
1762         u32 pos;
1763         u32 buf;
1764      } _ovly_table[];   -- one entry per overlay section
1765
1766    struct ovly_buf_table
1767      {
1768         u32 mapped;
1769      } _ovly_buf_table[];  -- one entry per overlay buffer
1770
1771    _ovly_table should never change.
1772
1773    Both tables are aligned to a 16-byte boundary, the symbols
1774    _ovly_table and _ovly_buf_table are of type STT_OBJECT and their
1775    size set to the size of the respective array. buf in _ovly_table is
1776    an index into _ovly_buf_table.
1777
1778    mapped is an index into _ovly_table.  Both the mapped and buf indices start
1779    from one to reference the first entry in their respective tables.  */
1780
1781 /* Using the per-objfile private data mechanism, we store for each
1782    objfile an array of "struct spu_overlay_table" structures, one
1783    for each obj_section of the objfile.  This structure holds two
1784    fields, MAPPED_PTR and MAPPED_VAL.  If MAPPED_PTR is zero, this
1785    is *not* an overlay section.  If it is non-zero, it represents
1786    a target address.  The overlay section is mapped iff the target
1787    integer at this location equals MAPPED_VAL.  */
1788
1789 static const struct objfile_data *spu_overlay_data;
1790
1791 struct spu_overlay_table
1792   {
1793     CORE_ADDR mapped_ptr;
1794     CORE_ADDR mapped_val;
1795   };
1796
1797 /* Retrieve the overlay table for OBJFILE.  If not already cached, read
1798    the _ovly_table data structure from the target and initialize the
1799    spu_overlay_table data structure from it.  */
1800 static struct spu_overlay_table *
1801 spu_get_overlay_table (struct objfile *objfile)
1802 {
1803   enum bfd_endian byte_order = bfd_big_endian (objfile->obfd)?
1804                    BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
1805   struct bound_minimal_symbol ovly_table_msym, ovly_buf_table_msym;
1806   CORE_ADDR ovly_table_base, ovly_buf_table_base;
1807   unsigned ovly_table_size, ovly_buf_table_size;
1808   struct spu_overlay_table *tbl;
1809   struct obj_section *osect;
1810   gdb_byte *ovly_table;
1811   int i;
1812
1813   tbl = objfile_data (objfile, spu_overlay_data);
1814   if (tbl)
1815     return tbl;
1816
1817   ovly_table_msym = lookup_minimal_symbol ("_ovly_table", NULL, objfile);
1818   if (!ovly_table_msym.minsym)
1819     return NULL;
1820
1821   ovly_buf_table_msym = lookup_minimal_symbol ("_ovly_buf_table",
1822                                                NULL, objfile);
1823   if (!ovly_buf_table_msym.minsym)
1824     return NULL;
1825
1826   ovly_table_base = BMSYMBOL_VALUE_ADDRESS (ovly_table_msym);
1827   ovly_table_size = MSYMBOL_SIZE (ovly_table_msym.minsym);
1828
1829   ovly_buf_table_base = BMSYMBOL_VALUE_ADDRESS (ovly_buf_table_msym);
1830   ovly_buf_table_size = MSYMBOL_SIZE (ovly_buf_table_msym.minsym);
1831
1832   ovly_table = xmalloc (ovly_table_size);
1833   read_memory (ovly_table_base, ovly_table, ovly_table_size);
1834
1835   tbl = OBSTACK_CALLOC (&objfile->objfile_obstack,
1836                         objfile->sections_end - objfile->sections,
1837                         struct spu_overlay_table);
1838
1839   for (i = 0; i < ovly_table_size / 16; i++)
1840     {
1841       CORE_ADDR vma  = extract_unsigned_integer (ovly_table + 16*i + 0,
1842                                                  4, byte_order);
1843       CORE_ADDR size = extract_unsigned_integer (ovly_table + 16*i + 4,
1844                                                  4, byte_order);
1845       CORE_ADDR pos  = extract_unsigned_integer (ovly_table + 16*i + 8,
1846                                                  4, byte_order);
1847       CORE_ADDR buf  = extract_unsigned_integer (ovly_table + 16*i + 12,
1848                                                  4, byte_order);
1849
1850       if (buf == 0 || (buf - 1) * 4 >= ovly_buf_table_size)
1851         continue;
1852
1853       ALL_OBJFILE_OSECTIONS (objfile, osect)
1854         if (vma == bfd_section_vma (objfile->obfd, osect->the_bfd_section)
1855             && pos == osect->the_bfd_section->filepos)
1856           {
1857             int ndx = osect - objfile->sections;
1858             tbl[ndx].mapped_ptr = ovly_buf_table_base + (buf - 1) * 4;
1859             tbl[ndx].mapped_val = i + 1;
1860             break;
1861           }
1862     }
1863
1864   xfree (ovly_table);
1865   set_objfile_data (objfile, spu_overlay_data, tbl);
1866   return tbl;
1867 }
1868
1869 /* Read _ovly_buf_table entry from the target to dermine whether
1870    OSECT is currently mapped, and update the mapped state.  */
1871 static void
1872 spu_overlay_update_osect (struct obj_section *osect)
1873 {
1874   enum bfd_endian byte_order = bfd_big_endian (osect->objfile->obfd)?
1875                    BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
1876   struct spu_overlay_table *ovly_table;
1877   CORE_ADDR id, val;
1878
1879   ovly_table = spu_get_overlay_table (osect->objfile);
1880   if (!ovly_table)
1881     return;
1882
1883   ovly_table += osect - osect->objfile->sections;
1884   if (ovly_table->mapped_ptr == 0)
1885     return;
1886
1887   id = SPUADDR_SPU (obj_section_addr (osect));
1888   val = read_memory_unsigned_integer (SPUADDR (id, ovly_table->mapped_ptr),
1889                                       4, byte_order);
1890   osect->ovly_mapped = (val == ovly_table->mapped_val);
1891 }
1892
1893 /* If OSECT is NULL, then update all sections' mapped state.
1894    If OSECT is non-NULL, then update only OSECT's mapped state.  */
1895 static void
1896 spu_overlay_update (struct obj_section *osect)
1897 {
1898   /* Just one section.  */
1899   if (osect)
1900     spu_overlay_update_osect (osect);
1901
1902   /* All sections.  */
1903   else
1904     {
1905       struct objfile *objfile;
1906
1907       ALL_OBJSECTIONS (objfile, osect)
1908         if (section_is_overlay (osect))
1909           spu_overlay_update_osect (osect);
1910     }
1911 }
1912
1913 /* Whenever a new objfile is loaded, read the target's _ovly_table.
1914    If there is one, go through all sections and make sure for non-
1915    overlay sections LMA equals VMA, while for overlay sections LMA
1916    is larger than SPU_OVERLAY_LMA.  */
1917 static void
1918 spu_overlay_new_objfile (struct objfile *objfile)
1919 {
1920   struct spu_overlay_table *ovly_table;
1921   struct obj_section *osect;
1922
1923   /* If we've already touched this file, do nothing.  */
1924   if (!objfile || objfile_data (objfile, spu_overlay_data) != NULL)
1925     return;
1926
1927   /* Consider only SPU objfiles.  */
1928   if (bfd_get_arch (objfile->obfd) != bfd_arch_spu)
1929     return;
1930
1931   /* Check if this objfile has overlays.  */
1932   ovly_table = spu_get_overlay_table (objfile);
1933   if (!ovly_table)
1934     return;
1935
1936   /* Now go and fiddle with all the LMAs.  */
1937   ALL_OBJFILE_OSECTIONS (objfile, osect)
1938     {
1939       bfd *obfd = objfile->obfd;
1940       asection *bsect = osect->the_bfd_section;
1941       int ndx = osect - objfile->sections;
1942
1943       if (ovly_table[ndx].mapped_ptr == 0)
1944         bfd_section_lma (obfd, bsect) = bfd_section_vma (obfd, bsect);
1945       else
1946         bfd_section_lma (obfd, bsect) = SPU_OVERLAY_LMA + bsect->filepos;
1947     }
1948 }
1949
1950
1951 /* Insert temporary breakpoint on "main" function of newly loaded
1952    SPE context OBJFILE.  */
1953 static void
1954 spu_catch_start (struct objfile *objfile)
1955 {
1956   struct bound_minimal_symbol minsym;
1957   struct symtab *symtab;
1958   CORE_ADDR pc;
1959   char buf[32];
1960
1961   /* Do this only if requested by "set spu stop-on-load on".  */
1962   if (!spu_stop_on_load_p)
1963     return;
1964
1965   /* Consider only SPU objfiles.  */
1966   if (!objfile || bfd_get_arch (objfile->obfd) != bfd_arch_spu)
1967     return;
1968
1969   /* The main objfile is handled differently.  */
1970   if (objfile == symfile_objfile)
1971     return;
1972
1973   /* There can be multiple symbols named "main".  Search for the
1974      "main" in *this* objfile.  */
1975   minsym = lookup_minimal_symbol ("main", NULL, objfile);
1976   if (!minsym.minsym)
1977     return;
1978
1979   /* If we have debugging information, try to use it -- this
1980      will allow us to properly skip the prologue.  */
1981   pc = BMSYMBOL_VALUE_ADDRESS (minsym);
1982   symtab = find_pc_sect_symtab (pc, MSYMBOL_OBJ_SECTION (minsym.objfile,
1983                                                          minsym.minsym));
1984   if (symtab != NULL)
1985     {
1986       const struct blockvector *bv = BLOCKVECTOR (symtab);
1987       struct block *block = BLOCKVECTOR_BLOCK (bv, GLOBAL_BLOCK);
1988       struct symbol *sym;
1989       struct symtab_and_line sal;
1990
1991       sym = lookup_block_symbol (block, "main", VAR_DOMAIN);
1992       if (sym)
1993         {
1994           fixup_symbol_section (sym, objfile);
1995           sal = find_function_start_sal (sym, 1);
1996           pc = sal.pc;
1997         }
1998     }
1999
2000   /* Use a numerical address for the set_breakpoint command to avoid having
2001      the breakpoint re-set incorrectly.  */
2002   xsnprintf (buf, sizeof buf, "*%s", core_addr_to_string (pc));
2003   create_breakpoint (get_objfile_arch (objfile), buf /* arg */,
2004                      NULL /* cond_string */, -1 /* thread */,
2005                      NULL /* extra_string */,
2006                      0 /* parse_condition_and_thread */, 1 /* tempflag */,
2007                      bp_breakpoint /* type_wanted */,
2008                      0 /* ignore_count */,
2009                      AUTO_BOOLEAN_FALSE /* pending_break_support */,
2010                      &bkpt_breakpoint_ops /* ops */, 0 /* from_tty */,
2011                      1 /* enabled */, 0 /* internal  */, 0);
2012 }
2013
2014
2015 /* Look up OBJFILE loaded into FRAME's SPU context.  */
2016 static struct objfile *
2017 spu_objfile_from_frame (struct frame_info *frame)
2018 {
2019   struct gdbarch *gdbarch = get_frame_arch (frame);
2020   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2021   struct objfile *obj;
2022
2023   if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
2024     return NULL;
2025
2026   ALL_OBJFILES (obj)
2027     {
2028       if (obj->sections != obj->sections_end
2029           && SPUADDR_SPU (obj_section_addr (obj->sections)) == tdep->id)
2030         return obj;
2031     }
2032
2033   return NULL;
2034 }
2035
2036 /* Flush cache for ea pointer access if available.  */
2037 static void
2038 flush_ea_cache (void)
2039 {
2040   struct bound_minimal_symbol msymbol;
2041   struct objfile *obj;
2042
2043   if (!has_stack_frames ())
2044     return;
2045
2046   obj = spu_objfile_from_frame (get_current_frame ());
2047   if (obj == NULL)
2048     return;
2049
2050   /* Lookup inferior function __cache_flush.  */
2051   msymbol = lookup_minimal_symbol ("__cache_flush", NULL, obj);
2052   if (msymbol.minsym != NULL)
2053     {
2054       struct type *type;
2055       CORE_ADDR addr;
2056
2057       type = objfile_type (obj)->builtin_void;
2058       type = lookup_function_type (type);
2059       type = lookup_pointer_type (type);
2060       addr = BMSYMBOL_VALUE_ADDRESS (msymbol);
2061
2062       call_function_by_hand (value_from_pointer (type, addr), 0, NULL);
2063     }
2064 }
2065
2066 /* This handler is called when the inferior has stopped.  If it is stopped in
2067    SPU architecture then flush the ea cache if used.  */
2068 static void
2069 spu_attach_normal_stop (struct bpstats *bs, int print_frame)
2070 {
2071   if (!spu_auto_flush_cache_p)
2072     return;
2073
2074   /* Temporarily reset spu_auto_flush_cache_p to avoid recursively
2075      re-entering this function when __cache_flush stops.  */
2076   spu_auto_flush_cache_p = 0;
2077   flush_ea_cache ();
2078   spu_auto_flush_cache_p = 1;
2079 }
2080
2081
2082 /* "info spu" commands.  */
2083
2084 static void
2085 info_spu_event_command (char *args, int from_tty)
2086 {
2087   struct frame_info *frame = get_selected_frame (NULL);
2088   ULONGEST event_status = 0;
2089   ULONGEST event_mask = 0;
2090   struct cleanup *chain;
2091   gdb_byte buf[100];
2092   char annex[32];
2093   LONGEST len;
2094   int id;
2095
2096   if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
2097     error (_("\"info spu\" is only supported on the SPU architecture."));
2098
2099   id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2100
2101   xsnprintf (annex, sizeof annex, "%d/event_status", id);
2102   len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2103                      buf, 0, (sizeof (buf) - 1));
2104   if (len <= 0)
2105     error (_("Could not read event_status."));
2106   buf[len] = '\0';
2107   event_status = strtoulst ((char *) buf, NULL, 16);
2108
2109   xsnprintf (annex, sizeof annex, "%d/event_mask", id);
2110   len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2111                      buf, 0, (sizeof (buf) - 1));
2112   if (len <= 0)
2113     error (_("Could not read event_mask."));
2114   buf[len] = '\0';
2115   event_mask = strtoulst ((char *) buf, NULL, 16);
2116
2117   chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "SPUInfoEvent");
2118
2119   if (ui_out_is_mi_like_p (current_uiout))
2120     {
2121       ui_out_field_fmt (current_uiout, "event_status",
2122                         "0x%s", phex_nz (event_status, 4));
2123       ui_out_field_fmt (current_uiout, "event_mask",
2124                         "0x%s", phex_nz (event_mask, 4));
2125     }
2126   else
2127     {
2128       printf_filtered (_("Event Status 0x%s\n"), phex (event_status, 4));
2129       printf_filtered (_("Event Mask   0x%s\n"), phex (event_mask, 4));
2130     }
2131
2132   do_cleanups (chain);
2133 }
2134
2135 static void
2136 info_spu_signal_command (char *args, int from_tty)
2137 {
2138   struct frame_info *frame = get_selected_frame (NULL);
2139   struct gdbarch *gdbarch = get_frame_arch (frame);
2140   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2141   ULONGEST signal1 = 0;
2142   ULONGEST signal1_type = 0;
2143   int signal1_pending = 0;
2144   ULONGEST signal2 = 0;
2145   ULONGEST signal2_type = 0;
2146   int signal2_pending = 0;
2147   struct cleanup *chain;
2148   char annex[32];
2149   gdb_byte buf[100];
2150   LONGEST len;
2151   int id;
2152
2153   if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
2154     error (_("\"info spu\" is only supported on the SPU architecture."));
2155
2156   id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2157
2158   xsnprintf (annex, sizeof annex, "%d/signal1", id);
2159   len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
2160   if (len < 0)
2161     error (_("Could not read signal1."));
2162   else if (len == 4)
2163     {
2164       signal1 = extract_unsigned_integer (buf, 4, byte_order);
2165       signal1_pending = 1;
2166     }
2167
2168   xsnprintf (annex, sizeof annex, "%d/signal1_type", id);
2169   len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2170                      buf, 0, (sizeof (buf) - 1));
2171   if (len <= 0)
2172     error (_("Could not read signal1_type."));
2173   buf[len] = '\0';
2174   signal1_type = strtoulst ((char *) buf, NULL, 16);
2175
2176   xsnprintf (annex, sizeof annex, "%d/signal2", id);
2177   len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
2178   if (len < 0)
2179     error (_("Could not read signal2."));
2180   else if (len == 4)
2181     {
2182       signal2 = extract_unsigned_integer (buf, 4, byte_order);
2183       signal2_pending = 1;
2184     }
2185
2186   xsnprintf (annex, sizeof annex, "%d/signal2_type", id);
2187   len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2188                      buf, 0, (sizeof (buf) - 1));
2189   if (len <= 0)
2190     error (_("Could not read signal2_type."));
2191   buf[len] = '\0';
2192   signal2_type = strtoulst ((char *) buf, NULL, 16);
2193
2194   chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "SPUInfoSignal");
2195
2196   if (ui_out_is_mi_like_p (current_uiout))
2197     {
2198       ui_out_field_int (current_uiout, "signal1_pending", signal1_pending);
2199       ui_out_field_fmt (current_uiout, "signal1", "0x%s", phex_nz (signal1, 4));
2200       ui_out_field_int (current_uiout, "signal1_type", signal1_type);
2201       ui_out_field_int (current_uiout, "signal2_pending", signal2_pending);
2202       ui_out_field_fmt (current_uiout, "signal2", "0x%s", phex_nz (signal2, 4));
2203       ui_out_field_int (current_uiout, "signal2_type", signal2_type);
2204     }
2205   else
2206     {
2207       if (signal1_pending)
2208         printf_filtered (_("Signal 1 control word 0x%s "), phex (signal1, 4));
2209       else
2210         printf_filtered (_("Signal 1 not pending "));
2211
2212       if (signal1_type)
2213         printf_filtered (_("(Type Or)\n"));
2214       else
2215         printf_filtered (_("(Type Overwrite)\n"));
2216
2217       if (signal2_pending)
2218         printf_filtered (_("Signal 2 control word 0x%s "), phex (signal2, 4));
2219       else
2220         printf_filtered (_("Signal 2 not pending "));
2221
2222       if (signal2_type)
2223         printf_filtered (_("(Type Or)\n"));
2224       else
2225         printf_filtered (_("(Type Overwrite)\n"));
2226     }
2227
2228   do_cleanups (chain);
2229 }
2230
2231 static void
2232 info_spu_mailbox_list (gdb_byte *buf, int nr, enum bfd_endian byte_order,
2233                        const char *field, const char *msg)
2234 {
2235   struct cleanup *chain;
2236   int i;
2237
2238   if (nr <= 0)
2239     return;
2240
2241   chain = make_cleanup_ui_out_table_begin_end (current_uiout, 1, nr, "mbox");
2242
2243   ui_out_table_header (current_uiout, 32, ui_left, field, msg);
2244   ui_out_table_body (current_uiout);
2245
2246   for (i = 0; i < nr; i++)
2247     {
2248       struct cleanup *val_chain;
2249       ULONGEST val;
2250       val_chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "mbox");
2251       val = extract_unsigned_integer (buf + 4*i, 4, byte_order);
2252       ui_out_field_fmt (current_uiout, field, "0x%s", phex (val, 4));
2253       do_cleanups (val_chain);
2254
2255       if (!ui_out_is_mi_like_p (current_uiout))
2256         printf_filtered ("\n");
2257     }
2258
2259   do_cleanups (chain);
2260 }
2261
2262 static void
2263 info_spu_mailbox_command (char *args, int from_tty)
2264 {
2265   struct frame_info *frame = get_selected_frame (NULL);
2266   struct gdbarch *gdbarch = get_frame_arch (frame);
2267   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2268   struct cleanup *chain;
2269   char annex[32];
2270   gdb_byte buf[1024];
2271   LONGEST len;
2272   int id;
2273
2274   if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
2275     error (_("\"info spu\" is only supported on the SPU architecture."));
2276
2277   id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2278
2279   chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "SPUInfoMailbox");
2280
2281   xsnprintf (annex, sizeof annex, "%d/mbox_info", id);
2282   len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2283                      buf, 0, sizeof buf);
2284   if (len < 0)
2285     error (_("Could not read mbox_info."));
2286
2287   info_spu_mailbox_list (buf, len / 4, byte_order,
2288                          "mbox", "SPU Outbound Mailbox");
2289
2290   xsnprintf (annex, sizeof annex, "%d/ibox_info", id);
2291   len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2292                      buf, 0, sizeof buf);
2293   if (len < 0)
2294     error (_("Could not read ibox_info."));
2295
2296   info_spu_mailbox_list (buf, len / 4, byte_order,
2297                          "ibox", "SPU Outbound Interrupt Mailbox");
2298
2299   xsnprintf (annex, sizeof annex, "%d/wbox_info", id);
2300   len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2301                      buf, 0, sizeof buf);
2302   if (len < 0)
2303     error (_("Could not read wbox_info."));
2304
2305   info_spu_mailbox_list (buf, len / 4, byte_order,
2306                          "wbox", "SPU Inbound Mailbox");
2307
2308   do_cleanups (chain);
2309 }
2310
2311 static ULONGEST
2312 spu_mfc_get_bitfield (ULONGEST word, int first, int last)
2313 {
2314   ULONGEST mask = ~(~(ULONGEST)0 << (last - first + 1));
2315   return (word >> (63 - last)) & mask;
2316 }
2317
2318 static void
2319 info_spu_dma_cmdlist (gdb_byte *buf, int nr, enum bfd_endian byte_order)
2320 {
2321   static char *spu_mfc_opcode[256] =
2322     {
2323     /* 00 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2324              NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2325     /* 10 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2326              NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2327     /* 20 */ "put", "putb", "putf", NULL, "putl", "putlb", "putlf", NULL,
2328              "puts", "putbs", "putfs", NULL, NULL, NULL, NULL, NULL,
2329     /* 30 */ "putr", "putrb", "putrf", NULL, "putrl", "putrlb", "putrlf", NULL,
2330              NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2331     /* 40 */ "get", "getb", "getf", NULL, "getl", "getlb", "getlf", NULL,
2332              "gets", "getbs", "getfs", NULL, NULL, NULL, NULL, NULL,
2333     /* 50 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2334              NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2335     /* 60 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2336              NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2337     /* 70 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2338              NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2339     /* 80 */ "sdcrt", "sdcrtst", NULL, NULL, NULL, NULL, NULL, NULL,
2340              NULL, "sdcrz", NULL, NULL, NULL, "sdcrst", NULL, "sdcrf",
2341     /* 90 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2342              NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2343     /* a0 */ "sndsig", "sndsigb", "sndsigf", NULL, NULL, NULL, NULL, NULL,
2344              NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2345     /* b0 */ "putlluc", NULL, NULL, NULL, "putllc", NULL, NULL, NULL,
2346              "putqlluc", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2347     /* c0 */ "barrier", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2348              "mfceieio", NULL, NULL, NULL, "mfcsync", NULL, NULL, NULL,
2349     /* d0 */ "getllar", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2350              NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2351     /* e0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2352              NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2353     /* f0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2354              NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
2355     };
2356
2357   int *seq = alloca (nr * sizeof (int));
2358   int done = 0;
2359   struct cleanup *chain;
2360   int i, j;
2361
2362
2363   /* Determine sequence in which to display (valid) entries.  */
2364   for (i = 0; i < nr; i++)
2365     {
2366       /* Search for the first valid entry all of whose
2367          dependencies are met.  */
2368       for (j = 0; j < nr; j++)
2369         {
2370           ULONGEST mfc_cq_dw3;
2371           ULONGEST dependencies;
2372
2373           if (done & (1 << (nr - 1 - j)))
2374             continue;
2375
2376           mfc_cq_dw3
2377             = extract_unsigned_integer (buf + 32*j + 24,8, byte_order);
2378           if (!spu_mfc_get_bitfield (mfc_cq_dw3, 16, 16))
2379             continue;
2380
2381           dependencies = spu_mfc_get_bitfield (mfc_cq_dw3, 0, nr - 1);
2382           if ((dependencies & done) != dependencies)
2383             continue;
2384
2385           seq[i] = j;
2386           done |= 1 << (nr - 1 - j);
2387           break;
2388         }
2389
2390       if (j == nr)
2391         break;
2392     }
2393
2394   nr = i;
2395
2396
2397   chain = make_cleanup_ui_out_table_begin_end (current_uiout, 10, nr,
2398                                                "dma_cmd");
2399
2400   ui_out_table_header (current_uiout, 7, ui_left, "opcode", "Opcode");
2401   ui_out_table_header (current_uiout, 3, ui_left, "tag", "Tag");
2402   ui_out_table_header (current_uiout, 3, ui_left, "tid", "TId");
2403   ui_out_table_header (current_uiout, 3, ui_left, "rid", "RId");
2404   ui_out_table_header (current_uiout, 18, ui_left, "ea", "EA");
2405   ui_out_table_header (current_uiout, 7, ui_left, "lsa", "LSA");
2406   ui_out_table_header (current_uiout, 7, ui_left, "size", "Size");
2407   ui_out_table_header (current_uiout, 7, ui_left, "lstaddr", "LstAddr");
2408   ui_out_table_header (current_uiout, 7, ui_left, "lstsize", "LstSize");
2409   ui_out_table_header (current_uiout, 1, ui_left, "error_p", "E");
2410
2411   ui_out_table_body (current_uiout);
2412
2413   for (i = 0; i < nr; i++)
2414     {
2415       struct cleanup *cmd_chain;
2416       ULONGEST mfc_cq_dw0;
2417       ULONGEST mfc_cq_dw1;
2418       ULONGEST mfc_cq_dw2;
2419       int mfc_cmd_opcode, mfc_cmd_tag, rclass_id, tclass_id;
2420       int list_lsa, list_size, mfc_lsa, mfc_size;
2421       ULONGEST mfc_ea;
2422       int list_valid_p, noop_valid_p, qw_valid_p, ea_valid_p, cmd_error_p;
2423
2424       /* Decode contents of MFC Command Queue Context Save/Restore Registers.
2425          See "Cell Broadband Engine Registers V1.3", section 3.3.2.1.  */
2426
2427       mfc_cq_dw0
2428         = extract_unsigned_integer (buf + 32*seq[i], 8, byte_order);
2429       mfc_cq_dw1
2430         = extract_unsigned_integer (buf + 32*seq[i] + 8, 8, byte_order);
2431       mfc_cq_dw2
2432         = extract_unsigned_integer (buf + 32*seq[i] + 16, 8, byte_order);
2433
2434       list_lsa = spu_mfc_get_bitfield (mfc_cq_dw0, 0, 14);
2435       list_size = spu_mfc_get_bitfield (mfc_cq_dw0, 15, 26);
2436       mfc_cmd_opcode = spu_mfc_get_bitfield (mfc_cq_dw0, 27, 34);
2437       mfc_cmd_tag = spu_mfc_get_bitfield (mfc_cq_dw0, 35, 39);
2438       list_valid_p = spu_mfc_get_bitfield (mfc_cq_dw0, 40, 40);
2439       rclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 41, 43);
2440       tclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 44, 46);
2441
2442       mfc_ea = spu_mfc_get_bitfield (mfc_cq_dw1, 0, 51) << 12
2443                 | spu_mfc_get_bitfield (mfc_cq_dw2, 25, 36);
2444
2445       mfc_lsa = spu_mfc_get_bitfield (mfc_cq_dw2, 0, 13);
2446       mfc_size = spu_mfc_get_bitfield (mfc_cq_dw2, 14, 24);
2447       noop_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 37, 37);
2448       qw_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 38, 38);
2449       ea_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 39, 39);
2450       cmd_error_p = spu_mfc_get_bitfield (mfc_cq_dw2, 40, 40);
2451
2452       cmd_chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "cmd");
2453
2454       if (spu_mfc_opcode[mfc_cmd_opcode])
2455         ui_out_field_string (current_uiout, "opcode", spu_mfc_opcode[mfc_cmd_opcode]);
2456       else
2457         ui_out_field_int (current_uiout, "opcode", mfc_cmd_opcode);
2458
2459       ui_out_field_int (current_uiout, "tag", mfc_cmd_tag);
2460       ui_out_field_int (current_uiout, "tid", tclass_id);
2461       ui_out_field_int (current_uiout, "rid", rclass_id);
2462
2463       if (ea_valid_p)
2464         ui_out_field_fmt (current_uiout, "ea", "0x%s", phex (mfc_ea, 8));
2465       else
2466         ui_out_field_skip (current_uiout, "ea");
2467
2468       ui_out_field_fmt (current_uiout, "lsa", "0x%05x", mfc_lsa << 4);
2469       if (qw_valid_p)
2470         ui_out_field_fmt (current_uiout, "size", "0x%05x", mfc_size << 4);
2471       else
2472         ui_out_field_fmt (current_uiout, "size", "0x%05x", mfc_size);
2473
2474       if (list_valid_p)
2475         {
2476           ui_out_field_fmt (current_uiout, "lstaddr", "0x%05x", list_lsa << 3);
2477           ui_out_field_fmt (current_uiout, "lstsize", "0x%05x", list_size << 3);
2478         }
2479       else
2480         {
2481           ui_out_field_skip (current_uiout, "lstaddr");
2482           ui_out_field_skip (current_uiout, "lstsize");
2483         }
2484
2485       if (cmd_error_p)
2486         ui_out_field_string (current_uiout, "error_p", "*");
2487       else
2488         ui_out_field_skip (current_uiout, "error_p");
2489
2490       do_cleanups (cmd_chain);
2491
2492       if (!ui_out_is_mi_like_p (current_uiout))
2493         printf_filtered ("\n");
2494     }
2495
2496   do_cleanups (chain);
2497 }
2498
2499 static void
2500 info_spu_dma_command (char *args, int from_tty)
2501 {
2502   struct frame_info *frame = get_selected_frame (NULL);
2503   struct gdbarch *gdbarch = get_frame_arch (frame);
2504   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2505   ULONGEST dma_info_type;
2506   ULONGEST dma_info_mask;
2507   ULONGEST dma_info_status;
2508   ULONGEST dma_info_stall_and_notify;
2509   ULONGEST dma_info_atomic_command_status;
2510   struct cleanup *chain;
2511   char annex[32];
2512   gdb_byte buf[1024];
2513   LONGEST len;
2514   int id;
2515
2516   if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
2517     error (_("\"info spu\" is only supported on the SPU architecture."));
2518
2519   id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2520
2521   xsnprintf (annex, sizeof annex, "%d/dma_info", id);
2522   len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2523                      buf, 0, 40 + 16 * 32);
2524   if (len <= 0)
2525     error (_("Could not read dma_info."));
2526
2527   dma_info_type
2528     = extract_unsigned_integer (buf, 8, byte_order);
2529   dma_info_mask
2530     = extract_unsigned_integer (buf + 8, 8, byte_order);
2531   dma_info_status
2532     = extract_unsigned_integer (buf + 16, 8, byte_order);
2533   dma_info_stall_and_notify
2534     = extract_unsigned_integer (buf + 24, 8, byte_order);
2535   dma_info_atomic_command_status
2536     = extract_unsigned_integer (buf + 32, 8, byte_order);
2537
2538   chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "SPUInfoDMA");
2539
2540   if (ui_out_is_mi_like_p (current_uiout))
2541     {
2542       ui_out_field_fmt (current_uiout, "dma_info_type", "0x%s",
2543                         phex_nz (dma_info_type, 4));
2544       ui_out_field_fmt (current_uiout, "dma_info_mask", "0x%s",
2545                         phex_nz (dma_info_mask, 4));
2546       ui_out_field_fmt (current_uiout, "dma_info_status", "0x%s",
2547                         phex_nz (dma_info_status, 4));
2548       ui_out_field_fmt (current_uiout, "dma_info_stall_and_notify", "0x%s",
2549                         phex_nz (dma_info_stall_and_notify, 4));
2550       ui_out_field_fmt (current_uiout, "dma_info_atomic_command_status", "0x%s",
2551                         phex_nz (dma_info_atomic_command_status, 4));
2552     }
2553   else
2554     {
2555       const char *query_msg = _("no query pending");
2556
2557       if (dma_info_type & 4)
2558         switch (dma_info_type & 3)
2559           {
2560             case 1: query_msg = _("'any' query pending"); break;
2561             case 2: query_msg = _("'all' query pending"); break;
2562             default: query_msg = _("undefined query type"); break;
2563           }
2564
2565       printf_filtered (_("Tag-Group Status  0x%s\n"),
2566                        phex (dma_info_status, 4));
2567       printf_filtered (_("Tag-Group Mask    0x%s (%s)\n"),
2568                        phex (dma_info_mask, 4), query_msg);
2569       printf_filtered (_("Stall-and-Notify  0x%s\n"),
2570                        phex (dma_info_stall_and_notify, 4));
2571       printf_filtered (_("Atomic Cmd Status 0x%s\n"),
2572                        phex (dma_info_atomic_command_status, 4));
2573       printf_filtered ("\n");
2574     }
2575
2576   info_spu_dma_cmdlist (buf + 40, 16, byte_order);
2577   do_cleanups (chain);
2578 }
2579
2580 static void
2581 info_spu_proxydma_command (char *args, int from_tty)
2582 {
2583   struct frame_info *frame = get_selected_frame (NULL);
2584   struct gdbarch *gdbarch = get_frame_arch (frame);
2585   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2586   ULONGEST dma_info_type;
2587   ULONGEST dma_info_mask;
2588   ULONGEST dma_info_status;
2589   struct cleanup *chain;
2590   char annex[32];
2591   gdb_byte buf[1024];
2592   LONGEST len;
2593   int id;
2594
2595   if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
2596     error (_("\"info spu\" is only supported on the SPU architecture."));
2597
2598   id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2599
2600   xsnprintf (annex, sizeof annex, "%d/proxydma_info", id);
2601   len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2602                      buf, 0, 24 + 8 * 32);
2603   if (len <= 0)
2604     error (_("Could not read proxydma_info."));
2605
2606   dma_info_type = extract_unsigned_integer (buf, 8, byte_order);
2607   dma_info_mask = extract_unsigned_integer (buf + 8, 8, byte_order);
2608   dma_info_status = extract_unsigned_integer (buf + 16, 8, byte_order);
2609
2610   chain = make_cleanup_ui_out_tuple_begin_end (current_uiout,
2611                                                "SPUInfoProxyDMA");
2612
2613   if (ui_out_is_mi_like_p (current_uiout))
2614     {
2615       ui_out_field_fmt (current_uiout, "proxydma_info_type", "0x%s",
2616                         phex_nz (dma_info_type, 4));
2617       ui_out_field_fmt (current_uiout, "proxydma_info_mask", "0x%s",
2618                         phex_nz (dma_info_mask, 4));
2619       ui_out_field_fmt (current_uiout, "proxydma_info_status", "0x%s",
2620                         phex_nz (dma_info_status, 4));
2621     }
2622   else
2623     {
2624       const char *query_msg;
2625
2626       switch (dma_info_type & 3)
2627         {
2628         case 0: query_msg = _("no query pending"); break;
2629         case 1: query_msg = _("'any' query pending"); break;
2630         case 2: query_msg = _("'all' query pending"); break;
2631         default: query_msg = _("undefined query type"); break;
2632         }
2633
2634       printf_filtered (_("Tag-Group Status  0x%s\n"),
2635                        phex (dma_info_status, 4));
2636       printf_filtered (_("Tag-Group Mask    0x%s (%s)\n"),
2637                        phex (dma_info_mask, 4), query_msg);
2638       printf_filtered ("\n");
2639     }
2640
2641   info_spu_dma_cmdlist (buf + 24, 8, byte_order);
2642   do_cleanups (chain);
2643 }
2644
2645 static void
2646 info_spu_command (char *args, int from_tty)
2647 {
2648   printf_unfiltered (_("\"info spu\" must be followed by "
2649                        "the name of an SPU facility.\n"));
2650   help_list (infospucmdlist, "info spu ", all_commands, gdb_stdout);
2651 }
2652
2653
2654 /* Root of all "set spu "/"show spu " commands.  */
2655
2656 static void
2657 show_spu_command (char *args, int from_tty)
2658 {
2659   help_list (showspucmdlist, "show spu ", all_commands, gdb_stdout);
2660 }
2661
2662 static void
2663 set_spu_command (char *args, int from_tty)
2664 {
2665   help_list (setspucmdlist, "set spu ", all_commands, gdb_stdout);
2666 }
2667
2668 static void
2669 show_spu_stop_on_load (struct ui_file *file, int from_tty,
2670                        struct cmd_list_element *c, const char *value)
2671 {
2672   fprintf_filtered (file, _("Stopping for new SPE threads is %s.\n"),
2673                     value);
2674 }
2675
2676 static void
2677 show_spu_auto_flush_cache (struct ui_file *file, int from_tty,
2678                            struct cmd_list_element *c, const char *value)
2679 {
2680   fprintf_filtered (file, _("Automatic software-cache flush is %s.\n"),
2681                     value);
2682 }
2683
2684
2685 /* Set up gdbarch struct.  */
2686
2687 static struct gdbarch *
2688 spu_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2689 {
2690   struct gdbarch *gdbarch;
2691   struct gdbarch_tdep *tdep;
2692   int id = -1;
2693
2694   /* Which spufs ID was requested as address space?  */
2695   if (info.tdep_info)
2696     id = *(int *)info.tdep_info;
2697   /* For objfile architectures of SPU solibs, decode the ID from the name.
2698      This assumes the filename convention employed by solib-spu.c.  */
2699   else if (info.abfd)
2700     {
2701       char *name = strrchr (info.abfd->filename, '@');
2702       if (name)
2703         sscanf (name, "@0x%*x <%d>", &id);
2704     }
2705
2706   /* Find a candidate among extant architectures.  */
2707   for (arches = gdbarch_list_lookup_by_info (arches, &info);
2708        arches != NULL;
2709        arches = gdbarch_list_lookup_by_info (arches->next, &info))
2710     {
2711       tdep = gdbarch_tdep (arches->gdbarch);
2712       if (tdep && tdep->id == id)
2713         return arches->gdbarch;
2714     }
2715
2716   /* None found, so create a new architecture.  */
2717   tdep = XCNEW (struct gdbarch_tdep);
2718   tdep->id = id;
2719   gdbarch = gdbarch_alloc (&info, tdep);
2720
2721   /* Disassembler.  */
2722   set_gdbarch_print_insn (gdbarch, gdb_print_insn_spu);
2723
2724   /* Registers.  */
2725   set_gdbarch_num_regs (gdbarch, SPU_NUM_REGS);
2726   set_gdbarch_num_pseudo_regs (gdbarch, SPU_NUM_PSEUDO_REGS);
2727   set_gdbarch_sp_regnum (gdbarch, SPU_SP_REGNUM);
2728   set_gdbarch_pc_regnum (gdbarch, SPU_PC_REGNUM);
2729   set_gdbarch_read_pc (gdbarch, spu_read_pc);
2730   set_gdbarch_write_pc (gdbarch, spu_write_pc);
2731   set_gdbarch_register_name (gdbarch, spu_register_name);
2732   set_gdbarch_register_type (gdbarch, spu_register_type);
2733   set_gdbarch_pseudo_register_read (gdbarch, spu_pseudo_register_read);
2734   set_gdbarch_pseudo_register_write (gdbarch, spu_pseudo_register_write);
2735   set_gdbarch_value_from_register (gdbarch, spu_value_from_register);
2736   set_gdbarch_register_reggroup_p (gdbarch, spu_register_reggroup_p);
2737   set_gdbarch_dwarf2_reg_to_regnum (gdbarch, spu_dwarf_reg_to_regnum);
2738   set_gdbarch_ax_pseudo_register_collect
2739     (gdbarch, spu_ax_pseudo_register_collect);
2740   set_gdbarch_ax_pseudo_register_push_stack
2741     (gdbarch, spu_ax_pseudo_register_push_stack);
2742
2743   /* Data types.  */
2744   set_gdbarch_char_signed (gdbarch, 0);
2745   set_gdbarch_ptr_bit (gdbarch, 32);
2746   set_gdbarch_addr_bit (gdbarch, 32);
2747   set_gdbarch_short_bit (gdbarch, 16);
2748   set_gdbarch_int_bit (gdbarch, 32);
2749   set_gdbarch_long_bit (gdbarch, 32);
2750   set_gdbarch_long_long_bit (gdbarch, 64);
2751   set_gdbarch_float_bit (gdbarch, 32);
2752   set_gdbarch_double_bit (gdbarch, 64);
2753   set_gdbarch_long_double_bit (gdbarch, 64);
2754   set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2755   set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2756   set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
2757
2758   /* Address handling.  */
2759   set_gdbarch_address_to_pointer (gdbarch, spu_address_to_pointer);
2760   set_gdbarch_pointer_to_address (gdbarch, spu_pointer_to_address);
2761   set_gdbarch_integer_to_address (gdbarch, spu_integer_to_address);
2762   set_gdbarch_address_class_type_flags (gdbarch, spu_address_class_type_flags);
2763   set_gdbarch_address_class_type_flags_to_name
2764     (gdbarch, spu_address_class_type_flags_to_name);
2765   set_gdbarch_address_class_name_to_type_flags
2766     (gdbarch, spu_address_class_name_to_type_flags);
2767
2768
2769   /* Inferior function calls.  */
2770   set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2771   set_gdbarch_frame_align (gdbarch, spu_frame_align);
2772   set_gdbarch_frame_red_zone_size (gdbarch, 2000);
2773   set_gdbarch_push_dummy_code (gdbarch, spu_push_dummy_code);
2774   set_gdbarch_push_dummy_call (gdbarch, spu_push_dummy_call);
2775   set_gdbarch_dummy_id (gdbarch, spu_dummy_id);
2776   set_gdbarch_return_value (gdbarch, spu_return_value);
2777
2778   /* Frame handling.  */
2779   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2780   dwarf2_append_unwinders (gdbarch);
2781   frame_unwind_append_unwinder (gdbarch, &spu_frame_unwind);
2782   frame_base_set_default (gdbarch, &spu_frame_base);
2783   set_gdbarch_unwind_pc (gdbarch, spu_unwind_pc);
2784   set_gdbarch_unwind_sp (gdbarch, spu_unwind_sp);
2785   set_gdbarch_virtual_frame_pointer (gdbarch, spu_virtual_frame_pointer);
2786   set_gdbarch_frame_args_skip (gdbarch, 0);
2787   set_gdbarch_skip_prologue (gdbarch, spu_skip_prologue);
2788   set_gdbarch_in_function_epilogue_p (gdbarch, spu_in_function_epilogue_p);
2789
2790   /* Cell/B.E. cross-architecture unwinder support.  */
2791   frame_unwind_prepend_unwinder (gdbarch, &spu2ppu_unwind);
2792
2793   /* Breakpoints.  */
2794   set_gdbarch_decr_pc_after_break (gdbarch, 4);
2795   set_gdbarch_breakpoint_from_pc (gdbarch, spu_breakpoint_from_pc);
2796   set_gdbarch_memory_remove_breakpoint (gdbarch, spu_memory_remove_breakpoint);
2797   set_gdbarch_cannot_step_breakpoint (gdbarch, 1);
2798   set_gdbarch_software_single_step (gdbarch, spu_software_single_step);
2799   set_gdbarch_get_longjmp_target (gdbarch, spu_get_longjmp_target);
2800
2801   /* Overlays.  */
2802   set_gdbarch_overlay_update (gdbarch, spu_overlay_update);
2803
2804   return gdbarch;
2805 }
2806
2807 /* Provide a prototype to silence -Wmissing-prototypes.  */
2808 extern initialize_file_ftype _initialize_spu_tdep;
2809
2810 void
2811 _initialize_spu_tdep (void)
2812 {
2813   register_gdbarch_init (bfd_arch_spu, spu_gdbarch_init);
2814
2815   /* Add ourselves to objfile event chain.  */
2816   observer_attach_new_objfile (spu_overlay_new_objfile);
2817   spu_overlay_data = register_objfile_data ();
2818
2819   /* Install spu stop-on-load handler.  */
2820   observer_attach_new_objfile (spu_catch_start);
2821
2822   /* Add ourselves to normal_stop event chain.  */
2823   observer_attach_normal_stop (spu_attach_normal_stop);
2824
2825   /* Add root prefix command for all "set spu"/"show spu" commands.  */
2826   add_prefix_cmd ("spu", no_class, set_spu_command,
2827                   _("Various SPU specific commands."),
2828                   &setspucmdlist, "set spu ", 0, &setlist);
2829   add_prefix_cmd ("spu", no_class, show_spu_command,
2830                   _("Various SPU specific commands."),
2831                   &showspucmdlist, "show spu ", 0, &showlist);
2832
2833   /* Toggle whether or not to add a temporary breakpoint at the "main"
2834      function of new SPE contexts.  */
2835   add_setshow_boolean_cmd ("stop-on-load", class_support,
2836                           &spu_stop_on_load_p, _("\
2837 Set whether to stop for new SPE threads."),
2838                            _("\
2839 Show whether to stop for new SPE threads."),
2840                            _("\
2841 Use \"on\" to give control to the user when a new SPE thread\n\
2842 enters its \"main\" function.\n\
2843 Use \"off\" to disable stopping for new SPE threads."),
2844                           NULL,
2845                           show_spu_stop_on_load,
2846                           &setspucmdlist, &showspucmdlist);
2847
2848   /* Toggle whether or not to automatically flush the software-managed
2849      cache whenever SPE execution stops.  */
2850   add_setshow_boolean_cmd ("auto-flush-cache", class_support,
2851                           &spu_auto_flush_cache_p, _("\
2852 Set whether to automatically flush the software-managed cache."),
2853                            _("\
2854 Show whether to automatically flush the software-managed cache."),
2855                            _("\
2856 Use \"on\" to automatically flush the software-managed cache\n\
2857 whenever SPE execution stops.\n\
2858 Use \"off\" to never automatically flush the software-managed cache."),
2859                           NULL,
2860                           show_spu_auto_flush_cache,
2861                           &setspucmdlist, &showspucmdlist);
2862
2863   /* Add root prefix command for all "info spu" commands.  */
2864   add_prefix_cmd ("spu", class_info, info_spu_command,
2865                   _("Various SPU specific commands."),
2866                   &infospucmdlist, "info spu ", 0, &infolist);
2867
2868   /* Add various "info spu" commands.  */
2869   add_cmd ("event", class_info, info_spu_event_command,
2870            _("Display SPU event facility status.\n"),
2871            &infospucmdlist);
2872   add_cmd ("signal", class_info, info_spu_signal_command,
2873            _("Display SPU signal notification facility status.\n"),
2874            &infospucmdlist);
2875   add_cmd ("mailbox", class_info, info_spu_mailbox_command,
2876            _("Display SPU mailbox facility status.\n"),
2877            &infospucmdlist);
2878   add_cmd ("dma", class_info, info_spu_dma_command,
2879            _("Display MFC DMA status.\n"),
2880            &infospucmdlist);
2881   add_cmd ("proxydma", class_info, info_spu_proxydma_command,
2882            _("Display MFC Proxy-DMA status.\n"),
2883            &infospucmdlist);
2884 }