gdb/spu-tdep.c

   1 /* SPU target-dependent code for GDB, the GNU debugger.
   2    Copyright (C) 2006, 2007, 2008, 2009 Free Software Foundation, Inc.
   3
   4    Contributed by Ulrich Weigand <uweigand@de.ibm.com>.
   5    Based on a port by Sid Manning <sid@us.ibm.com>.
   6
   7    This file is part of GDB.
   8
   9    This program is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3 of the License, or
  12    (at your option) any later version.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  21
  22 #include "defs.h"
  23 #include "arch-utils.h"
  24 #include "gdbtypes.h"
  25 #include "gdbcmd.h"
  26 #include "gdbcore.h"
  27 #include "gdb_string.h"
  28 #include "gdb_assert.h"
  29 #include "frame.h"
  30 #include "frame-unwind.h"
  31 #include "frame-base.h"
  32 #include "trad-frame.h"
  33 #include "symtab.h"
  34 #include "symfile.h"
  35 #include "value.h"
  36 #include "inferior.h"
  37 #include "dis-asm.h"
  38 #include "objfiles.h"
  39 #include "language.h"
  40 #include "regcache.h"
  41 #include "reggroups.h"
  42 #include "floatformat.h"
  43 #include "observer.h"
  44
  45 #include "spu-tdep.h"
  46
  47
  48 /* The tdep structure.  */
  49 struct gdbarch_tdep
  50 {
  51   /* SPU-specific vector type.  */
  52   struct type *spu_builtin_type_vec128;
  53 };
  54
  55
  56 /* SPU-specific vector type.  */
  57 static struct type *
  58 spu_builtin_type_vec128 (struct gdbarch *gdbarch)
  59 {
  60   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
  61
  62   if (!tdep->spu_builtin_type_vec128)
  63     {
  64       const struct builtin_type *bt = builtin_type (gdbarch);
  65       struct type *t;
  66
  67       t = init_composite_type ("__spu_builtin_type_vec128", TYPE_CODE_UNION);
  68       append_composite_type_field (t, "uint128", bt->builtin_int128);
  69       append_composite_type_field (t, "v2_int64",
  70                                    init_vector_type (bt->builtin_int64, 2));
  71       append_composite_type_field (t, "v4_int32",
  72                                    init_vector_type (bt->builtin_int32, 4));
  73       append_composite_type_field (t, "v8_int16",
  74                                    init_vector_type (bt->builtin_int16, 8));
  75       append_composite_type_field (t, "v16_int8",
  76                                    init_vector_type (bt->builtin_int8, 16));
  77       append_composite_type_field (t, "v2_double",
  78                                    init_vector_type (bt->builtin_double, 2));
  79       append_composite_type_field (t, "v4_float",
  80                                    init_vector_type (bt->builtin_float, 4));
  81
  82       TYPE_VECTOR (t) = 1;
  83       TYPE_NAME (t) = "spu_builtin_type_vec128";
  84
  85       tdep->spu_builtin_type_vec128 = t;
  86     }
  87
  88   return tdep->spu_builtin_type_vec128;
  89 }
  90
  91
  92 /* The list of available "info spu " commands.  */
  93 static struct cmd_list_element *infospucmdlist = NULL;
  94
  95 /* Registers.  */
  96
  97 static const char *
  98 spu_register_name (struct gdbarch *gdbarch, int reg_nr)
  99 {
 100   static char *register_names[] =
 101     {
 102       "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 103       "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 104       "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
 105       "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
 106       "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
 107       "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
 108       "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
 109       "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
 110       "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
 111       "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
 112       "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
 113       "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
 114       "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
 115       "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
 116       "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
 117       "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
 118       "id", "pc", "sp", "fpscr", "srr0", "lslr", "decr", "decr_status"
 119     };
 120
 121   if (reg_nr < 0)
 122     return NULL;
 123   if (reg_nr >= sizeof register_names / sizeof *register_names)
 124     return NULL;
 125
 126   return register_names[reg_nr];
 127 }
 128
 129 static struct type *
 130 spu_register_type (struct gdbarch *gdbarch, int reg_nr)
 131 {
 132   if (reg_nr < SPU_NUM_GPRS)
 133     return spu_builtin_type_vec128 (gdbarch);
 134
 135   switch (reg_nr)
 136     {
 137     case SPU_ID_REGNUM:
 138       return builtin_type (gdbarch)->builtin_uint32;
 139
 140     case SPU_PC_REGNUM:
 141       return builtin_type (gdbarch)->builtin_func_ptr;
 142
 143     case SPU_SP_REGNUM:
 144       return builtin_type (gdbarch)->builtin_data_ptr;
 145
 146     case SPU_FPSCR_REGNUM:
 147       return builtin_type (gdbarch)->builtin_uint128;
 148
 149     case SPU_SRR0_REGNUM:
 150       return builtin_type (gdbarch)->builtin_uint32;
 151
 152     case SPU_LSLR_REGNUM:
 153       return builtin_type (gdbarch)->builtin_uint32;
 154
 155     case SPU_DECR_REGNUM:
 156       return builtin_type (gdbarch)->builtin_uint32;
 157
 158     case SPU_DECR_STATUS_REGNUM:
 159       return builtin_type (gdbarch)->builtin_uint32;
 160
 161     default:
 162       internal_error (__FILE__, __LINE__, "invalid regnum");
 163     }
 164 }
 165
 166 /* Pseudo registers for preferred slots - stack pointer.  */
 167
 168 static void
 169 spu_pseudo_register_read_spu (struct regcache *regcache, const char *regname,
 170                               gdb_byte *buf)
 171 {
 172   gdb_byte reg[32];
 173   char annex[32];
 174   ULONGEST id;
 175
 176   regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
 177   xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
 178   memset (reg, 0, sizeof reg);
 179   target_read (&current_target, TARGET_OBJECT_SPU, annex,
 180                reg, 0, sizeof reg);
 181
 182   store_unsigned_integer (buf, 4, strtoulst (reg, NULL, 16));
 183 }
 184
 185 static void
 186 spu_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
 187                           int regnum, gdb_byte *buf)
 188 {
 189   gdb_byte reg[16];
 190   char annex[32];
 191   ULONGEST id;
 192
 193   switch (regnum)
 194     {
 195     case SPU_SP_REGNUM:
 196       regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
 197       memcpy (buf, reg, 4);
 198       break;
 199
 200     case SPU_FPSCR_REGNUM:
 201       regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
 202       xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
 203       target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
 204       break;
 205
 206     case SPU_SRR0_REGNUM:
 207       spu_pseudo_register_read_spu (regcache, "srr0", buf);
 208       break;
 209
 210     case SPU_LSLR_REGNUM:
 211       spu_pseudo_register_read_spu (regcache, "lslr", buf);
 212       break;
 213
 214     case SPU_DECR_REGNUM:
 215       spu_pseudo_register_read_spu (regcache, "decr", buf);
 216       break;
 217
 218     case SPU_DECR_STATUS_REGNUM:
 219       spu_pseudo_register_read_spu (regcache, "decr_status", buf);
 220       break;
 221
 222     default:
 223       internal_error (__FILE__, __LINE__, _("invalid regnum"));
 224     }
 225 }
 226
 227 static void
 228 spu_pseudo_register_write_spu (struct regcache *regcache, const char *regname,
 229                                const gdb_byte *buf)
 230 {
 231   gdb_byte reg[32];
 232   char annex[32];
 233   ULONGEST id;
 234
 235   regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
 236   xsnprintf (annex, sizeof annex, "%d/%s", (int) id, regname);
 237   xsnprintf (reg, sizeof reg, "0x%s",
 238              phex_nz (extract_unsigned_integer (buf, 4), 4));
 239   target_write (&current_target, TARGET_OBJECT_SPU, annex,
 240                 reg, 0, strlen (reg));
 241 }
 242
 243 static void
 244 spu_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
 245                            int regnum, const gdb_byte *buf)
 246 {
 247   gdb_byte reg[16];
 248   char annex[32];
 249   ULONGEST id;
 250
 251   switch (regnum)
 252     {
 253     case SPU_SP_REGNUM:
 254       regcache_raw_read (regcache, SPU_RAW_SP_REGNUM, reg);
 255       memcpy (reg, buf, 4);
 256       regcache_raw_write (regcache, SPU_RAW_SP_REGNUM, reg);
 257       break;
 258
 259     case SPU_FPSCR_REGNUM:
 260       regcache_raw_read_unsigned (regcache, SPU_ID_REGNUM, &id);
 261       xsnprintf (annex, sizeof annex, "%d/fpcr", (int) id);
 262       target_write (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 16);
 263       break;
 264
 265     case SPU_SRR0_REGNUM:
 266       spu_pseudo_register_write_spu (regcache, "srr0", buf);
 267       break;
 268
 269     case SPU_LSLR_REGNUM:
 270       spu_pseudo_register_write_spu (regcache, "lslr", buf);
 271       break;
 272
 273     case SPU_DECR_REGNUM:
 274       spu_pseudo_register_write_spu (regcache, "decr", buf);
 275       break;
 276
 277     case SPU_DECR_STATUS_REGNUM:
 278       spu_pseudo_register_write_spu (regcache, "decr_status", buf);
 279       break;
 280
 281     default:
 282       internal_error (__FILE__, __LINE__, _("invalid regnum"));
 283     }
 284 }
 285
 286 /* Value conversion -- access scalar values at the preferred slot.  */
 287
 288 static struct value *
 289 spu_value_from_register (struct type *type, int regnum,
 290                          struct frame_info *frame)
 291 {
 292   struct value *value = default_value_from_register (type, regnum, frame);
 293   int len = TYPE_LENGTH (type);
 294
 295   if (regnum < SPU_NUM_GPRS && len < 16)
 296     {
 297       int preferred_slot = len < 4 ? 4 - len : 0;
 298       set_value_offset (value, preferred_slot);
 299     }
 300
 301   return value;
 302 }
 303
 304 /* Register groups.  */
 305
 306 static int
 307 spu_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
 308                          struct reggroup *group)
 309 {
 310   /* Registers displayed via 'info regs'.  */
 311   if (group == general_reggroup)
 312     return 1;
 313
 314   /* Registers displayed via 'info float'.  */
 315   if (group == float_reggroup)
 316     return 0;
 317
 318   /* Registers that need to be saved/restored in order to
 319      push or pop frames.  */
 320   if (group == save_reggroup || group == restore_reggroup)
 321     return 1;
 322
 323   return default_register_reggroup_p (gdbarch, regnum, group);
 324 }
 325
 326 /* Address conversion.  */
 327
 328 static CORE_ADDR
 329 spu_pointer_to_address (struct gdbarch *gdbarch,
 330                         struct type *type, const gdb_byte *buf)
 331 {
 332   ULONGEST addr = extract_unsigned_integer (buf, TYPE_LENGTH (type));
 333   ULONGEST lslr = SPU_LS_SIZE - 1; /* Hard-wired LS size.  */
 334
 335   if (target_has_registers && target_has_stack && target_has_memory)
 336     lslr = get_frame_register_unsigned (get_selected_frame (NULL),
 337                                         SPU_LSLR_REGNUM);
 338
 339   return addr & lslr;
 340 }
 341
 342 static CORE_ADDR
 343 spu_integer_to_address (struct gdbarch *gdbarch,
 344                         struct type *type, const gdb_byte *buf)
 345 {
 346   ULONGEST addr = unpack_long (type, buf);
 347   ULONGEST lslr = SPU_LS_SIZE - 1; /* Hard-wired LS size.  */
 348
 349   if (target_has_registers && target_has_stack && target_has_memory)
 350     lslr = get_frame_register_unsigned (get_selected_frame (NULL),
 351                                         SPU_LSLR_REGNUM);
 352
 353   return addr & lslr;
 354 }
 355
 356
 357 /* Decoding SPU instructions.  */
 358
 359 enum
 360   {
 361     op_lqd   = 0x34,
 362     op_lqx   = 0x3c4,
 363     op_lqa   = 0x61,
 364     op_lqr   = 0x67,
 365     op_stqd  = 0x24,
 366     op_stqx  = 0x144,
 367     op_stqa  = 0x41,
 368     op_stqr  = 0x47,
 369
 370     op_il    = 0x081,
 371     op_ila   = 0x21,
 372     op_a     = 0x0c0,
 373     op_ai    = 0x1c,
 374
 375     op_selb  = 0x4,
 376
 377     op_br    = 0x64,
 378     op_bra   = 0x60,
 379     op_brsl  = 0x66,
 380     op_brasl = 0x62,
 381     op_brnz  = 0x42,
 382     op_brz   = 0x40,
 383     op_brhnz = 0x46,
 384     op_brhz  = 0x44,
 385     op_bi    = 0x1a8,
 386     op_bisl  = 0x1a9,
 387     op_biz   = 0x128,
 388     op_binz  = 0x129,
 389     op_bihz  = 0x12a,
 390     op_bihnz = 0x12b,
 391   };
 392
 393 static int
 394 is_rr (unsigned int insn, int op, int *rt, int *ra, int *rb)
 395 {
 396   if ((insn >> 21) == op)
 397     {
 398       *rt = insn & 127;
 399       *ra = (insn >> 7) & 127;
 400       *rb = (insn >> 14) & 127;
 401       return 1;
 402     }
 403
 404   return 0;
 405 }
 406
 407 static int
 408 is_rrr (unsigned int insn, int op, int *rt, int *ra, int *rb, int *rc)
 409 {
 410   if ((insn >> 28) == op)
 411     {
 412       *rt = (insn >> 21) & 127;
 413       *ra = (insn >> 7) & 127;
 414       *rb = (insn >> 14) & 127;
 415       *rc = insn & 127;
 416       return 1;
 417     }
 418
 419   return 0;
 420 }
 421
 422 static int
 423 is_ri7 (unsigned int insn, int op, int *rt, int *ra, int *i7)
 424 {
 425   if ((insn >> 21) == op)
 426     {
 427       *rt = insn & 127;
 428       *ra = (insn >> 7) & 127;
 429       *i7 = (((insn >> 14) & 127) ^ 0x40) - 0x40;
 430       return 1;
 431     }
 432
 433   return 0;
 434 }
 435
 436 static int
 437 is_ri10 (unsigned int insn, int op, int *rt, int *ra, int *i10)
 438 {
 439   if ((insn >> 24) == op)
 440     {
 441       *rt = insn & 127;
 442       *ra = (insn >> 7) & 127;
 443       *i10 = (((insn >> 14) & 0x3ff) ^ 0x200) - 0x200;
 444       return 1;
 445     }
 446
 447   return 0;
 448 }
 449
 450 static int
 451 is_ri16 (unsigned int insn, int op, int *rt, int *i16)
 452 {
 453   if ((insn >> 23) == op)
 454     {
 455       *rt = insn & 127;
 456       *i16 = (((insn >> 7) & 0xffff) ^ 0x8000) - 0x8000;
 457       return 1;
 458     }
 459
 460   return 0;
 461 }
 462
 463 static int
 464 is_ri18 (unsigned int insn, int op, int *rt, int *i18)
 465 {
 466   if ((insn >> 25) == op)
 467     {
 468       *rt = insn & 127;
 469       *i18 = (((insn >> 7) & 0x3ffff) ^ 0x20000) - 0x20000;
 470       return 1;
 471     }
 472
 473   return 0;
 474 }
 475
 476 static int
 477 is_branch (unsigned int insn, int *offset, int *reg)
 478 {
 479   int rt, i7, i16;
 480
 481   if (is_ri16 (insn, op_br, &rt, &i16)
 482       || is_ri16 (insn, op_brsl, &rt, &i16)
 483       || is_ri16 (insn, op_brnz, &rt, &i16)
 484       || is_ri16 (insn, op_brz, &rt, &i16)
 485       || is_ri16 (insn, op_brhnz, &rt, &i16)
 486       || is_ri16 (insn, op_brhz, &rt, &i16))
 487     {
 488       *reg = SPU_PC_REGNUM;
 489       *offset = i16 << 2;
 490       return 1;
 491     }
 492
 493   if (is_ri16 (insn, op_bra, &rt, &i16)
 494       || is_ri16 (insn, op_brasl, &rt, &i16))
 495     {
 496       *reg = -1;
 497       *offset = i16 << 2;
 498       return 1;
 499     }
 500
 501   if (is_ri7 (insn, op_bi, &rt, reg, &i7)
 502       || is_ri7 (insn, op_bisl, &rt, reg, &i7)
 503       || is_ri7 (insn, op_biz, &rt, reg, &i7)
 504       || is_ri7 (insn, op_binz, &rt, reg, &i7)
 505       || is_ri7 (insn, op_bihz, &rt, reg, &i7)
 506       || is_ri7 (insn, op_bihnz, &rt, reg, &i7))
 507     {
 508       *offset = 0;
 509       return 1;
 510     }
 511
 512   return 0;
 513 }
 514
 515
 516 /* Prolog parsing.  */
 517
 518 struct spu_prologue_data
 519   {
 520     /* Stack frame size.  -1 if analysis was unsuccessful.  */
 521     int size;
 522
 523     /* How to find the CFA.  The CFA is equal to SP at function entry.  */
 524     int cfa_reg;
 525     int cfa_offset;
 526
 527     /* Offset relative to CFA where a register is saved.  -1 if invalid.  */
 528     int reg_offset[SPU_NUM_GPRS];
 529   };
 530
 531 static CORE_ADDR
 532 spu_analyze_prologue (CORE_ADDR start_pc, CORE_ADDR end_pc,
 533                       struct spu_prologue_data *data)
 534 {
 535   int found_sp = 0;
 536   int found_fp = 0;
 537   int found_lr = 0;
 538   int reg_immed[SPU_NUM_GPRS];
 539   gdb_byte buf[16];
 540   CORE_ADDR prolog_pc = start_pc;
 541   CORE_ADDR pc;
 542   int i;
 543
 544
 545   /* Initialize DATA to default values.  */
 546   data->size = -1;
 547
 548   data->cfa_reg = SPU_RAW_SP_REGNUM;
 549   data->cfa_offset = 0;
 550
 551   for (i = 0; i < SPU_NUM_GPRS; i++)
 552     data->reg_offset[i] = -1;
 553
 554   /* Set up REG_IMMED array.  This is non-zero for a register if we know its
 555      preferred slot currently holds this immediate value.  */
 556   for (i = 0; i < SPU_NUM_GPRS; i++)
 557       reg_immed[i] = 0;
 558
 559   /* Scan instructions until the first branch.
 560
 561      The following instructions are important prolog components:
 562
 563         - The first instruction to set up the stack pointer.
 564         - The first instruction to set up the frame pointer.
 565         - The first instruction to save the link register.
 566
 567      We return the instruction after the latest of these three,
 568      or the incoming PC if none is found.  The first instruction
 569      to set up the stack pointer also defines the frame size.
 570
 571      Note that instructions saving incoming arguments to their stack
 572      slots are not counted as important, because they are hard to
 573      identify with certainty.  This should not matter much, because
 574      arguments are relevant only in code compiled with debug data,
 575      and in such code the GDB core will advance until the first source
 576      line anyway, using SAL data.
 577
 578      For purposes of stack unwinding, we analyze the following types
 579      of instructions in addition:
 580
 581       - Any instruction adding to the current frame pointer.
 582       - Any instruction loading an immediate constant into a register.
 583       - Any instruction storing a register onto the stack.
 584
 585      These are used to compute the CFA and REG_OFFSET output.  */
 586
 587   for (pc = start_pc; pc < end_pc; pc += 4)
 588     {
 589       unsigned int insn;
 590       int rt, ra, rb, rc, immed;
 591
 592       if (target_read_memory (pc, buf, 4))
 593         break;
 594       insn = extract_unsigned_integer (buf, 4);
 595
 596       /* AI is the typical instruction to set up a stack frame.
 597          It is also used to initialize the frame pointer.  */
 598       if (is_ri10 (insn, op_ai, &rt, &ra, &immed))
 599         {
 600           if (rt == data->cfa_reg && ra == data->cfa_reg)
 601             data->cfa_offset -= immed;
 602
 603           if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
 604               && !found_sp)
 605             {
 606               found_sp = 1;
 607               prolog_pc = pc + 4;
 608
 609               data->size = -immed;
 610             }
 611           else if (rt == SPU_FP_REGNUM && ra == SPU_RAW_SP_REGNUM
 612                    && !found_fp)
 613             {
 614               found_fp = 1;
 615               prolog_pc = pc + 4;
 616
 617               data->cfa_reg = SPU_FP_REGNUM;
 618               data->cfa_offset -= immed;
 619             }
 620         }
 621
 622       /* A is used to set up stack frames of size >= 512 bytes.
 623          If we have tracked the contents of the addend register,
 624          we can handle this as well.  */
 625       else if (is_rr (insn, op_a, &rt, &ra, &rb))
 626         {
 627           if (rt == data->cfa_reg && ra == data->cfa_reg)
 628             {
 629               if (reg_immed[rb] != 0)
 630                 data->cfa_offset -= reg_immed[rb];
 631               else
 632                 data->cfa_reg = -1;  /* We don't know the CFA any more.  */
 633             }
 634
 635           if (rt == SPU_RAW_SP_REGNUM && ra == SPU_RAW_SP_REGNUM
 636               && !found_sp)
 637             {
 638               found_sp = 1;
 639               prolog_pc = pc + 4;
 640
 641               if (reg_immed[rb] != 0)
 642                 data->size = -reg_immed[rb];
 643             }
 644         }
 645
 646       /* We need to track IL and ILA used to load immediate constants
 647          in case they are later used as input to an A instruction.  */
 648       else if (is_ri16 (insn, op_il, &rt, &immed))
 649         {
 650           reg_immed[rt] = immed;
 651
 652           if (rt == SPU_RAW_SP_REGNUM && !found_sp)
 653             found_sp = 1;
 654         }
 655
 656       else if (is_ri18 (insn, op_ila, &rt, &immed))
 657         {
 658           reg_immed[rt] = immed & 0x3ffff;
 659
 660           if (rt == SPU_RAW_SP_REGNUM && !found_sp)
 661             found_sp = 1;
 662         }
 663
 664       /* STQD is used to save registers to the stack.  */
 665       else if (is_ri10 (insn, op_stqd, &rt, &ra, &immed))
 666         {
 667           if (ra == data->cfa_reg)
 668             data->reg_offset[rt] = data->cfa_offset - (immed << 4);
 669
 670           if (ra == data->cfa_reg && rt == SPU_LR_REGNUM
 671               && !found_lr)
 672             {
 673               found_lr = 1;
 674               prolog_pc = pc + 4;
 675             }
 676         }
 677
 678       /* _start uses SELB to set up the stack pointer.  */
 679       else if (is_rrr (insn, op_selb, &rt, &ra, &rb, &rc))
 680         {
 681           if (rt == SPU_RAW_SP_REGNUM && !found_sp)
 682             found_sp = 1;
 683         }
 684
 685       /* We terminate if we find a branch.  */
 686       else if (is_branch (insn, &immed, &ra))
 687         break;
 688     }
 689
 690
 691   /* If we successfully parsed until here, and didn't find any instruction
 692      modifying SP, we assume we have a frameless function.  */
 693   if (!found_sp)
 694     data->size = 0;
 695
 696   /* Return cooked instead of raw SP.  */
 697   if (data->cfa_reg == SPU_RAW_SP_REGNUM)
 698     data->cfa_reg = SPU_SP_REGNUM;
 699
 700   return prolog_pc;
 701 }
 702
 703 /* Return the first instruction after the prologue starting at PC.  */
 704 static CORE_ADDR
 705 spu_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
 706 {
 707   struct spu_prologue_data data;
 708   return spu_analyze_prologue (pc, (CORE_ADDR)-1, &data);
 709 }
 710
 711 /* Return the frame pointer in use at address PC.  */
 712 static void
 713 spu_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc,
 714                            int *reg, LONGEST *offset)
 715 {
 716   struct spu_prologue_data data;
 717   spu_analyze_prologue (pc, (CORE_ADDR)-1, &data);
 718
 719   if (data.size != -1 && data.cfa_reg != -1)
 720     {
 721       /* The 'frame pointer' address is CFA minus frame size.  */
 722       *reg = data.cfa_reg;
 723       *offset = data.cfa_offset - data.size;
 724     }
 725   else
 726     {
 727       /* ??? We don't really know ... */
 728       *reg = SPU_SP_REGNUM;
 729       *offset = 0;
 730     }
 731 }
 732
 733 /* Return true if we are in the function's epilogue, i.e. after the
 734    instruction that destroyed the function's stack frame.
 735
 736    1) scan forward from the point of execution:
 737        a) If you find an instruction that modifies the stack pointer
 738           or transfers control (except a return), execution is not in
 739           an epilogue, return.
 740        b) Stop scanning if you find a return instruction or reach the
 741           end of the function or reach the hard limit for the size of
 742           an epilogue.
 743    2) scan backward from the point of execution:
 744         a) If you find an instruction that modifies the stack pointer,
 745             execution *is* in an epilogue, return.
 746         b) Stop scanning if you reach an instruction that transfers
 747            control or the beginning of the function or reach the hard
 748            limit for the size of an epilogue.  */
 749
 750 static int
 751 spu_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
 752 {
 753   CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
 754   bfd_byte buf[4];
 755   unsigned int insn;
 756   int rt, ra, rb, rc, immed;
 757
 758   /* Find the search limits based on function boundaries and hard limit.
 759      We assume the epilogue can be up to 64 instructions long.  */
 760
 761   const int spu_max_epilogue_size = 64 * 4;
 762
 763   if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
 764     return 0;
 765
 766   if (pc - func_start < spu_max_epilogue_size)
 767     epilogue_start = func_start;
 768   else
 769     epilogue_start = pc - spu_max_epilogue_size;
 770
 771   if (func_end - pc < spu_max_epilogue_size)
 772     epilogue_end = func_end;
 773   else
 774     epilogue_end = pc + spu_max_epilogue_size;
 775
 776   /* Scan forward until next 'bi $0'.  */
 777
 778   for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += 4)
 779     {
 780       if (target_read_memory (scan_pc, buf, 4))
 781         return 0;
 782       insn = extract_unsigned_integer (buf, 4);
 783
 784       if (is_branch (insn, &immed, &ra))
 785         {
 786           if (immed == 0 && ra == SPU_LR_REGNUM)
 787             break;
 788
 789           return 0;
 790         }
 791
 792       if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
 793           || is_rr (insn, op_a, &rt, &ra, &rb)
 794           || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
 795         {
 796           if (rt == SPU_RAW_SP_REGNUM)
 797             return 0;
 798         }
 799     }
 800
 801   if (scan_pc >= epilogue_end)
 802     return 0;
 803
 804   /* Scan backward until adjustment to stack pointer (R1).  */
 805
 806   for (scan_pc = pc - 4; scan_pc >= epilogue_start; scan_pc -= 4)
 807     {
 808       if (target_read_memory (scan_pc, buf, 4))
 809         return 0;
 810       insn = extract_unsigned_integer (buf, 4);
 811
 812       if (is_branch (insn, &immed, &ra))
 813         return 0;
 814
 815       if (is_ri10 (insn, op_ai, &rt, &ra, &immed)
 816           || is_rr (insn, op_a, &rt, &ra, &rb)
 817           || is_ri10 (insn, op_lqd, &rt, &ra, &immed))
 818         {
 819           if (rt == SPU_RAW_SP_REGNUM)
 820             return 1;
 821         }
 822     }
 823
 824   return 0;
 825 }
 826
 827
 828 /* Normal stack frames.  */
 829
 830 struct spu_unwind_cache
 831 {
 832   CORE_ADDR func;
 833   CORE_ADDR frame_base;
 834   CORE_ADDR local_base;
 835
 836   struct trad_frame_saved_reg *saved_regs;
 837 };
 838
 839 static struct spu_unwind_cache *
 840 spu_frame_unwind_cache (struct frame_info *this_frame,
 841                         void **this_prologue_cache)
 842 {
 843   struct spu_unwind_cache *info;
 844   struct spu_prologue_data data;
 845   gdb_byte buf[16];
 846
 847   if (*this_prologue_cache)
 848     return *this_prologue_cache;
 849
 850   info = FRAME_OBSTACK_ZALLOC (struct spu_unwind_cache);
 851   *this_prologue_cache = info;
 852   info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
 853   info->frame_base = 0;
 854   info->local_base = 0;
 855
 856   /* Find the start of the current function, and analyze its prologue.  */
 857   info->func = get_frame_func (this_frame);
 858   if (info->func == 0)
 859     {
 860       /* Fall back to using the current PC as frame ID.  */
 861       info->func = get_frame_pc (this_frame);
 862       data.size = -1;
 863     }
 864   else
 865     spu_analyze_prologue (info->func, get_frame_pc (this_frame), &data);
 866
 867
 868   /* If successful, use prologue analysis data.  */
 869   if (data.size != -1 && data.cfa_reg != -1)
 870     {
 871       CORE_ADDR cfa;
 872       int i;
 873
 874       /* Determine CFA via unwound CFA_REG plus CFA_OFFSET.  */
 875       get_frame_register (this_frame, data.cfa_reg, buf);
 876       cfa = extract_unsigned_integer (buf, 4) + data.cfa_offset;
 877
 878       /* Call-saved register slots.  */
 879       for (i = 0; i < SPU_NUM_GPRS; i++)
 880         if (i == SPU_LR_REGNUM
 881             || (i >= SPU_SAVED1_REGNUM && i <= SPU_SAVEDN_REGNUM))
 882           if (data.reg_offset[i] != -1)
 883             info->saved_regs[i].addr = cfa - data.reg_offset[i];
 884
 885       /* Frame bases.  */
 886       info->frame_base = cfa;
 887       info->local_base = cfa - data.size;
 888     }
 889
 890   /* Otherwise, fall back to reading the backchain link.  */
 891   else
 892     {
 893       CORE_ADDR reg;
 894       LONGEST backchain;
 895       int status;
 896
 897       /* Get the backchain.  */
 898       reg = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
 899       status = safe_read_memory_integer (reg, 4, &backchain);
 900
 901       /* A zero backchain terminates the frame chain.  Also, sanity
 902          check against the local store size limit.  */
 903       if (status && backchain > 0 && backchain < SPU_LS_SIZE)
 904         {
 905           /* Assume the link register is saved into its slot.  */
 906           if (backchain + 16 < SPU_LS_SIZE)
 907             info->saved_regs[SPU_LR_REGNUM].addr = backchain + 16;
 908
 909           /* Frame bases.  */
 910           info->frame_base = backchain;
 911           info->local_base = reg;
 912         }
 913     }
 914
 915   /* If we didn't find a frame, we cannot determine SP / return address.  */
 916   if (info->frame_base == 0)
 917     return info;
 918
 919   /* The previous SP is equal to the CFA.  */
 920   trad_frame_set_value (info->saved_regs, SPU_SP_REGNUM, info->frame_base);
 921
 922   /* Read full contents of the unwound link register in order to
 923      be able to determine the return address.  */
 924   if (trad_frame_addr_p (info->saved_regs, SPU_LR_REGNUM))
 925     target_read_memory (info->saved_regs[SPU_LR_REGNUM].addr, buf, 16);
 926   else
 927     get_frame_register (this_frame, SPU_LR_REGNUM, buf);
 928
 929   /* Normally, the return address is contained in the slot 0 of the
 930      link register, and slots 1-3 are zero.  For an overlay return,
 931      slot 0 contains the address of the overlay manager return stub,
 932      slot 1 contains the partition number of the overlay section to
 933      be returned to, and slot 2 contains the return address within
 934      that section.  Return the latter address in that case.  */
 935   if (extract_unsigned_integer (buf + 8, 4) != 0)
 936     trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
 937                           extract_unsigned_integer (buf + 8, 4));
 938   else
 939     trad_frame_set_value (info->saved_regs, SPU_PC_REGNUM,
 940                           extract_unsigned_integer (buf, 4));
 941
 942   return info;
 943 }
 944
 945 static void
 946 spu_frame_this_id (struct frame_info *this_frame,
 947                    void **this_prologue_cache, struct frame_id *this_id)
 948 {
 949   struct spu_unwind_cache *info =
 950     spu_frame_unwind_cache (this_frame, this_prologue_cache);
 951
 952   if (info->frame_base == 0)
 953     return;
 954
 955   *this_id = frame_id_build (info->frame_base, info->func);
 956 }
 957
 958 static struct value *
 959 spu_frame_prev_register (struct frame_info *this_frame,
 960                          void **this_prologue_cache, int regnum)
 961 {
 962   struct spu_unwind_cache *info
 963     = spu_frame_unwind_cache (this_frame, this_prologue_cache);
 964
 965   /* Special-case the stack pointer.  */
 966   if (regnum == SPU_RAW_SP_REGNUM)
 967     regnum = SPU_SP_REGNUM;
 968
 969   return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
 970 }
 971
 972 static const struct frame_unwind spu_frame_unwind = {
 973   NORMAL_FRAME,
 974   spu_frame_this_id,
 975   spu_frame_prev_register,
 976   NULL,
 977   default_frame_sniffer
 978 };
 979
 980 static CORE_ADDR
 981 spu_frame_base_address (struct frame_info *this_frame, void **this_cache)
 982 {
 983   struct spu_unwind_cache *info
 984     = spu_frame_unwind_cache (this_frame, this_cache);
 985   return info->local_base;
 986 }
 987
 988 static const struct frame_base spu_frame_base = {
 989   &spu_frame_unwind,
 990   spu_frame_base_address,
 991   spu_frame_base_address,
 992   spu_frame_base_address
 993 };
 994
 995 static CORE_ADDR
 996 spu_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
 997 {
 998   CORE_ADDR pc = frame_unwind_register_unsigned (next_frame, SPU_PC_REGNUM);
 999   /* Mask off interrupt enable bit.  */
1000   return pc & -4;
1001 }
1002
1003 static CORE_ADDR
1004 spu_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1005 {
1006   return frame_unwind_register_unsigned (next_frame, SPU_SP_REGNUM);
1007 }
1008
1009 static CORE_ADDR
1010 spu_read_pc (struct regcache *regcache)
1011 {
1012   ULONGEST pc;
1013   regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &pc);
1014   /* Mask off interrupt enable bit.  */
1015   return pc & -4;
1016 }
1017
1018 static void
1019 spu_write_pc (struct regcache *regcache, CORE_ADDR pc)
1020 {
1021   /* Keep interrupt enabled state unchanged.  */
1022   ULONGEST old_pc;
1023   regcache_cooked_read_unsigned (regcache, SPU_PC_REGNUM, &old_pc);
1024   regcache_cooked_write_unsigned (regcache, SPU_PC_REGNUM,
1025                                   (pc & -4) | (old_pc & 3));
1026 }
1027
1028
1029 /* Function calling convention.  */
1030
1031 static CORE_ADDR
1032 spu_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1033 {
1034   return sp & ~15;
1035 }
1036
1037 static CORE_ADDR
1038 spu_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
1039                      struct value **args, int nargs, struct type *value_type,
1040                      CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
1041                      struct regcache *regcache)
1042 {
1043   /* Allocate space sufficient for a breakpoint, keeping the stack aligned.  */
1044   sp = (sp - 4) & ~15;
1045   /* Store the address of that breakpoint */
1046   *bp_addr = sp;
1047   /* The call starts at the callee's entry point.  */
1048   *real_pc = funaddr;
1049
1050   return sp;
1051 }
1052
1053 static int
1054 spu_scalar_value_p (struct type *type)
1055 {
1056   switch (TYPE_CODE (type))
1057     {
1058     case TYPE_CODE_INT:
1059     case TYPE_CODE_ENUM:
1060     case TYPE_CODE_RANGE:
1061     case TYPE_CODE_CHAR:
1062     case TYPE_CODE_BOOL:
1063     case TYPE_CODE_PTR:
1064     case TYPE_CODE_REF:
1065       return TYPE_LENGTH (type) <= 16;
1066
1067     default:
1068       return 0;
1069     }
1070 }
1071
1072 static void
1073 spu_value_to_regcache (struct regcache *regcache, int regnum,
1074                        struct type *type, const gdb_byte *in)
1075 {
1076   int len = TYPE_LENGTH (type);
1077
1078   if (spu_scalar_value_p (type))
1079     {
1080       int preferred_slot = len < 4 ? 4 - len : 0;
1081       regcache_cooked_write_part (regcache, regnum, preferred_slot, len, in);
1082     }
1083   else
1084     {
1085       while (len >= 16)
1086         {
1087           regcache_cooked_write (regcache, regnum++, in);
1088           in += 16;
1089           len -= 16;
1090         }
1091
1092       if (len > 0)
1093         regcache_cooked_write_part (regcache, regnum, 0, len, in);
1094     }
1095 }
1096
1097 static void
1098 spu_regcache_to_value (struct regcache *regcache, int regnum,
1099                        struct type *type, gdb_byte *out)
1100 {
1101   int len = TYPE_LENGTH (type);
1102
1103   if (spu_scalar_value_p (type))
1104     {
1105       int preferred_slot = len < 4 ? 4 - len : 0;
1106       regcache_cooked_read_part (regcache, regnum, preferred_slot, len, out);
1107     }
1108   else
1109     {
1110       while (len >= 16)
1111         {
1112           regcache_cooked_read (regcache, regnum++, out);
1113           out += 16;
1114           len -= 16;
1115         }
1116
1117       if (len > 0)
1118         regcache_cooked_read_part (regcache, regnum, 0, len, out);
1119     }
1120 }
1121
1122 static CORE_ADDR
1123 spu_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1124                      struct regcache *regcache, CORE_ADDR bp_addr,
1125                      int nargs, struct value **args, CORE_ADDR sp,
1126                      int struct_return, CORE_ADDR struct_addr)
1127 {
1128   CORE_ADDR sp_delta;
1129   int i;
1130   int regnum = SPU_ARG1_REGNUM;
1131   int stack_arg = -1;
1132   gdb_byte buf[16];
1133
1134   /* Set the return address.  */
1135   memset (buf, 0, sizeof buf);
1136   store_unsigned_integer (buf, 4, bp_addr);
1137   regcache_cooked_write (regcache, SPU_LR_REGNUM, buf);
1138
1139   /* If STRUCT_RETURN is true, then the struct return address (in
1140      STRUCT_ADDR) will consume the first argument-passing register.
1141      Both adjust the register count and store that value.  */
1142   if (struct_return)
1143     {
1144       memset (buf, 0, sizeof buf);
1145       store_unsigned_integer (buf, 4, struct_addr);
1146       regcache_cooked_write (regcache, regnum++, buf);
1147     }
1148
1149   /* Fill in argument registers.  */
1150   for (i = 0; i < nargs; i++)
1151     {
1152       struct value *arg = args[i];
1153       struct type *type = check_typedef (value_type (arg));
1154       const gdb_byte *contents = value_contents (arg);
1155       int len = TYPE_LENGTH (type);
1156       int n_regs = align_up (len, 16) / 16;
1157
1158       /* If the argument doesn't wholly fit into registers, it and
1159          all subsequent arguments go to the stack.  */
1160       if (regnum + n_regs - 1 > SPU_ARGN_REGNUM)
1161         {
1162           stack_arg = i;
1163           break;
1164         }
1165
1166       spu_value_to_regcache (regcache, regnum, type, contents);
1167       regnum += n_regs;
1168     }
1169
1170   /* Overflow arguments go to the stack.  */
1171   if (stack_arg != -1)
1172     {
1173       CORE_ADDR ap;
1174
1175       /* Allocate all required stack size.  */
1176       for (i = stack_arg; i < nargs; i++)
1177         {
1178           struct type *type = check_typedef (value_type (args[i]));
1179           sp -= align_up (TYPE_LENGTH (type), 16);
1180         }
1181
1182       /* Fill in stack arguments.  */
1183       ap = sp;
1184       for (i = stack_arg; i < nargs; i++)
1185         {
1186           struct value *arg = args[i];
1187           struct type *type = check_typedef (value_type (arg));
1188           int len = TYPE_LENGTH (type);
1189           int preferred_slot;
1190
1191           if (spu_scalar_value_p (type))
1192             preferred_slot = len < 4 ? 4 - len : 0;
1193           else
1194             preferred_slot = 0;
1195
1196           target_write_memory (ap + preferred_slot, value_contents (arg), len);
1197           ap += align_up (TYPE_LENGTH (type), 16);
1198         }
1199     }
1200
1201   /* Allocate stack frame header.  */
1202   sp -= 32;
1203
1204   /* Store stack back chain.  */
1205   regcache_cooked_read (regcache, SPU_RAW_SP_REGNUM, buf);
1206   target_write_memory (sp, buf, 16);
1207
1208   /* Finally, update all slots of the SP register.  */
1209   sp_delta = sp - extract_unsigned_integer (buf, 4);
1210   for (i = 0; i < 4; i++)
1211     {
1212       CORE_ADDR sp_slot = extract_unsigned_integer (buf + 4*i, 4);
1213       store_unsigned_integer (buf + 4*i, 4, sp_slot + sp_delta);
1214     }
1215   regcache_cooked_write (regcache, SPU_RAW_SP_REGNUM, buf);
1216
1217   return sp;
1218 }
1219
1220 static struct frame_id
1221 spu_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1222 {
1223   CORE_ADDR pc = get_frame_register_unsigned (this_frame, SPU_PC_REGNUM);
1224   CORE_ADDR sp = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
1225   return frame_id_build (sp, pc & -4);
1226 }
1227
1228 /* Function return value access.  */
1229
1230 static enum return_value_convention
1231 spu_return_value (struct gdbarch *gdbarch, struct type *func_type,
1232                   struct type *type, struct regcache *regcache,
1233                   gdb_byte *out, const gdb_byte *in)
1234 {
1235   enum return_value_convention rvc;
1236
1237   if (TYPE_LENGTH (type) <= (SPU_ARGN_REGNUM - SPU_ARG1_REGNUM + 1) * 16)
1238     rvc = RETURN_VALUE_REGISTER_CONVENTION;
1239   else
1240     rvc = RETURN_VALUE_STRUCT_CONVENTION;
1241
1242   if (in)
1243     {
1244       switch (rvc)
1245         {
1246         case RETURN_VALUE_REGISTER_CONVENTION:
1247           spu_value_to_regcache (regcache, SPU_ARG1_REGNUM, type, in);
1248           break;
1249
1250         case RETURN_VALUE_STRUCT_CONVENTION:
1251           error ("Cannot set function return value.");
1252           break;
1253         }
1254     }
1255   else if (out)
1256     {
1257       switch (rvc)
1258         {
1259         case RETURN_VALUE_REGISTER_CONVENTION:
1260           spu_regcache_to_value (regcache, SPU_ARG1_REGNUM, type, out);
1261           break;
1262
1263         case RETURN_VALUE_STRUCT_CONVENTION:
1264           error ("Function return value unknown.");
1265           break;
1266         }
1267     }
1268
1269   return rvc;
1270 }
1271
1272
1273 /* Breakpoints.  */
1274
1275 static const gdb_byte *
1276 spu_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR * pcptr, int *lenptr)
1277 {
1278   static const gdb_byte breakpoint[] = { 0x00, 0x00, 0x3f, 0xff };
1279
1280   *lenptr = sizeof breakpoint;
1281   return breakpoint;
1282 }
1283
1284
1285 /* Software single-stepping support.  */
1286
1287 static int
1288 spu_software_single_step (struct frame_info *frame)
1289 {
1290   CORE_ADDR pc, next_pc;
1291   unsigned int insn;
1292   int offset, reg;
1293   gdb_byte buf[4];
1294
1295   pc = get_frame_pc (frame);
1296
1297   if (target_read_memory (pc, buf, 4))
1298     return 1;
1299   insn = extract_unsigned_integer (buf, 4);
1300
1301   /* Next sequential instruction is at PC + 4, except if the current
1302      instruction is a PPE-assisted call, in which case it is at PC + 8.
1303      Wrap around LS limit to be on the safe side.  */
1304   if ((insn & 0xffffff00) == 0x00002100)
1305     next_pc = (pc + 8) & (SPU_LS_SIZE - 1);
1306   else
1307     next_pc = (pc + 4) & (SPU_LS_SIZE - 1);
1308
1309   insert_single_step_breakpoint (next_pc);
1310
1311   if (is_branch (insn, &offset, &reg))
1312     {
1313       CORE_ADDR target = offset;
1314
1315       if (reg == SPU_PC_REGNUM)
1316         target += pc;
1317       else if (reg != -1)
1318         {
1319           get_frame_register_bytes (frame, reg, 0, 4, buf);
1320           target += extract_unsigned_integer (buf, 4) & -4;
1321         }
1322
1323       target = target & (SPU_LS_SIZE - 1);
1324       if (target != next_pc)
1325         insert_single_step_breakpoint (target);
1326     }
1327
1328   return 1;
1329 }
1330
1331
1332 /* Longjmp support.  */
1333
1334 static int
1335 spu_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc)
1336 {
1337   gdb_byte buf[4];
1338   CORE_ADDR jb_addr;
1339
1340   /* Jump buffer is pointed to by the argument register $r3.  */
1341   get_frame_register_bytes (frame, SPU_ARG1_REGNUM, 0, 4, buf);
1342   jb_addr = extract_unsigned_integer (buf, 4);
1343   if (target_read_memory (jb_addr, buf, 4))
1344     return 0;
1345
1346   *pc = extract_unsigned_integer (buf, 4);
1347   return 1;
1348 }
1349
1350
1351 /* Target overlays for the SPU overlay manager.
1352
1353    See the documentation of simple_overlay_update for how the
1354    interface is supposed to work.
1355
1356    Data structures used by the overlay manager:
1357
1358    struct ovly_table
1359      {
1360         u32 vma;
1361         u32 size;
1362         u32 pos;
1363         u32 buf;
1364      } _ovly_table[];   -- one entry per overlay section
1365
1366    struct ovly_buf_table
1367      {
1368         u32 mapped;
1369      } _ovly_buf_table[];  -- one entry per overlay buffer
1370
1371    _ovly_table should never change.
1372
1373    Both tables are aligned to a 16-byte boundary, the symbols _ovly_table
1374    and _ovly_buf_table are of type STT_OBJECT and their size set to the size
1375    of the respective array. buf in _ovly_table is an index into _ovly_buf_table.
1376
1377    mapped is an index into _ovly_table. Both the mapped and buf indices start
1378    from one to reference the first entry in their respective tables.  */
1379
1380 /* Using the per-objfile private data mechanism, we store for each
1381    objfile an array of "struct spu_overlay_table" structures, one
1382    for each obj_section of the objfile.  This structure holds two
1383    fields, MAPPED_PTR and MAPPED_VAL.  If MAPPED_PTR is zero, this
1384    is *not* an overlay section.  If it is non-zero, it represents
1385    a target address.  The overlay section is mapped iff the target
1386    integer at this location equals MAPPED_VAL.  */
1387
1388 static const struct objfile_data *spu_overlay_data;
1389
1390 struct spu_overlay_table
1391   {
1392     CORE_ADDR mapped_ptr;
1393     CORE_ADDR mapped_val;
1394   };
1395
1396 /* Retrieve the overlay table for OBJFILE.  If not already cached, read
1397    the _ovly_table data structure from the target and initialize the
1398    spu_overlay_table data structure from it.  */
1399 static struct spu_overlay_table *
1400 spu_get_overlay_table (struct objfile *objfile)
1401 {
1402   struct minimal_symbol *ovly_table_msym, *ovly_buf_table_msym;
1403   CORE_ADDR ovly_table_base, ovly_buf_table_base;
1404   unsigned ovly_table_size, ovly_buf_table_size;
1405   struct spu_overlay_table *tbl;
1406   struct obj_section *osect;
1407   char *ovly_table;
1408   int i;
1409
1410   tbl = objfile_data (objfile, spu_overlay_data);
1411   if (tbl)
1412     return tbl;
1413
1414   ovly_table_msym = lookup_minimal_symbol ("_ovly_table", NULL, objfile);
1415   if (!ovly_table_msym)
1416     return NULL;
1417
1418   ovly_buf_table_msym = lookup_minimal_symbol ("_ovly_buf_table", NULL, objfile);
1419   if (!ovly_buf_table_msym)
1420     return NULL;
1421
1422   ovly_table_base = SYMBOL_VALUE_ADDRESS (ovly_table_msym);
1423   ovly_table_size = MSYMBOL_SIZE (ovly_table_msym);
1424
1425   ovly_buf_table_base = SYMBOL_VALUE_ADDRESS (ovly_buf_table_msym);
1426   ovly_buf_table_size = MSYMBOL_SIZE (ovly_buf_table_msym);
1427
1428   ovly_table = xmalloc (ovly_table_size);
1429   read_memory (ovly_table_base, ovly_table, ovly_table_size);
1430
1431   tbl = OBSTACK_CALLOC (&objfile->objfile_obstack,
1432                         objfile->sections_end - objfile->sections,
1433                         struct spu_overlay_table);
1434
1435   for (i = 0; i < ovly_table_size / 16; i++)
1436     {
1437       CORE_ADDR vma  = extract_unsigned_integer (ovly_table + 16*i + 0, 4);
1438       CORE_ADDR size = extract_unsigned_integer (ovly_table + 16*i + 4, 4);
1439       CORE_ADDR pos  = extract_unsigned_integer (ovly_table + 16*i + 8, 4);
1440       CORE_ADDR buf  = extract_unsigned_integer (ovly_table + 16*i + 12, 4);
1441
1442       if (buf == 0 || (buf - 1) * 4 >= ovly_buf_table_size)
1443         continue;
1444
1445       ALL_OBJFILE_OSECTIONS (objfile, osect)
1446         if (vma == bfd_section_vma (objfile->obfd, osect->the_bfd_section)
1447             && pos == osect->the_bfd_section->filepos)
1448           {
1449             int ndx = osect - objfile->sections;
1450             tbl[ndx].mapped_ptr = ovly_buf_table_base + (buf - 1) * 4;
1451             tbl[ndx].mapped_val = i + 1;
1452             break;
1453           }
1454     }
1455
1456   xfree (ovly_table);
1457   set_objfile_data (objfile, spu_overlay_data, tbl);
1458   return tbl;
1459 }
1460
1461 /* Read _ovly_buf_table entry from the target to dermine whether
1462    OSECT is currently mapped, and update the mapped state.  */
1463 static void
1464 spu_overlay_update_osect (struct obj_section *osect)
1465 {
1466   struct spu_overlay_table *ovly_table;
1467   CORE_ADDR val;
1468
1469   ovly_table = spu_get_overlay_table (osect->objfile);
1470   if (!ovly_table)
1471     return;
1472
1473   ovly_table += osect - osect->objfile->sections;
1474   if (ovly_table->mapped_ptr == 0)
1475     return;
1476
1477   val = read_memory_unsigned_integer (ovly_table->mapped_ptr, 4);
1478   osect->ovly_mapped = (val == ovly_table->mapped_val);
1479 }
1480
1481 /* If OSECT is NULL, then update all sections' mapped state.
1482    If OSECT is non-NULL, then update only OSECT's mapped state.  */
1483 static void
1484 spu_overlay_update (struct obj_section *osect)
1485 {
1486   /* Just one section.  */
1487   if (osect)
1488     spu_overlay_update_osect (osect);
1489
1490   /* All sections.  */
1491   else
1492     {
1493       struct objfile *objfile;
1494
1495       ALL_OBJSECTIONS (objfile, osect)
1496         if (section_is_overlay (osect))
1497           spu_overlay_update_osect (osect);
1498     }
1499 }
1500
1501 /* Whenever a new objfile is loaded, read the target's _ovly_table.
1502    If there is one, go through all sections and make sure for non-
1503    overlay sections LMA equals VMA, while for overlay sections LMA
1504    is larger than local store size.  */
1505 static void
1506 spu_overlay_new_objfile (struct objfile *objfile)
1507 {
1508   struct spu_overlay_table *ovly_table;
1509   struct obj_section *osect;
1510
1511   /* If we've already touched this file, do nothing.  */
1512   if (!objfile || objfile_data (objfile, spu_overlay_data) != NULL)
1513     return;
1514
1515   /* Consider only SPU objfiles.  */
1516   if (bfd_get_arch (objfile->obfd) != bfd_arch_spu)
1517     return;
1518
1519   /* Check if this objfile has overlays.  */
1520   ovly_table = spu_get_overlay_table (objfile);
1521   if (!ovly_table)
1522     return;
1523
1524   /* Now go and fiddle with all the LMAs.  */
1525   ALL_OBJFILE_OSECTIONS (objfile, osect)
1526     {
1527       bfd *obfd = objfile->obfd;
1528       asection *bsect = osect->the_bfd_section;
1529       int ndx = osect - objfile->sections;
1530
1531       if (ovly_table[ndx].mapped_ptr == 0)
1532         bfd_section_lma (obfd, bsect) = bfd_section_vma (obfd, bsect);
1533       else
1534         bfd_section_lma (obfd, bsect) = bsect->filepos + SPU_LS_SIZE;
1535     }
1536 }
1537
1538
1539 /* "info spu" commands.  */
1540
1541 static void
1542 info_spu_event_command (char *args, int from_tty)
1543 {
1544   struct frame_info *frame = get_selected_frame (NULL);
1545   ULONGEST event_status = 0;
1546   ULONGEST event_mask = 0;
1547   struct cleanup *chain;
1548   gdb_byte buf[100];
1549   char annex[32];
1550   LONGEST len;
1551   int rc, id;
1552
1553   if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
1554     error (_("\"info spu\" is only supported on the SPU architecture."));
1555
1556   id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1557
1558   xsnprintf (annex, sizeof annex, "%d/event_status", id);
1559   len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1560                      buf, 0, (sizeof (buf) - 1));
1561   if (len <= 0)
1562     error (_("Could not read event_status."));
1563   buf[len] = '\0';
1564   event_status = strtoulst (buf, NULL, 16);
1565
1566   xsnprintf (annex, sizeof annex, "%d/event_mask", id);
1567   len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1568                      buf, 0, (sizeof (buf) - 1));
1569   if (len <= 0)
1570     error (_("Could not read event_mask."));
1571   buf[len] = '\0';
1572   event_mask = strtoulst (buf, NULL, 16);
1573
1574   chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoEvent");
1575
1576   if (ui_out_is_mi_like_p (uiout))
1577     {
1578       ui_out_field_fmt (uiout, "event_status",
1579                         "0x%s", phex_nz (event_status, 4));
1580       ui_out_field_fmt (uiout, "event_mask",
1581                         "0x%s", phex_nz (event_mask, 4));
1582     }
1583   else
1584     {
1585       printf_filtered (_("Event Status 0x%s\n"), phex (event_status, 4));
1586       printf_filtered (_("Event Mask   0x%s\n"), phex (event_mask, 4));
1587     }
1588
1589   do_cleanups (chain);
1590 }
1591
1592 static void
1593 info_spu_signal_command (char *args, int from_tty)
1594 {
1595   struct frame_info *frame = get_selected_frame (NULL);
1596   ULONGEST signal1 = 0;
1597   ULONGEST signal1_type = 0;
1598   int signal1_pending = 0;
1599   ULONGEST signal2 = 0;
1600   ULONGEST signal2_type = 0;
1601   int signal2_pending = 0;
1602   struct cleanup *chain;
1603   char annex[32];
1604   gdb_byte buf[100];
1605   LONGEST len;
1606   int rc, id;
1607
1608   if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
1609     error (_("\"info spu\" is only supported on the SPU architecture."));
1610
1611   id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1612
1613   xsnprintf (annex, sizeof annex, "%d/signal1", id);
1614   len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
1615   if (len < 0)
1616     error (_("Could not read signal1."));
1617   else if (len == 4)
1618     {
1619       signal1 = extract_unsigned_integer (buf, 4);
1620       signal1_pending = 1;
1621     }
1622
1623   xsnprintf (annex, sizeof annex, "%d/signal1_type", id);
1624   len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1625                      buf, 0, (sizeof (buf) - 1));
1626   if (len <= 0)
1627     error (_("Could not read signal1_type."));
1628   buf[len] = '\0';
1629   signal1_type = strtoulst (buf, NULL, 16);
1630
1631   xsnprintf (annex, sizeof annex, "%d/signal2", id);
1632   len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
1633   if (len < 0)
1634     error (_("Could not read signal2."));
1635   else if (len == 4)
1636     {
1637       signal2 = extract_unsigned_integer (buf, 4);
1638       signal2_pending = 1;
1639     }
1640
1641   xsnprintf (annex, sizeof annex, "%d/signal2_type", id);
1642   len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1643                      buf, 0, (sizeof (buf) - 1));
1644   if (len <= 0)
1645     error (_("Could not read signal2_type."));
1646   buf[len] = '\0';
1647   signal2_type = strtoulst (buf, NULL, 16);
1648
1649   chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoSignal");
1650
1651   if (ui_out_is_mi_like_p (uiout))
1652     {
1653       ui_out_field_int (uiout, "signal1_pending", signal1_pending);
1654       ui_out_field_fmt (uiout, "signal1", "0x%s", phex_nz (signal1, 4));
1655       ui_out_field_int (uiout, "signal1_type", signal1_type);
1656       ui_out_field_int (uiout, "signal2_pending", signal2_pending);
1657       ui_out_field_fmt (uiout, "signal2", "0x%s", phex_nz (signal2, 4));
1658       ui_out_field_int (uiout, "signal2_type", signal2_type);
1659     }
1660   else
1661     {
1662       if (signal1_pending)
1663         printf_filtered (_("Signal 1 control word 0x%s "), phex (signal1, 4));
1664       else
1665         printf_filtered (_("Signal 1 not pending "));
1666
1667       if (signal1_type)
1668         printf_filtered (_("(Type Or)\n"));
1669       else
1670         printf_filtered (_("(Type Overwrite)\n"));
1671
1672       if (signal2_pending)
1673         printf_filtered (_("Signal 2 control word 0x%s "), phex (signal2, 4));
1674       else
1675         printf_filtered (_("Signal 2 not pending "));
1676
1677       if (signal2_type)
1678         printf_filtered (_("(Type Or)\n"));
1679       else
1680         printf_filtered (_("(Type Overwrite)\n"));
1681     }
1682
1683   do_cleanups (chain);
1684 }
1685
1686 static void
1687 info_spu_mailbox_list (gdb_byte *buf, int nr,
1688                        const char *field, const char *msg)
1689 {
1690   struct cleanup *chain;
1691   int i;
1692
1693   if (nr <= 0)
1694     return;
1695
1696   chain = make_cleanup_ui_out_table_begin_end (uiout, 1, nr, "mbox");
1697
1698   ui_out_table_header (uiout, 32, ui_left, field, msg);
1699   ui_out_table_body (uiout);
1700
1701   for (i = 0; i < nr; i++)
1702     {
1703       struct cleanup *val_chain;
1704       ULONGEST val;
1705       val_chain = make_cleanup_ui_out_tuple_begin_end (uiout, "mbox");
1706       val = extract_unsigned_integer (buf + 4*i, 4);
1707       ui_out_field_fmt (uiout, field, "0x%s", phex (val, 4));
1708       do_cleanups (val_chain);
1709
1710       if (!ui_out_is_mi_like_p (uiout))
1711         printf_filtered ("\n");
1712     }
1713
1714   do_cleanups (chain);
1715 }
1716
1717 static void
1718 info_spu_mailbox_command (char *args, int from_tty)
1719 {
1720   struct frame_info *frame = get_selected_frame (NULL);
1721   struct cleanup *chain;
1722   char annex[32];
1723   gdb_byte buf[1024];
1724   LONGEST len;
1725   int i, id;
1726
1727   if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
1728     error (_("\"info spu\" is only supported on the SPU architecture."));
1729
1730   id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1731
1732   chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoMailbox");
1733
1734   xsnprintf (annex, sizeof annex, "%d/mbox_info", id);
1735   len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1736                      buf, 0, sizeof buf);
1737   if (len < 0)
1738     error (_("Could not read mbox_info."));
1739
1740   info_spu_mailbox_list (buf, len / 4, "mbox", "SPU Outbound Mailbox");
1741
1742   xsnprintf (annex, sizeof annex, "%d/ibox_info", id);
1743   len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1744                      buf, 0, sizeof buf);
1745   if (len < 0)
1746     error (_("Could not read ibox_info."));
1747
1748   info_spu_mailbox_list (buf, len / 4, "ibox", "SPU Outbound Interrupt Mailbox");
1749
1750   xsnprintf (annex, sizeof annex, "%d/wbox_info", id);
1751   len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1752                      buf, 0, sizeof buf);
1753   if (len < 0)
1754     error (_("Could not read wbox_info."));
1755
1756   info_spu_mailbox_list (buf, len / 4, "wbox", "SPU Inbound Mailbox");
1757
1758   do_cleanups (chain);
1759 }
1760
1761 static ULONGEST
1762 spu_mfc_get_bitfield (ULONGEST word, int first, int last)
1763 {
1764   ULONGEST mask = ~(~(ULONGEST)0 << (last - first + 1));
1765   return (word >> (63 - last)) & mask;
1766 }
1767
1768 static void
1769 info_spu_dma_cmdlist (gdb_byte *buf, int nr)
1770 {
1771   static char *spu_mfc_opcode[256] =
1772     {
1773     /* 00 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1774              NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1775     /* 10 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1776              NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1777     /* 20 */ "put", "putb", "putf", NULL, "putl", "putlb", "putlf", NULL,
1778              "puts", "putbs", "putfs", NULL, NULL, NULL, NULL, NULL,
1779     /* 30 */ "putr", "putrb", "putrf", NULL, "putrl", "putrlb", "putrlf", NULL,
1780              NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1781     /* 40 */ "get", "getb", "getf", NULL, "getl", "getlb", "getlf", NULL,
1782              "gets", "getbs", "getfs", NULL, NULL, NULL, NULL, NULL,
1783     /* 50 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1784              NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1785     /* 60 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1786              NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1787     /* 70 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1788              NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1789     /* 80 */ "sdcrt", "sdcrtst", NULL, NULL, NULL, NULL, NULL, NULL,
1790              NULL, "sdcrz", NULL, NULL, NULL, "sdcrst", NULL, "sdcrf",
1791     /* 90 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1792              NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1793     /* a0 */ "sndsig", "sndsigb", "sndsigf", NULL, NULL, NULL, NULL, NULL,
1794              NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1795     /* b0 */ "putlluc", NULL, NULL, NULL, "putllc", NULL, NULL, NULL,
1796              "putqlluc", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1797     /* c0 */ "barrier", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1798              "mfceieio", NULL, NULL, NULL, "mfcsync", NULL, NULL, NULL,
1799     /* d0 */ "getllar", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1800              NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1801     /* e0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1802              NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1803     /* f0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1804              NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1805     };
1806
1807   int *seq = alloca (nr * sizeof (int));
1808   int done = 0;
1809   struct cleanup *chain;
1810   int i, j;
1811
1812
1813   /* Determine sequence in which to display (valid) entries.  */
1814   for (i = 0; i < nr; i++)
1815     {
1816       /* Search for the first valid entry all of whose
1817          dependencies are met.  */
1818       for (j = 0; j < nr; j++)
1819         {
1820           ULONGEST mfc_cq_dw3;
1821           ULONGEST dependencies;
1822
1823           if (done & (1 << (nr - 1 - j)))
1824             continue;
1825
1826           mfc_cq_dw3 = extract_unsigned_integer (buf + 32*j + 24, 8);
1827           if (!spu_mfc_get_bitfield (mfc_cq_dw3, 16, 16))
1828             continue;
1829
1830           dependencies = spu_mfc_get_bitfield (mfc_cq_dw3, 0, nr - 1);
1831           if ((dependencies & done) != dependencies)
1832             continue;
1833
1834           seq[i] = j;
1835           done |= 1 << (nr - 1 - j);
1836           break;
1837         }
1838
1839       if (j == nr)
1840         break;
1841     }
1842
1843   nr = i;
1844
1845
1846   chain = make_cleanup_ui_out_table_begin_end (uiout, 10, nr, "dma_cmd");
1847
1848   ui_out_table_header (uiout, 7, ui_left, "opcode", "Opcode");
1849   ui_out_table_header (uiout, 3, ui_left, "tag", "Tag");
1850   ui_out_table_header (uiout, 3, ui_left, "tid", "TId");
1851   ui_out_table_header (uiout, 3, ui_left, "rid", "RId");
1852   ui_out_table_header (uiout, 18, ui_left, "ea", "EA");
1853   ui_out_table_header (uiout, 7, ui_left, "lsa", "LSA");
1854   ui_out_table_header (uiout, 7, ui_left, "size", "Size");
1855   ui_out_table_header (uiout, 7, ui_left, "lstaddr", "LstAddr");
1856   ui_out_table_header (uiout, 7, ui_left, "lstsize", "LstSize");
1857   ui_out_table_header (uiout, 1, ui_left, "error_p", "E");
1858
1859   ui_out_table_body (uiout);
1860
1861   for (i = 0; i < nr; i++)
1862     {
1863       struct cleanup *cmd_chain;
1864       ULONGEST mfc_cq_dw0;
1865       ULONGEST mfc_cq_dw1;
1866       ULONGEST mfc_cq_dw2;
1867       int mfc_cmd_opcode, mfc_cmd_tag, rclass_id, tclass_id;
1868       int lsa, size, list_lsa, list_size, mfc_lsa, mfc_size;
1869       ULONGEST mfc_ea;
1870       int list_valid_p, noop_valid_p, qw_valid_p, ea_valid_p, cmd_error_p;
1871
1872       /* Decode contents of MFC Command Queue Context Save/Restore Registers.
1873          See "Cell Broadband Engine Registers V1.3", section 3.3.2.1.  */
1874
1875       mfc_cq_dw0 = extract_unsigned_integer (buf + 32*seq[i], 8);
1876       mfc_cq_dw1 = extract_unsigned_integer (buf + 32*seq[i] + 8, 8);
1877       mfc_cq_dw2 = extract_unsigned_integer (buf + 32*seq[i] + 16, 8);
1878
1879       list_lsa = spu_mfc_get_bitfield (mfc_cq_dw0, 0, 14);
1880       list_size = spu_mfc_get_bitfield (mfc_cq_dw0, 15, 26);
1881       mfc_cmd_opcode = spu_mfc_get_bitfield (mfc_cq_dw0, 27, 34);
1882       mfc_cmd_tag = spu_mfc_get_bitfield (mfc_cq_dw0, 35, 39);
1883       list_valid_p = spu_mfc_get_bitfield (mfc_cq_dw0, 40, 40);
1884       rclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 41, 43);
1885       tclass_id = spu_mfc_get_bitfield (mfc_cq_dw0, 44, 46);
1886
1887       mfc_ea = spu_mfc_get_bitfield (mfc_cq_dw1, 0, 51) << 12
1888                 | spu_mfc_get_bitfield (mfc_cq_dw2, 25, 36);
1889
1890       mfc_lsa = spu_mfc_get_bitfield (mfc_cq_dw2, 0, 13);
1891       mfc_size = spu_mfc_get_bitfield (mfc_cq_dw2, 14, 24);
1892       noop_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 37, 37);
1893       qw_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 38, 38);
1894       ea_valid_p = spu_mfc_get_bitfield (mfc_cq_dw2, 39, 39);
1895       cmd_error_p = spu_mfc_get_bitfield (mfc_cq_dw2, 40, 40);
1896
1897       cmd_chain = make_cleanup_ui_out_tuple_begin_end (uiout, "cmd");
1898
1899       if (spu_mfc_opcode[mfc_cmd_opcode])
1900         ui_out_field_string (uiout, "opcode", spu_mfc_opcode[mfc_cmd_opcode]);
1901       else
1902         ui_out_field_int (uiout, "opcode", mfc_cmd_opcode);
1903
1904       ui_out_field_int (uiout, "tag", mfc_cmd_tag);
1905       ui_out_field_int (uiout, "tid", tclass_id);
1906       ui_out_field_int (uiout, "rid", rclass_id);
1907
1908       if (ea_valid_p)
1909         ui_out_field_fmt (uiout, "ea", "0x%s", phex (mfc_ea, 8));
1910       else
1911         ui_out_field_skip (uiout, "ea");
1912
1913       ui_out_field_fmt (uiout, "lsa", "0x%05x", mfc_lsa << 4);
1914       if (qw_valid_p)
1915         ui_out_field_fmt (uiout, "size", "0x%05x", mfc_size << 4);
1916       else
1917         ui_out_field_fmt (uiout, "size", "0x%05x", mfc_size);
1918
1919       if (list_valid_p)
1920         {
1921           ui_out_field_fmt (uiout, "lstaddr", "0x%05x", list_lsa << 3);
1922           ui_out_field_fmt (uiout, "lstsize", "0x%05x", list_size << 3);
1923         }
1924       else
1925         {
1926           ui_out_field_skip (uiout, "lstaddr");
1927           ui_out_field_skip (uiout, "lstsize");
1928         }
1929
1930       if (cmd_error_p)
1931         ui_out_field_string (uiout, "error_p", "*");
1932       else
1933         ui_out_field_skip (uiout, "error_p");
1934
1935       do_cleanups (cmd_chain);
1936
1937       if (!ui_out_is_mi_like_p (uiout))
1938         printf_filtered ("\n");
1939     }
1940
1941   do_cleanups (chain);
1942 }
1943
1944 static void
1945 info_spu_dma_command (char *args, int from_tty)
1946 {
1947   struct frame_info *frame = get_selected_frame (NULL);
1948   ULONGEST dma_info_type;
1949   ULONGEST dma_info_mask;
1950   ULONGEST dma_info_status;
1951   ULONGEST dma_info_stall_and_notify;
1952   ULONGEST dma_info_atomic_command_status;
1953   struct cleanup *chain;
1954   char annex[32];
1955   gdb_byte buf[1024];
1956   LONGEST len;
1957   int i, id;
1958
1959   if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
1960     error (_("\"info spu\" is only supported on the SPU architecture."));
1961
1962   id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
1963
1964   xsnprintf (annex, sizeof annex, "%d/dma_info", id);
1965   len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
1966                      buf, 0, 40 + 16 * 32);
1967   if (len <= 0)
1968     error (_("Could not read dma_info."));
1969
1970   dma_info_type = extract_unsigned_integer (buf, 8);
1971   dma_info_mask = extract_unsigned_integer (buf + 8, 8);
1972   dma_info_status = extract_unsigned_integer (buf + 16, 8);
1973   dma_info_stall_and_notify = extract_unsigned_integer (buf + 24, 8);
1974   dma_info_atomic_command_status = extract_unsigned_integer (buf + 32, 8);
1975
1976   chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoDMA");
1977
1978   if (ui_out_is_mi_like_p (uiout))
1979     {
1980       ui_out_field_fmt (uiout, "dma_info_type", "0x%s",
1981                         phex_nz (dma_info_type, 4));
1982       ui_out_field_fmt (uiout, "dma_info_mask", "0x%s",
1983                         phex_nz (dma_info_mask, 4));
1984       ui_out_field_fmt (uiout, "dma_info_status", "0x%s",
1985                         phex_nz (dma_info_status, 4));
1986       ui_out_field_fmt (uiout, "dma_info_stall_and_notify", "0x%s",
1987                         phex_nz (dma_info_stall_and_notify, 4));
1988       ui_out_field_fmt (uiout, "dma_info_atomic_command_status", "0x%s",
1989                         phex_nz (dma_info_atomic_command_status, 4));
1990     }
1991   else
1992     {
1993       const char *query_msg = _("no query pending");
1994
1995       if (dma_info_type & 4)
1996         switch (dma_info_type & 3)
1997           {
1998             case 1: query_msg = _("'any' query pending"); break;
1999             case 2: query_msg = _("'all' query pending"); break;
2000             default: query_msg = _("undefined query type"); break;
2001           }
2002
2003       printf_filtered (_("Tag-Group Status  0x%s\n"),
2004                        phex (dma_info_status, 4));
2005       printf_filtered (_("Tag-Group Mask    0x%s (%s)\n"),
2006                        phex (dma_info_mask, 4), query_msg);
2007       printf_filtered (_("Stall-and-Notify  0x%s\n"),
2008                        phex (dma_info_stall_and_notify, 4));
2009       printf_filtered (_("Atomic Cmd Status 0x%s\n"),
2010                        phex (dma_info_atomic_command_status, 4));
2011       printf_filtered ("\n");
2012     }
2013
2014   info_spu_dma_cmdlist (buf + 40, 16);
2015   do_cleanups (chain);
2016 }
2017
2018 static void
2019 info_spu_proxydma_command (char *args, int from_tty)
2020 {
2021   struct frame_info *frame = get_selected_frame (NULL);
2022   ULONGEST dma_info_type;
2023   ULONGEST dma_info_mask;
2024   ULONGEST dma_info_status;
2025   struct cleanup *chain;
2026   char annex[32];
2027   gdb_byte buf[1024];
2028   LONGEST len;
2029   int i, id;
2030
2031   if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
2032     error (_("\"info spu\" is only supported on the SPU architecture."));
2033
2034   id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
2035
2036   xsnprintf (annex, sizeof annex, "%d/proxydma_info", id);
2037   len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
2038                      buf, 0, 24 + 8 * 32);
2039   if (len <= 0)
2040     error (_("Could not read proxydma_info."));
2041
2042   dma_info_type = extract_unsigned_integer (buf, 8);
2043   dma_info_mask = extract_unsigned_integer (buf + 8, 8);
2044   dma_info_status = extract_unsigned_integer (buf + 16, 8);
2045
2046   chain = make_cleanup_ui_out_tuple_begin_end (uiout, "SPUInfoProxyDMA");
2047
2048   if (ui_out_is_mi_like_p (uiout))
2049     {
2050       ui_out_field_fmt (uiout, "proxydma_info_type", "0x%s",
2051                         phex_nz (dma_info_type, 4));
2052       ui_out_field_fmt (uiout, "proxydma_info_mask", "0x%s",
2053                         phex_nz (dma_info_mask, 4));
2054       ui_out_field_fmt (uiout, "proxydma_info_status", "0x%s",
2055                         phex_nz (dma_info_status, 4));
2056     }
2057   else
2058     {
2059       const char *query_msg;
2060
2061       switch (dma_info_type & 3)
2062         {
2063         case 0: query_msg = _("no query pending"); break;
2064         case 1: query_msg = _("'any' query pending"); break;
2065         case 2: query_msg = _("'all' query pending"); break;
2066         default: query_msg = _("undefined query type"); break;
2067         }
2068
2069       printf_filtered (_("Tag-Group Status  0x%s\n"),
2070                        phex (dma_info_status, 4));
2071       printf_filtered (_("Tag-Group Mask    0x%s (%s)\n"),
2072                        phex (dma_info_mask, 4), query_msg);
2073       printf_filtered ("\n");
2074     }
2075
2076   info_spu_dma_cmdlist (buf + 24, 8);
2077   do_cleanups (chain);
2078 }
2079
2080 static void
2081 info_spu_command (char *args, int from_tty)
2082 {
2083   printf_unfiltered (_("\"info spu\" must be followed by the name of an SPU facility.\n"));
2084   help_list (infospucmdlist, "info spu ", -1, gdb_stdout);
2085 }
2086
2087
2088 /* Set up gdbarch struct.  */
2089
2090 static struct gdbarch *
2091 spu_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2092 {
2093   struct gdbarch *gdbarch;
2094   struct gdbarch_tdep *tdep;
2095
2096   /* Find a candidate among the list of pre-declared architectures.  */
2097   arches = gdbarch_list_lookup_by_info (arches, &info);
2098   if (arches != NULL)
2099     return arches->gdbarch;
2100
2101   /* Is is for us?  */
2102   if (info.bfd_arch_info->mach != bfd_mach_spu)
2103     return NULL;
2104
2105   /* Yes, create a new architecture.  */
2106   tdep = XCALLOC (1, struct gdbarch_tdep);
2107   gdbarch = gdbarch_alloc (&info, tdep);
2108
2109   /* Disassembler.  */
2110   set_gdbarch_print_insn (gdbarch, print_insn_spu);
2111
2112   /* Registers.  */
2113   set_gdbarch_num_regs (gdbarch, SPU_NUM_REGS);
2114   set_gdbarch_num_pseudo_regs (gdbarch, SPU_NUM_PSEUDO_REGS);
2115   set_gdbarch_sp_regnum (gdbarch, SPU_SP_REGNUM);
2116   set_gdbarch_pc_regnum (gdbarch, SPU_PC_REGNUM);
2117   set_gdbarch_read_pc (gdbarch, spu_read_pc);
2118   set_gdbarch_write_pc (gdbarch, spu_write_pc);
2119   set_gdbarch_register_name (gdbarch, spu_register_name);
2120   set_gdbarch_register_type (gdbarch, spu_register_type);
2121   set_gdbarch_pseudo_register_read (gdbarch, spu_pseudo_register_read);
2122   set_gdbarch_pseudo_register_write (gdbarch, spu_pseudo_register_write);
2123   set_gdbarch_value_from_register (gdbarch, spu_value_from_register);
2124   set_gdbarch_register_reggroup_p (gdbarch, spu_register_reggroup_p);
2125
2126   /* Data types.  */
2127   set_gdbarch_char_signed (gdbarch, 0);
2128   set_gdbarch_ptr_bit (gdbarch, 32);
2129   set_gdbarch_addr_bit (gdbarch, 32);
2130   set_gdbarch_short_bit (gdbarch, 16);
2131   set_gdbarch_int_bit (gdbarch, 32);
2132   set_gdbarch_long_bit (gdbarch, 32);
2133   set_gdbarch_long_long_bit (gdbarch, 64);
2134   set_gdbarch_float_bit (gdbarch, 32);
2135   set_gdbarch_double_bit (gdbarch, 64);
2136   set_gdbarch_long_double_bit (gdbarch, 64);
2137   set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2138   set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2139   set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
2140
2141   /* Address conversion.  */
2142   set_gdbarch_pointer_to_address (gdbarch, spu_pointer_to_address);
2143   set_gdbarch_integer_to_address (gdbarch, spu_integer_to_address);
2144
2145   /* Inferior function calls.  */
2146   set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2147   set_gdbarch_frame_align (gdbarch, spu_frame_align);
2148   set_gdbarch_frame_red_zone_size (gdbarch, 2000);
2149   set_gdbarch_push_dummy_code (gdbarch, spu_push_dummy_code);
2150   set_gdbarch_push_dummy_call (gdbarch, spu_push_dummy_call);
2151   set_gdbarch_dummy_id (gdbarch, spu_dummy_id);
2152   set_gdbarch_return_value (gdbarch, spu_return_value);
2153
2154   /* Frame handling.  */
2155   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2156   frame_unwind_append_unwinder (gdbarch, &spu_frame_unwind);
2157   frame_base_set_default (gdbarch, &spu_frame_base);
2158   set_gdbarch_unwind_pc (gdbarch, spu_unwind_pc);
2159   set_gdbarch_unwind_sp (gdbarch, spu_unwind_sp);
2160   set_gdbarch_virtual_frame_pointer (gdbarch, spu_virtual_frame_pointer);
2161   set_gdbarch_frame_args_skip (gdbarch, 0);
2162   set_gdbarch_skip_prologue (gdbarch, spu_skip_prologue);
2163   set_gdbarch_in_function_epilogue_p (gdbarch, spu_in_function_epilogue_p);
2164
2165   /* Breakpoints.  */
2166   set_gdbarch_decr_pc_after_break (gdbarch, 4);
2167   set_gdbarch_breakpoint_from_pc (gdbarch, spu_breakpoint_from_pc);
2168   set_gdbarch_cannot_step_breakpoint (gdbarch, 1);
2169   set_gdbarch_software_single_step (gdbarch, spu_software_single_step);
2170   set_gdbarch_get_longjmp_target (gdbarch, spu_get_longjmp_target);
2171
2172   /* Overlays.  */
2173   set_gdbarch_overlay_update (gdbarch, spu_overlay_update);
2174
2175   return gdbarch;
2176 }
2177
2178 /* Provide a prototype to silence -Wmissing-prototypes.  */
2179 extern initialize_file_ftype _initialize_spu_tdep;
2180
2181 void
2182 _initialize_spu_tdep (void)
2183 {
2184   register_gdbarch_init (bfd_arch_spu, spu_gdbarch_init);
2185
2186   /* Add ourselves to objfile event chain.  */
2187   observer_attach_new_objfile (spu_overlay_new_objfile);
2188   spu_overlay_data = register_objfile_data ();
2189
2190   /* Add root prefix command for all "info spu" commands.  */
2191   add_prefix_cmd ("spu", class_info, info_spu_command,
2192                   _("Various SPU specific commands."),
2193                   &infospucmdlist, "info spu ", 0, &infolist);
2194
2195   /* Add various "info spu" commands.  */
2196   add_cmd ("event", class_info, info_spu_event_command,
2197            _("Display SPU event facility status.\n"),
2198            &infospucmdlist);
2199   add_cmd ("signal", class_info, info_spu_signal_command,
2200            _("Display SPU signal notification facility status.\n"),
2201            &infospucmdlist);
2202   add_cmd ("mailbox", class_info, info_spu_mailbox_command,
2203            _("Display SPU mailbox facility status.\n"),
2204            &infospucmdlist);
2205   add_cmd ("dma", class_info, info_spu_dma_command,
2206            _("Display MFC DMA status.\n"),
2207            &infospucmdlist);
2208   add_cmd ("proxydma", class_info, info_spu_proxydma_command,
2209            _("Display MFC Proxy-DMA status.\n"),
2210            &infospucmdlist);
2211 }