2 <xi:include href=
"core-regs.xml"/>
4 <vector id=
"v4int8" type=
"int8" count=
"4"/>
5 <vector id=
"v2int16" type=
"int16" count=
"2"/>
7 <field name=
"v4" type=
"v4int8"/>
8 <field name=
"v2" type=
"v2int16"/>
12 <field name=
"v4" type=
"v4int8"/>
13 <field name=
"v2" type=
"v2int16"/>
16 <struct id=
"struct2" size=
"8">
17 <field name=
"f1" start=
"0" end=
"34"/>
18 <field name=
"f2" start=
"63" end=
"63"/>
21 <flags id=
"flags" size=
"4">
22 <field name=
"X" start=
"0" end=
"0"/>
23 <field name=
"Y" start=
"2" end=
"2"/>
26 <enum id=
"Z_values" size=
"4">
27 <evalue name=
"yes" value=
"1"/>
28 <evalue name=
"no" value=
"0"/>
29 <evalue name=
"maybe" value=
"2"/>
30 <evalue name=
"so" value=
"3"/>
33 <flags id=
"mixed_flags" size=
"4">
34 <!-- Elided end and type. -->
35 <field name=
"A" start=
"0"/>
36 <!-- Elided end, unsigned int. -->
37 <field name=
"B" start=
"1" type=
"uint32"/>
38 <!-- Elided end, bool. -->
39 <field name=
"C" start=
"2" type=
"bool"/>
40 <!-- Elided type, single bitfield. -->
41 <field name=
"D" start=
"3" end=
"3"/>
42 <!-- Anonymous field. -->
43 <field name=
"" start=
"4" end=
"5"/>
44 <!-- Multi-bit bitfield, elided type. -->
45 <field name=
"E" start=
"6" end=
"7"/>
46 <!-- Enum bitfield. -->
47 <field name=
"Z" start=
"8" end=
"9" type=
"Z_values"/>
50 <reg name=
"extrareg" bitsize=
"32"/>
51 <reg name=
"uintreg" bitsize=
"32" type=
"uint32"/>
52 <reg name=
"vecreg" bitsize=
"32" type=
"v4int8"/>
53 <reg name=
"unionreg" bitsize=
"32" type=
"vecint"/>
54 <reg name=
"structreg" bitsize=
"64" type=
"struct1"/>
55 <reg name=
"bitfields" bitsize=
"64" type=
"struct2"/>
56 <reg name=
"flags" bitsize=
"32" type=
"flags"/>
57 <reg name=
"mixed_flags" bitsize=
"32" type=
"mixed_flags"/>
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