1 /* Target dependent code for GDB on TI C6x systems.
3 Copyright (C) 2010-2016 Free Software Foundation, Inc.
4 Contributed by Andrew Jenner <andrew@codesourcery.com>
5 Contributed by Yao Qi <yao@codesourcery.com>
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "frame-unwind.h"
25 #include "frame-base.h"
26 #include "trad-frame.h"
27 #include "dwarf2-frame.h"
38 #include "arch-utils.h"
39 #include "floatformat.h"
40 #include "glibc-tdep.h"
43 #include "tramp-frame.h"
44 #include "linux-tdep.h"
48 #include "tic6x-tdep.h"
50 #include "target-descriptions.h"
53 #include "features/tic6x-c64xp.c"
54 #include "features/tic6x-c64x.c"
55 #include "features/tic6x-c62x.c"
57 #define TIC6X_OPCODE_SIZE 4
58 #define TIC6X_FETCH_PACKET_SIZE 32
60 #define INST_S_BIT(INST) ((INST >> 1) & 1)
61 #define INST_X_BIT(INST) ((INST >> 12) & 1)
63 const gdb_byte tic6x_bkpt_illegal_opcode_be
[] = { 0x56, 0x45, 0x43, 0x14 };
64 const gdb_byte tic6x_bkpt_illegal_opcode_le
[] = { 0x14, 0x43, 0x45, 0x56 };
66 struct tic6x_unwind_cache
68 /* The frame's base, optionally used by the high-level debug info. */
71 /* The previous frame's inner most stack address. Used as this
72 frame ID's stack_addr. */
75 /* The address of the first instruction in this function */
78 /* Which register holds the return address for the frame. */
81 /* The offset of register saved on stack. If register is not saved, the
82 corresponding element is -1. */
83 CORE_ADDR reg_saved
[TIC6X_NUM_CORE_REGS
];
87 /* Name of TI C6x core registers. */
88 static const char *const tic6x_register_names
[] =
90 "A0", "A1", "A2", "A3", /* 0 1 2 3 */
91 "A4", "A5", "A6", "A7", /* 4 5 6 7 */
92 "A8", "A9", "A10", "A11", /* 8 9 10 11 */
93 "A12", "A13", "A14", "A15", /* 12 13 14 15 */
94 "B0", "B1", "B2", "B3", /* 16 17 18 19 */
95 "B4", "B5", "B6", "B7", /* 20 21 22 23 */
96 "B8", "B9", "B10", "B11", /* 24 25 26 27 */
97 "B12", "B13", "B14", "B15", /* 28 29 30 31 */
98 "CSR", "PC", /* 32 33 */
101 /* This array maps the arguments to the register number which passes argument
102 in function call according to C6000 ELF ABI. */
103 static const int arg_regs
[] = { 4, 20, 6, 22, 8, 24, 10, 26, 12, 28 };
105 /* This is the implementation of gdbarch method register_name. */
108 tic6x_register_name (struct gdbarch
*gdbarch
, int regno
)
113 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
114 return tdesc_register_name (gdbarch
, regno
);
115 else if (regno
>= ARRAY_SIZE (tic6x_register_names
))
118 return tic6x_register_names
[regno
];
121 /* This is the implementation of gdbarch method register_type. */
124 tic6x_register_type (struct gdbarch
*gdbarch
, int regno
)
127 if (regno
== TIC6X_PC_REGNUM
)
128 return builtin_type (gdbarch
)->builtin_func_ptr
;
130 return builtin_type (gdbarch
)->builtin_uint32
;
134 tic6x_setup_default (struct tic6x_unwind_cache
*cache
)
138 for (i
= 0; i
< TIC6X_NUM_CORE_REGS
; i
++)
139 cache
->reg_saved
[i
] = -1;
142 static unsigned long tic6x_fetch_instruction (struct gdbarch
*, CORE_ADDR
);
143 static int tic6x_register_number (int reg
, int side
, int crosspath
);
145 /* Do a full analysis of the prologue at START_PC and update CACHE accordingly.
146 Bail out early if CURRENT_PC is reached. Returns the address of the first
147 instruction after the prologue. */
150 tic6x_analyze_prologue (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
,
151 const CORE_ADDR current_pc
,
152 struct tic6x_unwind_cache
*cache
,
153 struct frame_info
*this_frame
)
156 unsigned int src_reg
, base_reg
, dst_reg
;
158 CORE_ADDR pc
= start_pc
;
159 CORE_ADDR return_pc
= start_pc
;
160 int frame_base_offset_to_sp
= 0;
161 /* Counter of non-stw instructions after first insn ` sub sp, xxx, sp'. */
162 int non_stw_insn_counter
= 0;
164 if (start_pc
>= current_pc
)
165 return_pc
= current_pc
;
169 /* The landmarks in prologue is one or two SUB instructions to SP.
170 Instructions on setting up dsbt are in the last part of prologue, if
171 needed. In maxim, prologue can be divided to three parts by two
172 `sub sp, xx, sp' insns. */
174 /* Step 1: Look for the 1st and 2nd insn `sub sp, xx, sp', in which, the
175 2nd one is optional. */
176 while (pc
< current_pc
)
178 unsigned long inst
= tic6x_fetch_instruction (gdbarch
, pc
);
180 if ((inst
& 0x1ffc) == 0x1dc0 || (inst
& 0x1ffc) == 0x1bc0
181 || (inst
& 0x0ffc) == 0x9c0)
183 /* SUBAW/SUBAH/SUB, and src1 is ucst 5. */
184 unsigned int src2
= tic6x_register_number ((inst
>> 18) & 0x1f,
185 INST_S_BIT (inst
), 0);
186 unsigned int dst
= tic6x_register_number ((inst
>> 23) & 0x1f,
187 INST_S_BIT (inst
), 0);
189 if (src2
== TIC6X_SP_REGNUM
&& dst
== TIC6X_SP_REGNUM
)
191 /* Extract const from insn SUBAW/SUBAH/SUB, and translate it to
192 offset. The constant offset is decoded in bit 13-17 in all
193 these three kinds of instructions. */
194 unsigned int ucst5
= (inst
>> 13) & 0x1f;
196 if ((inst
& 0x1ffc) == 0x1dc0) /* SUBAW */
197 frame_base_offset_to_sp
+= ucst5
<< 2;
198 else if ((inst
& 0x1ffc) == 0x1bc0) /* SUBAH */
199 frame_base_offset_to_sp
+= ucst5
<< 1;
200 else if ((inst
& 0x0ffc) == 0x9c0) /* SUB */
201 frame_base_offset_to_sp
+= ucst5
;
203 gdb_assert_not_reached ("unexpected instruction");
208 else if ((inst
& 0x174) == 0x74) /* stw SRC, *+b15(uconst) */
210 /* The y bit determines which file base is read from. */
211 base_reg
= tic6x_register_number ((inst
>> 18) & 0x1f,
214 if (base_reg
== TIC6X_SP_REGNUM
)
216 src_reg
= tic6x_register_number ((inst
>> 23) & 0x1f,
217 INST_S_BIT (inst
), 0);
219 cache
->reg_saved
[src_reg
] = ((inst
>> 13) & 0x1f) << 2;
223 non_stw_insn_counter
= 0;
227 non_stw_insn_counter
++;
228 /* Following instruction sequence may be emitted in prologue:
230 <+0>: subah .D2 b15,28,b15
231 <+4>: or .L2X 0,a4,b0
232 <+8>: || stw .D2T2 b14,*+b15(56)
233 <+12>:[!b0] b .S1 0xe50e4c1c <sleep+220>
234 <+16>:|| stw .D2T1 a10,*+b15(48)
235 <+20>:stw .D2T2 b3,*+b15(52)
236 <+24>:stw .D2T1 a4,*+b15(40)
238 we should look forward for next instruction instead of breaking loop
239 here. So far, we allow almost two sequential non-stw instructions
241 if (non_stw_insn_counter
>= 2)
248 /* Step 2: Skip insn on setting up dsbt if it is. Usually, it looks like,
249 ldw .D2T2 *+b14(0),b14 */
250 inst
= tic6x_fetch_instruction (gdbarch
, pc
);
251 /* The s bit determines which file dst will be loaded into, same effect as
253 dst_reg
= tic6x_register_number ((inst
>> 23) & 0x1f, (inst
>> 1) & 1, 0);
254 /* The y bit (bit 7), instead of s bit, determines which file base be
256 base_reg
= tic6x_register_number ((inst
>> 18) & 0x1f, (inst
>> 7) & 1, 0);
258 if ((inst
& 0x164) == 0x64 /* ldw */
259 && dst_reg
== TIC6X_DP_REGNUM
/* dst is B14 */
260 && base_reg
== TIC6X_DP_REGNUM
) /* baseR is B14 */
267 cache
->base
= get_frame_register_unsigned (this_frame
, TIC6X_SP_REGNUM
);
269 if (cache
->reg_saved
[TIC6X_FP_REGNUM
] != -1)
271 /* If the FP now holds an offset from the CFA then this is a frame
272 which uses the frame pointer. */
274 cache
->cfa
= get_frame_register_unsigned (this_frame
,
279 /* FP doesn't hold an offset from the CFA. If SP still holds an
280 offset from the CFA then we might be in a function which omits
281 the frame pointer. */
283 cache
->cfa
= cache
->base
+ frame_base_offset_to_sp
;
287 /* Adjust all the saved registers such that they contain addresses
288 instead of offsets. */
289 for (i
= 0; i
< TIC6X_NUM_CORE_REGS
; i
++)
290 if (cache
->reg_saved
[i
] != -1)
291 cache
->reg_saved
[i
] = cache
->base
+ cache
->reg_saved
[i
];
296 /* This is the implementation of gdbarch method skip_prologue. */
299 tic6x_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
302 struct tic6x_unwind_cache cache
;
304 /* See if we can determine the end of the prologue via the symbol table.
305 If so, then return either PC, or the PC after the prologue, whichever is
307 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
309 CORE_ADDR post_prologue_pc
310 = skip_prologue_using_sal (gdbarch
, func_addr
);
311 if (post_prologue_pc
!= 0)
312 return std::max (start_pc
, post_prologue_pc
);
315 /* Can't determine prologue from the symbol table, need to examine
317 return tic6x_analyze_prologue (gdbarch
, start_pc
, (CORE_ADDR
) -1, &cache
,
321 /* Implement the breakpoint_kind_from_pc gdbarch method. */
324 tic6x_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
329 /* Implement the sw_breakpoint_from_kind gdbarch method. */
331 static const gdb_byte
*
332 tic6x_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
334 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
338 if (tdep
== NULL
|| tdep
->breakpoint
== NULL
)
340 if (BFD_ENDIAN_BIG
== gdbarch_byte_order_for_code (gdbarch
))
341 return tic6x_bkpt_illegal_opcode_be
;
343 return tic6x_bkpt_illegal_opcode_le
;
346 return tdep
->breakpoint
;
349 /* This is the implementation of gdbarch method breakpiont_from_pc. */
351 GDBARCH_BREAKPOINT_FROM_PC (tic6x
)
353 /* This is the implementation of gdbarch method print_insn. */
356 tic6x_print_insn (bfd_vma memaddr
, disassemble_info
*info
)
358 return print_insn_tic6x (memaddr
, info
);
362 tic6x_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
363 struct dwarf2_frame_state_reg
*reg
,
364 struct frame_info
*this_frame
)
366 /* Mark the PC as the destination for the return address. */
367 if (regnum
== gdbarch_pc_regnum (gdbarch
))
368 reg
->how
= DWARF2_FRAME_REG_RA
;
370 /* Mark the stack pointer as the call frame address. */
371 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
372 reg
->how
= DWARF2_FRAME_REG_CFA
;
374 /* The above was taken from the default init_reg in dwarf2-frame.c
375 while the below is c6x specific. */
377 /* Callee save registers. The ABI designates A10-A15 and B10-B15 as
379 else if ((regnum
>= 10 && regnum
<= 15) || (regnum
>= 26 && regnum
<= 31))
380 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
382 /* All other registers are caller-save. */
383 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
386 /* This is the implementation of gdbarch method unwind_pc. */
389 tic6x_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
393 frame_unwind_register (next_frame
, TIC6X_PC_REGNUM
, buf
);
394 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
397 /* This is the implementation of gdbarch method unwind_sp. */
400 tic6x_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
402 return frame_unwind_register_unsigned (this_frame
, TIC6X_SP_REGNUM
);
406 /* Frame base handling. */
408 static struct tic6x_unwind_cache
*
409 tic6x_frame_unwind_cache (struct frame_info
*this_frame
,
410 void **this_prologue_cache
)
412 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
413 CORE_ADDR current_pc
;
414 struct tic6x_unwind_cache
*cache
;
416 if (*this_prologue_cache
)
417 return (struct tic6x_unwind_cache
*) *this_prologue_cache
;
419 cache
= FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache
);
420 (*this_prologue_cache
) = cache
;
422 cache
->return_regnum
= TIC6X_RA_REGNUM
;
424 tic6x_setup_default (cache
);
426 cache
->pc
= get_frame_func (this_frame
);
427 current_pc
= get_frame_pc (this_frame
);
429 /* Prologue analysis does the rest... */
431 tic6x_analyze_prologue (gdbarch
, cache
->pc
, current_pc
, cache
, this_frame
);
437 tic6x_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
438 struct frame_id
*this_id
)
440 struct tic6x_unwind_cache
*cache
=
441 tic6x_frame_unwind_cache (this_frame
, this_cache
);
443 /* This marks the outermost frame. */
444 if (cache
->base
== 0)
447 (*this_id
) = frame_id_build (cache
->cfa
, cache
->pc
);
450 static struct value
*
451 tic6x_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
454 struct tic6x_unwind_cache
*cache
=
455 tic6x_frame_unwind_cache (this_frame
, this_cache
);
457 gdb_assert (regnum
>= 0);
459 /* The PC of the previous frame is stored in the RA register of
460 the current frame. Frob regnum so that we pull the value from
461 the correct place. */
462 if (regnum
== TIC6X_PC_REGNUM
)
463 regnum
= cache
->return_regnum
;
465 if (regnum
== TIC6X_SP_REGNUM
&& cache
->cfa
)
466 return frame_unwind_got_constant (this_frame
, regnum
, cache
->cfa
);
468 /* If we've worked out where a register is stored then load it from
470 if (regnum
< TIC6X_NUM_CORE_REGS
&& cache
->reg_saved
[regnum
] != -1)
471 return frame_unwind_got_memory (this_frame
, regnum
,
472 cache
->reg_saved
[regnum
]);
474 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
478 tic6x_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
480 struct tic6x_unwind_cache
*info
481 = tic6x_frame_unwind_cache (this_frame
, this_cache
);
485 static const struct frame_unwind tic6x_frame_unwind
=
488 default_frame_unwind_stop_reason
,
490 tic6x_frame_prev_register
,
492 default_frame_sniffer
495 static const struct frame_base tic6x_frame_base
=
498 tic6x_frame_base_address
,
499 tic6x_frame_base_address
,
500 tic6x_frame_base_address
504 static struct tic6x_unwind_cache
*
505 tic6x_make_stub_cache (struct frame_info
*this_frame
)
507 struct tic6x_unwind_cache
*cache
;
509 cache
= FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache
);
511 cache
->return_regnum
= TIC6X_RA_REGNUM
;
513 tic6x_setup_default (cache
);
515 cache
->cfa
= get_frame_register_unsigned (this_frame
, TIC6X_SP_REGNUM
);
521 tic6x_stub_this_id (struct frame_info
*this_frame
, void **this_cache
,
522 struct frame_id
*this_id
)
524 struct tic6x_unwind_cache
*cache
;
526 if (*this_cache
== NULL
)
527 *this_cache
= tic6x_make_stub_cache (this_frame
);
528 cache
= (struct tic6x_unwind_cache
*) *this_cache
;
530 *this_id
= frame_id_build (cache
->cfa
, get_frame_pc (this_frame
));
534 tic6x_stub_unwind_sniffer (const struct frame_unwind
*self
,
535 struct frame_info
*this_frame
,
536 void **this_prologue_cache
)
538 CORE_ADDR addr_in_block
;
540 addr_in_block
= get_frame_address_in_block (this_frame
);
541 if (in_plt_section (addr_in_block
))
547 static const struct frame_unwind tic6x_stub_unwind
=
550 default_frame_unwind_stop_reason
,
552 tic6x_frame_prev_register
,
554 tic6x_stub_unwind_sniffer
557 /* Return the instruction on address PC. */
560 tic6x_fetch_instruction (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
562 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
563 return read_memory_unsigned_integer (pc
, TIC6X_OPCODE_SIZE
, byte_order
);
566 /* Compute the condition of INST if it is a conditional instruction. Always
567 return 1 if INST is not a conditional instruction. */
570 tic6x_condition_true (struct frame_info
*frame
, unsigned long inst
)
574 static const int register_numbers
[8] = { -1, 16, 17, 18, 1, 2, 0, -1 };
576 register_number
= register_numbers
[(inst
>> 29) & 7];
577 if (register_number
== -1)
580 register_value
= get_frame_register_signed (frame
, register_number
);
581 if ((inst
& 0x10000000) != 0)
582 return register_value
== 0;
583 return register_value
!= 0;
586 /* Get the register number by decoding raw bits REG, SIDE, and CROSSPATH in
590 tic6x_register_number (int reg
, int side
, int crosspath
)
592 int r
= (reg
& 15) | ((crosspath
^ side
) << 4);
593 if ((reg
& 16) != 0) /* A16 - A31, B16 - B31 */
599 tic6x_extract_signed_field (int value
, int low_bit
, int bits
)
601 int mask
= (1 << bits
) - 1;
602 int r
= (value
>> low_bit
) & mask
;
603 if ((r
& (1 << (bits
- 1))) != 0)
608 /* Determine where to set a single step breakpoint. */
611 tic6x_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
613 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
620 inst
= tic6x_fetch_instruction (gdbarch
, pc
);
624 if (inst
== TIC6X_INST_SWE
)
626 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
628 if (tdep
->syscall_next_pc
!= NULL
)
629 return tdep
->syscall_next_pc (frame
);
632 if (tic6x_condition_true (frame
, inst
))
634 if ((inst
& 0x0000007c) == 0x00000010)
636 /* B with displacement */
637 pc
&= ~(TIC6X_FETCH_PACKET_SIZE
- 1);
638 pc
+= tic6x_extract_signed_field (inst
, 7, 21) << 2;
641 if ((inst
& 0x0f83effc) == 0x00000360)
643 /* B with register */
645 register_number
= tic6x_register_number ((inst
>> 18) & 0x1f,
648 pc
= get_frame_register_unsigned (frame
, register_number
);
651 if ((inst
& 0x00001ffc) == 0x00001020)
654 register_number
= tic6x_register_number ((inst
>> 23) & 0x1f,
655 INST_S_BIT (inst
), 0);
656 if (get_frame_register_signed (frame
, register_number
) >= 0)
658 pc
&= ~(TIC6X_FETCH_PACKET_SIZE
- 1);
659 pc
+= tic6x_extract_signed_field (inst
, 7, 10) << 2;
663 if ((inst
& 0x00001ffc) == 0x00000120)
665 /* BNOP with displacement */
666 pc
&= ~(TIC6X_FETCH_PACKET_SIZE
- 1);
667 pc
+= tic6x_extract_signed_field (inst
, 16, 12) << 2;
670 if ((inst
& 0x0f830ffe) == 0x00800362)
672 /* BNOP with register */
673 register_number
= tic6x_register_number ((inst
>> 18) & 0x1f,
674 1, INST_X_BIT (inst
));
675 pc
= get_frame_register_unsigned (frame
, register_number
);
678 if ((inst
& 0x00001ffc) == 0x00000020)
681 register_number
= tic6x_register_number ((inst
>> 23) & 0x1f,
682 INST_S_BIT (inst
), 0);
683 if (get_frame_register_signed (frame
, register_number
) >= 0)
685 pc
&= ~(TIC6X_FETCH_PACKET_SIZE
- 1);
686 pc
+= tic6x_extract_signed_field (inst
, 13, 10) << 2;
690 if ((inst
& 0xf000007c) == 0x10000010)
693 pc
&= ~(TIC6X_FETCH_PACKET_SIZE
- 1);
694 pc
+= tic6x_extract_signed_field (inst
, 7, 21) << 2;
698 pc
+= TIC6X_OPCODE_SIZE
;
704 /* This is the implementation of gdbarch method software_single_step. */
707 tic6x_software_single_step (struct frame_info
*frame
)
709 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
710 struct address_space
*aspace
= get_frame_address_space (frame
);
711 CORE_ADDR next_pc
= tic6x_get_next_pc (frame
, get_frame_pc (frame
));
713 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
718 /* This is the implementation of gdbarch method frame_align. */
721 tic6x_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
723 return align_down (addr
, 8);
726 /* Given a return value in REGCACHE with a type VALTYPE, extract and copy its
727 value into VALBUF. */
730 tic6x_extract_return_value (struct type
*valtype
, struct regcache
*regcache
,
731 enum bfd_endian byte_order
, gdb_byte
*valbuf
)
733 int len
= TYPE_LENGTH (valtype
);
735 /* pointer types are returned in register A4,
736 up to 32-bit types in A4
737 up to 64-bit types in A5:A4 */
741 - one-byte structure or union occupies the LSB of single even register.
742 - for two-byte structure or union, the first byte occupies byte 1 of
743 register and the second byte occupies byte 0.
744 so, we read the contents in VAL from the LSBs of register. */
745 if (len
< 3 && byte_order
== BFD_ENDIAN_BIG
)
746 regcache_cooked_read_part (regcache
, TIC6X_A4_REGNUM
, 4 - len
, len
,
749 regcache_cooked_read (regcache
, TIC6X_A4_REGNUM
, valbuf
);
753 /* For a 5-8 byte structure or union in big-endian, the first byte
754 occupies byte 3 (the MSB) of the upper (odd) register and the
755 remaining bytes fill the decreasingly significant bytes. 5-7
756 byte structures or unions have padding in the LSBs of the
757 lower (even) register. */
758 if (byte_order
== BFD_ENDIAN_BIG
)
760 regcache_cooked_read (regcache
, TIC6X_A4_REGNUM
, valbuf
+ 4);
761 regcache_cooked_read (regcache
, TIC6X_A5_REGNUM
, valbuf
);
765 regcache_cooked_read (regcache
, TIC6X_A4_REGNUM
, valbuf
);
766 regcache_cooked_read (regcache
, TIC6X_A5_REGNUM
, valbuf
+ 4);
771 /* Write into appropriate registers a function return value
772 of type TYPE, given in virtual format. */
775 tic6x_store_return_value (struct type
*valtype
, struct regcache
*regcache
,
776 enum bfd_endian byte_order
, const gdb_byte
*valbuf
)
778 int len
= TYPE_LENGTH (valtype
);
780 /* return values of up to 8 bytes are returned in A5:A4 */
784 if (len
< 3 && byte_order
== BFD_ENDIAN_BIG
)
785 regcache_cooked_write_part (regcache
, TIC6X_A4_REGNUM
, 4 - len
, len
,
788 regcache_cooked_write (regcache
, TIC6X_A4_REGNUM
, valbuf
);
792 if (byte_order
== BFD_ENDIAN_BIG
)
794 regcache_cooked_write (regcache
, TIC6X_A4_REGNUM
, valbuf
+ 4);
795 regcache_cooked_write (regcache
, TIC6X_A5_REGNUM
, valbuf
);
799 regcache_cooked_write (regcache
, TIC6X_A4_REGNUM
, valbuf
);
800 regcache_cooked_write (regcache
, TIC6X_A5_REGNUM
, valbuf
+ 4);
805 /* This is the implementation of gdbarch method return_value. */
807 static enum return_value_convention
808 tic6x_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
809 struct type
*type
, struct regcache
*regcache
,
810 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
812 /* In C++, when function returns an object, even its size is small
813 enough, it stii has to be passed via reference, pointed by register
815 if (current_language
->la_language
== language_cplus
)
819 type
= check_typedef (type
);
820 if (language_pass_by_reference (type
))
821 return RETURN_VALUE_STRUCT_CONVENTION
;
825 if (TYPE_LENGTH (type
) > 8)
826 return RETURN_VALUE_STRUCT_CONVENTION
;
829 tic6x_extract_return_value (type
, regcache
,
830 gdbarch_byte_order (gdbarch
), readbuf
);
832 tic6x_store_return_value (type
, regcache
,
833 gdbarch_byte_order (gdbarch
), writebuf
);
835 return RETURN_VALUE_REGISTER_CONVENTION
;
838 /* This is the implementation of gdbarch method dummy_id. */
840 static struct frame_id
841 tic6x_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
843 return frame_id_build
844 (get_frame_register_unsigned (this_frame
, TIC6X_SP_REGNUM
),
845 get_frame_pc (this_frame
));
848 /* Get the alignment requirement of TYPE. */
851 tic6x_arg_type_alignment (struct type
*type
)
853 int len
= TYPE_LENGTH (check_typedef (type
));
854 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
856 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
858 /* The stack alignment of a structure (and union) passed by value is the
859 smallest power of two greater than or equal to its size.
860 This cannot exceed 8 bytes, which is the largest allowable size for
861 a structure passed by value. */
870 gdb_assert_not_reached ("unexpected length of data");
878 if (typecode
== TYPE_CODE_COMPLEX
)
885 if (typecode
== TYPE_CODE_COMPLEX
)
891 internal_error (__FILE__
, __LINE__
, _("unexpected length %d of type"),
896 /* This is the implementation of gdbarch method push_dummy_call. */
899 tic6x_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
900 struct regcache
*regcache
, CORE_ADDR bp_addr
,
901 int nargs
, struct value
**args
, CORE_ADDR sp
,
902 int struct_return
, CORE_ADDR struct_addr
)
906 int stack_offset
= 4;
907 int references_offset
= 4;
908 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
909 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
910 struct type
*func_type
= value_type (function
);
911 /* The first arg passed on stack. Mostly the first 10 args are passed by
913 int first_arg_on_stack
= 10;
915 /* Set the return address register to point to the entry point of
916 the program, where a breakpoint lies in wait. */
917 regcache_cooked_write_unsigned (regcache
, TIC6X_RA_REGNUM
, bp_addr
);
919 /* The caller must pass an argument in A3 containing a destination address
920 for the returned value. The callee returns the object by copying it to
921 the address in A3. */
923 regcache_cooked_write_unsigned (regcache
, 3, struct_addr
);
925 /* Determine the type of this function. */
926 func_type
= check_typedef (func_type
);
927 if (TYPE_CODE (func_type
) == TYPE_CODE_PTR
)
928 func_type
= check_typedef (TYPE_TARGET_TYPE (func_type
));
930 gdb_assert (TYPE_CODE (func_type
) == TYPE_CODE_FUNC
931 || TYPE_CODE (func_type
) == TYPE_CODE_METHOD
);
933 /* For a variadic C function, the last explicitly declared argument and all
934 remaining arguments are passed on the stack. */
935 if (TYPE_VARARGS (func_type
))
936 first_arg_on_stack
= TYPE_NFIELDS (func_type
) - 1;
938 /* Now make space on the stack for the args. */
939 for (argnum
= 0; argnum
< nargs
; argnum
++)
941 int len
= align_up (TYPE_LENGTH (value_type (args
[argnum
])), 4);
942 if (argnum
>= 10 - argreg
)
943 references_offset
+= len
;
947 /* SP should be 8-byte aligned, see C6000 ABI section 4.4.1
949 sp
= align_down (sp
, 8);
952 /* Now load as many as possible of the first arguments into
953 registers, and push the rest onto the stack. Loop through args
954 from first to last. */
955 for (argnum
= 0; argnum
< nargs
; argnum
++)
958 struct value
*arg
= args
[argnum
];
959 struct type
*arg_type
= check_typedef (value_type (arg
));
960 int len
= TYPE_LENGTH (arg_type
);
961 enum type_code typecode
= TYPE_CODE (arg_type
);
963 val
= value_contents (arg
);
965 /* Copy the argument to general registers or the stack in
966 register-sized pieces. */
967 if (argreg
< first_arg_on_stack
)
971 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
974 - one-byte structure or union occupies the LSB of single
976 - for two-byte structure or union, the first byte
977 occupies byte 1 of register and the second byte occupies
979 so, we write the contents in VAL to the lsp of
981 if (len
< 3 && byte_order
== BFD_ENDIAN_BIG
)
982 regcache_cooked_write_part (regcache
, arg_regs
[argreg
],
985 regcache_cooked_write (regcache
, arg_regs
[argreg
], val
);
989 /* The argument is being passed by value in a single
991 CORE_ADDR regval
= extract_unsigned_integer (val
, len
,
994 regcache_cooked_write_unsigned (regcache
, arg_regs
[argreg
],
1002 if (typecode
== TYPE_CODE_STRUCT
1003 || typecode
== TYPE_CODE_UNION
)
1005 /* For a 5-8 byte structure or union in big-endian, the
1006 first byte occupies byte 3 (the MSB) of the upper (odd)
1007 register and the remaining bytes fill the decreasingly
1008 significant bytes. 5-7 byte structures or unions have
1009 padding in the LSBs of the lower (even) register. */
1010 if (byte_order
== BFD_ENDIAN_BIG
)
1012 regcache_cooked_write (regcache
,
1013 arg_regs
[argreg
] + 1, val
);
1014 regcache_cooked_write_part (regcache
,
1015 arg_regs
[argreg
], 0,
1020 regcache_cooked_write (regcache
, arg_regs
[argreg
],
1022 regcache_cooked_write_part (regcache
,
1023 arg_regs
[argreg
] + 1, 0,
1029 /* The argument is being passed by value in a pair of
1031 ULONGEST regval
= extract_unsigned_integer (val
, len
,
1034 regcache_cooked_write_unsigned (regcache
,
1037 regcache_cooked_write_unsigned (regcache
,
1038 arg_regs
[argreg
] + 1,
1044 /* The argument is being passed by reference in a single
1048 /* It is not necessary to adjust REFERENCES_OFFSET to
1049 8-byte aligned in some cases, in which 4-byte alignment
1050 is sufficient. For simplicity, we adjust
1051 REFERENCES_OFFSET to 8-byte aligned. */
1052 references_offset
= align_up (references_offset
, 8);
1054 addr
= sp
+ references_offset
;
1055 write_memory (addr
, val
, len
);
1056 references_offset
+= align_up (len
, 4);
1057 regcache_cooked_write_unsigned (regcache
, arg_regs
[argreg
],
1065 /* The argument is being passed on the stack. */
1068 /* There are six different cases of alignment, and these rules can
1069 be found in tic6x_arg_type_alignment:
1071 1) 4-byte aligned if size is less than or equal to 4 byte, such
1072 as short, int, struct, union etc.
1073 2) 8-byte aligned if size is less than or equal to 8-byte, such
1074 as double, long long,
1075 3) 4-byte aligned if it is of type _Complex float, even its size
1077 4) 8-byte aligned if it is of type _Complex double or _Complex
1078 long double, even its size is 16-byte. Because, the address of
1079 variable is passed as reference.
1080 5) struct and union larger than 8-byte are passed by reference, so
1081 it is 4-byte aligned.
1082 6) struct and union of size between 4 byte and 8 byte varies.
1083 alignment of struct variable is the alignment of its first field,
1084 while alignment of union variable is the max of all its fields'
1088 ; /* Default is 4-byte aligned. Nothing to be done. */
1090 stack_offset
= align_up (stack_offset
,
1091 tic6x_arg_type_alignment (arg_type
));
1094 /* _Complex double or _Complex long double */
1095 if (typecode
== TYPE_CODE_COMPLEX
)
1097 /* The argument is being passed by reference on stack. */
1099 references_offset
= align_up (references_offset
, 8);
1101 addr
= sp
+ references_offset
;
1102 /* Store variable on stack. */
1103 write_memory (addr
, val
, len
);
1105 references_offset
+= align_up (len
, 4);
1107 /* Pass the address of variable on stack as reference. */
1108 store_unsigned_integer ((gdb_byte
*) val
, 4, byte_order
,
1114 internal_error (__FILE__
, __LINE__
,
1115 _("unexpected type %d of arg %d"),
1119 internal_error (__FILE__
, __LINE__
,
1120 _("unexpected length %d of arg %d"), len
, argnum
);
1122 addr
= sp
+ stack_offset
;
1123 write_memory (addr
, val
, len
);
1124 stack_offset
+= align_up (len
, 4);
1128 regcache_cooked_write_signed (regcache
, TIC6X_SP_REGNUM
, sp
);
1130 /* Return adjusted stack pointer. */
1134 /* This is the implementation of gdbarch method stack_frame_destroyed_p. */
1137 tic6x_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1139 unsigned long inst
= tic6x_fetch_instruction (gdbarch
, pc
);
1140 /* Normally, the epilogue is composed by instruction `b .S2 b3'. */
1141 if ((inst
& 0x0f83effc) == 0x360)
1143 unsigned int src2
= tic6x_register_number ((inst
>> 18) & 0x1f,
1146 if (src2
== TIC6X_RA_REGNUM
)
1153 /* This is the implementation of gdbarch method get_longjmp_target. */
1156 tic6x_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
1158 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1159 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1163 /* JMP_BUF is passed by reference in A4. */
1164 jb_addr
= get_frame_register_unsigned (frame
, 4);
1166 /* JMP_BUF contains 13 elements of type int, and return address is stored
1167 in the last slot. */
1168 if (target_read_memory (jb_addr
+ 12 * 4, buf
, 4))
1171 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
1176 /* This is the implementation of gdbarch method
1177 return_in_first_hidden_param_p. */
1180 tic6x_return_in_first_hidden_param_p (struct gdbarch
*gdbarch
,
1186 static struct gdbarch
*
1187 tic6x_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1189 struct gdbarch
*gdbarch
;
1190 struct gdbarch_tdep
*tdep
;
1191 struct tdesc_arch_data
*tdesc_data
= NULL
;
1192 const struct target_desc
*tdesc
= info
.target_desc
;
1195 /* Check any target description for validity. */
1196 if (tdesc_has_registers (tdesc
))
1198 const struct tdesc_feature
*feature
;
1201 feature
= tdesc_find_feature (tdesc
, "org.gnu.gdb.tic6x.core");
1203 if (feature
== NULL
)
1206 tdesc_data
= tdesc_data_alloc ();
1209 for (i
= 0; i
< 32; i
++) /* A0 - A15, B0 - B15 */
1210 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
1211 tic6x_register_names
[i
]);
1214 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++,
1215 tic6x_register_names
[TIC6X_CSR_REGNUM
]);
1216 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++,
1217 tic6x_register_names
[TIC6X_PC_REGNUM
]);
1221 tdesc_data_cleanup (tdesc_data
);
1225 feature
= tdesc_find_feature (tdesc
, "org.gnu.gdb.tic6x.gp");
1229 static const char *const gp
[] =
1231 "A16", "A17", "A18", "A19", "A20", "A21", "A22", "A23",
1232 "A24", "A25", "A26", "A27", "A28", "A29", "A30", "A31",
1233 "B16", "B17", "B18", "B19", "B20", "B21", "B22", "B23",
1234 "B24", "B25", "B26", "B27", "B28", "B29", "B30", "B31",
1239 for (j
= 0; j
< 32; j
++) /* A16 - A31, B16 - B31 */
1240 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++,
1245 tdesc_data_cleanup (tdesc_data
);
1250 feature
= tdesc_find_feature (tdesc
, "org.gnu.gdb.tic6x.c6xp");
1253 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++, "TSR");
1254 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++, "ILC");
1255 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++, "RILC");
1259 tdesc_data_cleanup (tdesc_data
);
1266 /* Find a candidate among extant architectures. */
1267 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1269 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
1271 tdep
= gdbarch_tdep (arches
->gdbarch
);
1273 if (has_gp
!= tdep
->has_gp
)
1276 if (tdep
&& tdep
->breakpoint
)
1277 return arches
->gdbarch
;
1280 tdep
= XCNEW (struct gdbarch_tdep
);
1282 tdep
->has_gp
= has_gp
;
1283 gdbarch
= gdbarch_alloc (&info
, tdep
);
1285 /* Data type sizes. */
1286 set_gdbarch_ptr_bit (gdbarch
, 32);
1287 set_gdbarch_addr_bit (gdbarch
, 32);
1288 set_gdbarch_short_bit (gdbarch
, 16);
1289 set_gdbarch_int_bit (gdbarch
, 32);
1290 set_gdbarch_long_bit (gdbarch
, 32);
1291 set_gdbarch_long_long_bit (gdbarch
, 64);
1292 set_gdbarch_float_bit (gdbarch
, 32);
1293 set_gdbarch_double_bit (gdbarch
, 64);
1295 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
1296 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
1298 /* The register set. */
1299 set_gdbarch_num_regs (gdbarch
, TIC6X_NUM_REGS
);
1300 set_gdbarch_sp_regnum (gdbarch
, TIC6X_SP_REGNUM
);
1301 set_gdbarch_pc_regnum (gdbarch
, TIC6X_PC_REGNUM
);
1303 set_gdbarch_register_name (gdbarch
, tic6x_register_name
);
1304 set_gdbarch_register_type (gdbarch
, tic6x_register_type
);
1306 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1308 set_gdbarch_skip_prologue (gdbarch
, tic6x_skip_prologue
);
1309 SET_GDBARCH_BREAKPOINT_MANIPULATION (tic6x
);
1311 set_gdbarch_unwind_pc (gdbarch
, tic6x_unwind_pc
);
1312 set_gdbarch_unwind_sp (gdbarch
, tic6x_unwind_sp
);
1315 dwarf2_append_unwinders (gdbarch
);
1317 frame_unwind_append_unwinder (gdbarch
, &tic6x_stub_unwind
);
1318 frame_unwind_append_unwinder (gdbarch
, &tic6x_frame_unwind
);
1319 frame_base_set_default (gdbarch
, &tic6x_frame_base
);
1321 dwarf2_frame_set_init_reg (gdbarch
, tic6x_dwarf2_frame_init_reg
);
1323 /* Single stepping. */
1324 set_gdbarch_software_single_step (gdbarch
, tic6x_software_single_step
);
1326 set_gdbarch_print_insn (gdbarch
, tic6x_print_insn
);
1328 /* Call dummy code. */
1329 set_gdbarch_frame_align (gdbarch
, tic6x_frame_align
);
1331 set_gdbarch_return_value (gdbarch
, tic6x_return_value
);
1333 set_gdbarch_dummy_id (gdbarch
, tic6x_dummy_id
);
1335 /* Enable inferior call support. */
1336 set_gdbarch_push_dummy_call (gdbarch
, tic6x_push_dummy_call
);
1338 set_gdbarch_get_longjmp_target (gdbarch
, tic6x_get_longjmp_target
);
1340 set_gdbarch_stack_frame_destroyed_p (gdbarch
, tic6x_stack_frame_destroyed_p
);
1342 set_gdbarch_return_in_first_hidden_param_p (gdbarch
,
1343 tic6x_return_in_first_hidden_param_p
);
1345 /* Hook in ABI-specific overrides, if they have been registered. */
1346 gdbarch_init_osabi (info
, gdbarch
);
1349 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
1354 /* -Wmissing-prototypes */
1355 extern initialize_file_ftype _initialize_tic6x_tdep
;
1358 _initialize_tic6x_tdep (void)
1360 register_gdbarch_init (bfd_arch_tic6x
, tic6x_gdbarch_init
);
1362 initialize_tdesc_tic6x_c64xp ();
1363 initialize_tdesc_tic6x_c64x ();
1364 initialize_tdesc_tic6x_c62x ();