1 /* Host-dependent code for GDB, for NYU Ultra3 running Sym1 OS.
2 Copyright (C) 1988, 1989, 1991 Free Software Foundation, Inc.
3 Contributed by David Wood (wood@nyu.edu) at New York University.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
28 #include <sys/types.h>
29 #include <sys/param.h>
31 #include <sys/ioctl.h>
38 #include <sys/ptrace.h>
40 /* Assumes support for AMD's Binary Compatibility Standard
41 for ptrace(). If you define ULTRA3, the ultra3 extensions to
42 ptrace() are used allowing the reading of more than one register
45 This file assumes KERNEL_DEBUGGING is turned off. This means
46 that if the user/gdb tries to read gr64-gr95 or any of the
47 protected special registers we silently return -1 (see the
48 CANNOT_STORE/FETCH_REGISTER macros). */
51 #if !defined (offsetof)
52 # define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER)
56 struct ptrace_user pt_struct
;
59 * Fetch an individual register (and supply it).
60 * return 0 on success, -1 on failure.
61 * NOTE: Assumes AMD's Binary Compatibility Standard for ptrace().
64 fetch_register (regno
)
70 if (CANNOT_FETCH_REGISTER(regno
)) {
72 supply_register (regno
, &val
);
75 val
= ptrace (PT_READ_U
, inferior_pid
,
76 (PTRACE_ARG3_TYPE
) register_addr(regno
,0), 0);
78 sprintf(buf
,"reading register %s (#%d)",reg_names
[regno
],regno
);
79 perror_with_name (buf
);
81 supply_register (regno
, &val
);
86 /* Get all available registers from the inferior. Registers that are
87 * defined in REGISTER_NAMES, but not available to the user/gdb are
88 * supplied as -1. This may include gr64-gr95 and the protected special
93 fetch_inferior_registers (regno
)
96 register int i
,j
,ret_val
=0;
100 fetch_register (regno
);
104 /* Global Registers */
107 ptrace (PT_READ_STRUCT
, inferior_pid
,
108 (PTRACE_ARG3_TYPE
) register_addr(GR96_REGNUM
,0),
109 (int)&pt_struct
.pt_gr
[0], 32*4);
111 perror_with_name ("reading global registers");
113 } else for (regno
=GR96_REGNUM
, j
=0 ; j
<32 ; regno
++, j
++) {
114 supply_register (regno
, &pt_struct
.pt_gr
[j
]);
117 for (regno
=GR96_REGNUM
; !ret_val
&& regno
< GR96_REGNUM
+32 ; regno
++)
118 fetch_register(regno
);
121 /* Local Registers */
124 ptrace (PT_READ_STRUCT
, inferior_pid
,
125 (PTRACE_ARG3_TYPE
) register_addr(LR0_REGNUM
,0),
126 (int)&pt_struct
.pt_lr
[0], 128*4);
128 perror_with_name ("reading local registers");
130 } else for (regno
=LR0_REGNUM
, j
=0 ; j
<128 ; regno
++, j
++) {
131 supply_register (regno
, &pt_struct
.pt_lr
[j
]);
134 for (regno
=LR0_REGNUM
; !ret_val
&& regno
< LR0_REGNUM
+128 ; regno
++)
135 fetch_register(regno
);
138 /* Special Registers */
139 fetch_register(GR1_REGNUM
);
140 fetch_register(CPS_REGNUM
);
141 fetch_register(PC_REGNUM
);
142 fetch_register(NPC_REGNUM
);
143 fetch_register(PC2_REGNUM
);
144 fetch_register(IPC_REGNUM
);
145 fetch_register(IPA_REGNUM
);
146 fetch_register(IPB_REGNUM
);
147 fetch_register(Q_REGNUM
);
148 fetch_register(BP_REGNUM
);
149 fetch_register(FC_REGNUM
);
151 /* Fake any registers that are in REGISTER_NAMES, but not available to gdb */
155 /* Store our register values back into the inferior.
156 * If REGNO is -1, do this for all registers.
157 * Otherwise, REGNO specifies which register (so we can save time).
158 * NOTE: Assumes AMD's binary compatibility standard.
162 store_inferior_registers (regno
)
165 register unsigned int regaddr
;
170 if (CANNOT_STORE_REGISTER(regno
))
172 regaddr
= register_addr (regno
, 0);
174 ptrace (PT_WRITE_U
, inferior_pid
,
175 (PTRACE_ARG3_TYPE
) regaddr
, read_register(regno
));
178 sprintf (buf
, "writing register %s (#%d)", reg_names
[regno
],regno
);
179 perror_with_name (buf
);
185 pt_struct
.pt_gr1
= read_register(GR1_REGNUM
);
186 for (regno
= GR96_REGNUM
; regno
< GR96_REGNUM
+32; regno
++)
187 pt_struct
.pt_gr
[regno
] = read_register(regno
);
188 for (regno
= LR0_REGNUM
; regno
< LR0_REGNUM
+128; regno
++)
189 pt_struct
.pt_gr
[regno
] = read_register(regno
);
191 ptrace (PT_WRITE_STRUCT
, inferior_pid
,
192 (PTRACE_ARG3_TYPE
) register_addr(GR1_REGNUM
,0),
193 (int)&pt_struct
.pt_gr1
,(1*32*128)*4);
196 sprintf (buf
, "writing all local/global registers");
197 perror_with_name (buf
);
199 pt_struct
.pt_psr
= read_register(CPS_REGNUM
);
200 pt_struct
.pt_pc0
= read_register(NPC_REGNUM
);
201 pt_struct
.pt_pc1
= read_register(PC_REGNUM
);
202 pt_struct
.pt_pc2
= read_register(PC2_REGNUM
);
203 pt_struct
.pt_ipc
= read_register(IPC_REGNUM
);
204 pt_struct
.pt_ipa
= read_register(IPA_REGNUM
);
205 pt_struct
.pt_ipb
= read_register(IPB_REGNUM
);
206 pt_struct
.pt_q
= read_register(Q_REGNUM
);
207 pt_struct
.pt_bp
= read_register(BP_REGNUM
);
208 pt_struct
.pt_fc
= read_register(FC_REGNUM
);
210 ptrace (PT_WRITE_STRUCT
, inferior_pid
,
211 (PTRACE_ARG3_TYPE
) register_addr(CPS_REGNUM
,0),
212 (int)&pt_struct
.pt_psr
,(10)*4);
215 sprintf (buf
, "writing all special registers");
216 perror_with_name (buf
);
220 store_inferior_registers(GR1_REGNUM
);
221 for (regno
=GR96_REGNUM
; regno
<GR96_REGNUM
+32 ; regno
++)
222 store_inferior_registers(regno
);
223 for (regno
=LR0_REGNUM
; regno
<LR0_REGNUM
+128 ; regno
++)
224 store_inferior_registers(regno
);
225 store_inferior_registers(CPS_REGNUM
);
226 store_inferior_registers(PC_REGNUM
);
227 store_inferior_registers(NPC_REGNUM
);
228 store_inferior_registers(PC2_REGNUM
);
229 store_inferior_registers(IPC_REGNUM
);
230 store_inferior_registers(IPA_REGNUM
);
231 store_inferior_registers(IPB_REGNUM
);
232 store_inferior_registers(Q_REGNUM
);
233 store_inferior_registers(BP_REGNUM
);
234 store_inferior_registers(FC_REGNUM
);
240 * Read AMD's Binary Compatibilty Standard conforming core file.
241 * struct ptrace_user is the first thing in the core file
245 fetch_core_registers ()
251 for (regno
= 0 ; regno
< NUM_REGS
; regno
++) {
252 if (!CANNOT_FETCH_REGISTER(regno
)) {
253 val
= bfd_seek (core_bfd
, register_addr (regno
, 0), 0);
254 if (val
< 0 || (val
= bfd_read (buf
, sizeof buf
, 1, core_bfd
)) < 0) {
255 char * buffer
= (char *) alloca (strlen (reg_names
[regno
]) + 35);
256 strcpy (buffer
, "Reading core register ");
257 strcat (buffer
, reg_names
[regno
]);
258 perror_with_name (buffer
);
260 supply_register (regno
, buf
);
264 /* Fake any registers that are in REGISTER_NAMES, but not available to gdb */
270 * Takes a register number as defined in tm.h via REGISTER_NAMES, and maps
271 * it to an offset in a struct ptrace_user defined by AMD's BCS.
272 * That is, it defines the mapping between gdb register numbers and items in
273 * a struct ptrace_user.
274 * A register protection scheme is set up here. If a register not
275 * available to the user is specified in 'regno', then an address that
276 * will cause ptrace() to fail is returned.
279 register_addr (regno
,blockend
)
283 if ((regno
>= LR0_REGNUM
) && (regno
< LR0_REGNUM
+ 128)) {
284 return(offsetof(struct ptrace_user
,pt_lr
[regno
-LR0_REGNUM
]));
285 } else if ((regno
>= GR96_REGNUM
) && (regno
< GR96_REGNUM
+ 32)) {
286 return(offsetof(struct ptrace_user
,pt_gr
[regno
-GR96_REGNUM
]));
289 case GR1_REGNUM
: return(offsetof(struct ptrace_user
,pt_gr1
));
290 case CPS_REGNUM
: return(offsetof(struct ptrace_user
,pt_psr
));
291 case NPC_REGNUM
: return(offsetof(struct ptrace_user
,pt_pc0
));
292 case PC_REGNUM
: return(offsetof(struct ptrace_user
,pt_pc1
));
293 case PC2_REGNUM
: return(offsetof(struct ptrace_user
,pt_pc2
));
294 case IPC_REGNUM
: return(offsetof(struct ptrace_user
,pt_ipc
));
295 case IPA_REGNUM
: return(offsetof(struct ptrace_user
,pt_ipa
));
296 case IPB_REGNUM
: return(offsetof(struct ptrace_user
,pt_ipb
));
297 case Q_REGNUM
: return(offsetof(struct ptrace_user
,pt_q
));
298 case BP_REGNUM
: return(offsetof(struct ptrace_user
,pt_bp
));
299 case FC_REGNUM
: return(offsetof(struct ptrace_user
,pt_fc
));
301 fprintf_filtered(stderr
,"register_addr():Bad register %s (%d)\n",
302 reg_names
[regno
],regno
);
303 return(0xffffffff); /* Should make ptrace() fail */
309 /* Assorted operating system circumventions */
313 /* FIXME: Kludge this for now. It really should be system call. */
318 /* FIXME: Fake out the fcntl() call, which we don't have. */
324 case F_GETFL
: return(O_RDONLY
); break;
326 printf("Ultra3's fcntl() failing, cmd = %d.\n",cmd
);
333 * 4.2 Signal support, requires linking with libjobs.
336 #define sigbit(s) (1L << ((s)-1))
340 /* Taken from the sym1 kernel in machdep.c:startup() */
341 _SigMask
= sigbit (SIGTSTP
) | sigbit (SIGTTOU
) | sigbit (SIGTTIN
) |
342 sigbit (SIGCHLD
) | sigbit (SIGTINT
);
348 return (1 << (signo
-1));
352 unsigned int sigmask
;
355 int lastmask
= _SigMask
;
357 for (i
=0 ; i
<NSIG
; i
++) {
358 if (sigmask
& mask
) {
359 if (!(_SigMask
& mask
)) {
363 } else if (_SigMask
& mask
) {
373 unsigned int sigmask
;
376 int lastmask
= _SigMask
;
378 for (i
=0 ; i
<NSIG
; i
++) {
379 if ((sigmask
& mask
) && !(_SigMask
& mask
)) {
390 /* Initialization code for this module. */
392 _initialize_ultra3 ()
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