2004-02-17 Andrew Cagney <cagney@redhat.com>
[deliverable/binutils-gdb.git] / gdb / x86-64-tdep.c
1 /* Target-dependent code for AMD64.
2
3 Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Jiri Smid, SuSE Labs.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
22
23 #include "defs.h"
24 #include "arch-utils.h"
25 #include "block.h"
26 #include "dummy-frame.h"
27 #include "frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
30 #include "inferior.h"
31 #include "gdbcmd.h"
32 #include "gdbcore.h"
33 #include "objfiles.h"
34 #include "regcache.h"
35 #include "regset.h"
36 #include "symfile.h"
37
38 #include "gdb_assert.h"
39
40 #include "x86-64-tdep.h"
41 #include "i387-tdep.h"
42
43 /* Note that the AMD64 architecture was previously known as x86-64.
44 The latter is (forever) engraved into the canonical system name as
45 returned bu config.guess, and used as the name for the AMD64 port
46 of GNU/Linux. The BSD's have renamed their ports to amd64; they
47 don't like to shout. For GDB we prefer the amd64_-prefix over the
48 x86_64_-prefix since it's so much easier to type. */
49
50 /* Register information. */
51
52 struct amd64_register_info
53 {
54 char *name;
55 struct type **type;
56 };
57
58 static struct amd64_register_info amd64_register_info[] =
59 {
60 { "rax", &builtin_type_int64 },
61 { "rbx", &builtin_type_int64 },
62 { "rcx", &builtin_type_int64 },
63 { "rdx", &builtin_type_int64 },
64 { "rsi", &builtin_type_int64 },
65 { "rdi", &builtin_type_int64 },
66 { "rbp", &builtin_type_void_data_ptr },
67 { "rsp", &builtin_type_void_data_ptr },
68
69 /* %r8 is indeed register number 8. */
70 { "r8", &builtin_type_int64 },
71 { "r9", &builtin_type_int64 },
72 { "r10", &builtin_type_int64 },
73 { "r11", &builtin_type_int64 },
74 { "r12", &builtin_type_int64 },
75 { "r13", &builtin_type_int64 },
76 { "r14", &builtin_type_int64 },
77 { "r15", &builtin_type_int64 },
78 { "rip", &builtin_type_void_func_ptr },
79 { "eflags", &builtin_type_int32 },
80 { "cs", &builtin_type_int32 },
81 { "ss", &builtin_type_int32 },
82 { "ds", &builtin_type_int32 },
83 { "es", &builtin_type_int32 },
84 { "fs", &builtin_type_int32 },
85 { "gs", &builtin_type_int32 },
86
87 /* %st0 is register number 24. */
88 { "st0", &builtin_type_i387_ext },
89 { "st1", &builtin_type_i387_ext },
90 { "st2", &builtin_type_i387_ext },
91 { "st3", &builtin_type_i387_ext },
92 { "st4", &builtin_type_i387_ext },
93 { "st5", &builtin_type_i387_ext },
94 { "st6", &builtin_type_i387_ext },
95 { "st7", &builtin_type_i387_ext },
96 { "fctrl", &builtin_type_int32 },
97 { "fstat", &builtin_type_int32 },
98 { "ftag", &builtin_type_int32 },
99 { "fiseg", &builtin_type_int32 },
100 { "fioff", &builtin_type_int32 },
101 { "foseg", &builtin_type_int32 },
102 { "fooff", &builtin_type_int32 },
103 { "fop", &builtin_type_int32 },
104
105 /* %xmm0 is register number 40. */
106 { "xmm0", &builtin_type_v4sf },
107 { "xmm1", &builtin_type_v4sf },
108 { "xmm2", &builtin_type_v4sf },
109 { "xmm3", &builtin_type_v4sf },
110 { "xmm4", &builtin_type_v4sf },
111 { "xmm5", &builtin_type_v4sf },
112 { "xmm6", &builtin_type_v4sf },
113 { "xmm7", &builtin_type_v4sf },
114 { "xmm8", &builtin_type_v4sf },
115 { "xmm9", &builtin_type_v4sf },
116 { "xmm10", &builtin_type_v4sf },
117 { "xmm11", &builtin_type_v4sf },
118 { "xmm12", &builtin_type_v4sf },
119 { "xmm13", &builtin_type_v4sf },
120 { "xmm14", &builtin_type_v4sf },
121 { "xmm15", &builtin_type_v4sf },
122 { "mxcsr", &builtin_type_int32 }
123 };
124
125 /* Total number of registers. */
126 #define AMD64_NUM_REGS \
127 (sizeof (amd64_register_info) / sizeof (amd64_register_info[0]))
128
129 /* Return the name of register REGNUM. */
130
131 static const char *
132 amd64_register_name (int regnum)
133 {
134 if (regnum >= 0 && regnum < AMD64_NUM_REGS)
135 return amd64_register_info[regnum].name;
136
137 return NULL;
138 }
139
140 /* Return the GDB type object for the "standard" data type of data in
141 register REGNUM. */
142
143 static struct type *
144 amd64_register_type (struct gdbarch *gdbarch, int regnum)
145 {
146 gdb_assert (regnum >= 0 && regnum < AMD64_NUM_REGS);
147
148 return *amd64_register_info[regnum].type;
149 }
150
151 /* DWARF Register Number Mapping as defined in the System V psABI,
152 section 3.6. */
153
154 static int amd64_dwarf_regmap[] =
155 {
156 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
157 X86_64_RAX_REGNUM, X86_64_RDX_REGNUM, 2, 1,
158 4, X86_64_RDI_REGNUM,
159
160 /* Frame Pointer Register RBP. */
161 X86_64_RBP_REGNUM,
162
163 /* Stack Pointer Register RSP. */
164 X86_64_RSP_REGNUM,
165
166 /* Extended Integer Registers 8 - 15. */
167 8, 9, 10, 11, 12, 13, 14, 15,
168
169 /* Return Address RA. Mapped to RIP. */
170 X86_64_RIP_REGNUM,
171
172 /* SSE Registers 0 - 7. */
173 X86_64_XMM0_REGNUM + 0, X86_64_XMM1_REGNUM,
174 X86_64_XMM0_REGNUM + 2, X86_64_XMM0_REGNUM + 3,
175 X86_64_XMM0_REGNUM + 4, X86_64_XMM0_REGNUM + 5,
176 X86_64_XMM0_REGNUM + 6, X86_64_XMM0_REGNUM + 7,
177
178 /* Extended SSE Registers 8 - 15. */
179 X86_64_XMM0_REGNUM + 8, X86_64_XMM0_REGNUM + 9,
180 X86_64_XMM0_REGNUM + 10, X86_64_XMM0_REGNUM + 11,
181 X86_64_XMM0_REGNUM + 12, X86_64_XMM0_REGNUM + 13,
182 X86_64_XMM0_REGNUM + 14, X86_64_XMM0_REGNUM + 15,
183
184 /* Floating Point Registers 0-7. */
185 X86_64_ST0_REGNUM + 0, X86_64_ST0_REGNUM + 1,
186 X86_64_ST0_REGNUM + 2, X86_64_ST0_REGNUM + 3,
187 X86_64_ST0_REGNUM + 4, X86_64_ST0_REGNUM + 5,
188 X86_64_ST0_REGNUM + 6, X86_64_ST0_REGNUM + 7
189 };
190
191 static const int amd64_dwarf_regmap_len =
192 (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0]));
193
194 /* Convert DWARF register number REG to the appropriate register
195 number used by GDB. */
196
197 static int
198 amd64_dwarf_reg_to_regnum (int reg)
199 {
200 int regnum = -1;
201
202 if (reg >= 0 || reg < amd64_dwarf_regmap_len)
203 regnum = amd64_dwarf_regmap[reg];
204
205 if (regnum == -1)
206 warning ("Unmapped DWARF Register #%d encountered\n", reg);
207
208 return regnum;
209 }
210
211 /* Return nonzero if a value of type TYPE stored in register REGNUM
212 needs any special handling. */
213
214 static int
215 amd64_convert_register_p (int regnum, struct type *type)
216 {
217 return i386_fp_regnum_p (regnum);
218 }
219 \f
220
221 /* Register classes as defined in the psABI. */
222
223 enum amd64_reg_class
224 {
225 AMD64_INTEGER,
226 AMD64_SSE,
227 AMD64_SSEUP,
228 AMD64_X87,
229 AMD64_X87UP,
230 AMD64_COMPLEX_X87,
231 AMD64_NO_CLASS,
232 AMD64_MEMORY
233 };
234
235 /* Return the union class of CLASS1 and CLASS2. See the psABI for
236 details. */
237
238 static enum amd64_reg_class
239 amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2)
240 {
241 /* Rule (a): If both classes are equal, this is the resulting class. */
242 if (class1 == class2)
243 return class1;
244
245 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
246 is the other class. */
247 if (class1 == AMD64_NO_CLASS)
248 return class2;
249 if (class2 == AMD64_NO_CLASS)
250 return class1;
251
252 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
253 if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY)
254 return AMD64_MEMORY;
255
256 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
257 if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER)
258 return AMD64_INTEGER;
259
260 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
261 MEMORY is used as class. */
262 if (class1 == AMD64_X87 || class1 == AMD64_X87UP
263 || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87
264 || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87)
265 return AMD64_MEMORY;
266
267 /* Rule (f): Otherwise class SSE is used. */
268 return AMD64_SSE;
269 }
270
271 static void amd64_classify (struct type *type, enum amd64_reg_class class[2]);
272
273 /* Return non-zero if TYPE is a non-POD structure or union type. */
274
275 static int
276 amd64_non_pod_p (struct type *type)
277 {
278 /* ??? A class with a base class certainly isn't POD, but does this
279 catch all non-POD structure types? */
280 if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0)
281 return 1;
282
283 return 0;
284 }
285
286 /* Classify TYPE according to the rules for aggregate (structures and
287 arrays) and union types, and store the result in CLASS. */
288
289 static void
290 amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2])
291 {
292 int len = TYPE_LENGTH (type);
293
294 /* 1. If the size of an object is larger than two eightbytes, or in
295 C++, is a non-POD structure or union type, or contains
296 unaligned fields, it has class memory. */
297 if (len > 16 || amd64_non_pod_p (type))
298 {
299 class[0] = class[1] = AMD64_MEMORY;
300 return;
301 }
302
303 /* 2. Both eightbytes get initialized to class NO_CLASS. */
304 class[0] = class[1] = AMD64_NO_CLASS;
305
306 /* 3. Each field of an object is classified recursively so that
307 always two fields are considered. The resulting class is
308 calculated according to the classes of the fields in the
309 eightbyte: */
310
311 if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
312 {
313 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type));
314
315 /* All fields in an array have the same type. */
316 amd64_classify (subtype, class);
317 if (len > 8 && class[1] == AMD64_NO_CLASS)
318 class[1] = class[0];
319 }
320 else
321 {
322 int i;
323
324 /* Structure or union. */
325 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT
326 || TYPE_CODE (type) == TYPE_CODE_UNION);
327
328 for (i = 0; i < TYPE_NFIELDS (type); i++)
329 {
330 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i));
331 int pos = TYPE_FIELD_BITPOS (type, i) / 64;
332 enum amd64_reg_class subclass[2];
333
334 /* Ignore static fields. */
335 if (TYPE_FIELD_STATIC (type, i))
336 continue;
337
338 gdb_assert (pos == 0 || pos == 1);
339
340 amd64_classify (subtype, subclass);
341 class[pos] = amd64_merge_classes (class[pos], subclass[0]);
342 if (pos == 0)
343 class[1] = amd64_merge_classes (class[1], subclass[1]);
344 }
345 }
346
347 /* 4. Then a post merger cleanup is done: */
348
349 /* Rule (a): If one of the classes is MEMORY, the whole argument is
350 passed in memory. */
351 if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY)
352 class[0] = class[1] = AMD64_MEMORY;
353
354 /* Rule (b): If SSEUP is not preceeded by SSE, it is converted to
355 SSE. */
356 if (class[0] == AMD64_SSEUP)
357 class[0] = AMD64_SSE;
358 if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE)
359 class[1] = AMD64_SSE;
360 }
361
362 /* Classify TYPE, and store the result in CLASS. */
363
364 static void
365 amd64_classify (struct type *type, enum amd64_reg_class class[2])
366 {
367 enum type_code code = TYPE_CODE (type);
368 int len = TYPE_LENGTH (type);
369
370 class[0] = class[1] = AMD64_NO_CLASS;
371
372 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
373 long, long long, and pointers are in the INTEGER class. */
374 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM
375 || code == TYPE_CODE_PTR || code == TYPE_CODE_REF)
376 && (len == 1 || len == 2 || len == 4 || len == 8))
377 class[0] = AMD64_INTEGER;
378
379 /* Arguments of types float, double and __m64 are in class SSE. */
380 else if (code == TYPE_CODE_FLT && (len == 4 || len == 8))
381 /* FIXME: __m64 . */
382 class[0] = AMD64_SSE;
383
384 /* Arguments of types __float128 and __m128 are split into two
385 halves. The least significant ones belong to class SSE, the most
386 significant one to class SSEUP. */
387 /* FIXME: __float128, __m128. */
388
389 /* The 64-bit mantissa of arguments of type long double belongs to
390 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
391 class X87UP. */
392 else if (code == TYPE_CODE_FLT && len == 16)
393 /* Class X87 and X87UP. */
394 class[0] = AMD64_X87, class[1] = AMD64_X87UP;
395
396 /* Aggregates. */
397 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT
398 || code == TYPE_CODE_UNION)
399 amd64_classify_aggregate (type, class);
400 }
401
402 static enum return_value_convention
403 amd64_return_value (struct gdbarch *gdbarch, struct type *type,
404 struct regcache *regcache,
405 void *readbuf, const void *writebuf)
406 {
407 enum amd64_reg_class class[2];
408 int len = TYPE_LENGTH (type);
409 static int integer_regnum[] = { X86_64_RAX_REGNUM, X86_64_RDX_REGNUM };
410 static int sse_regnum[] = { X86_64_XMM0_REGNUM, X86_64_XMM1_REGNUM };
411 int integer_reg = 0;
412 int sse_reg = 0;
413 int i;
414
415 gdb_assert (!(readbuf && writebuf));
416
417 /* 1. Classify the return type with the classification algorithm. */
418 amd64_classify (type, class);
419
420 /* 2. If the type has class MEMORY, then the caller provides space
421 for the return value and passes the address of this storage in
422 %rdi as if it were the first argument to the function. In
423 effect, this address becomes a hidden first argument. */
424 if (class[0] == AMD64_MEMORY)
425 return RETURN_VALUE_STRUCT_CONVENTION;
426
427 gdb_assert (class[1] != AMD64_MEMORY);
428 gdb_assert (len <= 16);
429
430 for (i = 0; len > 0; i++, len -= 8)
431 {
432 int regnum = -1;
433 int offset = 0;
434
435 switch (class[i])
436 {
437 case AMD64_INTEGER:
438 /* 3. If the class is INTEGER, the next available register
439 of the sequence %rax, %rdx is used. */
440 regnum = integer_regnum[integer_reg++];
441 break;
442
443 case AMD64_SSE:
444 /* 4. If the class is SSE, the next available SSE register
445 of the sequence %xmm0, %xmm1 is used. */
446 regnum = sse_regnum[sse_reg++];
447 break;
448
449 case AMD64_SSEUP:
450 /* 5. If the class is SSEUP, the eightbyte is passed in the
451 upper half of the last used SSE register. */
452 gdb_assert (sse_reg > 0);
453 regnum = sse_regnum[sse_reg - 1];
454 offset = 8;
455 break;
456
457 case AMD64_X87:
458 /* 6. If the class is X87, the value is returned on the X87
459 stack in %st0 as 80-bit x87 number. */
460 regnum = X86_64_ST0_REGNUM;
461 if (writebuf)
462 i387_return_value (gdbarch, regcache);
463 break;
464
465 case AMD64_X87UP:
466 /* 7. If the class is X87UP, the value is returned together
467 with the previous X87 value in %st0. */
468 gdb_assert (i > 0 && class[0] == AMD64_X87);
469 regnum = X86_64_ST0_REGNUM;
470 offset = 8;
471 len = 2;
472 break;
473
474 case AMD64_NO_CLASS:
475 continue;
476
477 default:
478 gdb_assert (!"Unexpected register class.");
479 }
480
481 gdb_assert (regnum != -1);
482
483 if (readbuf)
484 regcache_raw_read_part (regcache, regnum, offset, min (len, 8),
485 (char *) readbuf + i * 8);
486 if (writebuf)
487 regcache_raw_write_part (regcache, regnum, offset, min (len, 8),
488 (const char *) writebuf + i * 8);
489 }
490
491 return RETURN_VALUE_REGISTER_CONVENTION;
492 }
493 \f
494
495 static CORE_ADDR
496 amd64_push_arguments (struct regcache *regcache, int nargs,
497 struct value **args, CORE_ADDR sp, int struct_return)
498 {
499 static int integer_regnum[] =
500 {
501 X86_64_RDI_REGNUM, 4, /* %rdi, %rsi */
502 X86_64_RDX_REGNUM, 2, /* %rdx, %rcx */
503 8, 9 /* %r8, %r9 */
504 };
505 static int sse_regnum[] =
506 {
507 /* %xmm0 ... %xmm7 */
508 X86_64_XMM0_REGNUM + 0, X86_64_XMM1_REGNUM,
509 X86_64_XMM0_REGNUM + 2, X86_64_XMM0_REGNUM + 3,
510 X86_64_XMM0_REGNUM + 4, X86_64_XMM0_REGNUM + 5,
511 X86_64_XMM0_REGNUM + 6, X86_64_XMM0_REGNUM + 7,
512 };
513 struct value **stack_args = alloca (nargs * sizeof (struct value *));
514 int num_stack_args = 0;
515 int num_elements = 0;
516 int element = 0;
517 int integer_reg = 0;
518 int sse_reg = 0;
519 int i;
520
521 /* Reserve a register for the "hidden" argument. */
522 if (struct_return)
523 integer_reg++;
524
525 for (i = 0; i < nargs; i++)
526 {
527 struct type *type = VALUE_TYPE (args[i]);
528 int len = TYPE_LENGTH (type);
529 enum amd64_reg_class class[2];
530 int needed_integer_regs = 0;
531 int needed_sse_regs = 0;
532 int j;
533
534 /* Classify argument. */
535 amd64_classify (type, class);
536
537 /* Calculate the number of integer and SSE registers needed for
538 this argument. */
539 for (j = 0; j < 2; j++)
540 {
541 if (class[j] == AMD64_INTEGER)
542 needed_integer_regs++;
543 else if (class[j] == AMD64_SSE)
544 needed_sse_regs++;
545 }
546
547 /* Check whether enough registers are available, and if the
548 argument should be passed in registers at all. */
549 if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum)
550 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum)
551 || (needed_integer_regs == 0 && needed_sse_regs == 0))
552 {
553 /* The argument will be passed on the stack. */
554 num_elements += ((len + 7) / 8);
555 stack_args[num_stack_args++] = args[i];
556 }
557 else
558 {
559 /* The argument will be passed in registers. */
560 char *valbuf = VALUE_CONTENTS (args[i]);
561 char buf[8];
562
563 gdb_assert (len <= 16);
564
565 for (j = 0; len > 0; j++, len -= 8)
566 {
567 int regnum = -1;
568 int offset = 0;
569
570 switch (class[j])
571 {
572 case AMD64_INTEGER:
573 regnum = integer_regnum[integer_reg++];
574 break;
575
576 case AMD64_SSE:
577 regnum = sse_regnum[sse_reg++];
578 break;
579
580 case AMD64_SSEUP:
581 gdb_assert (sse_reg > 0);
582 regnum = sse_regnum[sse_reg - 1];
583 offset = 8;
584 break;
585
586 default:
587 gdb_assert (!"Unexpected register class.");
588 }
589
590 gdb_assert (regnum != -1);
591 memset (buf, 0, sizeof buf);
592 memcpy (buf, valbuf + j * 8, min (len, 8));
593 regcache_raw_write_part (regcache, regnum, offset, 8, buf);
594 }
595 }
596 }
597
598 /* Allocate space for the arguments on the stack. */
599 sp -= num_elements * 8;
600
601 /* The psABI says that "The end of the input argument area shall be
602 aligned on a 16 byte boundary." */
603 sp &= ~0xf;
604
605 /* Write out the arguments to the stack. */
606 for (i = 0; i < num_stack_args; i++)
607 {
608 struct type *type = VALUE_TYPE (stack_args[i]);
609 char *valbuf = VALUE_CONTENTS (stack_args[i]);
610 int len = TYPE_LENGTH (type);
611
612 write_memory (sp + element * 8, valbuf, len);
613 element += ((len + 7) / 8);
614 }
615
616 /* The psABI says that "For calls that may call functions that use
617 varargs or stdargs (prototype-less calls or calls to functions
618 containing ellipsis (...) in the declaration) %al is used as
619 hidden argument to specify the number of SSE registers used. */
620 regcache_raw_write_unsigned (regcache, X86_64_RAX_REGNUM, sse_reg);
621 return sp;
622 }
623
624 static CORE_ADDR
625 amd64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
626 struct regcache *regcache, CORE_ADDR bp_addr,
627 int nargs, struct value **args, CORE_ADDR sp,
628 int struct_return, CORE_ADDR struct_addr)
629 {
630 char buf[8];
631
632 /* Pass arguments. */
633 sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return);
634
635 /* Pass "hidden" argument". */
636 if (struct_return)
637 {
638 store_unsigned_integer (buf, 8, struct_addr);
639 regcache_cooked_write (regcache, X86_64_RDI_REGNUM, buf);
640 }
641
642 /* Store return address. */
643 sp -= 8;
644 store_unsigned_integer (buf, 8, bp_addr);
645 write_memory (sp, buf, 8);
646
647 /* Finally, update the stack pointer... */
648 store_unsigned_integer (buf, 8, sp);
649 regcache_cooked_write (regcache, X86_64_RSP_REGNUM, buf);
650
651 /* ...and fake a frame pointer. */
652 regcache_cooked_write (regcache, X86_64_RBP_REGNUM, buf);
653
654 return sp + 16;
655 }
656 \f
657
658 /* The maximum number of saved registers. This should include %rip. */
659 #define AMD64_NUM_SAVED_REGS X86_64_NUM_GREGS
660
661 struct amd64_frame_cache
662 {
663 /* Base address. */
664 CORE_ADDR base;
665 CORE_ADDR sp_offset;
666 CORE_ADDR pc;
667
668 /* Saved registers. */
669 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS];
670 CORE_ADDR saved_sp;
671
672 /* Do we have a frame? */
673 int frameless_p;
674 };
675
676 /* Allocate and initialize a frame cache. */
677
678 static struct amd64_frame_cache *
679 amd64_alloc_frame_cache (void)
680 {
681 struct amd64_frame_cache *cache;
682 int i;
683
684 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache);
685
686 /* Base address. */
687 cache->base = 0;
688 cache->sp_offset = -8;
689 cache->pc = 0;
690
691 /* Saved registers. We initialize these to -1 since zero is a valid
692 offset (that's where %rbp is supposed to be stored). */
693 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
694 cache->saved_regs[i] = -1;
695 cache->saved_sp = 0;
696
697 /* Frameless until proven otherwise. */
698 cache->frameless_p = 1;
699
700 return cache;
701 }
702
703 /* Do a limited analysis of the prologue at PC and update CACHE
704 accordingly. Bail out early if CURRENT_PC is reached. Return the
705 address where the analysis stopped.
706
707 We will handle only functions beginning with:
708
709 pushq %rbp 0x55
710 movq %rsp, %rbp 0x48 0x89 0xe5
711
712 Any function that doesn't start with this sequence will be assumed
713 to have no prologue and thus no valid frame pointer in %rbp. */
714
715 static CORE_ADDR
716 amd64_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
717 struct amd64_frame_cache *cache)
718 {
719 static unsigned char proto[3] = { 0x48, 0x89, 0xe5 };
720 unsigned char buf[3];
721 unsigned char op;
722
723 if (current_pc <= pc)
724 return current_pc;
725
726 op = read_memory_unsigned_integer (pc, 1);
727
728 if (op == 0x55) /* pushq %rbp */
729 {
730 /* Take into account that we've executed the `pushq %rbp' that
731 starts this instruction sequence. */
732 cache->saved_regs[X86_64_RBP_REGNUM] = 0;
733 cache->sp_offset += 8;
734
735 /* If that's all, return now. */
736 if (current_pc <= pc + 1)
737 return current_pc;
738
739 /* Check for `movq %rsp, %rbp'. */
740 read_memory (pc + 1, buf, 3);
741 if (memcmp (buf, proto, 3) != 0)
742 return pc + 1;
743
744 /* OK, we actually have a frame. */
745 cache->frameless_p = 0;
746 return pc + 4;
747 }
748
749 return pc;
750 }
751
752 /* Return PC of first real instruction. */
753
754 static CORE_ADDR
755 amd64_skip_prologue (CORE_ADDR start_pc)
756 {
757 struct amd64_frame_cache cache;
758 CORE_ADDR pc;
759
760 pc = amd64_analyze_prologue (start_pc, 0xffffffffffffffff, &cache);
761 if (cache.frameless_p)
762 return start_pc;
763
764 return pc;
765 }
766 \f
767
768 /* Normal frames. */
769
770 static struct amd64_frame_cache *
771 amd64_frame_cache (struct frame_info *next_frame, void **this_cache)
772 {
773 struct amd64_frame_cache *cache;
774 char buf[8];
775 int i;
776
777 if (*this_cache)
778 return *this_cache;
779
780 cache = amd64_alloc_frame_cache ();
781 *this_cache = cache;
782
783 cache->pc = frame_func_unwind (next_frame);
784 if (cache->pc != 0)
785 amd64_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache);
786
787 if (cache->frameless_p)
788 {
789 /* We didn't find a valid frame, which means that CACHE->base
790 currently holds the frame pointer for our calling frame. If
791 we're at the start of a function, or somewhere half-way its
792 prologue, the function's frame probably hasn't been fully
793 setup yet. Try to reconstruct the base address for the stack
794 frame by looking at the stack pointer. For truly "frameless"
795 functions this might work too. */
796
797 frame_unwind_register (next_frame, X86_64_RSP_REGNUM, buf);
798 cache->base = extract_unsigned_integer (buf, 8) + cache->sp_offset;
799 }
800 else
801 {
802 frame_unwind_register (next_frame, X86_64_RBP_REGNUM, buf);
803 cache->base = extract_unsigned_integer (buf, 8);
804 }
805
806 /* Now that we have the base address for the stack frame we can
807 calculate the value of %rsp in the calling frame. */
808 cache->saved_sp = cache->base + 16;
809
810 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
811 frame we find it at the same offset from the reconstructed base
812 address. */
813 cache->saved_regs[X86_64_RIP_REGNUM] = 8;
814
815 /* Adjust all the saved registers such that they contain addresses
816 instead of offsets. */
817 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++)
818 if (cache->saved_regs[i] != -1)
819 cache->saved_regs[i] += cache->base;
820
821 return cache;
822 }
823
824 static void
825 amd64_frame_this_id (struct frame_info *next_frame, void **this_cache,
826 struct frame_id *this_id)
827 {
828 struct amd64_frame_cache *cache =
829 amd64_frame_cache (next_frame, this_cache);
830
831 /* This marks the outermost frame. */
832 if (cache->base == 0)
833 return;
834
835 (*this_id) = frame_id_build (cache->base + 16, cache->pc);
836 }
837
838 static void
839 amd64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
840 int regnum, int *optimizedp,
841 enum lval_type *lvalp, CORE_ADDR *addrp,
842 int *realnump, void *valuep)
843 {
844 struct amd64_frame_cache *cache =
845 amd64_frame_cache (next_frame, this_cache);
846
847 gdb_assert (regnum >= 0);
848
849 if (regnum == SP_REGNUM && cache->saved_sp)
850 {
851 *optimizedp = 0;
852 *lvalp = not_lval;
853 *addrp = 0;
854 *realnump = -1;
855 if (valuep)
856 {
857 /* Store the value. */
858 store_unsigned_integer (valuep, 8, cache->saved_sp);
859 }
860 return;
861 }
862
863 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
864 {
865 *optimizedp = 0;
866 *lvalp = lval_memory;
867 *addrp = cache->saved_regs[regnum];
868 *realnump = -1;
869 if (valuep)
870 {
871 /* Read the value in from memory. */
872 read_memory (*addrp, valuep,
873 register_size (current_gdbarch, regnum));
874 }
875 return;
876 }
877
878 frame_register_unwind (next_frame, regnum,
879 optimizedp, lvalp, addrp, realnump, valuep);
880 }
881
882 static const struct frame_unwind amd64_frame_unwind =
883 {
884 NORMAL_FRAME,
885 amd64_frame_this_id,
886 amd64_frame_prev_register
887 };
888
889 static const struct frame_unwind *
890 amd64_frame_sniffer (struct frame_info *next_frame)
891 {
892 return &amd64_frame_unwind;
893 }
894 \f
895
896 /* Signal trampolines. */
897
898 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
899 64-bit variants. This would require using identical frame caches
900 on both platforms. */
901
902 static struct amd64_frame_cache *
903 amd64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
904 {
905 struct amd64_frame_cache *cache;
906 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
907 CORE_ADDR addr;
908 char buf[8];
909 int i;
910
911 if (*this_cache)
912 return *this_cache;
913
914 cache = amd64_alloc_frame_cache ();
915
916 frame_unwind_register (next_frame, X86_64_RSP_REGNUM, buf);
917 cache->base = extract_unsigned_integer (buf, 8) - 8;
918
919 addr = tdep->sigcontext_addr (next_frame);
920 gdb_assert (tdep->sc_reg_offset);
921 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS);
922 for (i = 0; i < tdep->sc_num_regs; i++)
923 if (tdep->sc_reg_offset[i] != -1)
924 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
925
926 *this_cache = cache;
927 return cache;
928 }
929
930 static void
931 amd64_sigtramp_frame_this_id (struct frame_info *next_frame,
932 void **this_cache, struct frame_id *this_id)
933 {
934 struct amd64_frame_cache *cache =
935 amd64_sigtramp_frame_cache (next_frame, this_cache);
936
937 (*this_id) = frame_id_build (cache->base + 16, frame_pc_unwind (next_frame));
938 }
939
940 static void
941 amd64_sigtramp_frame_prev_register (struct frame_info *next_frame,
942 void **this_cache,
943 int regnum, int *optimizedp,
944 enum lval_type *lvalp, CORE_ADDR *addrp,
945 int *realnump, void *valuep)
946 {
947 /* Make sure we've initialized the cache. */
948 amd64_sigtramp_frame_cache (next_frame, this_cache);
949
950 amd64_frame_prev_register (next_frame, this_cache, regnum,
951 optimizedp, lvalp, addrp, realnump, valuep);
952 }
953
954 static const struct frame_unwind amd64_sigtramp_frame_unwind =
955 {
956 SIGTRAMP_FRAME,
957 amd64_sigtramp_frame_this_id,
958 amd64_sigtramp_frame_prev_register
959 };
960
961 static const struct frame_unwind *
962 amd64_sigtramp_frame_sniffer (struct frame_info *next_frame)
963 {
964 CORE_ADDR pc = frame_pc_unwind (next_frame);
965 char *name;
966
967 find_pc_partial_function (pc, &name, NULL, NULL);
968 if (PC_IN_SIGTRAMP (pc, name))
969 {
970 gdb_assert (gdbarch_tdep (current_gdbarch)->sigcontext_addr);
971
972 return &amd64_sigtramp_frame_unwind;
973 }
974
975 return NULL;
976 }
977 \f
978
979 static CORE_ADDR
980 amd64_frame_base_address (struct frame_info *next_frame, void **this_cache)
981 {
982 struct amd64_frame_cache *cache =
983 amd64_frame_cache (next_frame, this_cache);
984
985 return cache->base;
986 }
987
988 static const struct frame_base amd64_frame_base =
989 {
990 &amd64_frame_unwind,
991 amd64_frame_base_address,
992 amd64_frame_base_address,
993 amd64_frame_base_address
994 };
995
996 static struct frame_id
997 amd64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
998 {
999 char buf[8];
1000 CORE_ADDR fp;
1001
1002 frame_unwind_register (next_frame, X86_64_RBP_REGNUM, buf);
1003 fp = extract_unsigned_integer (buf, 8);
1004
1005 return frame_id_build (fp + 16, frame_pc_unwind (next_frame));
1006 }
1007
1008 /* 16 byte align the SP per frame requirements. */
1009
1010 static CORE_ADDR
1011 amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1012 {
1013 return sp & -(CORE_ADDR)16;
1014 }
1015 \f
1016
1017 /* Supply register REGNUM from the floating-point register set REGSET
1018 to register cache REGCACHE. If REGNUM is -1, do this for all
1019 registers in REGSET. */
1020
1021 static void
1022 amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache,
1023 int regnum, const void *fpregs, size_t len)
1024 {
1025 const struct gdbarch_tdep *tdep = regset->descr;
1026
1027 gdb_assert (len == tdep->sizeof_fpregset);
1028 x86_64_supply_fxsave (regcache, regnum, fpregs);
1029 }
1030
1031 /* Return the appropriate register set for the core section identified
1032 by SECT_NAME and SECT_SIZE. */
1033
1034 static const struct regset *
1035 amd64_regset_from_core_section (struct gdbarch *gdbarch,
1036 const char *sect_name, size_t sect_size)
1037 {
1038 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1039
1040 if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset)
1041 {
1042 if (tdep->fpregset == NULL)
1043 {
1044 tdep->fpregset = XMALLOC (struct regset);
1045 tdep->fpregset->descr = tdep;
1046 tdep->fpregset->supply_regset = amd64_supply_fpregset;
1047 }
1048
1049 return tdep->fpregset;
1050 }
1051
1052 return i386_regset_from_core_section (gdbarch, sect_name, sect_size);
1053 }
1054 \f
1055
1056 void
1057 x86_64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
1058 {
1059 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1060
1061 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
1062 floating-point registers. */
1063 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE;
1064
1065 /* AMD64 has an FPU and 16 SSE registers. */
1066 tdep->st0_regnum = X86_64_ST0_REGNUM;
1067 tdep->num_xmm_regs = 16;
1068
1069 /* This is what all the fuss is about. */
1070 set_gdbarch_long_bit (gdbarch, 64);
1071 set_gdbarch_long_long_bit (gdbarch, 64);
1072 set_gdbarch_ptr_bit (gdbarch, 64);
1073
1074 /* In contrast to the i386, on AMD64 a `long double' actually takes
1075 up 128 bits, even though it's still based on the i387 extended
1076 floating-point format which has only 80 significant bits. */
1077 set_gdbarch_long_double_bit (gdbarch, 128);
1078
1079 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS);
1080 set_gdbarch_register_name (gdbarch, amd64_register_name);
1081 set_gdbarch_register_type (gdbarch, amd64_register_type);
1082
1083 /* Register numbers of various important registers. */
1084 set_gdbarch_sp_regnum (gdbarch, X86_64_RSP_REGNUM); /* %rsp */
1085 set_gdbarch_pc_regnum (gdbarch, X86_64_RIP_REGNUM); /* %rip */
1086 set_gdbarch_ps_regnum (gdbarch, X86_64_EFLAGS_REGNUM); /* %eflags */
1087 set_gdbarch_fp0_regnum (gdbarch, X86_64_ST0_REGNUM); /* %st(0) */
1088
1089 /* The "default" register numbering scheme for AMD64 is referred to
1090 as the "DWARF Register Number Mapping" in the System V psABI.
1091 The preferred debugging format for all known AMD64 targets is
1092 actually DWARF2, and GCC doesn't seem to support DWARF (that is
1093 DWARF-1), but we provide the same mapping just in case. This
1094 mapping is also used for stabs, which GCC does support. */
1095 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
1096 set_gdbarch_dwarf_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
1097 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum);
1098
1099 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
1100 be in use on any of the supported AMD64 targets. */
1101
1102 /* Call dummy code. */
1103 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call);
1104 set_gdbarch_frame_align (gdbarch, amd64_frame_align);
1105 set_gdbarch_frame_red_zone_size (gdbarch, 128);
1106
1107 set_gdbarch_convert_register_p (gdbarch, amd64_convert_register_p);
1108 set_gdbarch_register_to_value (gdbarch, i387_register_to_value);
1109 set_gdbarch_value_to_register (gdbarch, i387_value_to_register);
1110
1111 set_gdbarch_return_value (gdbarch, amd64_return_value);
1112
1113 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue);
1114
1115 /* Avoid wiring in the MMX registers for now. */
1116 set_gdbarch_num_pseudo_regs (gdbarch, 0);
1117 tdep->mm0_regnum = -1;
1118
1119 set_gdbarch_unwind_dummy_id (gdbarch, amd64_unwind_dummy_id);
1120
1121 /* FIXME: kettenis/20021026: This is ELF-specific. Fine for now,
1122 since all supported AMD64 targets are ELF, but that might change
1123 in the future. */
1124 set_gdbarch_in_solib_call_trampoline (gdbarch, in_plt_section);
1125
1126 frame_unwind_append_sniffer (gdbarch, amd64_sigtramp_frame_sniffer);
1127 frame_unwind_append_sniffer (gdbarch, amd64_frame_sniffer);
1128 frame_base_set_default (gdbarch, &amd64_frame_base);
1129
1130 /* If we have a register mapping, enable the generic core file support. */
1131 if (tdep->gregset_reg_offset)
1132 set_gdbarch_regset_from_core_section (gdbarch,
1133 amd64_regset_from_core_section);
1134 }
1135 \f
1136
1137 #define I387_ST0_REGNUM X86_64_ST0_REGNUM
1138
1139 /* The 64-bit FXSAVE format differs from the 32-bit format in the
1140 sense that the instruction pointer and data pointer are simply
1141 64-bit offsets into the code segment and the data segment instead
1142 of a selector offset pair. The functions below store the upper 32
1143 bits of these pointers (instead of just the 16-bits of the segment
1144 selector). */
1145
1146 /* Fill register REGNUM in REGCACHE with the appropriate
1147 floating-point or SSE register value from *FXSAVE. If REGNUM is
1148 -1, do this for all registers. This function masks off any of the
1149 reserved bits in *FXSAVE. */
1150
1151 void
1152 x86_64_supply_fxsave (struct regcache *regcache, int regnum,
1153 const void *fxsave)
1154 {
1155 i387_supply_fxsave (regcache, regnum, fxsave);
1156
1157 if (fxsave)
1158 {
1159 const char *regs = fxsave;
1160
1161 if (regnum == -1 || regnum == I387_FISEG_REGNUM)
1162 regcache_raw_supply (regcache, I387_FISEG_REGNUM, regs + 12);
1163 if (regnum == -1 || regnum == I387_FOSEG_REGNUM)
1164 regcache_raw_supply (regcache, I387_FOSEG_REGNUM, regs + 20);
1165 }
1166 }
1167
1168 /* Fill register REGNUM (if it is a floating-point or SSE register) in
1169 *FXSAVE with the value in GDB's register cache. If REGNUM is -1, do
1170 this for all registers. This function doesn't touch any of the
1171 reserved bits in *FXSAVE. */
1172
1173 void
1174 x86_64_fill_fxsave (char *fxsave, int regnum)
1175 {
1176 i387_fill_fxsave (fxsave, regnum);
1177
1178 if (regnum == -1 || regnum == I387_FISEG_REGNUM)
1179 regcache_collect (I387_FISEG_REGNUM, fxsave + 12);
1180 if (regnum == -1 || regnum == I387_FOSEG_REGNUM)
1181 regcache_collect (I387_FOSEG_REGNUM, fxsave + 20);
1182 }
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