1 /* Target-dependent code for AMD64.
3 Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Jiri Smid, SuSE Labs.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 #include "arch-utils.h"
26 #include "dummy-frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
38 #include "gdb_assert.h"
40 #include "x86-64-tdep.h"
41 #include "i387-tdep.h"
43 /* Note that the AMD64 architecture was previously known as x86-64.
44 The latter is (forever) engraved into the canonical system name as
45 returned bu config.guess, and used as the name for the AMD64 port
46 of GNU/Linux. The BSD's have renamed their ports to amd64; they
47 don't like to shout. For GDB we prefer the amd64_-prefix over the
48 x86_64_-prefix since it's so much easier to type. */
50 /* Register information. */
52 struct amd64_register_info
58 static struct amd64_register_info amd64_register_info
[] =
60 { "rax", &builtin_type_int64
},
61 { "rbx", &builtin_type_int64
},
62 { "rcx", &builtin_type_int64
},
63 { "rdx", &builtin_type_int64
},
64 { "rsi", &builtin_type_int64
},
65 { "rdi", &builtin_type_int64
},
66 { "rbp", &builtin_type_void_data_ptr
},
67 { "rsp", &builtin_type_void_data_ptr
},
69 /* %r8 is indeed register number 8. */
70 { "r8", &builtin_type_int64
},
71 { "r9", &builtin_type_int64
},
72 { "r10", &builtin_type_int64
},
73 { "r11", &builtin_type_int64
},
74 { "r12", &builtin_type_int64
},
75 { "r13", &builtin_type_int64
},
76 { "r14", &builtin_type_int64
},
77 { "r15", &builtin_type_int64
},
78 { "rip", &builtin_type_void_func_ptr
},
79 { "eflags", &builtin_type_int32
},
80 { "cs", &builtin_type_int32
},
81 { "ss", &builtin_type_int32
},
82 { "ds", &builtin_type_int32
},
83 { "es", &builtin_type_int32
},
84 { "fs", &builtin_type_int32
},
85 { "gs", &builtin_type_int32
},
87 /* %st0 is register number 24. */
88 { "st0", &builtin_type_i387_ext
},
89 { "st1", &builtin_type_i387_ext
},
90 { "st2", &builtin_type_i387_ext
},
91 { "st3", &builtin_type_i387_ext
},
92 { "st4", &builtin_type_i387_ext
},
93 { "st5", &builtin_type_i387_ext
},
94 { "st6", &builtin_type_i387_ext
},
95 { "st7", &builtin_type_i387_ext
},
96 { "fctrl", &builtin_type_int32
},
97 { "fstat", &builtin_type_int32
},
98 { "ftag", &builtin_type_int32
},
99 { "fiseg", &builtin_type_int32
},
100 { "fioff", &builtin_type_int32
},
101 { "foseg", &builtin_type_int32
},
102 { "fooff", &builtin_type_int32
},
103 { "fop", &builtin_type_int32
},
105 /* %xmm0 is register number 40. */
106 { "xmm0", &builtin_type_v4sf
},
107 { "xmm1", &builtin_type_v4sf
},
108 { "xmm2", &builtin_type_v4sf
},
109 { "xmm3", &builtin_type_v4sf
},
110 { "xmm4", &builtin_type_v4sf
},
111 { "xmm5", &builtin_type_v4sf
},
112 { "xmm6", &builtin_type_v4sf
},
113 { "xmm7", &builtin_type_v4sf
},
114 { "xmm8", &builtin_type_v4sf
},
115 { "xmm9", &builtin_type_v4sf
},
116 { "xmm10", &builtin_type_v4sf
},
117 { "xmm11", &builtin_type_v4sf
},
118 { "xmm12", &builtin_type_v4sf
},
119 { "xmm13", &builtin_type_v4sf
},
120 { "xmm14", &builtin_type_v4sf
},
121 { "xmm15", &builtin_type_v4sf
},
122 { "mxcsr", &builtin_type_int32
}
125 /* Total number of registers. */
126 #define AMD64_NUM_REGS \
127 (sizeof (amd64_register_info) / sizeof (amd64_register_info[0]))
129 /* Return the name of register REGNUM. */
132 amd64_register_name (int regnum
)
134 if (regnum
>= 0 && regnum
< AMD64_NUM_REGS
)
135 return amd64_register_info
[regnum
].name
;
140 /* Return the GDB type object for the "standard" data type of data in
144 amd64_register_type (struct gdbarch
*gdbarch
, int regnum
)
146 gdb_assert (regnum
>= 0 && regnum
< AMD64_NUM_REGS
);
148 return *amd64_register_info
[regnum
].type
;
151 /* DWARF Register Number Mapping as defined in the System V psABI,
154 static int amd64_dwarf_regmap
[] =
156 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
157 X86_64_RAX_REGNUM
, X86_64_RDX_REGNUM
, 2, 1,
158 4, X86_64_RDI_REGNUM
,
160 /* Frame Pointer Register RBP. */
163 /* Stack Pointer Register RSP. */
166 /* Extended Integer Registers 8 - 15. */
167 8, 9, 10, 11, 12, 13, 14, 15,
169 /* Return Address RA. Mapped to RIP. */
172 /* SSE Registers 0 - 7. */
173 X86_64_XMM0_REGNUM
+ 0, X86_64_XMM1_REGNUM
,
174 X86_64_XMM0_REGNUM
+ 2, X86_64_XMM0_REGNUM
+ 3,
175 X86_64_XMM0_REGNUM
+ 4, X86_64_XMM0_REGNUM
+ 5,
176 X86_64_XMM0_REGNUM
+ 6, X86_64_XMM0_REGNUM
+ 7,
178 /* Extended SSE Registers 8 - 15. */
179 X86_64_XMM0_REGNUM
+ 8, X86_64_XMM0_REGNUM
+ 9,
180 X86_64_XMM0_REGNUM
+ 10, X86_64_XMM0_REGNUM
+ 11,
181 X86_64_XMM0_REGNUM
+ 12, X86_64_XMM0_REGNUM
+ 13,
182 X86_64_XMM0_REGNUM
+ 14, X86_64_XMM0_REGNUM
+ 15,
184 /* Floating Point Registers 0-7. */
185 X86_64_ST0_REGNUM
+ 0, X86_64_ST0_REGNUM
+ 1,
186 X86_64_ST0_REGNUM
+ 2, X86_64_ST0_REGNUM
+ 3,
187 X86_64_ST0_REGNUM
+ 4, X86_64_ST0_REGNUM
+ 5,
188 X86_64_ST0_REGNUM
+ 6, X86_64_ST0_REGNUM
+ 7
191 static const int amd64_dwarf_regmap_len
=
192 (sizeof (amd64_dwarf_regmap
) / sizeof (amd64_dwarf_regmap
[0]));
194 /* Convert DWARF register number REG to the appropriate register
195 number used by GDB. */
198 amd64_dwarf_reg_to_regnum (int reg
)
202 if (reg
>= 0 || reg
< amd64_dwarf_regmap_len
)
203 regnum
= amd64_dwarf_regmap
[reg
];
206 warning ("Unmapped DWARF Register #%d encountered\n", reg
);
211 /* Return nonzero if a value of type TYPE stored in register REGNUM
212 needs any special handling. */
215 amd64_convert_register_p (int regnum
, struct type
*type
)
217 return i386_fp_regnum_p (regnum
);
221 /* Register classes as defined in the psABI. */
235 /* Return the union class of CLASS1 and CLASS2. See the psABI for
238 static enum amd64_reg_class
239 amd64_merge_classes (enum amd64_reg_class class1
, enum amd64_reg_class class2
)
241 /* Rule (a): If both classes are equal, this is the resulting class. */
242 if (class1
== class2
)
245 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
246 is the other class. */
247 if (class1
== AMD64_NO_CLASS
)
249 if (class2
== AMD64_NO_CLASS
)
252 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
253 if (class1
== AMD64_MEMORY
|| class2
== AMD64_MEMORY
)
256 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
257 if (class1
== AMD64_INTEGER
|| class2
== AMD64_INTEGER
)
258 return AMD64_INTEGER
;
260 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
261 MEMORY is used as class. */
262 if (class1
== AMD64_X87
|| class1
== AMD64_X87UP
263 || class1
== AMD64_COMPLEX_X87
|| class2
== AMD64_X87
264 || class2
== AMD64_X87UP
|| class2
== AMD64_COMPLEX_X87
)
267 /* Rule (f): Otherwise class SSE is used. */
271 static void amd64_classify (struct type
*type
, enum amd64_reg_class
class[2]);
273 /* Classify TYPE according to the rules for aggregate (structures and
274 arrays) and union types, and store the result in CLASS. */
277 amd64_classify_aggregate (struct type
*type
, enum amd64_reg_class
class[2])
279 int len
= TYPE_LENGTH (type
);
281 /* 1. If the size of an object is larger than two eightbytes, or in
282 C++, is a non-POD structure or union type, or contains
283 unaligned fields, it has class memory. */
286 class[0] = class[1] = AMD64_MEMORY
;
290 /* 2. Both eightbytes get initialized to class NO_CLASS. */
291 class[0] = class[1] = AMD64_NO_CLASS
;
293 /* 3. Each field of an object is classified recursively so that
294 always two fields are considered. The resulting class is
295 calculated according to the classes of the fields in the
298 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
300 struct type
*subtype
= check_typedef (TYPE_TARGET_TYPE (type
));
302 /* All fields in an array have the same type. */
303 amd64_classify (subtype
, class);
304 if (len
> 8 && class[1] == AMD64_NO_CLASS
)
311 /* Structure or union. */
312 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_STRUCT
313 || TYPE_CODE (type
) == TYPE_CODE_UNION
);
315 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
317 struct type
*subtype
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
318 int pos
= TYPE_FIELD_BITPOS (type
, i
) / 64;
319 enum amd64_reg_class subclass
[2];
321 gdb_assert (pos
== 0 || pos
== 1);
323 amd64_classify (subtype
, subclass
);
324 class[pos
] = amd64_merge_classes (class[pos
], subclass
[0]);
326 class[1] = amd64_merge_classes (class[1], subclass
[1]);
330 /* 4. Then a post merger cleanup is done: */
332 /* Rule (a): If one of the classes is MEMORY, the whole argument is
334 if (class[0] == AMD64_MEMORY
|| class[1] == AMD64_MEMORY
)
335 class[0] = class[1] = AMD64_MEMORY
;
337 /* Rule (b): If SSEUP is not preceeded by SSE, it is converted to
339 if (class[0] == AMD64_SSEUP
)
340 class[0] = AMD64_SSE
;
341 if (class[1] == AMD64_SSEUP
&& class[0] != AMD64_SSE
)
342 class[1] = AMD64_SSE
;
345 /* Classify TYPE, and store the result in CLASS. */
348 amd64_classify (struct type
*type
, enum amd64_reg_class
class[2])
350 enum type_code code
= TYPE_CODE (type
);
351 int len
= TYPE_LENGTH (type
);
353 class[0] = class[1] = AMD64_NO_CLASS
;
355 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
356 long, long long, and pointers are in the INTEGER class. */
357 if ((code
== TYPE_CODE_INT
|| code
== TYPE_CODE_ENUM
358 || code
== TYPE_CODE_PTR
|| code
== TYPE_CODE_REF
)
359 && (len
== 1 || len
== 2 || len
== 4 || len
== 8))
360 class[0] = AMD64_INTEGER
;
362 /* Arguments of types float, double and __m64 are in class SSE. */
363 else if (code
== TYPE_CODE_FLT
&& (len
== 4 || len
== 8))
365 class[0] = AMD64_SSE
;
367 /* Arguments of types __float128 and __m128 are split into two
368 halves. The least significant ones belong to class SSE, the most
369 significant one to class SSEUP. */
370 /* FIXME: __float128, __m128. */
372 /* The 64-bit mantissa of arguments of type long double belongs to
373 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
375 else if (code
== TYPE_CODE_FLT
&& len
== 16)
376 /* Class X87 and X87UP. */
377 class[0] = AMD64_X87
, class[1] = AMD64_X87UP
;
380 else if (code
== TYPE_CODE_ARRAY
|| code
== TYPE_CODE_STRUCT
381 || code
== TYPE_CODE_UNION
)
382 amd64_classify_aggregate (type
, class);
385 static enum return_value_convention
386 amd64_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
387 struct regcache
*regcache
,
388 void *readbuf
, const void *writebuf
)
390 enum amd64_reg_class
class[2];
391 int len
= TYPE_LENGTH (type
);
392 static int integer_regnum
[] = { X86_64_RAX_REGNUM
, X86_64_RDX_REGNUM
};
393 static int sse_regnum
[] = { X86_64_XMM0_REGNUM
, X86_64_XMM1_REGNUM
};
398 gdb_assert (!(readbuf
&& writebuf
));
400 /* 1. Classify the return type with the classification algorithm. */
401 amd64_classify (type
, class);
403 /* 2. If the type has class MEMORY, then the caller provides space
404 for the return value and passes the address of this storage in
405 %rdi as if it were the first argument to the function. In
406 effect, this address becomes a hidden first argument. */
407 if (class[0] == AMD64_MEMORY
)
408 return RETURN_VALUE_STRUCT_CONVENTION
;
410 gdb_assert (class[1] != AMD64_MEMORY
);
411 gdb_assert (len
<= 16);
413 for (i
= 0; len
> 0; i
++, len
-= 8)
421 /* 3. If the class is INTEGER, the next available register
422 of the sequence %rax, %rdx is used. */
423 regnum
= integer_regnum
[integer_reg
++];
427 /* 4. If the class is SSE, the next available SSE register
428 of the sequence %xmm0, %xmm1 is used. */
429 regnum
= sse_regnum
[sse_reg
++];
433 /* 5. If the class is SSEUP, the eightbyte is passed in the
434 upper half of the last used SSE register. */
435 gdb_assert (sse_reg
> 0);
436 regnum
= sse_regnum
[sse_reg
- 1];
441 /* 6. If the class is X87, the value is returned on the X87
442 stack in %st0 as 80-bit x87 number. */
443 regnum
= X86_64_ST0_REGNUM
;
445 i387_return_value (gdbarch
, regcache
);
449 /* 7. If the class is X87UP, the value is returned together
450 with the previous X87 value in %st0. */
451 gdb_assert (i
> 0 && class[0] == AMD64_X87
);
452 regnum
= X86_64_ST0_REGNUM
;
461 gdb_assert (!"Unexpected register class.");
464 gdb_assert (regnum
!= -1);
467 regcache_raw_read_part (regcache
, regnum
, offset
, min (len
, 8),
468 (char *) readbuf
+ i
* 8);
470 regcache_raw_write_part (regcache
, regnum
, offset
, min (len
, 8),
471 (const char *) writebuf
+ i
* 8);
474 return RETURN_VALUE_REGISTER_CONVENTION
;
479 amd64_push_arguments (struct regcache
*regcache
, int nargs
,
480 struct value
**args
, CORE_ADDR sp
)
482 static int integer_regnum
[] =
484 X86_64_RDI_REGNUM
, 4, /* %rdi, %rsi */
485 X86_64_RDX_REGNUM
, 2, /* %rdx, %rcx */
488 static int sse_regnum
[] =
490 /* %xmm0 ... %xmm7 */
491 X86_64_XMM0_REGNUM
+ 0, X86_64_XMM1_REGNUM
,
492 X86_64_XMM0_REGNUM
+ 2, X86_64_XMM0_REGNUM
+ 3,
493 X86_64_XMM0_REGNUM
+ 4, X86_64_XMM0_REGNUM
+ 5,
494 X86_64_XMM0_REGNUM
+ 6, X86_64_XMM0_REGNUM
+ 7,
496 struct value
**stack_args
= alloca (nargs
* sizeof (struct value
*));
497 int num_stack_args
= 0;
498 int num_elements
= 0;
504 for (i
= 0; i
< nargs
; i
++)
506 struct type
*type
= VALUE_TYPE (args
[i
]);
507 int len
= TYPE_LENGTH (type
);
508 enum amd64_reg_class
class[2];
509 int needed_integer_regs
= 0;
510 int needed_sse_regs
= 0;
513 /* Classify argument. */
514 amd64_classify (type
, class);
516 /* Calculate the number of integer and SSE registers needed for
518 for (j
= 0; j
< 2; j
++)
520 if (class[j
] == AMD64_INTEGER
)
521 needed_integer_regs
++;
522 else if (class[j
] == AMD64_SSE
)
526 /* Check whether enough registers are available, and if the
527 argument should be passed in registers at all. */
528 if (integer_reg
+ needed_integer_regs
> ARRAY_SIZE (integer_regnum
)
529 || sse_reg
+ needed_sse_regs
> ARRAY_SIZE (sse_regnum
)
530 || (needed_integer_regs
== 0 && needed_sse_regs
== 0))
532 /* The argument will be passed on the stack. */
533 num_elements
+= ((len
+ 7) / 8);
534 stack_args
[num_stack_args
++] = args
[i
];
538 /* The argument will be passed in registers. */
539 char *valbuf
= VALUE_CONTENTS (args
[i
]);
542 gdb_assert (len
<= 16);
544 for (j
= 0; len
> 0; j
++, len
-= 8)
552 regnum
= integer_regnum
[integer_reg
++];
556 regnum
= sse_regnum
[sse_reg
++];
560 gdb_assert (sse_reg
> 0);
561 regnum
= sse_regnum
[sse_reg
- 1];
566 gdb_assert (!"Unexpected register class.");
569 gdb_assert (regnum
!= -1);
570 memset (buf
, 0, sizeof buf
);
571 memcpy (buf
, valbuf
+ j
* 8, min (len
, 8));
572 regcache_raw_write_part (regcache
, regnum
, offset
, 8, buf
);
577 /* Allocate space for the arguments on the stack. */
578 sp
-= num_elements
* 8;
580 /* The psABI says that "The end of the input argument area shall be
581 aligned on a 16 byte boundary." */
584 /* Write out the arguments to the stack. */
585 for (i
= 0; i
< num_stack_args
; i
++)
587 struct type
*type
= VALUE_TYPE (stack_args
[i
]);
588 char *valbuf
= VALUE_CONTENTS (stack_args
[i
]);
589 int len
= TYPE_LENGTH (type
);
591 write_memory (sp
+ element
* 8, valbuf
, len
);
592 element
+= ((len
+ 7) / 8);
595 /* The psABI says that "For calls that may call functions that use
596 varargs or stdargs (prototype-less calls or calls to functions
597 containing ellipsis (...) in the declaration) %al is used as
598 hidden argument to specify the number of SSE registers used. */
599 regcache_raw_write_unsigned (regcache
, X86_64_RAX_REGNUM
, sse_reg
);
604 amd64_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
605 struct regcache
*regcache
, CORE_ADDR bp_addr
,
606 int nargs
, struct value
**args
, CORE_ADDR sp
,
607 int struct_return
, CORE_ADDR struct_addr
)
611 /* Pass arguments. */
612 sp
= amd64_push_arguments (regcache
, nargs
, args
, sp
);
614 /* Pass "hidden" argument". */
617 store_unsigned_integer (buf
, 8, struct_addr
);
618 regcache_cooked_write (regcache
, X86_64_RDI_REGNUM
, buf
);
621 /* Store return address. */
623 store_unsigned_integer (buf
, 8, bp_addr
);
624 write_memory (sp
, buf
, 8);
626 /* Finally, update the stack pointer... */
627 store_unsigned_integer (buf
, 8, sp
);
628 regcache_cooked_write (regcache
, X86_64_RSP_REGNUM
, buf
);
630 /* ...and fake a frame pointer. */
631 regcache_cooked_write (regcache
, X86_64_RBP_REGNUM
, buf
);
637 /* The maximum number of saved registers. This should include %rip. */
638 #define AMD64_NUM_SAVED_REGS X86_64_NUM_GREGS
640 struct amd64_frame_cache
647 /* Saved registers. */
648 CORE_ADDR saved_regs
[AMD64_NUM_SAVED_REGS
];
651 /* Do we have a frame? */
655 /* Allocate and initialize a frame cache. */
657 static struct amd64_frame_cache
*
658 amd64_alloc_frame_cache (void)
660 struct amd64_frame_cache
*cache
;
663 cache
= FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache
);
667 cache
->sp_offset
= -8;
670 /* Saved registers. We initialize these to -1 since zero is a valid
671 offset (that's where %rbp is supposed to be stored). */
672 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
673 cache
->saved_regs
[i
] = -1;
676 /* Frameless until proven otherwise. */
677 cache
->frameless_p
= 1;
682 /* Do a limited analysis of the prologue at PC and update CACHE
683 accordingly. Bail out early if CURRENT_PC is reached. Return the
684 address where the analysis stopped.
686 We will handle only functions beginning with:
689 movq %rsp, %rbp 0x48 0x89 0xe5
691 Any function that doesn't start with this sequence will be assumed
692 to have no prologue and thus no valid frame pointer in %rbp. */
695 amd64_analyze_prologue (CORE_ADDR pc
, CORE_ADDR current_pc
,
696 struct amd64_frame_cache
*cache
)
698 static unsigned char proto
[3] = { 0x48, 0x89, 0xe5 };
699 unsigned char buf
[3];
702 if (current_pc
<= pc
)
705 op
= read_memory_unsigned_integer (pc
, 1);
707 if (op
== 0x55) /* pushq %rbp */
709 /* Take into account that we've executed the `pushq %rbp' that
710 starts this instruction sequence. */
711 cache
->saved_regs
[X86_64_RBP_REGNUM
] = 0;
712 cache
->sp_offset
+= 8;
714 /* If that's all, return now. */
715 if (current_pc
<= pc
+ 1)
718 /* Check for `movq %rsp, %rbp'. */
719 read_memory (pc
+ 1, buf
, 3);
720 if (memcmp (buf
, proto
, 3) != 0)
723 /* OK, we actually have a frame. */
724 cache
->frameless_p
= 0;
731 /* Return PC of first real instruction. */
734 amd64_skip_prologue (CORE_ADDR start_pc
)
736 struct amd64_frame_cache cache
;
739 pc
= amd64_analyze_prologue (start_pc
, 0xffffffffffffffff, &cache
);
740 if (cache
.frameless_p
)
749 static struct amd64_frame_cache
*
750 amd64_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
752 struct amd64_frame_cache
*cache
;
759 cache
= amd64_alloc_frame_cache ();
762 cache
->pc
= frame_func_unwind (next_frame
);
764 amd64_analyze_prologue (cache
->pc
, frame_pc_unwind (next_frame
), cache
);
766 if (cache
->frameless_p
)
768 /* We didn't find a valid frame, which means that CACHE->base
769 currently holds the frame pointer for our calling frame. If
770 we're at the start of a function, or somewhere half-way its
771 prologue, the function's frame probably hasn't been fully
772 setup yet. Try to reconstruct the base address for the stack
773 frame by looking at the stack pointer. For truly "frameless"
774 functions this might work too. */
776 frame_unwind_register (next_frame
, X86_64_RSP_REGNUM
, buf
);
777 cache
->base
= extract_unsigned_integer (buf
, 8) + cache
->sp_offset
;
781 frame_unwind_register (next_frame
, X86_64_RBP_REGNUM
, buf
);
782 cache
->base
= extract_unsigned_integer (buf
, 8);
785 /* Now that we have the base address for the stack frame we can
786 calculate the value of %rsp in the calling frame. */
787 cache
->saved_sp
= cache
->base
+ 16;
789 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
790 frame we find it at the same offset from the reconstructed base
792 cache
->saved_regs
[X86_64_RIP_REGNUM
] = 8;
794 /* Adjust all the saved registers such that they contain addresses
795 instead of offsets. */
796 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
797 if (cache
->saved_regs
[i
] != -1)
798 cache
->saved_regs
[i
] += cache
->base
;
804 amd64_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
805 struct frame_id
*this_id
)
807 struct amd64_frame_cache
*cache
=
808 amd64_frame_cache (next_frame
, this_cache
);
810 /* This marks the outermost frame. */
811 if (cache
->base
== 0)
814 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
818 amd64_frame_prev_register (struct frame_info
*next_frame
, void **this_cache
,
819 int regnum
, int *optimizedp
,
820 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
821 int *realnump
, void *valuep
)
823 struct amd64_frame_cache
*cache
=
824 amd64_frame_cache (next_frame
, this_cache
);
826 gdb_assert (regnum
>= 0);
828 if (regnum
== SP_REGNUM
&& cache
->saved_sp
)
836 /* Store the value. */
837 store_unsigned_integer (valuep
, 8, cache
->saved_sp
);
842 if (regnum
< AMD64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
845 *lvalp
= lval_memory
;
846 *addrp
= cache
->saved_regs
[regnum
];
850 /* Read the value in from memory. */
851 read_memory (*addrp
, valuep
,
852 register_size (current_gdbarch
, regnum
));
857 frame_register_unwind (next_frame
, regnum
,
858 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
861 static const struct frame_unwind amd64_frame_unwind
=
865 amd64_frame_prev_register
868 static const struct frame_unwind
*
869 amd64_frame_sniffer (struct frame_info
*next_frame
)
871 return &amd64_frame_unwind
;
875 /* Signal trampolines. */
877 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
878 64-bit variants. This would require using identical frame caches
879 on both platforms. */
881 static struct amd64_frame_cache
*
882 amd64_sigtramp_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
884 struct amd64_frame_cache
*cache
;
885 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
893 cache
= amd64_alloc_frame_cache ();
895 frame_unwind_register (next_frame
, X86_64_RSP_REGNUM
, buf
);
896 cache
->base
= extract_unsigned_integer (buf
, 8) - 8;
898 addr
= tdep
->sigcontext_addr (next_frame
);
899 gdb_assert (tdep
->sc_reg_offset
);
900 gdb_assert (tdep
->sc_num_regs
<= AMD64_NUM_SAVED_REGS
);
901 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
902 if (tdep
->sc_reg_offset
[i
] != -1)
903 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
910 amd64_sigtramp_frame_this_id (struct frame_info
*next_frame
,
911 void **this_cache
, struct frame_id
*this_id
)
913 struct amd64_frame_cache
*cache
=
914 amd64_sigtramp_frame_cache (next_frame
, this_cache
);
916 (*this_id
) = frame_id_build (cache
->base
+ 16, frame_pc_unwind (next_frame
));
920 amd64_sigtramp_frame_prev_register (struct frame_info
*next_frame
,
922 int regnum
, int *optimizedp
,
923 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
924 int *realnump
, void *valuep
)
926 /* Make sure we've initialized the cache. */
927 amd64_sigtramp_frame_cache (next_frame
, this_cache
);
929 amd64_frame_prev_register (next_frame
, this_cache
, regnum
,
930 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
933 static const struct frame_unwind amd64_sigtramp_frame_unwind
=
936 amd64_sigtramp_frame_this_id
,
937 amd64_sigtramp_frame_prev_register
940 static const struct frame_unwind
*
941 amd64_sigtramp_frame_sniffer (struct frame_info
*next_frame
)
943 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
946 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
947 if (PC_IN_SIGTRAMP (pc
, name
))
949 gdb_assert (gdbarch_tdep (current_gdbarch
)->sigcontext_addr
);
951 return &amd64_sigtramp_frame_unwind
;
959 amd64_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
961 struct amd64_frame_cache
*cache
=
962 amd64_frame_cache (next_frame
, this_cache
);
967 static const struct frame_base amd64_frame_base
=
970 amd64_frame_base_address
,
971 amd64_frame_base_address
,
972 amd64_frame_base_address
975 static struct frame_id
976 amd64_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
981 frame_unwind_register (next_frame
, X86_64_RBP_REGNUM
, buf
);
982 fp
= extract_unsigned_integer (buf
, 8);
984 return frame_id_build (fp
+ 16, frame_pc_unwind (next_frame
));
987 /* 16 byte align the SP per frame requirements. */
990 amd64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
992 return sp
& -(CORE_ADDR
)16;
996 /* Supply register REGNUM from the floating-point register set REGSET
997 to register cache REGCACHE. If REGNUM is -1, do this for all
998 registers in REGSET. */
1001 amd64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
1002 int regnum
, const void *fpregs
, size_t len
)
1004 const struct gdbarch_tdep
*tdep
= regset
->descr
;
1006 gdb_assert (len
== tdep
->sizeof_fpregset
);
1007 x86_64_supply_fxsave (regcache
, regnum
, fpregs
);
1010 /* Return the appropriate register set for the core section identified
1011 by SECT_NAME and SECT_SIZE. */
1013 static const struct regset
*
1014 amd64_regset_from_core_section (struct gdbarch
*gdbarch
,
1015 const char *sect_name
, size_t sect_size
)
1017 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1019 if (strcmp (sect_name
, ".reg2") == 0 && sect_size
== tdep
->sizeof_fpregset
)
1021 if (tdep
->fpregset
== NULL
)
1023 tdep
->fpregset
= XMALLOC (struct regset
);
1024 tdep
->fpregset
->descr
= tdep
;
1025 tdep
->fpregset
->supply_regset
= amd64_supply_fpregset
;
1028 return tdep
->fpregset
;
1031 return i386_regset_from_core_section (gdbarch
, sect_name
, sect_size
);
1036 x86_64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
1038 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1040 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
1041 floating-point registers. */
1042 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
1044 /* AMD64 has an FPU and 16 SSE registers. */
1045 tdep
->st0_regnum
= X86_64_ST0_REGNUM
;
1046 tdep
->num_xmm_regs
= 16;
1048 /* This is what all the fuss is about. */
1049 set_gdbarch_long_bit (gdbarch
, 64);
1050 set_gdbarch_long_long_bit (gdbarch
, 64);
1051 set_gdbarch_ptr_bit (gdbarch
, 64);
1053 /* In contrast to the i386, on AMD64 a `long double' actually takes
1054 up 128 bits, even though it's still based on the i387 extended
1055 floating-point format which has only 80 significant bits. */
1056 set_gdbarch_long_double_bit (gdbarch
, 128);
1058 set_gdbarch_num_regs (gdbarch
, AMD64_NUM_REGS
);
1059 set_gdbarch_register_name (gdbarch
, amd64_register_name
);
1060 set_gdbarch_register_type (gdbarch
, amd64_register_type
);
1062 /* Register numbers of various important registers. */
1063 set_gdbarch_sp_regnum (gdbarch
, X86_64_RSP_REGNUM
); /* %rsp */
1064 set_gdbarch_pc_regnum (gdbarch
, X86_64_RIP_REGNUM
); /* %rip */
1065 set_gdbarch_ps_regnum (gdbarch
, X86_64_EFLAGS_REGNUM
); /* %eflags */
1066 set_gdbarch_fp0_regnum (gdbarch
, X86_64_ST0_REGNUM
); /* %st(0) */
1068 /* The "default" register numbering scheme for AMD64 is referred to
1069 as the "DWARF Register Number Mapping" in the System V psABI.
1070 The preferred debugging format for all known AMD64 targets is
1071 actually DWARF2, and GCC doesn't seem to support DWARF (that is
1072 DWARF-1), but we provide the same mapping just in case. This
1073 mapping is also used for stabs, which GCC does support. */
1074 set_gdbarch_stab_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
1075 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
1076 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
1078 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
1079 be in use on any of the supported AMD64 targets. */
1081 /* Call dummy code. */
1082 set_gdbarch_push_dummy_call (gdbarch
, amd64_push_dummy_call
);
1083 set_gdbarch_frame_align (gdbarch
, amd64_frame_align
);
1084 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
1086 set_gdbarch_convert_register_p (gdbarch
, amd64_convert_register_p
);
1087 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
1088 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
1090 set_gdbarch_return_value (gdbarch
, amd64_return_value
);
1091 /* Override, since this is handled by amd64_extract_return_value. */
1092 set_gdbarch_extract_struct_value_address (gdbarch
, NULL
);
1094 set_gdbarch_skip_prologue (gdbarch
, amd64_skip_prologue
);
1096 /* Avoid wiring in the MMX registers for now. */
1097 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
1098 tdep
->mm0_regnum
= -1;
1100 set_gdbarch_unwind_dummy_id (gdbarch
, amd64_unwind_dummy_id
);
1102 /* FIXME: kettenis/20021026: This is ELF-specific. Fine for now,
1103 since all supported AMD64 targets are ELF, but that might change
1105 set_gdbarch_in_solib_call_trampoline (gdbarch
, in_plt_section
);
1107 frame_unwind_append_sniffer (gdbarch
, amd64_sigtramp_frame_sniffer
);
1108 frame_unwind_append_sniffer (gdbarch
, amd64_frame_sniffer
);
1109 frame_base_set_default (gdbarch
, &amd64_frame_base
);
1111 /* If we have a register mapping, enable the generic core file support. */
1112 if (tdep
->gregset_reg_offset
)
1113 set_gdbarch_regset_from_core_section (gdbarch
,
1114 amd64_regset_from_core_section
);
1118 #define I387_ST0_REGNUM X86_64_ST0_REGNUM
1120 /* The 64-bit FXSAVE format differs from the 32-bit format in the
1121 sense that the instruction pointer and data pointer are simply
1122 64-bit offsets into the code segment and the data segment instead
1123 of a selector offset pair. The functions below store the upper 32
1124 bits of these pointers (instead of just the 16-bits of the segment
1127 /* Fill register REGNUM in REGCACHE with the appropriate
1128 floating-point or SSE register value from *FXSAVE. If REGNUM is
1129 -1, do this for all registers. This function masks off any of the
1130 reserved bits in *FXSAVE. */
1133 x86_64_supply_fxsave (struct regcache
*regcache
, int regnum
,
1136 i387_supply_fxsave (regcache
, regnum
, fxsave
);
1140 const char *regs
= fxsave
;
1142 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM
)
1143 regcache_raw_supply (regcache
, I387_FISEG_REGNUM
, regs
+ 12);
1144 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM
)
1145 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM
, regs
+ 20);
1149 /* Fill register REGNUM (if it is a floating-point or SSE register) in
1150 *FXSAVE with the value in GDB's register cache. If REGNUM is -1, do
1151 this for all registers. This function doesn't touch any of the
1152 reserved bits in *FXSAVE. */
1155 x86_64_fill_fxsave (char *fxsave
, int regnum
)
1157 i387_fill_fxsave (fxsave
, regnum
);
1159 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM
)
1160 regcache_collect (I387_FISEG_REGNUM
, fxsave
+ 12);
1161 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM
)
1162 regcache_collect (I387_FOSEG_REGNUM
, fxsave
+ 20);