1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003-2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "solib-svr4.h"
33 #include "reggroups.h"
36 #include "dummy-frame.h"
38 #include "dwarf2-frame.h"
39 #include "dwarf2loc.h"
40 #include "frame-base.h"
41 #include "frame-unwind.h"
43 #include "arch-utils.h"
51 #include "xtensa-isa.h"
52 #include "xtensa-tdep.h"
53 #include "xtensa-config.h"
57 static unsigned int xtensa_debug_level
= 0;
59 #define DEBUGWARN(args...) \
60 if (xtensa_debug_level > 0) \
61 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
63 #define DEBUGINFO(args...) \
64 if (xtensa_debug_level > 1) \
65 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
67 #define DEBUGTRACE(args...) \
68 if (xtensa_debug_level > 2) \
69 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
71 #define DEBUGVERB(args...) \
72 if (xtensa_debug_level > 3) \
73 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
76 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
77 #define SP_ALIGNMENT 16
80 /* On Windowed ABI, we use a6 through a11 for passing arguments
81 to a function called by GDB because CALL4 is used. */
82 #define ARGS_NUM_REGS 6
83 #define REGISTER_SIZE 4
86 /* Extract the call size from the return address or PS register. */
87 #define PS_CALLINC_SHIFT 16
88 #define PS_CALLINC_MASK 0x00030000
89 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
90 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
92 /* On TX, hardware can be configured without Exception Option.
93 There is no PS register in this case. Inside XT-GDB, let us treat
94 it as a virtual read-only register always holding the same value. */
97 /* ABI-independent macros. */
98 #define ARG_NOF(gdbarch) \
99 (gdbarch_tdep (gdbarch)->call_abi \
100 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
101 #define ARG_1ST(gdbarch) \
102 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
103 ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \
104 : (gdbarch_tdep (gdbarch)->a0_base + 6))
106 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
107 indicates that the instruction is an ENTRY instruction. */
109 #define XTENSA_IS_ENTRY(gdbarch, op1) \
110 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
111 ? ((op1) == 0x6c) : ((op1) == 0x36))
113 #define XTENSA_ENTRY_LENGTH 3
115 /* windowing_enabled() returns true, if windowing is enabled.
116 WOE must be set to 1; EXCM to 0.
117 Note: We assume that EXCM is always 0 for XEA1. */
119 #define PS_WOE (1<<18)
120 #define PS_EXC (1<<4)
122 /* Big enough to hold the size of the largest register in bytes. */
123 #define XTENSA_MAX_REGISTER_SIZE 64
126 windowing_enabled (struct gdbarch
*gdbarch
, unsigned int ps
)
128 /* If we know CALL0 ABI is set explicitly, say it is Call0. */
129 if (gdbarch_tdep (gdbarch
)->call_abi
== CallAbiCall0Only
)
132 return ((ps
& PS_EXC
) == 0 && (ps
& PS_WOE
) != 0);
135 /* Convert a live A-register number to the corresponding AR-register
138 arreg_number (struct gdbarch
*gdbarch
, int a_regnum
, ULONGEST wb
)
140 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
143 arreg
= a_regnum
- tdep
->a0_base
;
144 arreg
+= (wb
& ((tdep
->num_aregs
- 1) >> 2)) << WB_SHIFT
;
145 arreg
&= tdep
->num_aregs
- 1;
147 return arreg
+ tdep
->ar_base
;
150 /* Convert a live AR-register number to the corresponding A-register order
151 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
153 areg_number (struct gdbarch
*gdbarch
, int ar_regnum
, unsigned int wb
)
155 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
158 areg
= ar_regnum
- tdep
->ar_base
;
159 if (areg
< 0 || areg
>= tdep
->num_aregs
)
161 areg
= (areg
- wb
* 4) & (tdep
->num_aregs
- 1);
162 return (areg
> 15) ? -1 : areg
;
165 /* Read Xtensa register directly from the hardware. */
167 xtensa_read_register (int regnum
)
171 regcache_raw_read_unsigned (get_current_regcache (), regnum
, &value
);
172 return (unsigned long) value
;
175 /* Write Xtensa register directly to the hardware. */
177 xtensa_write_register (int regnum
, ULONGEST value
)
179 regcache_raw_write_unsigned (get_current_regcache (), regnum
, value
);
182 /* Return the window size of the previous call to the function from which we
185 This function is used to extract the return value after a called function
186 has returned to the caller. On Xtensa, the register that holds the return
187 value (from the perspective of the caller) depends on what call
188 instruction was used. For now, we are assuming that the call instruction
189 precedes the current address, so we simply analyze the call instruction.
190 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
191 method to call the inferior function. */
194 extract_call_winsize (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
196 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
201 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc
);
203 /* Read the previous instruction (should be a call[x]{4|8|12}. */
204 read_memory (pc
-3, buf
, 3);
205 insn
= extract_unsigned_integer (buf
, 3, byte_order
);
207 /* Decode call instruction:
209 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
210 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
212 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
213 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
215 if (byte_order
== BFD_ENDIAN_LITTLE
)
217 if (((insn
& 0xf) == 0x5) || ((insn
& 0xcf) == 0xc0))
218 winsize
= (insn
& 0x30) >> 2; /* 0, 4, 8, 12. */
222 if (((insn
>> 20) == 0x5) || (((insn
>> 16) & 0xf3) == 0x03))
223 winsize
= (insn
>> 16) & 0xc; /* 0, 4, 8, 12. */
229 /* REGISTER INFORMATION */
231 /* Find register by name. */
233 xtensa_find_register_by_name (struct gdbarch
*gdbarch
, const char *name
)
237 for (i
= 0; i
< gdbarch_num_regs (gdbarch
)
238 + gdbarch_num_pseudo_regs (gdbarch
);
241 if (strcasecmp (gdbarch_tdep (gdbarch
)->regmap
[i
].name
, name
) == 0)
247 /* Returns the name of a register. */
249 xtensa_register_name (struct gdbarch
*gdbarch
, int regnum
)
251 /* Return the name stored in the register map. */
252 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
)
253 + gdbarch_num_pseudo_regs (gdbarch
))
254 return gdbarch_tdep (gdbarch
)->regmap
[regnum
].name
;
256 internal_error (__FILE__
, __LINE__
, _("invalid register %d"), regnum
);
260 /* Return the type of a register. Create a new type, if necessary. */
263 xtensa_register_type (struct gdbarch
*gdbarch
, int regnum
)
265 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
267 /* Return signed integer for ARx and Ax registers. */
268 if ((regnum
>= tdep
->ar_base
269 && regnum
< tdep
->ar_base
+ tdep
->num_aregs
)
270 || (regnum
>= tdep
->a0_base
271 && regnum
< tdep
->a0_base
+ 16))
272 return builtin_type (gdbarch
)->builtin_int
;
274 if (regnum
== gdbarch_pc_regnum (gdbarch
)
275 || regnum
== tdep
->a0_base
+ 1)
276 return builtin_type (gdbarch
)->builtin_data_ptr
;
278 /* Return the stored type for all other registers. */
279 else if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
)
280 + gdbarch_num_pseudo_regs (gdbarch
))
282 xtensa_register_t
* reg
= &tdep
->regmap
[regnum
];
284 /* Set ctype for this register (only the first time). */
288 struct ctype_cache
*tp
;
289 int size
= reg
->byte_size
;
291 /* We always use the memory representation,
292 even if the register width is smaller. */
296 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint8
;
300 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint16
;
304 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint32
;
308 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint64
;
312 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint128
;
316 for (tp
= tdep
->type_entries
; tp
!= NULL
; tp
= tp
->next
)
317 if (tp
->size
== size
)
322 std::string name
= string_printf ("int%d", size
* 8);
324 tp
= XNEW (struct ctype_cache
);
325 tp
->next
= tdep
->type_entries
;
326 tdep
->type_entries
= tp
;
329 = arch_integer_type (gdbarch
, size
* 8, 1, name
.c_str ());
332 reg
->ctype
= tp
->virtual_type
;
338 internal_error (__FILE__
, __LINE__
, _("invalid register number %d"), regnum
);
343 /* Return the 'local' register number for stubs, dwarf2, etc.
344 The debugging information enumerates registers starting from 0 for A0
345 to n for An. So, we only have to add the base number for A0. */
348 xtensa_reg_to_regnum (struct gdbarch
*gdbarch
, int regnum
)
352 if (regnum
>= 0 && regnum
< 16)
353 return gdbarch_tdep (gdbarch
)->a0_base
+ regnum
;
356 i
< gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
358 if (regnum
== gdbarch_tdep (gdbarch
)->regmap
[i
].target_number
)
365 /* Write the bits of a masked register to the various registers.
366 Only the masked areas of these registers are modified; the other
367 fields are untouched. The size of masked registers is always less
368 than or equal to 32 bits. */
371 xtensa_register_write_masked (struct regcache
*regcache
,
372 xtensa_register_t
*reg
, const gdb_byte
*buffer
)
374 unsigned int value
[(XTENSA_MAX_REGISTER_SIZE
+ 3) / 4];
375 const xtensa_mask_t
*mask
= reg
->mask
;
377 int shift
= 0; /* Shift for next mask (mod 32). */
378 int start
, size
; /* Start bit and size of current mask. */
380 unsigned int *ptr
= value
;
381 unsigned int regval
, m
, mem
= 0;
383 int bytesize
= reg
->byte_size
;
384 int bitsize
= bytesize
* 8;
387 DEBUGTRACE ("xtensa_register_write_masked ()\n");
389 /* Copy the masked register to host byte-order. */
390 if (gdbarch_byte_order (regcache
->arch ()) == BFD_ENDIAN_BIG
)
391 for (i
= 0; i
< bytesize
; i
++)
394 mem
|= (buffer
[bytesize
- i
- 1] << 24);
399 for (i
= 0; i
< bytesize
; i
++)
402 mem
|= (buffer
[i
] << 24);
407 /* We might have to shift the final value:
408 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
409 bytesize & 3 == x -> shift (4-x) * 8. */
411 *ptr
= mem
>> (((0 - bytesize
) & 3) * 8);
415 /* Write the bits to the masked areas of the other registers. */
416 for (i
= 0; i
< mask
->count
; i
++)
418 start
= mask
->mask
[i
].bit_start
;
419 size
= mask
->mask
[i
].bit_size
;
420 regval
= mem
>> shift
;
422 if ((shift
+= size
) > bitsize
)
423 error (_("size of all masks is larger than the register"));
432 regval
|= mem
<< (size
- shift
);
435 /* Make sure we have a valid register. */
436 r
= mask
->mask
[i
].reg_num
;
437 if (r
>= 0 && size
> 0)
439 /* Don't overwrite the unmasked areas. */
441 regcache_cooked_read_unsigned (regcache
, r
, &old_val
);
442 m
= 0xffffffff >> (32 - size
) << start
;
444 regval
= (regval
& m
) | (old_val
& ~m
);
445 regcache_cooked_write_unsigned (regcache
, r
, regval
);
451 /* Read a tie state or mapped registers. Read the masked areas
452 of the registers and assemble them into a single value. */
454 static enum register_status
455 xtensa_register_read_masked (readable_regcache
*regcache
,
456 xtensa_register_t
*reg
, gdb_byte
*buffer
)
458 unsigned int value
[(XTENSA_MAX_REGISTER_SIZE
+ 3) / 4];
459 const xtensa_mask_t
*mask
= reg
->mask
;
464 unsigned int *ptr
= value
;
465 unsigned int regval
, mem
= 0;
467 int bytesize
= reg
->byte_size
;
468 int bitsize
= bytesize
* 8;
471 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
472 reg
->name
== 0 ? "" : reg
->name
);
474 /* Assemble the register from the masked areas of other registers. */
475 for (i
= 0; i
< mask
->count
; i
++)
477 int r
= mask
->mask
[i
].reg_num
;
480 enum register_status status
;
483 status
= regcache
->cooked_read (r
, &val
);
484 if (status
!= REG_VALID
)
486 regval
= (unsigned int) val
;
491 start
= mask
->mask
[i
].bit_start
;
492 size
= mask
->mask
[i
].bit_size
;
497 regval
&= (0xffffffff >> (32 - size
));
499 mem
|= regval
<< shift
;
501 if ((shift
+= size
) > bitsize
)
502 error (_("size of all masks is larger than the register"));
513 mem
= regval
>> (size
- shift
);
520 /* Copy value to target byte order. */
524 if (gdbarch_byte_order (regcache
->arch ()) == BFD_ENDIAN_BIG
)
525 for (i
= 0; i
< bytesize
; i
++)
529 buffer
[bytesize
- i
- 1] = mem
& 0xff;
533 for (i
= 0; i
< bytesize
; i
++)
537 buffer
[i
] = mem
& 0xff;
545 /* Read pseudo registers. */
547 static enum register_status
548 xtensa_pseudo_register_read (struct gdbarch
*gdbarch
,
549 readable_regcache
*regcache
,
553 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
554 regnum
, xtensa_register_name (gdbarch
, regnum
));
556 /* Read aliases a0..a15, if this is a Windowed ABI. */
557 if (gdbarch_tdep (gdbarch
)->isa_use_windowed_registers
558 && (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
)
559 && (regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15))
562 enum register_status status
;
564 status
= regcache
->raw_read (gdbarch_tdep (gdbarch
)->wb_regnum
,
566 if (status
!= REG_VALID
)
568 regnum
= arreg_number (gdbarch
, regnum
, value
);
571 /* We can always read non-pseudo registers. */
572 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
573 return regcache
->raw_read (regnum
, buffer
);
575 /* We have to find out how to deal with priveleged registers.
576 Let's treat them as pseudo-registers, but we cannot read/write them. */
578 else if (gdbarch_tdep (gdbarch
)->call_abi
== CallAbiCall0Only
579 || regnum
< gdbarch_tdep (gdbarch
)->a0_base
)
581 buffer
[0] = (gdb_byte
)0;
582 buffer
[1] = (gdb_byte
)0;
583 buffer
[2] = (gdb_byte
)0;
584 buffer
[3] = (gdb_byte
)0;
587 /* Pseudo registers. */
589 && regnum
< gdbarch_num_regs (gdbarch
)
590 + gdbarch_num_pseudo_regs (gdbarch
))
592 xtensa_register_t
*reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
593 xtensa_register_type_t type
= reg
->type
;
594 int flags
= gdbarch_tdep (gdbarch
)->target_flags
;
596 /* We cannot read Unknown or Unmapped registers. */
597 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
599 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
601 warning (_("cannot read register %s"),
602 xtensa_register_name (gdbarch
, regnum
));
607 /* Some targets cannot read TIE register files. */
608 else if (type
== xtRegisterTypeTieRegfile
)
610 /* Use 'fetch' to get register? */
611 if (flags
& xtTargetFlagsUseFetchStore
)
613 warning (_("cannot read register"));
617 /* On some targets (esp. simulators), we can always read the reg. */
618 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
620 warning (_("cannot read register"));
625 /* We can always read mapped registers. */
626 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
627 return xtensa_register_read_masked (regcache
, reg
, buffer
);
629 /* Assume that we can read the register. */
630 return regcache
->raw_read (regnum
, buffer
);
633 internal_error (__FILE__
, __LINE__
,
634 _("invalid register number %d"), regnum
);
638 /* Write pseudo registers. */
641 xtensa_pseudo_register_write (struct gdbarch
*gdbarch
,
642 struct regcache
*regcache
,
644 const gdb_byte
*buffer
)
646 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
647 regnum
, xtensa_register_name (gdbarch
, regnum
));
649 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
650 if (gdbarch_tdep (gdbarch
)->isa_use_windowed_registers
651 && (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
)
652 && (regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15))
655 regcache_raw_read_unsigned (regcache
,
656 gdbarch_tdep (gdbarch
)->wb_regnum
, &value
);
657 regnum
= arreg_number (gdbarch
, regnum
, value
);
660 /* We can always write 'core' registers.
661 Note: We might have converted Ax->ARy. */
662 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
663 regcache
->raw_write (regnum
, buffer
);
665 /* We have to find out how to deal with priveleged registers.
666 Let's treat them as pseudo-registers, but we cannot read/write them. */
668 else if (regnum
< gdbarch_tdep (gdbarch
)->a0_base
)
672 /* Pseudo registers. */
674 && regnum
< gdbarch_num_regs (gdbarch
)
675 + gdbarch_num_pseudo_regs (gdbarch
))
677 xtensa_register_t
*reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
678 xtensa_register_type_t type
= reg
->type
;
679 int flags
= gdbarch_tdep (gdbarch
)->target_flags
;
681 /* On most targets, we cannot write registers
682 of type "Unknown" or "Unmapped". */
683 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
685 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
687 warning (_("cannot write register %s"),
688 xtensa_register_name (gdbarch
, regnum
));
693 /* Some targets cannot read TIE register files. */
694 else if (type
== xtRegisterTypeTieRegfile
)
696 /* Use 'store' to get register? */
697 if (flags
& xtTargetFlagsUseFetchStore
)
699 warning (_("cannot write register"));
703 /* On some targets (esp. simulators), we can always write
705 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
707 warning (_("cannot write register"));
712 /* We can always write mapped registers. */
713 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
715 xtensa_register_write_masked (regcache
, reg
, buffer
);
719 /* Assume that we can write the register. */
720 regcache
->raw_write (regnum
, buffer
);
723 internal_error (__FILE__
, __LINE__
,
724 _("invalid register number %d"), regnum
);
727 static struct reggroup
*xtensa_ar_reggroup
;
728 static struct reggroup
*xtensa_user_reggroup
;
729 static struct reggroup
*xtensa_vectra_reggroup
;
730 static struct reggroup
*xtensa_cp
[XTENSA_MAX_COPROCESSOR
];
733 xtensa_init_reggroups (void)
737 xtensa_ar_reggroup
= reggroup_new ("ar", USER_REGGROUP
);
738 xtensa_user_reggroup
= reggroup_new ("user", USER_REGGROUP
);
739 xtensa_vectra_reggroup
= reggroup_new ("vectra", USER_REGGROUP
);
741 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
742 xtensa_cp
[i
] = reggroup_new (xstrprintf ("cp%d", i
), USER_REGGROUP
);
746 xtensa_add_reggroups (struct gdbarch
*gdbarch
)
750 /* Predefined groups. */
751 reggroup_add (gdbarch
, all_reggroup
);
752 reggroup_add (gdbarch
, save_reggroup
);
753 reggroup_add (gdbarch
, restore_reggroup
);
754 reggroup_add (gdbarch
, system_reggroup
);
755 reggroup_add (gdbarch
, vector_reggroup
);
756 reggroup_add (gdbarch
, general_reggroup
);
757 reggroup_add (gdbarch
, float_reggroup
);
759 /* Xtensa-specific groups. */
760 reggroup_add (gdbarch
, xtensa_ar_reggroup
);
761 reggroup_add (gdbarch
, xtensa_user_reggroup
);
762 reggroup_add (gdbarch
, xtensa_vectra_reggroup
);
764 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
765 reggroup_add (gdbarch
, xtensa_cp
[i
]);
769 xtensa_coprocessor_register_group (struct reggroup
*group
)
773 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
774 if (group
== xtensa_cp
[i
])
780 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
781 | XTENSA_REGISTER_FLAGS_WRITABLE \
782 | XTENSA_REGISTER_FLAGS_VOLATILE)
784 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
785 | XTENSA_REGISTER_FLAGS_WRITABLE)
788 xtensa_register_reggroup_p (struct gdbarch
*gdbarch
,
790 struct reggroup
*group
)
792 xtensa_register_t
* reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
793 xtensa_register_type_t type
= reg
->type
;
794 xtensa_register_group_t rg
= reg
->group
;
797 if (group
== save_reggroup
)
798 /* Every single register should be included into the list of registers
799 to be watched for changes while using -data-list-changed-registers. */
802 /* First, skip registers that are not visible to this target
803 (unknown and unmapped registers when not using ISS). */
805 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
807 if (group
== all_reggroup
)
809 if (group
== xtensa_ar_reggroup
)
810 return rg
& xtRegisterGroupAddrReg
;
811 if (group
== xtensa_user_reggroup
)
812 return rg
& xtRegisterGroupUser
;
813 if (group
== float_reggroup
)
814 return rg
& xtRegisterGroupFloat
;
815 if (group
== general_reggroup
)
816 return rg
& xtRegisterGroupGeneral
;
817 if (group
== system_reggroup
)
818 return rg
& xtRegisterGroupState
;
819 if (group
== vector_reggroup
|| group
== xtensa_vectra_reggroup
)
820 return rg
& xtRegisterGroupVectra
;
821 if (group
== restore_reggroup
)
822 return (regnum
< gdbarch_num_regs (gdbarch
)
823 && (reg
->flags
& SAVE_REST_FLAGS
) == SAVE_REST_VALID
);
824 cp_number
= xtensa_coprocessor_register_group (group
);
826 return rg
& (xtRegisterGroupCP0
<< cp_number
);
832 /* Supply register REGNUM from the buffer specified by GREGS and LEN
833 in the general-purpose register set REGSET to register cache
834 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
837 xtensa_supply_gregset (const struct regset
*regset
,
843 const xtensa_elf_gregset_t
*regs
= (const xtensa_elf_gregset_t
*) gregs
;
844 struct gdbarch
*gdbarch
= rc
->arch ();
847 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum
);
849 if (regnum
== gdbarch_pc_regnum (gdbarch
) || regnum
== -1)
850 rc
->raw_supply (gdbarch_pc_regnum (gdbarch
), (char *) ®s
->pc
);
851 if (regnum
== gdbarch_ps_regnum (gdbarch
) || regnum
== -1)
852 rc
->raw_supply (gdbarch_ps_regnum (gdbarch
), (char *) ®s
->ps
);
853 if (regnum
== gdbarch_tdep (gdbarch
)->wb_regnum
|| regnum
== -1)
854 rc
->raw_supply (gdbarch_tdep (gdbarch
)->wb_regnum
,
855 (char *) ®s
->windowbase
);
856 if (regnum
== gdbarch_tdep (gdbarch
)->ws_regnum
|| regnum
== -1)
857 rc
->raw_supply (gdbarch_tdep (gdbarch
)->ws_regnum
,
858 (char *) ®s
->windowstart
);
859 if (regnum
== gdbarch_tdep (gdbarch
)->lbeg_regnum
|| regnum
== -1)
860 rc
->raw_supply (gdbarch_tdep (gdbarch
)->lbeg_regnum
,
861 (char *) ®s
->lbeg
);
862 if (regnum
== gdbarch_tdep (gdbarch
)->lend_regnum
|| regnum
== -1)
863 rc
->raw_supply (gdbarch_tdep (gdbarch
)->lend_regnum
,
864 (char *) ®s
->lend
);
865 if (regnum
== gdbarch_tdep (gdbarch
)->lcount_regnum
|| regnum
== -1)
866 rc
->raw_supply (gdbarch_tdep (gdbarch
)->lcount_regnum
,
867 (char *) ®s
->lcount
);
868 if (regnum
== gdbarch_tdep (gdbarch
)->sar_regnum
|| regnum
== -1)
869 rc
->raw_supply (gdbarch_tdep (gdbarch
)->sar_regnum
,
870 (char *) ®s
->sar
);
871 if (regnum
>=gdbarch_tdep (gdbarch
)->ar_base
872 && regnum
< gdbarch_tdep (gdbarch
)->ar_base
873 + gdbarch_tdep (gdbarch
)->num_aregs
)
875 (regnum
, (char *) ®s
->ar
[regnum
- gdbarch_tdep (gdbarch
)->ar_base
]);
876 else if (regnum
== -1)
878 for (i
= 0; i
< gdbarch_tdep (gdbarch
)->num_aregs
; ++i
)
879 rc
->raw_supply (gdbarch_tdep (gdbarch
)->ar_base
+ i
,
880 (char *) ®s
->ar
[i
]);
885 /* Xtensa register set. */
891 xtensa_supply_gregset
895 /* Iterate over supported core file register note sections. */
898 xtensa_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
899 iterate_over_regset_sections_cb
*cb
,
901 const struct regcache
*regcache
)
903 DEBUGTRACE ("xtensa_iterate_over_regset_sections\n");
905 cb (".reg", sizeof (xtensa_elf_gregset_t
), sizeof (xtensa_elf_gregset_t
),
906 &xtensa_gregset
, NULL
, cb_data
);
910 /* Handling frames. */
912 /* Number of registers to save in case of Windowed ABI. */
913 #define XTENSA_NUM_SAVED_AREGS 12
915 /* Frame cache part for Windowed ABI. */
916 typedef struct xtensa_windowed_frame_cache
918 int wb
; /* WINDOWBASE of the previous frame. */
919 int callsize
; /* Call size of this frame. */
920 int ws
; /* WINDOWSTART of the previous frame. It keeps track of
921 life windows only. If there is no bit set for the
922 window, that means it had been already spilled
923 because of window overflow. */
925 /* Addresses of spilled A-registers.
926 AREGS[i] == -1, if corresponding AR is alive. */
927 CORE_ADDR aregs
[XTENSA_NUM_SAVED_AREGS
];
928 } xtensa_windowed_frame_cache_t
;
930 /* Call0 ABI Definitions. */
932 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue
934 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
935 #define C0_SP 1 /* Register used as SP. */
936 #define C0_FP 15 /* Register used as FP. */
937 #define C0_RA 0 /* Register used as return address. */
938 #define C0_ARGS 2 /* Register used as first arg/retval. */
939 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
941 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
942 A-register where the current content of the reg came from (in terms
943 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
944 mean that the orignal content of the register was saved to the stack.
945 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
946 know where SP will end up until the entire prologue has been analyzed. */
948 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
949 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
950 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
952 extern xtensa_isa xtensa_default_isa
;
954 typedef struct xtensa_c0reg
956 int fr_reg
; /* original register from which register content
957 is derived, or C0_CONST, or C0_INEXP. */
958 int fr_ofs
; /* constant offset from reg, or immediate value. */
959 int to_stk
; /* offset from original SP to register (4-byte aligned),
960 or C0_NOSTK if register has not been saved. */
963 /* Frame cache part for Call0 ABI. */
964 typedef struct xtensa_call0_frame_cache
966 int c0_frmsz
; /* Stack frame size. */
967 int c0_hasfp
; /* Current frame uses frame pointer. */
968 int fp_regnum
; /* A-register used as FP. */
969 int c0_fp
; /* Actual value of frame pointer. */
970 int c0_fpalign
; /* Dinamic adjustment for the stack
971 pointer. It's an AND mask. Zero,
972 if alignment was not adjusted. */
973 int c0_old_sp
; /* In case of dynamic adjustment, it is
974 a register holding unaligned sp.
975 C0_INEXP, when undefined. */
976 int c0_sp_ofs
; /* If "c0_old_sp" was spilled it's a
977 stack offset. C0_NOSTK otherwise. */
979 xtensa_c0reg_t c0_rt
[C0_NREGS
]; /* Register tracking information. */
980 } xtensa_call0_frame_cache_t
;
982 typedef struct xtensa_frame_cache
984 CORE_ADDR base
; /* Stack pointer of this frame. */
985 CORE_ADDR pc
; /* PC of this frame at the function entry point. */
986 CORE_ADDR ra
; /* The raw return address of this frame. */
987 CORE_ADDR ps
; /* The PS register of the previous (older) frame. */
988 CORE_ADDR prev_sp
; /* Stack Pointer of the previous (older) frame. */
989 int call0
; /* It's a call0 framework (else windowed). */
992 xtensa_windowed_frame_cache_t wd
; /* call0 == false. */
993 xtensa_call0_frame_cache_t c0
; /* call0 == true. */
995 } xtensa_frame_cache_t
;
998 static struct xtensa_frame_cache
*
999 xtensa_alloc_frame_cache (int windowed
)
1001 xtensa_frame_cache_t
*cache
;
1004 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
1006 cache
= FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t
);
1013 cache
->call0
= !windowed
;
1016 cache
->c0
.c0_frmsz
= -1;
1017 cache
->c0
.c0_hasfp
= 0;
1018 cache
->c0
.fp_regnum
= -1;
1019 cache
->c0
.c0_fp
= -1;
1020 cache
->c0
.c0_fpalign
= 0;
1021 cache
->c0
.c0_old_sp
= C0_INEXP
;
1022 cache
->c0
.c0_sp_ofs
= C0_NOSTK
;
1024 for (i
= 0; i
< C0_NREGS
; i
++)
1026 cache
->c0
.c0_rt
[i
].fr_reg
= i
;
1027 cache
->c0
.c0_rt
[i
].fr_ofs
= 0;
1028 cache
->c0
.c0_rt
[i
].to_stk
= C0_NOSTK
;
1035 cache
->wd
.callsize
= -1;
1037 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
1038 cache
->wd
.aregs
[i
] = -1;
1045 xtensa_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
1047 return address
& ~15;
1052 xtensa_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1057 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1058 host_address_to_string (next_frame
));
1060 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1061 pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1063 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc
);
1069 static struct frame_id
1070 xtensa_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1074 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1076 pc
= get_frame_pc (this_frame
);
1077 fp
= get_frame_register_unsigned
1078 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1080 /* Make dummy frame ID unique by adding a constant. */
1081 return frame_id_build (fp
+ SP_ALIGNMENT
, pc
);
1084 /* Returns true, if instruction to execute next is unique to Xtensa Window
1085 Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */
1088 xtensa_window_interrupt_insn (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1090 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1091 unsigned int insn
= read_memory_integer (pc
, 4, byte_order
);
1094 if (byte_order
== BFD_ENDIAN_BIG
)
1096 /* Check, if this is L32E or S32E. */
1097 code
= insn
& 0xf000ff00;
1098 if ((code
== 0x00009000) || (code
== 0x00009400))
1100 /* Check, if this is RFWU or RFWO. */
1101 code
= insn
& 0xffffff00;
1102 return ((code
== 0x00430000) || (code
== 0x00530000));
1106 /* Check, if this is L32E or S32E. */
1107 code
= insn
& 0x00ff000f;
1108 if ((code
== 0x090000) || (code
== 0x490000))
1110 /* Check, if this is RFWU or RFWO. */
1111 code
= insn
& 0x00ffffff;
1112 return ((code
== 0x00003400) || (code
== 0x00003500));
1116 /* Returns the best guess about which register is a frame pointer
1117 for the function containing CURRENT_PC. */
1119 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1120 #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */
1123 xtensa_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR current_pc
)
1125 #define RETURN_FP goto done
1127 unsigned int fp_regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ 1;
1128 CORE_ADDR start_addr
;
1130 xtensa_insnbuf ins
, slot
;
1131 gdb_byte ibuf
[XTENSA_ISA_BSZ
];
1132 CORE_ADDR ia
, bt
, ba
;
1134 int ilen
, islots
, is
;
1136 const char *opcname
;
1138 find_pc_partial_function (current_pc
, NULL
, &start_addr
, NULL
);
1139 if (start_addr
== 0)
1142 isa
= xtensa_default_isa
;
1143 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
1144 ins
= xtensa_insnbuf_alloc (isa
);
1145 slot
= xtensa_insnbuf_alloc (isa
);
1148 for (ia
= start_addr
, bt
= ia
; ia
< current_pc
; ia
+= ilen
)
1150 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
1153 bt
= (ba
+ XTENSA_ISA_BSZ
) < current_pc
1154 ? ba
+ XTENSA_ISA_BSZ
: current_pc
;
1155 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0)
1159 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
1160 ifmt
= xtensa_format_decode (isa
, ins
);
1161 if (ifmt
== XTENSA_UNDEFINED
)
1163 ilen
= xtensa_format_length (isa
, ifmt
);
1164 if (ilen
== XTENSA_UNDEFINED
)
1166 islots
= xtensa_format_num_slots (isa
, ifmt
);
1167 if (islots
== XTENSA_UNDEFINED
)
1170 for (is
= 0; is
< islots
; ++is
)
1172 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
1175 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
1176 if (opc
== XTENSA_UNDEFINED
)
1179 opcname
= xtensa_opcode_name (isa
, opc
);
1181 if (strcasecmp (opcname
, "mov.n") == 0
1182 || strcasecmp (opcname
, "or") == 0)
1184 unsigned int register_operand
;
1186 /* Possible candidate for setting frame pointer
1187 from A1. This is what we are looking for. */
1189 if (xtensa_operand_get_field (isa
, opc
, 1, ifmt
,
1190 is
, slot
, ®ister_operand
) != 0)
1192 if (xtensa_operand_decode (isa
, opc
, 1, ®ister_operand
) != 0)
1194 if (register_operand
== 1) /* Mov{.n} FP A1. */
1196 if (xtensa_operand_get_field (isa
, opc
, 0, ifmt
, is
, slot
,
1197 ®ister_operand
) != 0)
1199 if (xtensa_operand_decode (isa
, opc
, 0,
1200 ®ister_operand
) != 0)
1204 = gdbarch_tdep (gdbarch
)->a0_base
+ register_operand
;
1210 /* We have problems decoding the memory. */
1212 || strcasecmp (opcname
, "ill") == 0
1213 || strcasecmp (opcname
, "ill.n") == 0
1214 /* Hit planted breakpoint. */
1215 || strcasecmp (opcname
, "break") == 0
1216 || strcasecmp (opcname
, "break.n") == 0
1217 /* Flow control instructions finish prologue. */
1218 || xtensa_opcode_is_branch (isa
, opc
) > 0
1219 || xtensa_opcode_is_jump (isa
, opc
) > 0
1220 || xtensa_opcode_is_loop (isa
, opc
) > 0
1221 || xtensa_opcode_is_call (isa
, opc
) > 0
1222 || strcasecmp (opcname
, "simcall") == 0
1223 || strcasecmp (opcname
, "syscall") == 0)
1224 /* Can not continue analysis. */
1229 xtensa_insnbuf_free(isa
, slot
);
1230 xtensa_insnbuf_free(isa
, ins
);
1234 /* The key values to identify the frame using "cache" are
1236 cache->base = SP (or best guess about FP) of this frame;
1237 cache->pc = entry-PC (entry point of the frame function);
1238 cache->prev_sp = SP of the previous frame. */
1241 call0_frame_cache (struct frame_info
*this_frame
,
1242 xtensa_frame_cache_t
*cache
, CORE_ADDR pc
);
1245 xtensa_window_interrupt_frame_cache (struct frame_info
*this_frame
,
1246 xtensa_frame_cache_t
*cache
,
1249 static struct xtensa_frame_cache
*
1250 xtensa_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1252 xtensa_frame_cache_t
*cache
;
1253 CORE_ADDR ra
, wb
, ws
, pc
, sp
, ps
;
1254 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1255 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1256 unsigned int fp_regnum
;
1257 int windowed
, ps_regnum
;
1260 return (struct xtensa_frame_cache
*) *this_cache
;
1262 pc
= get_frame_register_unsigned (this_frame
, gdbarch_pc_regnum (gdbarch
));
1263 ps_regnum
= gdbarch_ps_regnum (gdbarch
);
1264 ps
= (ps_regnum
>= 0
1265 ? get_frame_register_unsigned (this_frame
, ps_regnum
) : TX_PS
);
1267 windowed
= windowing_enabled (gdbarch
, ps
);
1269 /* Get pristine xtensa-frame. */
1270 cache
= xtensa_alloc_frame_cache (windowed
);
1271 *this_cache
= cache
;
1277 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1278 wb
= get_frame_register_unsigned (this_frame
,
1279 gdbarch_tdep (gdbarch
)->wb_regnum
);
1280 ws
= get_frame_register_unsigned (this_frame
,
1281 gdbarch_tdep (gdbarch
)->ws_regnum
);
1283 if (safe_read_memory_integer (pc
, 1, byte_order
, &op1
)
1284 && XTENSA_IS_ENTRY (gdbarch
, op1
))
1286 int callinc
= CALLINC (ps
);
1287 ra
= get_frame_register_unsigned
1288 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ callinc
* 4);
1290 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1291 cache
->wd
.callsize
= 0;
1294 cache
->prev_sp
= get_frame_register_unsigned
1295 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1297 /* This only can be the outermost frame since we are
1298 just about to execute ENTRY. SP hasn't been set yet.
1299 We can assume any frame size, because it does not
1300 matter, and, let's fake frame base in cache. */
1301 cache
->base
= cache
->prev_sp
- 16;
1304 cache
->ra
= (cache
->pc
& 0xc0000000) | (ra
& 0x3fffffff);
1305 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1306 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1312 fp_regnum
= xtensa_scan_prologue (gdbarch
, pc
);
1313 ra
= get_frame_register_unsigned (this_frame
,
1314 gdbarch_tdep (gdbarch
)->a0_base
);
1315 cache
->wd
.callsize
= WINSIZE (ra
);
1316 cache
->wd
.wb
= (wb
- cache
->wd
.callsize
/ 4)
1317 & (gdbarch_tdep (gdbarch
)->num_aregs
/ 4 - 1);
1318 cache
->wd
.ws
= ws
& ~(1 << wb
);
1320 cache
->pc
= get_frame_func (this_frame
);
1321 cache
->ra
= (pc
& 0xc0000000) | (ra
& 0x3fffffff);
1322 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1323 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1326 if (cache
->wd
.ws
== 0)
1331 sp
= get_frame_register_unsigned
1332 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1) - 16;
1334 for (i
= 0; i
< 4; i
++, sp
+= 4)
1336 cache
->wd
.aregs
[i
] = sp
;
1339 if (cache
->wd
.callsize
> 4)
1341 /* Set A4...A7/A11. */
1342 /* Get the SP of the frame previous to the previous one.
1343 To achieve this, we have to dereference SP twice. */
1344 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4, byte_order
);
1345 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4, byte_order
);
1346 sp
-= cache
->wd
.callsize
* 4;
1348 for ( i
= 4; i
< cache
->wd
.callsize
; i
++, sp
+= 4)
1350 cache
->wd
.aregs
[i
] = sp
;
1355 if ((cache
->prev_sp
== 0) && ( ra
!= 0 ))
1356 /* If RA is equal to 0 this frame is an outermost frame. Leave
1357 cache->prev_sp unchanged marking the boundary of the frame stack. */
1359 if ((cache
->wd
.ws
& (1 << cache
->wd
.wb
)) == 0)
1361 /* Register window overflow already happened.
1362 We can read caller's SP from the proper spill loction. */
1363 sp
= get_frame_register_unsigned
1364 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1365 cache
->prev_sp
= read_memory_integer (sp
- 12, 4, byte_order
);
1369 /* Read caller's frame SP directly from the previous window. */
1370 int regnum
= arreg_number
1371 (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ 1,
1374 cache
->prev_sp
= xtensa_read_register (regnum
);
1378 else if (xtensa_window_interrupt_insn (gdbarch
, pc
))
1380 /* Execution stopped inside Xtensa Window Interrupt Handler. */
1382 xtensa_window_interrupt_frame_cache (this_frame
, cache
, pc
);
1383 /* Everything was set already, including cache->base. */
1386 else /* Call0 framework. */
1388 call0_frame_cache (this_frame
, cache
, pc
);
1389 fp_regnum
= cache
->c0
.fp_regnum
;
1392 cache
->base
= get_frame_register_unsigned (this_frame
, fp_regnum
);
1397 static int xtensa_session_once_reported
= 1;
1399 /* Report a problem with prologue analysis while doing backtracing.
1400 But, do it only once to avoid annoyng repeated messages. */
1405 if (xtensa_session_once_reported
== 0)
1407 \nUnrecognised function prologue. Stack trace cannot be resolved. \
1408 This message will not be repeated in this session.\n"));
1410 xtensa_session_once_reported
= 1;
1415 xtensa_frame_this_id (struct frame_info
*this_frame
,
1417 struct frame_id
*this_id
)
1419 struct xtensa_frame_cache
*cache
=
1420 xtensa_frame_cache (this_frame
, this_cache
);
1422 if (cache
->prev_sp
== 0)
1425 (*this_id
) = frame_id_build (cache
->prev_sp
, cache
->pc
);
1428 static struct value
*
1429 xtensa_frame_prev_register (struct frame_info
*this_frame
,
1433 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1434 struct xtensa_frame_cache
*cache
;
1435 ULONGEST saved_reg
= 0;
1438 if (*this_cache
== NULL
)
1439 *this_cache
= xtensa_frame_cache (this_frame
, this_cache
);
1440 cache
= (struct xtensa_frame_cache
*) *this_cache
;
1442 if (regnum
==gdbarch_pc_regnum (gdbarch
))
1443 saved_reg
= cache
->ra
;
1444 else if (regnum
== gdbarch_tdep (gdbarch
)->a0_base
+ 1)
1445 saved_reg
= cache
->prev_sp
;
1446 else if (!cache
->call0
)
1448 if (regnum
== gdbarch_tdep (gdbarch
)->ws_regnum
)
1449 saved_reg
= cache
->wd
.ws
;
1450 else if (regnum
== gdbarch_tdep (gdbarch
)->wb_regnum
)
1451 saved_reg
= cache
->wd
.wb
;
1452 else if (regnum
== gdbarch_ps_regnum (gdbarch
))
1453 saved_reg
= cache
->ps
;
1461 return frame_unwind_got_constant (this_frame
, regnum
, saved_reg
);
1463 if (!cache
->call0
) /* Windowed ABI. */
1465 /* Convert A-register numbers to AR-register numbers,
1466 if we deal with A-register. */
1467 if (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
1468 && regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15)
1469 regnum
= arreg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1471 /* Check, if we deal with AR-register saved on stack. */
1472 if (regnum
>= gdbarch_tdep (gdbarch
)->ar_base
1473 && regnum
<= (gdbarch_tdep (gdbarch
)->ar_base
1474 + gdbarch_tdep (gdbarch
)->num_aregs
))
1476 int areg
= areg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1479 && areg
< XTENSA_NUM_SAVED_AREGS
1480 && cache
->wd
.aregs
[areg
] != -1)
1481 return frame_unwind_got_memory (this_frame
, regnum
,
1482 cache
->wd
.aregs
[areg
]);
1485 else /* Call0 ABI. */
1487 int reg
= (regnum
>= gdbarch_tdep (gdbarch
)->ar_base
1488 && regnum
<= (gdbarch_tdep (gdbarch
)->ar_base
1490 ? regnum
- gdbarch_tdep (gdbarch
)->ar_base
: regnum
;
1497 /* If register was saved in the prologue, retrieve it. */
1498 stkofs
= cache
->c0
.c0_rt
[reg
].to_stk
;
1499 if (stkofs
!= C0_NOSTK
)
1501 /* Determine SP on entry based on FP. */
1502 spe
= cache
->c0
.c0_fp
1503 - cache
->c0
.c0_rt
[cache
->c0
.fp_regnum
].fr_ofs
;
1505 return frame_unwind_got_memory (this_frame
, regnum
,
1511 /* All other registers have been either saved to
1512 the stack or are still alive in the processor. */
1514 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1518 static const struct frame_unwind
1522 default_frame_unwind_stop_reason
,
1523 xtensa_frame_this_id
,
1524 xtensa_frame_prev_register
,
1526 default_frame_sniffer
1530 xtensa_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1532 struct xtensa_frame_cache
*cache
=
1533 xtensa_frame_cache (this_frame
, this_cache
);
1538 static const struct frame_base
1542 xtensa_frame_base_address
,
1543 xtensa_frame_base_address
,
1544 xtensa_frame_base_address
1549 xtensa_extract_return_value (struct type
*type
,
1550 struct regcache
*regcache
,
1553 struct gdbarch
*gdbarch
= regcache
->arch ();
1554 bfd_byte
*valbuf
= (bfd_byte
*) dst
;
1555 int len
= TYPE_LENGTH (type
);
1560 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1562 gdb_assert(len
> 0);
1564 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1566 /* First, we have to find the caller window in the register file. */
1567 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1568 callsize
= extract_call_winsize (gdbarch
, pc
);
1570 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1571 if (len
> (callsize
> 8 ? 8 : 16))
1572 internal_error (__FILE__
, __LINE__
,
1573 _("cannot extract return value of %d bytes long"),
1576 /* Get the register offset of the return
1577 register (A2) in the caller window. */
1578 regcache_raw_read_unsigned
1579 (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, &wb
);
1580 areg
= arreg_number (gdbarch
,
1581 gdbarch_tdep (gdbarch
)->a0_base
+ 2 + callsize
, wb
);
1585 /* No windowing hardware - Call0 ABI. */
1586 areg
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_ARGS
;
1589 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg
, len
);
1591 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1594 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1597 regcache
->raw_read_part (areg
, offset
, len
, valbuf
);
1599 regcache
->raw_read (areg
, valbuf
);
1605 xtensa_store_return_value (struct type
*type
,
1606 struct regcache
*regcache
,
1609 struct gdbarch
*gdbarch
= regcache
->arch ();
1610 const bfd_byte
*valbuf
= (const bfd_byte
*) dst
;
1614 int len
= TYPE_LENGTH (type
);
1617 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1619 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1621 regcache_raw_read_unsigned
1622 (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, &wb
);
1623 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1624 callsize
= extract_call_winsize (gdbarch
, pc
);
1626 if (len
> (callsize
> 8 ? 8 : 16))
1627 internal_error (__FILE__
, __LINE__
,
1628 _("unimplemented for this length: %d"),
1629 TYPE_LENGTH (type
));
1630 areg
= arreg_number (gdbarch
,
1631 gdbarch_tdep (gdbarch
)->a0_base
+ 2 + callsize
, wb
);
1633 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1634 callsize
, (int) wb
);
1638 areg
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_ARGS
;
1641 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1644 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1647 regcache
->raw_write_part (areg
, offset
, len
, valbuf
);
1649 regcache
->raw_write (areg
, valbuf
);
1654 static enum return_value_convention
1655 xtensa_return_value (struct gdbarch
*gdbarch
,
1656 struct value
*function
,
1657 struct type
*valtype
,
1658 struct regcache
*regcache
,
1660 const gdb_byte
*writebuf
)
1662 /* Structures up to 16 bytes are returned in registers. */
1664 int struct_return
= ((TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
1665 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
1666 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
1667 && TYPE_LENGTH (valtype
) > 16);
1670 return RETURN_VALUE_STRUCT_CONVENTION
;
1672 DEBUGTRACE ("xtensa_return_value(...)\n");
1674 if (writebuf
!= NULL
)
1676 xtensa_store_return_value (valtype
, regcache
, writebuf
);
1679 if (readbuf
!= NULL
)
1681 gdb_assert (!struct_return
);
1682 xtensa_extract_return_value (valtype
, regcache
, readbuf
);
1684 return RETURN_VALUE_REGISTER_CONVENTION
;
1691 xtensa_push_dummy_call (struct gdbarch
*gdbarch
,
1692 struct value
*function
,
1693 struct regcache
*regcache
,
1696 struct value
**args
,
1699 CORE_ADDR struct_addr
)
1701 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1702 int size
, onstack_size
;
1703 gdb_byte
*buf
= (gdb_byte
*) alloca (16);
1705 struct argument_info
1707 const bfd_byte
*contents
;
1709 int onstack
; /* onstack == 0 => in reg */
1710 int align
; /* alignment */
1713 int offset
; /* stack offset if on stack. */
1714 int regno
; /* regno if in register. */
1718 struct argument_info
*arg_info
=
1719 (struct argument_info
*) alloca (nargs
* sizeof (struct argument_info
));
1723 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1725 if (xtensa_debug_level
> 3)
1727 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs
);
1728 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1729 "struct_addr=0x%x\n",
1730 (int) sp
, (int) struct_return
, (int) struct_addr
);
1732 for (int i
= 0; i
< nargs
; i
++)
1734 struct value
*arg
= args
[i
];
1735 struct type
*arg_type
= check_typedef (value_type (arg
));
1736 fprintf_unfiltered (gdb_stdlog
, "%2d: %s %3d ", i
,
1737 host_address_to_string (arg
),
1738 TYPE_LENGTH (arg_type
));
1739 switch (TYPE_CODE (arg_type
))
1742 fprintf_unfiltered (gdb_stdlog
, "int");
1744 case TYPE_CODE_STRUCT
:
1745 fprintf_unfiltered (gdb_stdlog
, "struct");
1748 fprintf_unfiltered (gdb_stdlog
, "%3d", TYPE_CODE (arg_type
));
1751 fprintf_unfiltered (gdb_stdlog
, " %s\n",
1752 host_address_to_string (value_contents (arg
)));
1756 /* First loop: collect information.
1757 Cast into type_long. (This shouldn't happen often for C because
1758 GDB already does this earlier.) It's possible that GDB could
1759 do it all the time but it's harmless to leave this code here. */
1765 size
= REGISTER_SIZE
;
1767 for (int i
= 0; i
< nargs
; i
++)
1769 struct argument_info
*info
= &arg_info
[i
];
1770 struct value
*arg
= args
[i
];
1771 struct type
*arg_type
= check_typedef (value_type (arg
));
1773 switch (TYPE_CODE (arg_type
))
1776 case TYPE_CODE_BOOL
:
1777 case TYPE_CODE_CHAR
:
1778 case TYPE_CODE_RANGE
:
1779 case TYPE_CODE_ENUM
:
1781 /* Cast argument to long if necessary as the mask does it too. */
1782 if (TYPE_LENGTH (arg_type
)
1783 < TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
))
1785 arg_type
= builtin_type (gdbarch
)->builtin_long
;
1786 arg
= value_cast (arg_type
, arg
);
1788 /* Aligment is equal to the type length for the basic types. */
1789 info
->align
= TYPE_LENGTH (arg_type
);
1794 /* Align doubles correctly. */
1795 if (TYPE_LENGTH (arg_type
)
1796 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
))
1797 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
);
1799 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
);
1802 case TYPE_CODE_STRUCT
:
1804 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
);
1807 info
->length
= TYPE_LENGTH (arg_type
);
1808 info
->contents
= value_contents (arg
);
1810 /* Align size and onstack_size. */
1811 size
= (size
+ info
->align
- 1) & ~(info
->align
- 1);
1812 onstack_size
= (onstack_size
+ info
->align
- 1) & ~(info
->align
- 1);
1814 if (size
+ info
->length
> REGISTER_SIZE
* ARG_NOF (gdbarch
))
1817 info
->u
.offset
= onstack_size
;
1818 onstack_size
+= info
->length
;
1823 info
->u
.regno
= ARG_1ST (gdbarch
) + size
/ REGISTER_SIZE
;
1825 size
+= info
->length
;
1828 /* Adjust the stack pointer and align it. */
1829 sp
= align_down (sp
- onstack_size
, SP_ALIGNMENT
);
1831 /* Simulate MOVSP, if Windowed ABI. */
1832 if ((gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1835 read_memory (osp
- 16, buf
, 16);
1836 write_memory (sp
- 16, buf
, 16);
1839 /* Second Loop: Load arguments. */
1843 store_unsigned_integer (buf
, REGISTER_SIZE
, byte_order
, struct_addr
);
1844 regcache
->cooked_write (ARG_1ST (gdbarch
), buf
);
1847 for (int i
= 0; i
< nargs
; i
++)
1849 struct argument_info
*info
= &arg_info
[i
];
1853 int n
= info
->length
;
1854 CORE_ADDR offset
= sp
+ info
->u
.offset
;
1856 /* Odd-sized structs are aligned to the lower side of a memory
1857 word in big-endian mode and require a shift. This only
1858 applies for structures smaller than one word. */
1860 if (n
< REGISTER_SIZE
1861 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1862 offset
+= (REGISTER_SIZE
- n
);
1864 write_memory (offset
, info
->contents
, info
->length
);
1869 int n
= info
->length
;
1870 const bfd_byte
*cp
= info
->contents
;
1871 int r
= info
->u
.regno
;
1873 /* Odd-sized structs are aligned to the lower side of registers in
1874 big-endian mode and require a shift. The odd-sized leftover will
1875 be at the end. Note that this is only true for structures smaller
1876 than REGISTER_SIZE; for larger odd-sized structures the excess
1877 will be left-aligned in the register on both endiannesses. */
1879 if (n
< REGISTER_SIZE
&& byte_order
== BFD_ENDIAN_BIG
)
1882 v
= extract_unsigned_integer (cp
, REGISTER_SIZE
, byte_order
);
1883 v
= v
>> ((REGISTER_SIZE
- n
) * TARGET_CHAR_BIT
);
1885 store_unsigned_integer (buf
, REGISTER_SIZE
, byte_order
, v
);
1886 regcache
->cooked_write (r
, buf
);
1888 cp
+= REGISTER_SIZE
;
1895 regcache
->cooked_write (r
, cp
);
1897 cp
+= REGISTER_SIZE
;
1904 /* Set the return address of dummy frame to the dummy address.
1905 The return address for the current function (in A0) is
1906 saved in the dummy frame, so we can savely overwrite A0 here. */
1908 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1912 ra
= (bp_addr
& 0x3fffffff) | 0x40000000;
1913 regcache_raw_read_unsigned (regcache
, gdbarch_ps_regnum (gdbarch
), &val
);
1914 ps
= (unsigned long) val
& ~0x00030000;
1915 regcache_cooked_write_unsigned
1916 (regcache
, gdbarch_tdep (gdbarch
)->a0_base
+ 4, ra
);
1917 regcache_cooked_write_unsigned (regcache
,
1918 gdbarch_ps_regnum (gdbarch
),
1921 /* All the registers have been saved. After executing
1922 dummy call, they all will be restored. So it's safe
1923 to modify WINDOWSTART register to make it look like there
1924 is only one register window corresponding to WINDOWEBASE. */
1926 regcache
->raw_read (gdbarch_tdep (gdbarch
)->wb_regnum
, buf
);
1927 regcache_cooked_write_unsigned
1928 (regcache
, gdbarch_tdep (gdbarch
)->ws_regnum
,
1929 1 << extract_unsigned_integer (buf
, 4, byte_order
));
1933 /* Simulate CALL0: write RA into A0 register. */
1934 regcache_cooked_write_unsigned
1935 (regcache
, gdbarch_tdep (gdbarch
)->a0_base
, bp_addr
);
1938 /* Set new stack pointer and return it. */
1939 regcache_cooked_write_unsigned (regcache
,
1940 gdbarch_tdep (gdbarch
)->a0_base
+ 1, sp
);
1941 /* Make dummy frame ID unique by adding a constant. */
1942 return sp
+ SP_ALIGNMENT
;
1945 /* Implement the breakpoint_kind_from_pc gdbarch method. */
1948 xtensa_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
1950 if (gdbarch_tdep (gdbarch
)->isa_use_density_instructions
)
1956 /* Return a breakpoint for the current location of PC. We always use
1957 the density version if we have density instructions (regardless of the
1958 current instruction at PC), and use regular instructions otherwise. */
1960 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1961 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1962 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1963 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1965 /* Implement the sw_breakpoint_from_kind gdbarch method. */
1967 static const gdb_byte
*
1968 xtensa_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
1974 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
1975 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
1977 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1978 return big_breakpoint
;
1980 return little_breakpoint
;
1984 static unsigned char density_big_breakpoint
[] = DENSITY_BIG_BREAKPOINT
;
1985 static unsigned char density_little_breakpoint
[]
1986 = DENSITY_LITTLE_BREAKPOINT
;
1988 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1989 return density_big_breakpoint
;
1991 return density_little_breakpoint
;
1995 /* Call0 ABI support routines. */
1997 /* Return true, if PC points to "ret" or "ret.n". */
2000 call0_ret (CORE_ADDR start_pc
, CORE_ADDR finish_pc
)
2002 #define RETURN_RET goto done
2004 xtensa_insnbuf ins
, slot
;
2005 gdb_byte ibuf
[XTENSA_ISA_BSZ
];
2006 CORE_ADDR ia
, bt
, ba
;
2008 int ilen
, islots
, is
;
2010 const char *opcname
;
2013 isa
= xtensa_default_isa
;
2014 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2015 ins
= xtensa_insnbuf_alloc (isa
);
2016 slot
= xtensa_insnbuf_alloc (isa
);
2019 for (ia
= start_pc
, bt
= ia
; ia
< finish_pc
; ia
+= ilen
)
2021 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2024 bt
= (ba
+ XTENSA_ISA_BSZ
) < finish_pc
2025 ? ba
+ XTENSA_ISA_BSZ
: finish_pc
;
2026 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0 )
2030 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2031 ifmt
= xtensa_format_decode (isa
, ins
);
2032 if (ifmt
== XTENSA_UNDEFINED
)
2034 ilen
= xtensa_format_length (isa
, ifmt
);
2035 if (ilen
== XTENSA_UNDEFINED
)
2037 islots
= xtensa_format_num_slots (isa
, ifmt
);
2038 if (islots
== XTENSA_UNDEFINED
)
2041 for (is
= 0; is
< islots
; ++is
)
2043 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
2046 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2047 if (opc
== XTENSA_UNDEFINED
)
2050 opcname
= xtensa_opcode_name (isa
, opc
);
2052 if ((strcasecmp (opcname
, "ret.n") == 0)
2053 || (strcasecmp (opcname
, "ret") == 0))
2061 xtensa_insnbuf_free(isa
, slot
);
2062 xtensa_insnbuf_free(isa
, ins
);
2066 /* Call0 opcode class. Opcodes are preclassified according to what they
2067 mean for Call0 prologue analysis, and their number of significant operands.
2068 The purpose of this is to simplify prologue analysis by separating
2069 instruction decoding (libisa) from the semantics of prologue analysis. */
2073 c0opc_illegal
, /* Unknown to libisa (invalid) or 'ill' opcode. */
2074 c0opc_uninteresting
, /* Not interesting for Call0 prologue analysis. */
2075 c0opc_flow
, /* Flow control insn. */
2076 c0opc_entry
, /* ENTRY indicates non-Call0 prologue. */
2077 c0opc_break
, /* Debugger software breakpoints. */
2078 c0opc_add
, /* Adding two registers. */
2079 c0opc_addi
, /* Adding a register and an immediate. */
2080 c0opc_and
, /* Bitwise "and"-ing two registers. */
2081 c0opc_sub
, /* Subtracting a register from a register. */
2082 c0opc_mov
, /* Moving a register to a register. */
2083 c0opc_movi
, /* Moving an immediate to a register. */
2084 c0opc_l32r
, /* Loading a literal. */
2085 c0opc_s32i
, /* Storing word at fixed offset from a base register. */
2086 c0opc_rwxsr
, /* RSR, WRS, or XSR instructions. */
2087 c0opc_l32e
, /* L32E instruction. */
2088 c0opc_s32e
, /* S32E instruction. */
2089 c0opc_rfwo
, /* RFWO instruction. */
2090 c0opc_rfwu
, /* RFWU instruction. */
2091 c0opc_NrOf
/* Number of opcode classifications. */
2094 /* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */
2097 rwx_special_register (const char *opcname
)
2099 char ch
= *opcname
++;
2101 if ((ch
!= 'r') && (ch
!= 'w') && (ch
!= 'x'))
2103 if (*opcname
++ != 's')
2105 if (*opcname
++ != 'r')
2107 if (*opcname
++ != '.')
2113 /* Classify an opcode based on what it means for Call0 prologue analysis. */
2115 static xtensa_insn_kind
2116 call0_classify_opcode (xtensa_isa isa
, xtensa_opcode opc
)
2118 const char *opcname
;
2119 xtensa_insn_kind opclass
= c0opc_uninteresting
;
2121 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc
);
2123 /* Get opcode name and handle special classifications. */
2125 opcname
= xtensa_opcode_name (isa
, opc
);
2128 || strcasecmp (opcname
, "ill") == 0
2129 || strcasecmp (opcname
, "ill.n") == 0)
2130 opclass
= c0opc_illegal
;
2131 else if (strcasecmp (opcname
, "break") == 0
2132 || strcasecmp (opcname
, "break.n") == 0)
2133 opclass
= c0opc_break
;
2134 else if (strcasecmp (opcname
, "entry") == 0)
2135 opclass
= c0opc_entry
;
2136 else if (strcasecmp (opcname
, "rfwo") == 0)
2137 opclass
= c0opc_rfwo
;
2138 else if (strcasecmp (opcname
, "rfwu") == 0)
2139 opclass
= c0opc_rfwu
;
2140 else if (xtensa_opcode_is_branch (isa
, opc
) > 0
2141 || xtensa_opcode_is_jump (isa
, opc
) > 0
2142 || xtensa_opcode_is_loop (isa
, opc
) > 0
2143 || xtensa_opcode_is_call (isa
, opc
) > 0
2144 || strcasecmp (opcname
, "simcall") == 0
2145 || strcasecmp (opcname
, "syscall") == 0)
2146 opclass
= c0opc_flow
;
2148 /* Also, classify specific opcodes that need to be tracked. */
2149 else if (strcasecmp (opcname
, "add") == 0
2150 || strcasecmp (opcname
, "add.n") == 0)
2151 opclass
= c0opc_add
;
2152 else if (strcasecmp (opcname
, "and") == 0)
2153 opclass
= c0opc_and
;
2154 else if (strcasecmp (opcname
, "addi") == 0
2155 || strcasecmp (opcname
, "addi.n") == 0
2156 || strcasecmp (opcname
, "addmi") == 0)
2157 opclass
= c0opc_addi
;
2158 else if (strcasecmp (opcname
, "sub") == 0)
2159 opclass
= c0opc_sub
;
2160 else if (strcasecmp (opcname
, "mov.n") == 0
2161 || strcasecmp (opcname
, "or") == 0) /* Could be 'mov' asm macro. */
2162 opclass
= c0opc_mov
;
2163 else if (strcasecmp (opcname
, "movi") == 0
2164 || strcasecmp (opcname
, "movi.n") == 0)
2165 opclass
= c0opc_movi
;
2166 else if (strcasecmp (opcname
, "l32r") == 0)
2167 opclass
= c0opc_l32r
;
2168 else if (strcasecmp (opcname
, "s32i") == 0
2169 || strcasecmp (opcname
, "s32i.n") == 0)
2170 opclass
= c0opc_s32i
;
2171 else if (strcasecmp (opcname
, "l32e") == 0)
2172 opclass
= c0opc_l32e
;
2173 else if (strcasecmp (opcname
, "s32e") == 0)
2174 opclass
= c0opc_s32e
;
2175 else if (rwx_special_register (opcname
))
2176 opclass
= c0opc_rwxsr
;
2181 /* Tracks register movement/mutation for a given operation, which may
2182 be within a bundle. Updates the destination register tracking info
2183 accordingly. The pc is needed only for pc-relative load instructions
2184 (eg. l32r). The SP register number is needed to identify stores to
2185 the stack frame. Returns 0, if analysis was succesfull, non-zero
2189 call0_track_op (struct gdbarch
*gdbarch
, xtensa_c0reg_t dst
[], xtensa_c0reg_t src
[],
2190 xtensa_insn_kind opclass
, int nods
, unsigned odv
[],
2191 CORE_ADDR pc
, int spreg
, xtensa_frame_cache_t
*cache
)
2193 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2194 unsigned litbase
, litaddr
, litval
;
2199 /* 3 operands: dst, src, imm. */
2200 gdb_assert (nods
== 3);
2201 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2202 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ odv
[2];
2205 /* 3 operands: dst, src1, src2. */
2206 gdb_assert (nods
== 3);
2207 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2209 dst
[odv
[0]].fr_reg
= src
[odv
[2]].fr_reg
;
2210 dst
[odv
[0]].fr_ofs
= src
[odv
[2]].fr_ofs
+ src
[odv
[1]].fr_ofs
;
2212 else if (src
[odv
[2]].fr_reg
== C0_CONST
)
2214 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2215 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ src
[odv
[2]].fr_ofs
;
2217 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2220 /* 3 operands: dst, src1, src2. */
2221 gdb_assert (nods
== 3);
2222 if (cache
->c0
.c0_fpalign
== 0)
2224 /* Handle dynamic stack alignment. */
2225 if ((src
[odv
[0]].fr_reg
== spreg
) && (src
[odv
[1]].fr_reg
== spreg
))
2227 if (src
[odv
[2]].fr_reg
== C0_CONST
)
2228 cache
->c0
.c0_fpalign
= src
[odv
[2]].fr_ofs
;
2231 else if ((src
[odv
[0]].fr_reg
== spreg
)
2232 && (src
[odv
[2]].fr_reg
== spreg
))
2234 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2235 cache
->c0
.c0_fpalign
= src
[odv
[1]].fr_ofs
;
2238 /* else fall through. */
2240 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2242 dst
[odv
[0]].fr_reg
= src
[odv
[2]].fr_reg
;
2243 dst
[odv
[0]].fr_ofs
= src
[odv
[2]].fr_ofs
& src
[odv
[1]].fr_ofs
;
2245 else if (src
[odv
[2]].fr_reg
== C0_CONST
)
2247 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2248 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
& src
[odv
[2]].fr_ofs
;
2250 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2253 /* 3 operands: dst, src1, src2. */
2254 gdb_assert (nods
== 3);
2255 if (src
[odv
[2]].fr_reg
== C0_CONST
)
2257 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2258 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
- src
[odv
[2]].fr_ofs
;
2260 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2263 /* 2 operands: dst, src [, src]. */
2264 gdb_assert (nods
== 2);
2265 /* First, check if it's a special case of saving unaligned SP
2266 to a spare register in case of dynamic stack adjustment.
2267 But, only do it one time. The second time could be initializing
2268 frame pointer. We don't want to overwrite the first one. */
2269 if ((odv
[1] == spreg
) && (cache
->c0
.c0_old_sp
== C0_INEXP
))
2270 cache
->c0
.c0_old_sp
= odv
[0];
2272 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2273 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
;
2276 /* 2 operands: dst, imm. */
2277 gdb_assert (nods
== 2);
2278 dst
[odv
[0]].fr_reg
= C0_CONST
;
2279 dst
[odv
[0]].fr_ofs
= odv
[1];
2282 /* 2 operands: dst, literal offset. */
2283 gdb_assert (nods
== 2);
2284 /* litbase = xtensa_get_litbase (pc); can be also used. */
2285 litbase
= (gdbarch_tdep (gdbarch
)->litbase_regnum
== -1)
2286 ? 0 : xtensa_read_register
2287 (gdbarch_tdep (gdbarch
)->litbase_regnum
);
2288 litaddr
= litbase
& 1
2289 ? (litbase
& ~1) + (signed)odv
[1]
2290 : (pc
+ 3 + (signed)odv
[1]) & ~3;
2291 litval
= read_memory_integer (litaddr
, 4, byte_order
);
2292 dst
[odv
[0]].fr_reg
= C0_CONST
;
2293 dst
[odv
[0]].fr_ofs
= litval
;
2296 /* 3 operands: value, base, offset. */
2297 gdb_assert (nods
== 3 && spreg
>= 0 && spreg
< C0_NREGS
);
2298 /* First, check if it's a spill for saved unaligned SP,
2299 when dynamic stack adjustment was applied to this frame. */
2300 if ((cache
->c0
.c0_fpalign
!= 0) /* Dynamic stack adjustment. */
2301 && (odv
[1] == spreg
) /* SP usage indicates spill. */
2302 && (odv
[0] == cache
->c0
.c0_old_sp
)) /* Old SP register spilled. */
2303 cache
->c0
.c0_sp_ofs
= odv
[2];
2305 if (src
[odv
[1]].fr_reg
== spreg
/* Store to stack frame. */
2306 && (src
[odv
[1]].fr_ofs
& 3) == 0 /* Alignment preserved. */
2307 && src
[odv
[0]].fr_reg
>= 0 /* Value is from a register. */
2308 && src
[odv
[0]].fr_ofs
== 0 /* Value hasn't been modified. */
2309 && src
[src
[odv
[0]].fr_reg
].to_stk
== C0_NOSTK
) /* First time. */
2311 /* ISA encoding guarantees alignment. But, check it anyway. */
2312 gdb_assert ((odv
[2] & 3) == 0);
2313 dst
[src
[odv
[0]].fr_reg
].to_stk
= src
[odv
[1]].fr_ofs
+ odv
[2];
2316 /* If we end up inside Window Overflow / Underflow interrupt handler
2317 report an error because these handlers should have been handled
2318 already in a different way. */
2330 /* Analyze prologue of the function at start address to determine if it uses
2331 the Call0 ABI, and if so track register moves and linear modifications
2332 in the prologue up to the PC or just beyond the prologue, whichever is
2333 first. An 'entry' instruction indicates non-Call0 ABI and the end of the
2334 prologue. The prologue may overlap non-prologue instructions but is
2335 guaranteed to end by the first flow-control instruction (jump, branch,
2336 call or return). Since an optimized function may move information around
2337 and change the stack frame arbitrarily during the prologue, the information
2338 is guaranteed valid only at the point in the function indicated by the PC.
2339 May be used to skip the prologue or identify the ABI, w/o tracking.
2341 Returns: Address of first instruction after prologue, or PC (whichever
2342 is first), or 0, if decoding failed (in libisa).
2344 start Start address of function/prologue.
2345 pc Program counter to stop at. Use 0 to continue to end of prologue.
2346 If 0, avoids infinite run-on in corrupt code memory by bounding
2347 the scan to the end of the function if that can be determined.
2348 nregs Number of general registers to track.
2350 cache Xtensa frame cache.
2352 Note that these may produce useful results even if decoding fails
2353 because they begin with default assumptions that analysis may change. */
2356 call0_analyze_prologue (struct gdbarch
*gdbarch
,
2357 CORE_ADDR start
, CORE_ADDR pc
,
2358 int nregs
, xtensa_frame_cache_t
*cache
)
2360 CORE_ADDR ia
; /* Current insn address in prologue. */
2361 CORE_ADDR ba
= 0; /* Current address at base of insn buffer. */
2362 CORE_ADDR bt
; /* Current address at top+1 of insn buffer. */
2363 gdb_byte ibuf
[XTENSA_ISA_BSZ
];/* Instruction buffer for decoding prologue. */
2364 xtensa_isa isa
; /* libisa ISA handle. */
2365 xtensa_insnbuf ins
, slot
; /* libisa handle to decoded insn, slot. */
2366 xtensa_format ifmt
; /* libisa instruction format. */
2367 int ilen
, islots
, is
; /* Instruction length, nbr slots, current slot. */
2368 xtensa_opcode opc
; /* Opcode in current slot. */
2369 xtensa_insn_kind opclass
; /* Opcode class for Call0 prologue analysis. */
2370 int nods
; /* Opcode number of operands. */
2371 unsigned odv
[C0_MAXOPDS
]; /* Operand values in order provided by libisa. */
2372 xtensa_c0reg_t
*rtmp
; /* Register tracking info snapshot. */
2373 int j
; /* General loop counter. */
2374 int fail
= 0; /* Set non-zero and exit, if decoding fails. */
2375 CORE_ADDR body_pc
; /* The PC for the first non-prologue insn. */
2376 CORE_ADDR end_pc
; /* The PC for the lust function insn. */
2378 struct symtab_and_line prologue_sal
;
2380 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2381 (int)start
, (int)pc
);
2383 /* Try to limit the scan to the end of the function if a non-zero pc
2384 arg was not supplied to avoid probing beyond the end of valid memory.
2385 If memory is full of garbage that classifies as c0opc_uninteresting.
2386 If this fails (eg. if no symbols) pc ends up 0 as it was.
2387 Initialize the Call0 frame and register tracking info.
2388 Assume it's Call0 until an 'entry' instruction is encountered.
2389 Assume we may be in the prologue until we hit a flow control instr. */
2395 /* Find out, if we have an information about the prologue from DWARF. */
2396 prologue_sal
= find_pc_line (start
, 0);
2397 if (prologue_sal
.line
!= 0) /* Found debug info. */
2398 body_pc
= prologue_sal
.end
;
2400 /* If we are going to analyze the prologue in general without knowing about
2401 the current PC, make the best assumtion for the end of the prologue. */
2404 find_pc_partial_function (start
, 0, NULL
, &end_pc
);
2405 body_pc
= std::min (end_pc
, body_pc
);
2408 body_pc
= std::min (pc
, body_pc
);
2411 rtmp
= (xtensa_c0reg_t
*) alloca(nregs
* sizeof(xtensa_c0reg_t
));
2413 isa
= xtensa_default_isa
;
2414 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2415 ins
= xtensa_insnbuf_alloc (isa
);
2416 slot
= xtensa_insnbuf_alloc (isa
);
2418 for (ia
= start
, bt
= ia
; ia
< body_pc
; ia
+= ilen
)
2420 /* (Re)fill instruction buffer from memory if necessary, but do not
2421 read memory beyond PC to be sure we stay within text section
2422 (this protection only works if a non-zero pc is supplied). */
2424 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2427 bt
= (ba
+ XTENSA_ISA_BSZ
) < body_pc
? ba
+ XTENSA_ISA_BSZ
: body_pc
;
2428 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0 )
2429 error (_("Unable to read target memory ..."));
2432 /* Decode format information. */
2434 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2435 ifmt
= xtensa_format_decode (isa
, ins
);
2436 if (ifmt
== XTENSA_UNDEFINED
)
2441 ilen
= xtensa_format_length (isa
, ifmt
);
2442 if (ilen
== XTENSA_UNDEFINED
)
2447 islots
= xtensa_format_num_slots (isa
, ifmt
);
2448 if (islots
== XTENSA_UNDEFINED
)
2454 /* Analyze a bundle or a single instruction, using a snapshot of
2455 the register tracking info as input for the entire bundle so that
2456 register changes do not take effect within this bundle. */
2458 for (j
= 0; j
< nregs
; ++j
)
2459 rtmp
[j
] = cache
->c0
.c0_rt
[j
];
2461 for (is
= 0; is
< islots
; ++is
)
2463 /* Decode a slot and classify the opcode. */
2465 fail
= xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
);
2469 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2470 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2472 if (opc
== XTENSA_UNDEFINED
)
2473 opclass
= c0opc_illegal
;
2475 opclass
= call0_classify_opcode (isa
, opc
);
2477 /* Decide whether to track this opcode, ignore it, or bail out. */
2486 case c0opc_uninteresting
:
2489 case c0opc_flow
: /* Flow control instructions stop analysis. */
2490 case c0opc_rwxsr
: /* RSR, WSR, XSR instructions stop analysis. */
2495 ia
+= ilen
; /* Skip over 'entry' insn. */
2502 /* Only expected opcodes should get this far. */
2504 /* Extract and decode the operands. */
2505 nods
= xtensa_opcode_num_operands (isa
, opc
);
2506 if (nods
== XTENSA_UNDEFINED
)
2512 for (j
= 0; j
< nods
&& j
< C0_MAXOPDS
; ++j
)
2514 fail
= xtensa_operand_get_field (isa
, opc
, j
, ifmt
,
2519 fail
= xtensa_operand_decode (isa
, opc
, j
, &odv
[j
]);
2524 /* Check operands to verify use of 'mov' assembler macro. */
2525 if (opclass
== c0opc_mov
&& nods
== 3)
2527 if (odv
[2] == odv
[1])
2530 if ((odv
[0] == 1) && (odv
[1] != 1))
2531 /* OR A1, An, An , where n != 1.
2532 This means we are inside epilogue already. */
2537 opclass
= c0opc_uninteresting
;
2542 /* Track register movement and modification for this operation. */
2543 fail
= call0_track_op (gdbarch
, cache
->c0
.c0_rt
, rtmp
,
2544 opclass
, nods
, odv
, ia
, 1, cache
);
2550 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2551 (unsigned)ia
, fail
? "failed" : "succeeded");
2552 xtensa_insnbuf_free(isa
, slot
);
2553 xtensa_insnbuf_free(isa
, ins
);
2554 return fail
? XTENSA_ISA_BADPC
: ia
;
2557 /* Initialize frame cache for the current frame in CALL0 ABI. */
2560 call0_frame_cache (struct frame_info
*this_frame
,
2561 xtensa_frame_cache_t
*cache
, CORE_ADDR pc
)
2563 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2564 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2565 CORE_ADDR start_pc
; /* The beginning of the function. */
2566 CORE_ADDR body_pc
=UINT_MAX
; /* PC, where prologue analysis stopped. */
2567 CORE_ADDR sp
, fp
, ra
;
2568 int fp_regnum
= C0_SP
, c0_hasfp
= 0, c0_frmsz
= 0, prev_sp
= 0, to_stk
;
2570 sp
= get_frame_register_unsigned
2571 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
2572 fp
= sp
; /* Assume FP == SP until proven otherwise. */
2574 /* Find the beginning of the prologue of the function containing the PC
2575 and analyze it up to the PC or the end of the prologue. */
2577 if (find_pc_partial_function (pc
, NULL
, &start_pc
, NULL
))
2579 body_pc
= call0_analyze_prologue (gdbarch
, start_pc
, pc
, C0_NREGS
, cache
);
2581 if (body_pc
== XTENSA_ISA_BADPC
)
2585 goto finish_frame_analysis
;
2589 /* Get the frame information and FP (if used) at the current PC.
2590 If PC is in the prologue, the prologue analysis is more reliable
2591 than DWARF info. We don't not know for sure, if PC is in the prologue,
2592 but we do know no calls have yet taken place, so we can almost
2593 certainly rely on the prologue analysis. */
2597 /* Prologue analysis was successful up to the PC.
2598 It includes the cases when PC == START_PC. */
2599 c0_hasfp
= cache
->c0
.c0_rt
[C0_FP
].fr_reg
== C0_SP
;
2600 /* c0_hasfp == true means there is a frame pointer because
2601 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2602 was derived from SP. Otherwise, it would be C0_FP. */
2603 fp_regnum
= c0_hasfp
? C0_FP
: C0_SP
;
2604 c0_frmsz
= - cache
->c0
.c0_rt
[fp_regnum
].fr_ofs
;
2605 fp_regnum
+= gdbarch_tdep (gdbarch
)->a0_base
;
2607 else /* No data from the prologue analysis. */
2610 fp_regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_SP
;
2615 if (cache
->c0
.c0_fpalign
)
2617 /* This frame has a special prologue with a dynamic stack adjustment
2618 to force an alignment, which is bigger than standard 16 bytes. */
2620 CORE_ADDR unaligned_sp
;
2622 if (cache
->c0
.c0_old_sp
== C0_INEXP
)
2623 /* This can't be. Prologue code should be consistent.
2624 Unaligned stack pointer should be saved in a spare register. */
2628 goto finish_frame_analysis
;
2631 if (cache
->c0
.c0_sp_ofs
== C0_NOSTK
)
2632 /* Saved unaligned value of SP is kept in a register. */
2633 unaligned_sp
= get_frame_register_unsigned
2634 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ cache
->c0
.c0_old_sp
);
2636 /* Get the value from stack. */
2637 unaligned_sp
= (CORE_ADDR
)
2638 read_memory_integer (fp
+ cache
->c0
.c0_sp_ofs
, 4, byte_order
);
2640 prev_sp
= unaligned_sp
+ c0_frmsz
;
2643 prev_sp
= fp
+ c0_frmsz
;
2645 /* Frame size from debug info or prologue tracking does not account for
2646 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2649 fp
= get_frame_register_unsigned (this_frame
, fp_regnum
);
2651 /* Update the stack frame size. */
2652 c0_frmsz
+= fp
- sp
;
2655 /* Get the return address (RA) from the stack if saved,
2656 or try to get it from a register. */
2658 to_stk
= cache
->c0
.c0_rt
[C0_RA
].to_stk
;
2659 if (to_stk
!= C0_NOSTK
)
2661 read_memory_integer (sp
+ c0_frmsz
+ cache
->c0
.c0_rt
[C0_RA
].to_stk
,
2664 else if (cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_CONST
2665 && cache
->c0
.c0_rt
[C0_RA
].fr_ofs
== 0)
2667 /* Special case for terminating backtrace at a function that wants to
2668 be seen as the outermost one. Such a function will clear it's RA (A0)
2669 register to 0 in the prologue instead of saving its original value. */
2674 /* RA was copied to another register or (before any function call) may
2675 still be in the original RA register. This is not always reliable:
2676 even in a leaf function, register tracking stops after prologue, and
2677 even in prologue, non-prologue instructions (not tracked) may overwrite
2678 RA or any register it was copied to. If likely in prologue or before
2679 any call, use retracking info and hope for the best (compiler should
2680 have saved RA in stack if not in a leaf function). If not in prologue,
2686 && (i
== C0_RA
|| cache
->c0
.c0_rt
[i
].fr_reg
!= C0_RA
);
2688 if (i
>= C0_NREGS
&& cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_RA
)
2692 ra
= get_frame_register_unsigned
2694 gdbarch_tdep (gdbarch
)->a0_base
+ cache
->c0
.c0_rt
[i
].fr_reg
);
2699 finish_frame_analysis
:
2700 cache
->pc
= start_pc
;
2702 /* RA == 0 marks the outermost frame. Do not go past it. */
2703 cache
->prev_sp
= (ra
!= 0) ? prev_sp
: 0;
2704 cache
->c0
.fp_regnum
= fp_regnum
;
2705 cache
->c0
.c0_frmsz
= c0_frmsz
;
2706 cache
->c0
.c0_hasfp
= c0_hasfp
;
2707 cache
->c0
.c0_fp
= fp
;
2710 static CORE_ADDR a0_saved
;
2711 static CORE_ADDR a7_saved
;
2712 static CORE_ADDR a11_saved
;
2713 static int a0_was_saved
;
2714 static int a7_was_saved
;
2715 static int a11_was_saved
;
2717 /* Simulate L32E instruction: AT <-- ref (AS + offset). */
2719 execute_l32e (struct gdbarch
*gdbarch
, int at
, int as
, int offset
, CORE_ADDR wb
)
2721 int atreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ at
, wb
);
2722 int asreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ as
, wb
);
2723 CORE_ADDR addr
= xtensa_read_register (asreg
) + offset
;
2724 unsigned int spilled_value
2725 = read_memory_unsigned_integer (addr
, 4, gdbarch_byte_order (gdbarch
));
2727 if ((at
== 0) && !a0_was_saved
)
2729 a0_saved
= xtensa_read_register (atreg
);
2732 else if ((at
== 7) && !a7_was_saved
)
2734 a7_saved
= xtensa_read_register (atreg
);
2737 else if ((at
== 11) && !a11_was_saved
)
2739 a11_saved
= xtensa_read_register (atreg
);
2743 xtensa_write_register (atreg
, spilled_value
);
2746 /* Simulate S32E instruction: AT --> ref (AS + offset). */
2748 execute_s32e (struct gdbarch
*gdbarch
, int at
, int as
, int offset
, CORE_ADDR wb
)
2750 int atreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ at
, wb
);
2751 int asreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ as
, wb
);
2752 CORE_ADDR addr
= xtensa_read_register (asreg
) + offset
;
2753 ULONGEST spilled_value
= xtensa_read_register (atreg
);
2755 write_memory_unsigned_integer (addr
, 4,
2756 gdbarch_byte_order (gdbarch
),
2760 #define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200
2766 xtNoExceptionHandler
2767 } xtensa_exception_handler_t
;
2769 /* Execute instruction stream from current PC until hitting RFWU or RFWO.
2770 Return type of Xtensa Window Interrupt Handler on success. */
2771 static xtensa_exception_handler_t
2772 execute_code (struct gdbarch
*gdbarch
, CORE_ADDR current_pc
, CORE_ADDR wb
)
2775 xtensa_insnbuf ins
, slot
;
2776 gdb_byte ibuf
[XTENSA_ISA_BSZ
];
2777 CORE_ADDR ia
, bt
, ba
;
2779 int ilen
, islots
, is
;
2782 void (*func
) (struct gdbarch
*, int, int, int, CORE_ADDR
);
2784 uint32_t at
, as
, offset
;
2786 /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */
2787 int WindowUnderflow12
= (current_pc
& 0x1ff) >= 0x140;
2789 isa
= xtensa_default_isa
;
2790 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2791 ins
= xtensa_insnbuf_alloc (isa
);
2792 slot
= xtensa_insnbuf_alloc (isa
);
2801 while (insn_num
++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN
)
2803 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2806 bt
= (ba
+ XTENSA_ISA_BSZ
);
2807 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0)
2808 return xtNoExceptionHandler
;
2810 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2811 ifmt
= xtensa_format_decode (isa
, ins
);
2812 if (ifmt
== XTENSA_UNDEFINED
)
2813 return xtNoExceptionHandler
;
2814 ilen
= xtensa_format_length (isa
, ifmt
);
2815 if (ilen
== XTENSA_UNDEFINED
)
2816 return xtNoExceptionHandler
;
2817 islots
= xtensa_format_num_slots (isa
, ifmt
);
2818 if (islots
== XTENSA_UNDEFINED
)
2819 return xtNoExceptionHandler
;
2820 for (is
= 0; is
< islots
; ++is
)
2822 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
2823 return xtNoExceptionHandler
;
2824 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2825 if (opc
== XTENSA_UNDEFINED
)
2826 return xtNoExceptionHandler
;
2827 switch (call0_classify_opcode (isa
, opc
))
2833 /* We expect none of them here. */
2834 return xtNoExceptionHandler
;
2836 func
= execute_l32e
;
2839 func
= execute_s32e
;
2841 case c0opc_rfwo
: /* RFWO. */
2842 /* Here, we return from WindowOverflow handler and,
2843 if we stopped at the very beginning, which means
2844 A0 was saved, we have to restore it now. */
2847 int arreg
= arreg_number (gdbarch
,
2848 gdbarch_tdep (gdbarch
)->a0_base
,
2850 xtensa_write_register (arreg
, a0_saved
);
2852 return xtWindowOverflow
;
2853 case c0opc_rfwu
: /* RFWU. */
2854 /* Here, we return from WindowUnderflow handler.
2855 Let's see if either A7 or A11 has to be restored. */
2856 if (WindowUnderflow12
)
2860 int arreg
= arreg_number (gdbarch
,
2861 gdbarch_tdep (gdbarch
)->a0_base
+ 11,
2863 xtensa_write_register (arreg
, a11_saved
);
2866 else if (a7_was_saved
)
2868 int arreg
= arreg_number (gdbarch
,
2869 gdbarch_tdep (gdbarch
)->a0_base
+ 7,
2871 xtensa_write_register (arreg
, a7_saved
);
2873 return xtWindowUnderflow
;
2874 default: /* Simply skip this insns. */
2878 /* Decode arguments for L32E / S32E and simulate their execution. */
2879 if ( xtensa_opcode_num_operands (isa
, opc
) != 3 )
2880 return xtNoExceptionHandler
;
2881 if (xtensa_operand_get_field (isa
, opc
, 0, ifmt
, is
, slot
, &at
))
2882 return xtNoExceptionHandler
;
2883 if (xtensa_operand_decode (isa
, opc
, 0, &at
))
2884 return xtNoExceptionHandler
;
2885 if (xtensa_operand_get_field (isa
, opc
, 1, ifmt
, is
, slot
, &as
))
2886 return xtNoExceptionHandler
;
2887 if (xtensa_operand_decode (isa
, opc
, 1, &as
))
2888 return xtNoExceptionHandler
;
2889 if (xtensa_operand_get_field (isa
, opc
, 2, ifmt
, is
, slot
, &offset
))
2890 return xtNoExceptionHandler
;
2891 if (xtensa_operand_decode (isa
, opc
, 2, &offset
))
2892 return xtNoExceptionHandler
;
2894 (*func
) (gdbarch
, at
, as
, offset
, wb
);
2899 return xtNoExceptionHandler
;
2902 /* Handle Window Overflow / Underflow exception frames. */
2905 xtensa_window_interrupt_frame_cache (struct frame_info
*this_frame
,
2906 xtensa_frame_cache_t
*cache
,
2909 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2910 CORE_ADDR ps
, wb
, ws
, ra
;
2911 int epc1_regnum
, i
, regnum
;
2912 xtensa_exception_handler_t eh_type
;
2914 /* Read PS, WB, and WS from the hardware. Note that PS register
2915 must be present, if Windowed ABI is supported. */
2916 ps
= xtensa_read_register (gdbarch_ps_regnum (gdbarch
));
2917 wb
= xtensa_read_register (gdbarch_tdep (gdbarch
)->wb_regnum
);
2918 ws
= xtensa_read_register (gdbarch_tdep (gdbarch
)->ws_regnum
);
2920 /* Execute all the remaining instructions from Window Interrupt Handler
2921 by simulating them on the remote protocol level. On return, set the
2922 type of Xtensa Window Interrupt Handler, or report an error. */
2923 eh_type
= execute_code (gdbarch
, pc
, wb
);
2924 if (eh_type
== xtNoExceptionHandler
)
2926 Unable to decode Xtensa Window Interrupt Handler's code."));
2928 cache
->ps
= ps
^ PS_EXC
; /* Clear the exception bit in PS. */
2929 cache
->call0
= 0; /* It's Windowed ABI. */
2931 /* All registers for the cached frame will be alive. */
2932 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
2933 cache
->wd
.aregs
[i
] = -1;
2935 if (eh_type
== xtWindowOverflow
)
2936 cache
->wd
.ws
= ws
^ (1 << wb
);
2937 else /* eh_type == xtWindowUnderflow. */
2938 cache
->wd
.ws
= ws
| (1 << wb
);
2940 cache
->wd
.wb
= (ps
& 0xf00) >> 8; /* Set WB to OWB. */
2941 regnum
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
,
2943 ra
= xtensa_read_register (regnum
);
2944 cache
->wd
.callsize
= WINSIZE (ra
);
2945 cache
->prev_sp
= xtensa_read_register (regnum
+ 1);
2946 /* Set regnum to a frame pointer of the frame being cached. */
2947 regnum
= xtensa_scan_prologue (gdbarch
, pc
);
2948 regnum
= arreg_number (gdbarch
,
2949 gdbarch_tdep (gdbarch
)->a0_base
+ regnum
,
2951 cache
->base
= get_frame_register_unsigned (this_frame
, regnum
);
2953 /* Read PC of interrupted function from EPC1 register. */
2954 epc1_regnum
= xtensa_find_register_by_name (gdbarch
,"epc1");
2955 if (epc1_regnum
< 0)
2956 error(_("Unable to read Xtensa register EPC1"));
2957 cache
->ra
= xtensa_read_register (epc1_regnum
);
2958 cache
->pc
= get_frame_func (this_frame
);
2962 /* Skip function prologue.
2964 Return the pc of the first instruction after prologue. GDB calls this to
2965 find the address of the first line of the function or (if there is no line
2966 number information) to skip the prologue for planting breakpoints on
2967 function entries. Use debug info (if present) or prologue analysis to skip
2968 the prologue to achieve reliable debugging behavior. For windowed ABI,
2969 only the 'entry' instruction is skipped. It is not strictly necessary to
2970 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2971 backtrace at any point in the prologue, however certain potential hazards
2972 are avoided and a more "normal" debugging experience is ensured by
2973 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2974 For example, if we don't skip the prologue:
2975 - Some args may not yet have been saved to the stack where the debug
2976 info expects to find them (true anyway when only 'entry' is skipped);
2977 - Software breakpoints ('break' instrs) may not have been unplanted
2978 when the prologue analysis is done on initializing the frame cache,
2979 and breaks in the prologue will throw off the analysis.
2981 If we have debug info ( line-number info, in particular ) we simply skip
2982 the code associated with the first function line effectively skipping
2983 the prologue code. It works even in cases like
2986 { int local_var = 1;
2990 because, for this source code, both Xtensa compilers will generate two
2991 separate entries ( with the same line number ) in dwarf line-number
2992 section to make sure there is a boundary between the prologue code and
2993 the rest of the function.
2995 If there is no debug info, we need to analyze the code. */
2997 /* #define DONT_SKIP_PROLOGUE */
3000 xtensa_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
3002 struct symtab_and_line prologue_sal
;
3005 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc
);
3007 #if DONT_SKIP_PROLOGUE
3011 /* Try to find first body line from debug info. */
3013 prologue_sal
= find_pc_line (start_pc
, 0);
3014 if (prologue_sal
.line
!= 0) /* Found debug info. */
3016 /* In Call0, it is possible to have a function with only one instruction
3017 ('ret') resulting from a one-line optimized function that does nothing.
3018 In that case, prologue_sal.end may actually point to the start of the
3019 next function in the text section, causing a breakpoint to be set at
3020 the wrong place. Check, if the end address is within a different
3021 function, and if so return the start PC. We know we have symbol
3026 if ((gdbarch_tdep (gdbarch
)->call_abi
== CallAbiCall0Only
)
3027 && call0_ret (start_pc
, prologue_sal
.end
))
3030 find_pc_partial_function (prologue_sal
.end
, NULL
, &end_func
, NULL
);
3031 if (end_func
!= start_pc
)
3034 return prologue_sal
.end
;
3037 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
3038 body_pc
= call0_analyze_prologue (gdbarch
, start_pc
, 0, 0,
3039 xtensa_alloc_frame_cache (0));
3040 return body_pc
!= 0 ? body_pc
: start_pc
;
3043 /* Verify the current configuration. */
3045 xtensa_verify_config (struct gdbarch
*gdbarch
)
3047 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3050 /* Verify that we got a reasonable number of AREGS. */
3051 if ((tdep
->num_aregs
& -tdep
->num_aregs
) != tdep
->num_aregs
)
3053 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
3056 /* Verify that certain registers exist. */
3058 if (tdep
->pc_regnum
== -1)
3059 log
.printf (_("\n\tpc_regnum: No PC register"));
3060 if (tdep
->isa_use_exceptions
&& tdep
->ps_regnum
== -1)
3061 log
.printf (_("\n\tps_regnum: No PS register"));
3063 if (tdep
->isa_use_windowed_registers
)
3065 if (tdep
->wb_regnum
== -1)
3066 log
.printf (_("\n\twb_regnum: No WB register"));
3067 if (tdep
->ws_regnum
== -1)
3068 log
.printf (_("\n\tws_regnum: No WS register"));
3069 if (tdep
->ar_base
== -1)
3070 log
.printf (_("\n\tar_base: No AR registers"));
3073 if (tdep
->a0_base
== -1)
3074 log
.printf (_("\n\ta0_base: No Ax registers"));
3077 internal_error (__FILE__
, __LINE__
,
3078 _("the following are invalid: %s"), log
.c_str ());
3082 /* Derive specific register numbers from the array of registers. */
3085 xtensa_derive_tdep (struct gdbarch_tdep
*tdep
)
3087 xtensa_register_t
* rmap
;
3088 int n
, max_size
= 4;
3091 tdep
->num_nopriv_regs
= 0;
3093 /* Special registers 0..255 (core). */
3094 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
3095 /* User registers 0..255. */
3096 #define XTENSA_DBREGN_UREG(n) (0x0300+(n))
3098 for (rmap
= tdep
->regmap
, n
= 0; rmap
->target_number
!= -1; n
++, rmap
++)
3100 if (rmap
->target_number
== 0x0020)
3101 tdep
->pc_regnum
= n
;
3102 else if (rmap
->target_number
== 0x0100)
3104 else if (rmap
->target_number
== 0x0000)
3106 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(72))
3107 tdep
->wb_regnum
= n
;
3108 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(73))
3109 tdep
->ws_regnum
= n
;
3110 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(233))
3111 tdep
->debugcause_regnum
= n
;
3112 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(232))
3113 tdep
->exccause_regnum
= n
;
3114 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(238))
3115 tdep
->excvaddr_regnum
= n
;
3116 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(0))
3117 tdep
->lbeg_regnum
= n
;
3118 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(1))
3119 tdep
->lend_regnum
= n
;
3120 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(2))
3121 tdep
->lcount_regnum
= n
;
3122 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(3))
3123 tdep
->sar_regnum
= n
;
3124 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(5))
3125 tdep
->litbase_regnum
= n
;
3126 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(230))
3127 tdep
->ps_regnum
= n
;
3128 else if (rmap
->target_number
== XTENSA_DBREGN_UREG(231))
3129 tdep
->threadptr_regnum
= n
;
3131 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(226))
3132 tdep
->interrupt_regnum
= n
;
3133 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(227))
3134 tdep
->interrupt2_regnum
= n
;
3135 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(224))
3136 tdep
->cpenable_regnum
= n
;
3139 if (rmap
->byte_size
> max_size
)
3140 max_size
= rmap
->byte_size
;
3141 if (rmap
->mask
!= 0 && tdep
->num_regs
== 0)
3143 if ((rmap
->flags
& XTENSA_REGISTER_FLAGS_PRIVILEGED
) != 0
3144 && tdep
->num_nopriv_regs
== 0)
3145 tdep
->num_nopriv_regs
= n
;
3147 if (tdep
->num_regs
== 0)
3148 tdep
->num_regs
= tdep
->num_nopriv_regs
;
3150 /* Number of pseudo registers. */
3151 tdep
->num_pseudo_regs
= n
- tdep
->num_regs
;
3153 /* Empirically determined maximum sizes. */
3154 tdep
->max_register_raw_size
= max_size
;
3155 tdep
->max_register_virtual_size
= max_size
;
3158 /* Module "constructor" function. */
3160 extern struct gdbarch_tdep xtensa_tdep
;
3162 static struct gdbarch
*
3163 xtensa_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3165 struct gdbarch_tdep
*tdep
;
3166 struct gdbarch
*gdbarch
;
3168 DEBUGTRACE ("gdbarch_init()\n");
3170 if (!xtensa_default_isa
)
3171 xtensa_default_isa
= xtensa_isa_init (0, 0);
3173 /* We have to set the byte order before we call gdbarch_alloc. */
3174 info
.byte_order
= XCHAL_HAVE_BE
? BFD_ENDIAN_BIG
: BFD_ENDIAN_LITTLE
;
3176 tdep
= &xtensa_tdep
;
3177 gdbarch
= gdbarch_alloc (&info
, tdep
);
3178 xtensa_derive_tdep (tdep
);
3180 /* Verify our configuration. */
3181 xtensa_verify_config (gdbarch
);
3182 xtensa_session_once_reported
= 0;
3184 set_gdbarch_wchar_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
3185 set_gdbarch_wchar_signed (gdbarch
, 0);
3187 /* Pseudo-Register read/write. */
3188 set_gdbarch_pseudo_register_read (gdbarch
, xtensa_pseudo_register_read
);
3189 set_gdbarch_pseudo_register_write (gdbarch
, xtensa_pseudo_register_write
);
3191 /* Set target information. */
3192 set_gdbarch_num_regs (gdbarch
, tdep
->num_regs
);
3193 set_gdbarch_num_pseudo_regs (gdbarch
, tdep
->num_pseudo_regs
);
3194 set_gdbarch_sp_regnum (gdbarch
, tdep
->a0_base
+ 1);
3195 set_gdbarch_pc_regnum (gdbarch
, tdep
->pc_regnum
);
3196 set_gdbarch_ps_regnum (gdbarch
, tdep
->ps_regnum
);
3198 /* Renumber registers for known formats (stabs and dwarf2). */
3199 set_gdbarch_stab_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
3200 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
3202 /* We provide our own function to get register information. */
3203 set_gdbarch_register_name (gdbarch
, xtensa_register_name
);
3204 set_gdbarch_register_type (gdbarch
, xtensa_register_type
);
3206 /* To call functions from GDB using dummy frame. */
3207 set_gdbarch_push_dummy_call (gdbarch
, xtensa_push_dummy_call
);
3209 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
3211 set_gdbarch_return_value (gdbarch
, xtensa_return_value
);
3213 /* Advance PC across any prologue instructions to reach "real" code. */
3214 set_gdbarch_skip_prologue (gdbarch
, xtensa_skip_prologue
);
3216 /* Stack grows downward. */
3217 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3219 /* Set breakpoints. */
3220 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
3221 xtensa_breakpoint_kind_from_pc
);
3222 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
3223 xtensa_sw_breakpoint_from_kind
);
3225 /* After breakpoint instruction or illegal instruction, pc still
3226 points at break instruction, so don't decrement. */
3227 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
3229 /* We don't skip args. */
3230 set_gdbarch_frame_args_skip (gdbarch
, 0);
3232 set_gdbarch_unwind_pc (gdbarch
, xtensa_unwind_pc
);
3234 set_gdbarch_frame_align (gdbarch
, xtensa_frame_align
);
3236 set_gdbarch_dummy_id (gdbarch
, xtensa_dummy_id
);
3238 /* Frame handling. */
3239 frame_base_set_default (gdbarch
, &xtensa_frame_base
);
3240 frame_unwind_append_unwinder (gdbarch
, &xtensa_unwind
);
3241 dwarf2_append_unwinders (gdbarch
);
3243 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3245 xtensa_add_reggroups (gdbarch
);
3246 set_gdbarch_register_reggroup_p (gdbarch
, xtensa_register_reggroup_p
);
3248 set_gdbarch_iterate_over_regset_sections
3249 (gdbarch
, xtensa_iterate_over_regset_sections
);
3251 set_solib_svr4_fetch_link_map_offsets
3252 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
3254 /* Hook in the ABI-specific overrides, if they have been registered. */
3255 gdbarch_init_osabi (info
, gdbarch
);
3261 xtensa_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3263 error (_("xtensa_dump_tdep(): not implemented"));
3267 _initialize_xtensa_tdep (void)
3269 gdbarch_register (bfd_arch_xtensa
, xtensa_gdbarch_init
, xtensa_dump_tdep
);
3270 xtensa_init_reggroups ();
3272 add_setshow_zuinteger_cmd ("xtensa",
3274 &xtensa_debug_level
,
3275 _("Set Xtensa debugging."),
3276 _("Show Xtensa debugging."), _("\
3277 When non-zero, Xtensa-specific debugging is enabled. \
3278 Can be 1, 2, 3, or 4 indicating the level of debugging."),
3281 &setdebuglist
, &showdebuglist
);