1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003, 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
32 #include "floatformat.h"
34 #include "reggroups.h"
37 #include "dummy-frame.h"
38 #include "elf/dwarf2.h"
39 #include "dwarf2-frame.h"
40 #include "dwarf2loc.h"
42 #include "frame-base.h"
43 #include "frame-unwind.h"
45 #include "arch-utils.h"
52 #include "gdb_assert.h"
54 #include "xtensa-tdep.h"
57 static int xtensa_debug_level
= 0;
59 #define DEBUGWARN(args...) \
60 if (xtensa_debug_level > 0) \
61 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
63 #define DEBUGINFO(args...) \
64 if (xtensa_debug_level > 1) \
65 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
67 #define DEBUGTRACE(args...) \
68 if (xtensa_debug_level > 2) \
69 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
71 #define DEBUGVERB(args...) \
72 if (xtensa_debug_level > 3) \
73 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
76 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
78 #define SP_ALIGNMENT 16
81 /* We use a6 through a11 for passing arguments to a function called by GDB. */
83 #define ARGS_FIRST_REG A6_REGNUM
84 #define ARGS_NUM_REGS 6
85 #define REGISTER_SIZE 4
88 /* Extract the call size from the return address or ps register. */
90 #define PS_CALLINC_SHIFT 16
91 #define PS_CALLINC_MASK 0x00030000
92 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
93 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
96 /* Convert a live Ax register number to the corresponding Areg number. */
98 #define AREG_NUMBER(r, wb) \
99 ((((r) - A0_REGNUM + (((wb) & WB_MASK)<<WB_SHIFT)) & AREGS_MASK) + AR_BASE)
102 /* Define prototypes. */
104 extern struct gdbarch_tdep
*xtensa_config_tdep (struct gdbarch_info
*);
105 extern int xtensa_config_byte_order (struct gdbarch_info
*);
108 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
109 indicates that the instruction is an ENTRY instruction. */
111 #define XTENSA_IS_ENTRY(op1) \
112 ((gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) \
113 ? ((op1) == 0x6c) : ((op1) == 0x36))
115 #define XTENSA_ENTRY_LENGTH 3
118 /* windowing_enabled() returns true, if windowing is enabled.
119 WOE must be set to 1; EXCM to 0.
120 Note: We assume that EXCM is always 0 for XEA1. */
123 windowing_enabled (CORE_ADDR ps
)
125 return ((ps
& (1 << 4)) == 0 && (ps
& (1 << 18)) != 0);
128 /* Return the window size of the previous call to the function from which we
131 This function is used to extract the return value after a called function
132 has returned to the callee. On Xtensa, the register that holds the return
133 value (from the perspective of the caller) depends on what call
134 instruction was used. For now, we are assuming that the call instruction
135 precedes the current address, so we simply analyze the call instruction.
136 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
137 method to call the inferior function. */
140 extract_call_winsize (CORE_ADDR pc
)
142 int winsize
= 4; /* Default: No call, e.g. dummy frame. */
146 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc
);
148 /* Read the previous instruction (should be a call[x]{4|8|12}. */
149 read_memory (pc
-3, buf
, 3);
150 insn
= extract_unsigned_integer (buf
, 3);
152 /* Decode call instruction:
154 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
155 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
157 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
158 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
161 (Return the default value (4) if we can't find a valid call insn. */
163 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_LITTLE
)
165 if (((insn
& 0xf) == 0x5) || ((insn
& 0xcf) == 0xc0))
166 winsize
= (insn
& 0x30) >> 2; /* 0, 4, 8, 12 */
170 if (((insn
>> 20) == 0x5) || (((insn
>> 16) & 0xf3) == 0x03))
171 winsize
= (insn
>> 16) & 0xc; /* 0, 4, 8, 12 */
177 /* REGISTER INFORMATION */
179 /* Returns the name of a register. */
182 xtensa_register_name (int regnum
)
184 /* Return the name stored in the register map. */
185 if (regnum
>= 0 && regnum
< gdbarch_num_regs (current_gdbarch
)
186 + gdbarch_num_pseudo_regs (current_gdbarch
))
187 return REGMAP
[regnum
].name
;
189 /* Invalid register number. */
190 internal_error (__FILE__
, __LINE__
, _("invalid register %d"), regnum
);
195 /* Return the type of a register. Create a new type, if necessary. */
197 static struct ctype_cache
199 struct ctype_cache
*next
;
201 struct type
*virtual_type
;
202 } *type_entries
= NULL
;
205 xtensa_register_type (struct gdbarch
*gdbarch
, int regnum
)
207 /* Return signed integer for ARx and Ax registers. */
208 if ((regnum
>= AR_BASE
&& regnum
< AR_BASE
+ NUM_AREGS
)
209 || (regnum
>= A0_BASE
&& regnum
< A0_BASE
+ 16))
210 return builtin_type_int
;
212 if (regnum
== PC_REGNUM
|| regnum
== A1_REGNUM
)
213 return lookup_pointer_type (builtin_type_void
);
215 /* Return the stored type for all other registers. */
216 else if (regnum
>= 0 && regnum
< gdbarch_num_regs (current_gdbarch
)
217 + gdbarch_num_pseudo_regs (current_gdbarch
))
219 xtensa_register_t
* reg
= ®MAP
[regnum
];
221 /* Set ctype for this register (only the first time we ask for it). */
225 struct ctype_cache
*tp
;
226 int size
= reg
->byte_size
;
228 /* We always use the memory representation, even if the register
233 reg
->ctype
= builtin_type_uint8
;
237 reg
->ctype
= builtin_type_uint16
;
241 reg
->ctype
= builtin_type_uint32
;
245 reg
->ctype
= builtin_type_uint64
;
249 reg
->ctype
= builtin_type_uint128
;
253 for (tp
= type_entries
; tp
!= NULL
; tp
= tp
->next
)
254 if (tp
->size
== size
)
259 char *name
= xmalloc (16);
260 tp
= xmalloc (sizeof (struct ctype_cache
));
261 tp
->next
= type_entries
;
265 sprintf (name
, "int%d", size
* 8);
266 tp
->virtual_type
= init_type (TYPE_CODE_INT
, size
,
267 TYPE_FLAG_UNSIGNED
, name
,
271 reg
->ctype
= tp
->virtual_type
;
277 /* Invalid register number. */
278 internal_error (__FILE__
, __LINE__
, _("invalid register number %d"), regnum
);
283 /* Returns the 'local' register number for stubs, dwarf2, etc.
284 The debugging information enumerates registers starting from 0 for A0
285 to n for An. So, we only have to add the base number for A0. */
288 xtensa_reg_to_regnum (int regnum
)
292 if (regnum
>= 0 && regnum
< 16)
293 return A0_BASE
+ regnum
;
296 i
< gdbarch_num_regs (current_gdbarch
)
297 + gdbarch_num_pseudo_regs (current_gdbarch
);
299 if (regnum
== REGMAP
[i
].target_number
)
302 /* Invalid register number. */
303 internal_error (__FILE__
, __LINE__
,
304 _("invalid dwarf/stabs register number %d"), regnum
);
309 /* Handle the special case of masked registers. */
311 /* Write the bits of a masked register to the various registers that
312 are combined into this register. Only the masked areas of these
313 registers are modified; the other fields are untouched.
314 (Note: The size of masked registers is always less or equal 32 bits.) */
317 xtensa_register_write_masked (xtensa_register_t
*reg
, unsigned char *buffer
)
319 unsigned int value
[(MAX_REGISTER_SIZE
+ 3) / 4];
321 const xtensa_mask_t
*mask
= reg
->mask
;
323 int shift
= 0; /* Shift for next mask (mod 32). */
324 int start
, size
; /* Start bit and size of current mask. */
326 unsigned int *ptr
= value
;
327 unsigned int regval
, m
, mem
= 0;
329 int bytesize
= reg
->byte_size
;
330 int bitsize
= bytesize
* 8;
333 DEBUGTRACE ("xtensa_register_write_masked ()\n");
335 /* Copy the masked register to host byte-order. */
336 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
337 for (i
= 0; i
< bytesize
; i
++)
340 mem
|= (buffer
[bytesize
- i
- 1] << 24);
345 for (i
= 0; i
< bytesize
; i
++)
348 mem
|= (buffer
[i
] << 24);
353 /* We might have to shift the final value:
354 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
355 bytesize & 3 == x -> shift (4-x) * 8. */
357 *ptr
= mem
>> (((0 - bytesize
) & 3) * 8);
361 /* Write the bits to the masked areas of the other registers. */
362 for (i
= 0; i
< mask
->count
; i
++)
364 start
= mask
->mask
[i
].bit_start
;
365 size
= mask
->mask
[i
].bit_size
;
366 regval
= mem
>> shift
;
368 if ((shift
+= size
) > bitsize
)
369 error (_("size of all masks is larger than the register"));
378 regval
|= mem
<< (size
- shift
);
381 /* Make sure we have a valid register. */
382 r
= mask
->mask
[i
].reg_num
;
383 if (r
>= 0 && size
> 0)
385 /* Don't overwrite the unmasked areas. */
386 m
= 0xffffffff >> (32 - size
) << start
;
388 regval
= (regval
& m
) | (read_register (r
) & ~m
);
389 write_register (r
, regval
);
395 /* Read the masked areas of the registers and assemble it into a single
399 xtensa_register_read_masked (xtensa_register_t
*reg
, unsigned char *buffer
)
401 unsigned int value
[(MAX_REGISTER_SIZE
+ 3) / 4];
403 const xtensa_mask_t
*mask
= reg
->mask
;
408 unsigned int *ptr
= value
;
409 unsigned int regval
, mem
= 0;
411 int bytesize
= reg
->byte_size
;
412 int bitsize
= bytesize
* 8;
415 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
416 reg
->name
== 0 ? "" : reg
->name
);
418 /* Assemble the register from the masked areas of other registers. */
419 for (i
= 0; i
< mask
->count
; i
++)
421 int r
= mask
->mask
[i
].reg_num
;
422 regval
= (r
>= 0) ? read_register (r
) : 0;
423 start
= mask
->mask
[i
].bit_start
;
424 size
= mask
->mask
[i
].bit_size
;
429 regval
&= (0xffffffff >> (32 - size
));
431 mem
|= regval
<< shift
;
433 if ((shift
+= size
) > bitsize
)
434 error (_("size of all masks is larger than the register"));
445 mem
= regval
>> (size
- shift
);
452 /* Copy value to target byte order. */
456 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
457 for (i
= 0; i
< bytesize
; i
++)
461 buffer
[bytesize
- i
- 1] = mem
& 0xff;
465 for (i
= 0; i
< bytesize
; i
++)
469 buffer
[i
] = mem
& 0xff;
475 /* Read pseudo registers. */
478 xtensa_pseudo_register_read (struct gdbarch
*gdbarch
,
479 struct regcache
*regcache
,
483 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
484 regnum
, xtensa_register_name (regnum
));
486 /* Check if it is FP (renumber it in this case -> A0...A15). */
487 if (regnum
== FP_ALIAS
)
488 error (_("trying to read FP"));
490 /* Read aliases a0..a15. */
491 if (regnum
>= A0_REGNUM
&& regnum
<= A15_REGNUM
)
493 gdb_byte
*buf
= (gdb_byte
*) alloca (MAX_REGISTER_SIZE
);
495 regcache_raw_read (regcache
, WB_REGNUM
, buf
);
496 regnum
= AREG_NUMBER (regnum
, extract_unsigned_integer (buf
, 4));
499 /* We can always read 'regular' registers. */
500 if (regnum
>= 0 && regnum
< gdbarch_num_regs (current_gdbarch
))
501 regcache_raw_read (regcache
, regnum
, buffer
);
503 /* Pseudo registers. */
505 && regnum
< gdbarch_num_regs (current_gdbarch
)
506 + gdbarch_num_pseudo_regs (current_gdbarch
))
508 xtensa_register_t
*reg
= ®MAP
[regnum
];
509 xtensa_register_type_t type
= reg
->type
;
510 int flags
= XTENSA_TARGET_FLAGS
;
512 /* Can we read Unknown or Unmapped registers? */
513 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
515 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
517 warning (_("cannot read register %s"),
518 xtensa_register_name (regnum
));
523 /* Some targets cannot read TIE register files. */
524 else if (type
== xtRegisterTypeTieRegfile
)
526 /* Use 'fetch' to get register? */
527 if (flags
& xtTargetFlagsUseFetchStore
)
529 warning (_("cannot read register"));
533 /* On some targets (esp. simulators), we can always read the reg. */
534 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
536 warning (_("cannot read register"));
541 /* We can always read mapped registers. */
542 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
544 xtensa_register_read_masked (reg
, (unsigned char *) buffer
);
548 /* Assume that we can read the register. */
549 regcache_raw_read (regcache
, regnum
, buffer
);
553 internal_error (__FILE__
, __LINE__
,
554 _("invalid register number %d"), regnum
);
558 /* Write pseudo registers. */
561 xtensa_pseudo_register_write (struct gdbarch
*gdbarch
,
562 struct regcache
*regcache
,
564 const gdb_byte
*buffer
)
566 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
567 regnum
, xtensa_register_name (regnum
));
569 /* Check if this is FP. */
570 if (regnum
== FP_ALIAS
)
571 error (_("trying to write FP"));
573 /* Renumber register, if aliase a0..a15. */
574 if (regnum
>= A0_REGNUM
&& regnum
<= A15_REGNUM
)
576 gdb_byte
*buf
= (gdb_byte
*) alloca (MAX_REGISTER_SIZE
);
579 regcache_raw_read (regcache
, WB_REGNUM
, buf
);
580 regnum
= AREG_NUMBER (regnum
, extract_unsigned_integer (buf
, 4));
583 /* We can always write 'core' registers.
584 Note: We might have converted Ax->ARy. */
585 if (regnum
>= 0 && regnum
< gdbarch_num_regs (current_gdbarch
))
586 regcache_raw_write (regcache
, regnum
, buffer
);
588 /* Pseudo registers. */
590 && regnum
< gdbarch_num_regs (current_gdbarch
)
591 + gdbarch_num_pseudo_regs (current_gdbarch
))
593 xtensa_register_t
*reg
= ®MAP
[regnum
];
594 xtensa_register_type_t type
= reg
->type
;
595 int flags
= XTENSA_TARGET_FLAGS
;
597 /* On most targets, we can't write registers of type "Unknown"
599 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
601 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
603 warning (_("cannot write register %s"),
604 xtensa_register_name (regnum
));
609 /* Some targets cannot read TIE register files. */
610 else if (type
== xtRegisterTypeTieRegfile
)
612 /* Use 'store' to get register? */
613 if (flags
& xtTargetFlagsUseFetchStore
)
615 warning (_("cannot write register"));
619 /* On some targets (esp. simulators), we can always write
622 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
624 warning (_("cannot write register"));
629 /* We can always write mapped registers. */
630 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
632 xtensa_register_write_masked (reg
, (unsigned char *) buffer
);
636 /* Assume that we can write the register. */
637 regcache_raw_write (regcache
, regnum
, buffer
);
641 internal_error (__FILE__
, __LINE__
,
642 _("invalid register number %d"), regnum
);
646 static struct reggroup
*xtensa_ar_reggroup
;
647 static struct reggroup
*xtensa_user_reggroup
;
648 static struct reggroup
*xtensa_vectra_reggroup
;
651 xtensa_init_reggroups (void)
653 xtensa_ar_reggroup
= reggroup_new ("ar", USER_REGGROUP
);
654 xtensa_user_reggroup
= reggroup_new ("user", USER_REGGROUP
);
655 xtensa_vectra_reggroup
= reggroup_new ("vectra", USER_REGGROUP
);
660 xtensa_add_reggroups (struct gdbarch
*gdbarch
)
662 reggroup_add (gdbarch
, all_reggroup
);
663 reggroup_add (gdbarch
, save_reggroup
);
664 reggroup_add (gdbarch
, restore_reggroup
);
665 reggroup_add (gdbarch
, system_reggroup
);
666 reggroup_add (gdbarch
, vector_reggroup
); /* vectra */
667 reggroup_add (gdbarch
, general_reggroup
); /* core */
668 reggroup_add (gdbarch
, float_reggroup
); /* float */
670 reggroup_add (gdbarch
, xtensa_ar_reggroup
); /* ar */
671 reggroup_add (gdbarch
, xtensa_user_reggroup
); /* user */
672 reggroup_add (gdbarch
, xtensa_vectra_reggroup
); /* vectra */
676 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
677 | XTENSA_REGISTER_FLAGS_WRITABLE \
678 | XTENSA_REGISTER_FLAGS_VOLATILE)
680 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
681 | XTENSA_REGISTER_FLAGS_WRITABLE)
684 xtensa_register_reggroup_p (struct gdbarch
*gdbarch
,
686 struct reggroup
*group
)
688 xtensa_register_t
* reg
= ®MAP
[regnum
];
689 xtensa_register_type_t type
= reg
->type
;
690 xtensa_register_group_t rg
= reg
->group
;
692 /* First, skip registers that are not visible to this target
693 (unknown and unmapped registers when not using ISS). */
695 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
697 if (group
== all_reggroup
)
699 if (group
== xtensa_ar_reggroup
)
700 return rg
& xtRegisterGroupAddrReg
;
701 if (group
== xtensa_user_reggroup
)
702 return rg
& xtRegisterGroupUser
;
703 if (group
== float_reggroup
)
704 return rg
& xtRegisterGroupFloat
;
705 if (group
== general_reggroup
)
706 return rg
& xtRegisterGroupGeneral
;
707 if (group
== float_reggroup
)
708 return rg
& xtRegisterGroupFloat
;
709 if (group
== system_reggroup
)
710 return rg
& xtRegisterGroupState
;
711 if (group
== vector_reggroup
|| group
== xtensa_vectra_reggroup
)
712 return rg
& xtRegisterGroupVectra
;
713 if (group
== save_reggroup
|| group
== restore_reggroup
)
714 return (regnum
< gdbarch_num_regs (current_gdbarch
)
715 && (reg
->flags
& SAVE_REST_FLAGS
) == SAVE_REST_VALID
);
721 /* CORE FILE SUPPORT */
723 /* Supply register REGNUM from the buffer specified by GREGS and LEN
724 in the general-purpose register set REGSET to register cache
725 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
728 xtensa_supply_gregset (const struct regset
*regset
,
734 const xtensa_elf_gregset_t
*regs
= gregs
;
737 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...) \n", regnum
);
739 if (regnum
== PC_REGNUM
|| regnum
== -1)
740 regcache_raw_supply (rc
, PC_REGNUM
, (char *) ®s
->pc
);
741 if (regnum
== PS_REGNUM
|| regnum
== -1)
742 regcache_raw_supply (rc
, PS_REGNUM
, (char *) ®s
->ps
);
743 if (regnum
== WB_REGNUM
|| regnum
== -1)
744 regcache_raw_supply (rc
, WB_REGNUM
, (char *) ®s
->windowbase
);
745 if (regnum
== WS_REGNUM
|| regnum
== -1)
746 regcache_raw_supply (rc
, WS_REGNUM
, (char *) ®s
->windowstart
);
747 if (regnum
== LBEG_REGNUM
|| regnum
== -1)
748 regcache_raw_supply (rc
, LBEG_REGNUM
, (char *) ®s
->lbeg
);
749 if (regnum
== LEND_REGNUM
|| regnum
== -1)
750 regcache_raw_supply (rc
, LEND_REGNUM
, (char *) ®s
->lend
);
751 if (regnum
== LCOUNT_REGNUM
|| regnum
== -1)
752 regcache_raw_supply (rc
, LCOUNT_REGNUM
, (char *) ®s
->lcount
);
753 if (regnum
== SAR_REGNUM
|| regnum
== -1)
754 regcache_raw_supply (rc
, SAR_REGNUM
, (char *) ®s
->sar
);
755 if (regnum
== EXCCAUSE_REGNUM
|| regnum
== -1)
756 regcache_raw_supply (rc
, EXCCAUSE_REGNUM
, (char *) ®s
->exccause
);
757 if (regnum
== EXCVADDR_REGNUM
|| regnum
== -1)
758 regcache_raw_supply (rc
, EXCVADDR_REGNUM
, (char *) ®s
->excvaddr
);
759 if (regnum
>= AR_BASE
&& regnum
< AR_BASE
+ NUM_AREGS
)
760 regcache_raw_supply (rc
, regnum
, (char *) ®s
->ar
[regnum
- AR_BASE
]);
761 else if (regnum
== -1)
763 for (i
= 0; i
< NUM_AREGS
; ++i
)
764 regcache_raw_supply (rc
, AR_BASE
+ i
, (char *) ®s
->ar
[i
]);
769 /* Xtensa register set. */
775 xtensa_supply_gregset
779 /* Return the appropriate register set for the core section identified
780 by SECT_NAME and SECT_SIZE. */
782 static const struct regset
*
783 xtensa_regset_from_core_section (struct gdbarch
*core_arch
,
784 const char *sect_name
,
787 DEBUGTRACE ("xtensa_regset_from_core_section "
788 "(..., sect_name==\"%s\", sect_size==%x) \n",
789 sect_name
, (int) sect_size
);
791 if (strcmp (sect_name
, ".reg") == 0
792 && sect_size
>= sizeof(xtensa_elf_gregset_t
))
793 return &xtensa_gregset
;
801 /* We currently don't support the call0-abi, so we have at max. 12 registers
802 saved on the stack. */
804 #define XTENSA_NUM_SAVED_AREGS 12
806 typedef struct xtensa_frame_cache
810 CORE_ADDR ra
; /* The raw return address; use to compute call_inc. */
812 int wb
; /* Base for this frame; -1 if not in regfile. */
813 int callsize
; /* Call size to next frame. */
815 CORE_ADDR aregs
[XTENSA_NUM_SAVED_AREGS
];
817 } xtensa_frame_cache_t
;
820 static struct xtensa_frame_cache
*
821 xtensa_alloc_frame_cache (void)
823 xtensa_frame_cache_t
*cache
;
826 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
828 cache
= FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t
);
835 cache
->callsize
= -1;
838 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
839 cache
->aregs
[i
] = -1;
846 xtensa_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
848 return address
& ~15;
853 xtensa_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
857 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %p)\n", next_frame
);
859 frame_unwind_register (next_frame
, PC_REGNUM
, buf
);
861 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int)
862 extract_typed_address (buf
, builtin_type_void_func_ptr
));
864 return extract_typed_address (buf
, builtin_type_void_func_ptr
);
868 static struct frame_id
869 xtensa_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
874 /* next_frame->prev is a dummy frame. Return a frame ID of that frame. */
876 DEBUGTRACE ("xtensa_unwind_dummy_id ()\n");
878 pc
= frame_pc_unwind (next_frame
);
879 frame_unwind_register (next_frame
, A1_REGNUM
, buf
);
880 fp
= extract_unsigned_integer (buf
, 4);
882 /* Make dummy frame ID unique by adding a constant. */
883 return frame_id_build (fp
+SP_ALIGNMENT
, pc
);
887 static struct xtensa_frame_cache
*
888 xtensa_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
890 xtensa_frame_cache_t
*cache
;
892 CORE_ADDR ra
, wb
, ws
, pc
, sp
, ps
;
895 DEBUGTRACE ("xtensa_frame_cache (next_frame %p, *this_cache %p)\n",
896 next_frame
, this_cache
? *this_cache
: (void*)0xdeadbeef);
898 /* Already cached? */
902 /* Get pristine xtensa-frame. */
903 cache
= xtensa_alloc_frame_cache ();
906 /* Get windowbase, windowstart, ps, and pc. */
907 wb
= frame_unwind_register_unsigned (next_frame
, WB_REGNUM
);
908 ws
= frame_unwind_register_unsigned (next_frame
, WS_REGNUM
);
909 ps
= frame_unwind_register_unsigned (next_frame
, PS_REGNUM
);
910 pc
= frame_unwind_register_unsigned (next_frame
, PC_REGNUM
);
912 op1
= read_memory_integer (pc
, 1);
913 if (XTENSA_IS_ENTRY (op1
) || !windowing_enabled (read_register (PS_REGNUM
)))
915 int callinc
= CALLINC (frame_unwind_register_unsigned (next_frame
,
917 ra
= frame_unwind_register_unsigned (next_frame
,
918 A0_REGNUM
+ callinc
* 4);
920 DEBUGINFO("[xtensa_frame_cache] 'entry' at 0x%08x\n (callinc = %d)",
923 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
927 cache
->prev_sp
= read_register (A1_REGNUM
);
931 ra
= frame_unwind_register_unsigned (next_frame
, A0_REGNUM
);
932 cache
->callsize
= WINSIZE (ra
);
933 cache
->wb
= (wb
- (cache
->callsize
/ 4)) & ((NUM_AREGS
/ 4) - 1);
934 cache
->ws
= ws
& ~(1 << wb
);
937 cache
->pc
= ((frame_func_unwind (next_frame
, NORMAL_FRAME
) & 0xc0000000)
938 | (ra
& 0x3fffffff));
939 cache
->ps
= (ps
& ~PS_CALLINC_MASK
) | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
942 /* Note: We could also calculate the location on stack when we actually
943 access the register. However, this approach, saving the location
944 in the cache frame, is probably easier to support the call0 ABI. */
951 sp
= frame_unwind_register_unsigned (next_frame
, A1_REGNUM
) - 16;
953 for (i
= 0; i
< 4; i
++, sp
+= 4)
955 cache
->aregs
[i
] = sp
;
958 if (cache
->callsize
> 4)
960 /* Set A4...A7/A11. */
962 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4);
963 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4);
964 sp
-= cache
->callsize
* 4;
966 for ( /* i=4 */ ; i
< cache
->callsize
; i
++, sp
+= 4)
968 cache
->aregs
[i
] = sp
;
973 if (cache
->prev_sp
== 0)
977 /* Register window overflow already happened.
978 We can read caller's frame SP from the proper spill loction. */
980 read_memory_integer (cache
->aregs
[1],
981 register_size (current_gdbarch
,
986 /* Read caller's frame SP directly from the previous window. */
988 int regnum
= AREG_NUMBER (A1_REGNUM
, cache
->wb
);
990 cache
->prev_sp
= read_register (regnum
);
994 cache
->base
= frame_unwind_register_unsigned (next_frame
,A1_REGNUM
);
996 DEBUGINFO ("[xtensa_frame_cache] base 0x%08x, wb %d, "
997 "ws 0x%08x, callsize %d, pc 0x%08x, ps 0x%08x, prev_sp 0x%08x\n",
998 (unsigned int) cache
->base
, (unsigned int) cache
->wb
,
999 cache
->ws
, cache
->callsize
, (unsigned int) cache
->pc
,
1000 (unsigned int) cache
->ps
, (unsigned int) cache
->prev_sp
);
1007 xtensa_frame_this_id (struct frame_info
*next_frame
,
1009 struct frame_id
*this_id
)
1011 struct xtensa_frame_cache
*cache
=
1012 xtensa_frame_cache (next_frame
, this_cache
);
1014 DEBUGTRACE ("xtensa_frame_this_id (next %p, *this %p)\n",
1015 next_frame
, *this_cache
);
1017 if (cache
->prev_sp
== 0)
1020 (*this_id
) = frame_id_build (cache
->prev_sp
, cache
->pc
);
1025 xtensa_frame_prev_register (struct frame_info
*next_frame
,
1029 enum lval_type
*lvalp
,
1034 struct xtensa_frame_cache
*cache
=
1035 xtensa_frame_cache (next_frame
, this_cache
);
1036 CORE_ADDR saved_reg
= 0;
1039 DEBUGTRACE ("xtensa_frame_prev_register (next %p, "
1040 "*this %p, regnum %d (%s), ...)\n",
1042 *this_cache
? *this_cache
: 0, regnum
,
1043 xtensa_register_name (regnum
));
1045 if (regnum
== WS_REGNUM
)
1048 saved_reg
= cache
->ws
;
1050 saved_reg
= 1 << cache
->wb
;
1052 else if (regnum
== WB_REGNUM
)
1053 saved_reg
= cache
->wb
;
1054 else if (regnum
== PC_REGNUM
)
1055 saved_reg
= cache
->pc
;
1056 else if (regnum
== PS_REGNUM
)
1057 saved_reg
= cache
->ps
;
1068 store_unsigned_integer (valuep
, 4, saved_reg
);
1073 /* Convert Ax register numbers to ARx register numbers. */
1074 if (regnum
>= A0_REGNUM
&& regnum
<= A15_REGNUM
)
1075 regnum
= AREG_NUMBER (regnum
, cache
->wb
);
1077 /* Check if ARx register has been saved to stack. */
1078 if (regnum
>= AR_BASE
&& regnum
<= (AR_BASE
+ NUM_AREGS
))
1080 int areg
= regnum
- AR_BASE
- (cache
->wb
* 4);
1083 && areg
< XTENSA_NUM_SAVED_AREGS
1084 && cache
->aregs
[areg
] != -1)
1087 *lvalp
= lval_memory
;
1088 *addrp
= cache
->aregs
[areg
];
1092 read_memory (*addrp
, valuep
,
1093 register_size (current_gdbarch
, regnum
));
1095 DEBUGINFO ("[xtensa_frame_prev_register] register on stack\n");
1100 /* Note: All other registers have been either saved to the dummy stack
1101 or are still alive in the processor. */
1104 *lvalp
= lval_register
;
1108 frame_unwind_register (next_frame
, (*realnump
), valuep
);
1112 static const struct frame_unwind
1113 xtensa_frame_unwind
=
1116 xtensa_frame_this_id
,
1117 xtensa_frame_prev_register
1120 static const struct frame_unwind
*
1121 xtensa_frame_sniffer (struct frame_info
*next_frame
)
1123 return &xtensa_frame_unwind
;
1127 xtensa_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
1129 struct xtensa_frame_cache
*cache
=
1130 xtensa_frame_cache (next_frame
, this_cache
);
1135 static const struct frame_base
1138 &xtensa_frame_unwind
,
1139 xtensa_frame_base_address
,
1140 xtensa_frame_base_address
,
1141 xtensa_frame_base_address
1146 xtensa_extract_return_value (struct type
*type
,
1147 struct regcache
*regcache
,
1150 bfd_byte
*valbuf
= dst
;
1151 int len
= TYPE_LENGTH (type
);
1156 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1158 gdb_assert(len
> 0);
1160 /* First, we have to find the caller window in the register file. */
1161 regcache_raw_read_unsigned (regcache
, PC_REGNUM
, &pc
);
1162 callsize
= extract_call_winsize (pc
);
1164 /* On Xtensa, we can return up to 4 words (or 2 when called by call12). */
1165 if (len
> (callsize
> 8 ? 8 : 16))
1166 internal_error (__FILE__
, __LINE__
,
1167 _("cannot extract return value of %d bytes long"), len
);
1169 /* Get the register offset of the return register (A2) in the caller
1171 regcache_raw_read_unsigned (regcache
, WB_REGNUM
, &wb
);
1172 areg
= AREG_NUMBER(A2_REGNUM
+ callsize
, wb
);
1174 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg
, len
);
1176 if (len
< 4 && gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1179 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1182 regcache_raw_read_part (regcache
, areg
, offset
, len
, valbuf
);
1184 regcache_raw_read (regcache
, areg
, valbuf
);
1190 xtensa_store_return_value (struct type
*type
,
1191 struct regcache
*regcache
,
1194 const bfd_byte
*valbuf
= dst
;
1198 int len
= TYPE_LENGTH (type
);
1201 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1203 regcache_raw_read_unsigned (regcache
, WB_REGNUM
, &wb
);
1204 regcache_raw_read_unsigned (regcache
, PC_REGNUM
, &pc
);
1205 callsize
= extract_call_winsize (pc
);
1207 if (len
> (callsize
> 8 ? 8 : 16))
1208 internal_error (__FILE__
, __LINE__
,
1209 _("unimplemented for this length: %d"),
1210 TYPE_LENGTH (type
));
1212 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1213 callsize
, (int) wb
);
1215 if (len
< 4 && gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1218 areg
= AREG_NUMBER (A2_REGNUM
+ callsize
, wb
);
1220 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1223 regcache_raw_write_part (regcache
, areg
, offset
, len
, valbuf
);
1225 regcache_raw_write (regcache
, areg
, valbuf
);
1230 enum return_value_convention
1231 xtensa_return_value (struct gdbarch
*gdbarch
,
1232 struct type
*valtype
,
1233 struct regcache
*regcache
,
1235 const gdb_byte
*writebuf
)
1237 /* Note: Structures up to 16 bytes are returned in registers. */
1239 int struct_return
= ((TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
1240 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
1241 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
1242 && TYPE_LENGTH (valtype
) > 16);
1245 return RETURN_VALUE_STRUCT_CONVENTION
;
1247 DEBUGTRACE ("xtensa_return_value(...)\n");
1249 if (writebuf
!= NULL
)
1251 xtensa_store_return_value (valtype
, regcache
, writebuf
);
1254 if (readbuf
!= NULL
)
1256 gdb_assert (!struct_return
);
1257 xtensa_extract_return_value (valtype
, regcache
, readbuf
);
1259 return RETURN_VALUE_REGISTER_CONVENTION
;
1266 xtensa_push_dummy_call (struct gdbarch
*gdbarch
,
1267 struct value
*function
,
1268 struct regcache
*regcache
,
1271 struct value
**args
,
1274 CORE_ADDR struct_addr
)
1277 int size
, onstack_size
;
1278 gdb_byte
*buf
= (gdb_byte
*) alloca (16);
1280 struct argument_info
1282 const bfd_byte
*contents
;
1284 int onstack
; /* onstack == 0 => in reg */
1285 int align
; /* alignment */
1288 int offset
; /* stack offset if on stack */
1289 int regno
; /* regno if in register */
1293 struct argument_info
*arg_info
=
1294 (struct argument_info
*) alloca (nargs
* sizeof (struct argument_info
));
1298 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1300 if (xtensa_debug_level
> 3)
1303 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs
);
1304 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1305 "struct_addr=0x%x\n",
1306 (int) sp
, (int) struct_return
, (int) struct_addr
);
1308 for (i
= 0; i
< nargs
; i
++)
1310 struct value
*arg
= args
[i
];
1311 struct type
*arg_type
= check_typedef (value_type (arg
));
1312 fprintf_unfiltered (gdb_stdlog
, "%2d: %p %3d ",
1313 i
, arg
, TYPE_LENGTH (arg_type
));
1314 switch (TYPE_CODE (arg_type
))
1317 fprintf_unfiltered (gdb_stdlog
, "int");
1319 case TYPE_CODE_STRUCT
:
1320 fprintf_unfiltered (gdb_stdlog
, "struct");
1323 fprintf_unfiltered (gdb_stdlog
, "%3d", TYPE_CODE (arg_type
));
1326 fprintf_unfiltered (gdb_stdlog
, " %p\n",
1327 value_contents (arg
));
1331 /* First loop: collect information.
1332 Cast into type_long. (This shouldn't happen often for C because
1333 GDB already does this earlier.) It's possible that GDB could
1334 do it all the time but it's harmless to leave this code here. */
1341 size
= REGISTER_SIZE
;
1343 for (i
= 0; i
< nargs
; i
++)
1345 struct argument_info
*info
= &arg_info
[i
];
1346 struct value
*arg
= args
[i
];
1347 struct type
*arg_type
= check_typedef (value_type (arg
));
1349 switch (TYPE_CODE (arg_type
))
1352 case TYPE_CODE_BOOL
:
1353 case TYPE_CODE_CHAR
:
1354 case TYPE_CODE_RANGE
:
1355 case TYPE_CODE_ENUM
:
1357 /* Cast argument to long if necessary as the mask does it too. */
1358 if (TYPE_LENGTH (arg_type
) < TYPE_LENGTH (builtin_type_long
))
1360 arg_type
= builtin_type_long
;
1361 arg
= value_cast (arg_type
, arg
);
1363 info
->align
= TYPE_LENGTH (builtin_type_long
);
1368 /* Align doubles correctly. */
1369 if (TYPE_LENGTH (arg_type
) == TYPE_LENGTH (builtin_type_double
))
1370 info
->align
= TYPE_LENGTH (builtin_type_double
);
1372 info
->align
= TYPE_LENGTH (builtin_type_long
);
1375 case TYPE_CODE_STRUCT
:
1377 info
->align
= TYPE_LENGTH (builtin_type_long
);
1380 info
->length
= TYPE_LENGTH (arg_type
);
1381 info
->contents
= value_contents (arg
);
1383 /* Align size and onstack_size. */
1384 size
= (size
+ info
->align
- 1) & ~(info
->align
- 1);
1385 onstack_size
= (onstack_size
+ info
->align
- 1) & ~(info
->align
- 1);
1387 if (size
+ info
->length
> REGISTER_SIZE
* ARGS_NUM_REGS
)
1390 info
->u
.offset
= onstack_size
;
1391 onstack_size
+= info
->length
;
1396 info
->u
.regno
= ARGS_FIRST_REG
+ size
/ REGISTER_SIZE
;
1398 size
+= info
->length
;
1401 /* Adjust the stack pointer and align it. */
1402 sp
= align_down (sp
- onstack_size
, SP_ALIGNMENT
);
1404 /* Simulate MOVSP. */
1407 read_memory (osp
- 16, buf
, 16);
1408 write_memory (sp
- 16, buf
, 16);
1411 /* Second Loop: Load arguments. */
1415 store_unsigned_integer (buf
, REGISTER_SIZE
, struct_addr
);
1416 regcache_cooked_write (regcache
, ARGS_FIRST_REG
, buf
);
1419 for (i
= 0; i
< nargs
; i
++)
1421 struct argument_info
*info
= &arg_info
[i
];
1425 int n
= info
->length
;
1426 CORE_ADDR offset
= sp
+ info
->u
.offset
;
1428 /* Odd-sized structs are aligned to the lower side of a memory
1429 word in big-endian mode and require a shift. This only
1430 applies for structures smaller than one word. */
1432 if (n
< REGISTER_SIZE
1433 && gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1434 offset
+= (REGISTER_SIZE
- n
);
1436 write_memory (offset
, info
->contents
, info
->length
);
1441 int n
= info
->length
;
1442 const bfd_byte
*cp
= info
->contents
;
1443 int r
= info
->u
.regno
;
1445 /* Odd-sized structs are aligned to the lower side of registers in
1446 big-endian mode and require a shift. The odd-sized leftover will
1447 be at the end. Note that this is only true for structures smaller
1448 than REGISTER_SIZE; for larger odd-sized structures the excess
1449 will be left-aligned in the register on both endiannesses. */
1451 if (n
< REGISTER_SIZE
1452 && gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1454 ULONGEST v
= extract_unsigned_integer (cp
, REGISTER_SIZE
);
1455 v
= v
>> ((REGISTER_SIZE
- n
) * TARGET_CHAR_BIT
);
1457 store_unsigned_integer (buf
, REGISTER_SIZE
, v
);
1458 regcache_cooked_write (regcache
, r
, buf
);
1460 cp
+= REGISTER_SIZE
;
1467 /* ULONGEST v = extract_unsigned_integer (cp, REGISTER_SIZE);*/
1468 regcache_cooked_write (regcache
, r
, cp
);
1470 /* write_register (r, v); */
1471 cp
+= REGISTER_SIZE
;
1479 /* Set the return address of dummy frame to the dummy address.
1480 Note: The return address for the current function (in A0) is
1481 saved in the dummy frame, so we can savely overwrite A0 here. */
1483 ra
= (bp_addr
& 0x3fffffff) | 0x40000000;
1484 regcache_raw_read (regcache
, PS_REGNUM
, buf
);
1485 ps
= extract_unsigned_integer (buf
, 4) & ~0x00030000;
1486 regcache_cooked_write_unsigned (regcache
, A4_REGNUM
, ra
);
1487 regcache_cooked_write_unsigned (regcache
, PS_REGNUM
, ps
| 0x00010000);
1489 /* Set new stack pointer and return it. */
1490 regcache_cooked_write_unsigned (regcache
, A1_REGNUM
, sp
);
1491 /* Make dummy frame ID unique by adding a constant. */
1492 return sp
+ SP_ALIGNMENT
;
1496 /* Return a breakpoint for the current location of PC. We always use
1497 the density version if we have density instructions (regardless of the
1498 current instruction at PC), and use regular instructions otherwise. */
1500 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1501 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1502 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1503 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1505 const unsigned char *
1506 xtensa_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
1508 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
1509 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
1510 static unsigned char density_big_breakpoint
[] = DENSITY_BIG_BREAKPOINT
;
1511 static unsigned char density_little_breakpoint
[] = DENSITY_LITTLE_BREAKPOINT
;
1513 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr
);
1515 if (ISA_USE_DENSITY_INSTRUCTIONS
)
1517 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1519 *lenptr
= sizeof (density_big_breakpoint
);
1520 return density_big_breakpoint
;
1524 *lenptr
= sizeof (density_little_breakpoint
);
1525 return density_little_breakpoint
;
1530 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
1532 *lenptr
= sizeof (big_breakpoint
);
1533 return big_breakpoint
;
1537 *lenptr
= sizeof (little_breakpoint
);
1538 return little_breakpoint
;
1544 /* Return the pc of the first real instruction. We assume that this
1545 machine uses register windows.
1547 If we have debug info ( line-number info, in particular ) we simply skip
1548 the code associated with the first function line effectively skipping
1549 the prologue code. It works even in cases like
1552 { int local_var = 1;
1556 because, for this source code, both Xtensa compilers will generate two
1557 separate entries ( with the same line number ) in dwarf line-number
1558 section to make sure there is a boundary between the prologue code and
1559 the rest of the function.
1561 If there is no debug info, we need to analyze the code. */
1564 xtensa_skip_prologue (CORE_ADDR start_pc
)
1566 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc
);
1568 if (ISA_USE_WINDOWED_REGISTERS
)
1571 struct symtab_and_line prologue_sal
;
1573 op1
= read_memory_integer (start_pc
, 1);
1574 if (!XTENSA_IS_ENTRY (op1
))
1577 prologue_sal
= find_pc_line (start_pc
, 0);
1578 if (prologue_sal
.line
!= 0)
1579 return prologue_sal
.end
;
1581 return start_pc
+ XTENSA_ENTRY_LENGTH
;
1585 internal_error (__FILE__
, __LINE__
,
1586 _("non-windowed configurations are not supported"));
1592 /* CONFIGURATION CHECK */
1594 /* Verify the current configuration. */
1597 xtensa_verify_config (struct gdbarch
*gdbarch
)
1599 struct ui_file
*log
;
1600 struct cleanup
*cleanups
;
1601 struct gdbarch_tdep
*tdep
;
1605 tdep
= gdbarch_tdep (gdbarch
);
1606 log
= mem_fileopen ();
1607 cleanups
= make_cleanup_ui_file_delete (log
);
1609 /* Verify that we got a reasonable number of AREGS. */
1610 if ((tdep
->num_aregs
& -tdep
->num_aregs
) != tdep
->num_aregs
)
1611 fprintf_unfiltered (log
, "\n\tnum_aregs: Number of AR registers (%d) "
1612 "is not a power of two!", tdep
->num_aregs
);
1614 /* Verify that certain registers exist. */
1615 if (tdep
->pc_regnum
== -1)
1616 fprintf_unfiltered (log
, "\n\tpc_regnum: No PC register");
1617 if (tdep
->ps_regnum
== -1)
1618 fprintf_unfiltered (log
, "\n\tps_regnum: No PS register");
1619 if (tdep
->wb_regnum
== -1)
1620 fprintf_unfiltered (log
, "\n\twb_regnum: No WB register");
1621 if (tdep
->ws_regnum
== -1)
1622 fprintf_unfiltered (log
, "\n\tws_regnum: No WS register");
1623 if (tdep
->ar_base
== -1)
1624 fprintf_unfiltered (log
, "\n\tar_base: No AR registers");
1625 if (tdep
->a0_base
== -1)
1626 fprintf_unfiltered (log
, "\n\ta0_base: No Ax registers");
1628 buf
= ui_file_xstrdup (log
, &dummy
);
1629 make_cleanup (xfree
, buf
);
1630 if (strlen (buf
) > 0)
1631 internal_error (__FILE__
, __LINE__
,
1632 _("the following are invalid: %s"), buf
);
1633 do_cleanups (cleanups
);
1637 /* Module "constructor" function. */
1639 static struct gdbarch
*
1640 xtensa_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1642 struct gdbarch_tdep
*tdep
;
1643 struct gdbarch
*gdbarch
;
1644 struct xtensa_abi_handler
*abi_handler
;
1646 DEBUGTRACE ("gdbarch_init()\n");
1648 /* We have to set the byte order before we call gdbarch_alloc. */
1649 info
.byte_order
= xtensa_config_byte_order (&info
);
1651 tdep
= xtensa_config_tdep (&info
);
1652 gdbarch
= gdbarch_alloc (&info
, tdep
);
1654 /* Verify our configuration. */
1655 xtensa_verify_config (gdbarch
);
1657 /* Pseudo-Register read/write */
1658 set_gdbarch_pseudo_register_read (gdbarch
, xtensa_pseudo_register_read
);
1659 set_gdbarch_pseudo_register_write (gdbarch
, xtensa_pseudo_register_write
);
1661 /* Set target information. */
1662 set_gdbarch_num_regs (gdbarch
, tdep
->num_regs
);
1663 set_gdbarch_num_pseudo_regs (gdbarch
, tdep
->num_pseudo_regs
);
1664 set_gdbarch_sp_regnum (gdbarch
, tdep
->a0_base
+ 1);
1665 set_gdbarch_pc_regnum (gdbarch
, tdep
->pc_regnum
);
1666 set_gdbarch_ps_regnum (gdbarch
, tdep
->ps_regnum
);
1668 /* Renumber registers for known formats (stab, dwarf, and dwarf2). */
1669 set_gdbarch_stab_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
1670 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
1671 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
1673 /* We provide our own function to get register information. */
1674 set_gdbarch_register_name (gdbarch
, xtensa_register_name
);
1675 set_gdbarch_register_type (gdbarch
, xtensa_register_type
);
1677 /* To call functions from GDB using dummy frame */
1678 set_gdbarch_push_dummy_call (gdbarch
, xtensa_push_dummy_call
);
1680 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
1682 set_gdbarch_return_value (gdbarch
, xtensa_return_value
);
1684 /* Advance PC across any prologue instructions to reach "real" code. */
1685 set_gdbarch_skip_prologue (gdbarch
, xtensa_skip_prologue
);
1687 /* Stack grows downward. */
1688 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1690 /* Set breakpoints. */
1691 set_gdbarch_breakpoint_from_pc (gdbarch
, xtensa_breakpoint_from_pc
);
1693 /* After breakpoint instruction or illegal instruction, pc still
1694 points at break instruction, so don't decrement. */
1695 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
1697 /* We don't skip args. */
1698 set_gdbarch_frame_args_skip (gdbarch
, 0);
1700 set_gdbarch_unwind_pc (gdbarch
, xtensa_unwind_pc
);
1702 set_gdbarch_frame_align (gdbarch
, xtensa_frame_align
);
1704 set_gdbarch_unwind_dummy_id (gdbarch
, xtensa_unwind_dummy_id
);
1706 /* Frame handling. */
1707 frame_base_set_default (gdbarch
, &xtensa_frame_base
);
1708 frame_unwind_append_sniffer (gdbarch
, xtensa_frame_sniffer
);
1710 set_gdbarch_print_insn (gdbarch
, print_insn_xtensa
);
1712 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
1714 xtensa_add_reggroups (gdbarch
);
1715 set_gdbarch_register_reggroup_p (gdbarch
, xtensa_register_reggroup_p
);
1717 set_gdbarch_regset_from_core_section (gdbarch
,
1718 xtensa_regset_from_core_section
);
1724 /* Dump xtensa tdep structure. */
1727 xtensa_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
1729 error (_("xtensa_dump_tdep(): not implemented"));
1734 _initialize_xtensa_tdep (void)
1736 struct cmd_list_element
*c
;
1738 gdbarch_register (bfd_arch_xtensa
, xtensa_gdbarch_init
, xtensa_dump_tdep
);
1739 xtensa_init_reggroups ();
1741 add_setshow_zinteger_cmd ("xtensa",
1743 &xtensa_debug_level
, _("\
1744 Set Xtensa debugging."), _("\
1745 Show Xtensa debugging."), _("\
1746 When non-zero, Xtensa-specific debugging is enabled. \
1747 Can be 1, 2, 3, or 4 indicating the level of debugging."),
1750 &setdebuglist
, &showdebuglist
);