1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "solib-svr4.h"
32 #include "floatformat.h"
34 #include "reggroups.h"
37 #include "dummy-frame.h"
38 #include "elf/dwarf2.h"
39 #include "dwarf2-frame.h"
40 #include "dwarf2loc.h"
42 #include "frame-base.h"
43 #include "frame-unwind.h"
45 #include "arch-utils.h"
52 #include "gdb_assert.h"
54 #include "xtensa-isa.h"
55 #include "xtensa-tdep.h"
56 #include "xtensa-config.h"
59 static int xtensa_debug_level
= 0;
61 #define DEBUGWARN(args...) \
62 if (xtensa_debug_level > 0) \
63 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
65 #define DEBUGINFO(args...) \
66 if (xtensa_debug_level > 1) \
67 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
69 #define DEBUGTRACE(args...) \
70 if (xtensa_debug_level > 2) \
71 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
73 #define DEBUGVERB(args...) \
74 if (xtensa_debug_level > 3) \
75 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
78 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
79 #define SP_ALIGNMENT 16
82 /* On Windowed ABI, we use a6 through a11 for passing arguments
83 to a function called by GDB because CALL4 is used. */
84 #define ARGS_NUM_REGS 6
85 #define REGISTER_SIZE 4
88 /* Extract the call size from the return address or PS register. */
89 #define PS_CALLINC_SHIFT 16
90 #define PS_CALLINC_MASK 0x00030000
91 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
92 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
94 /* ABI-independent macros. */
95 #define ARG_NOF(gdbarch) \
96 (gdbarch_tdep (gdbarch)->call_abi \
97 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
98 #define ARG_1ST(gdbarch) \
99 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
100 ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \
101 : (gdbarch_tdep (gdbarch)->a0_base + 6))
103 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
104 indicates that the instruction is an ENTRY instruction. */
106 #define XTENSA_IS_ENTRY(gdbarch, op1) \
107 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
108 ? ((op1) == 0x6c) : ((op1) == 0x36))
110 #define XTENSA_ENTRY_LENGTH 3
112 /* windowing_enabled() returns true, if windowing is enabled.
113 WOE must be set to 1; EXCM to 0.
114 Note: We assume that EXCM is always 0 for XEA1. */
116 #define PS_WOE (1<<18)
117 #define PS_EXC (1<<4)
119 /* Convert a live A-register number to the corresponding AR-register number. */
121 arreg_number (struct gdbarch
*gdbarch
, int a_regnum
, ULONGEST wb
)
123 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
126 arreg
= a_regnum
- tdep
->a0_base
;
127 arreg
+= (wb
& ((tdep
->num_aregs
- 1) >> 2)) << WB_SHIFT
;
128 arreg
&= tdep
->num_aregs
- 1;
130 return arreg
+ tdep
->ar_base
;
133 /* Convert a live AR-register number to the corresponding A-register order
134 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
136 areg_number (struct gdbarch
*gdbarch
, int ar_regnum
, unsigned int wb
)
138 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
141 areg
= ar_regnum
- tdep
->ar_base
;
142 if (areg
< 0 || areg
>= tdep
->num_aregs
)
144 areg
= (areg
- wb
* 4) & (tdep
->num_aregs
- 1);
145 return (areg
> 15) ? -1 : areg
;
149 windowing_enabled (CORE_ADDR ps
)
151 return ((ps
& PS_EXC
) == 0 && (ps
& PS_WOE
) != 0);
154 /* Return the window size of the previous call to the function from which we
157 This function is used to extract the return value after a called function
158 has returned to the caller. On Xtensa, the register that holds the return
159 value (from the perspective of the caller) depends on what call
160 instruction was used. For now, we are assuming that the call instruction
161 precedes the current address, so we simply analyze the call instruction.
162 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
163 method to call the inferior function. */
166 extract_call_winsize (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
172 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc
);
174 /* Read the previous instruction (should be a call[x]{4|8|12}. */
175 read_memory (pc
-3, buf
, 3);
176 insn
= extract_unsigned_integer (buf
, 3);
178 /* Decode call instruction:
180 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
181 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
183 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
184 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
186 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
188 if (((insn
& 0xf) == 0x5) || ((insn
& 0xcf) == 0xc0))
189 winsize
= (insn
& 0x30) >> 2; /* 0, 4, 8, 12. */
193 if (((insn
>> 20) == 0x5) || (((insn
>> 16) & 0xf3) == 0x03))
194 winsize
= (insn
>> 16) & 0xc; /* 0, 4, 8, 12. */
200 /* REGISTER INFORMATION */
202 /* Returns the name of a register. */
204 xtensa_register_name (struct gdbarch
*gdbarch
, int regnum
)
206 /* Return the name stored in the register map. */
207 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
)
208 + gdbarch_num_pseudo_regs (gdbarch
))
209 return gdbarch_tdep (gdbarch
)->regmap
[regnum
].name
;
211 internal_error (__FILE__
, __LINE__
, _("invalid register %d"), regnum
);
215 /* Return the type of a register. Create a new type, if necessary. */
218 xtensa_register_type (struct gdbarch
*gdbarch
, int regnum
)
220 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
222 /* Return signed integer for ARx and Ax registers. */
223 if ((regnum
>= tdep
->ar_base
224 && regnum
< tdep
->ar_base
+ tdep
->num_aregs
)
225 || (regnum
>= tdep
->a0_base
226 && regnum
< tdep
->a0_base
+ 16))
227 return builtin_type (gdbarch
)->builtin_int
;
229 if (regnum
== gdbarch_pc_regnum (gdbarch
)
230 || regnum
== tdep
->a0_base
+ 1)
231 return builtin_type (gdbarch
)->builtin_data_ptr
;
233 /* Return the stored type for all other registers. */
234 else if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
)
235 + gdbarch_num_pseudo_regs (gdbarch
))
237 xtensa_register_t
* reg
= &tdep
->regmap
[regnum
];
239 /* Set ctype for this register (only the first time). */
243 struct ctype_cache
*tp
;
244 int size
= reg
->byte_size
;
246 /* We always use the memory representation,
247 even if the register width is smaller. */
251 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint8
;
255 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint16
;
259 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint32
;
263 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint64
;
267 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint128
;
271 for (tp
= tdep
->type_entries
; tp
!= NULL
; tp
= tp
->next
)
272 if (tp
->size
== size
)
277 char *name
= xmalloc (16);
278 tp
= xmalloc (sizeof (struct ctype_cache
));
279 tp
->next
= tdep
->type_entries
;
280 tdep
->type_entries
= tp
;
283 sprintf (name
, "int%d", size
* 8);
284 tp
->virtual_type
= init_type (TYPE_CODE_INT
, size
,
285 TYPE_FLAG_UNSIGNED
, name
,
289 reg
->ctype
= tp
->virtual_type
;
295 internal_error (__FILE__
, __LINE__
, _("invalid register number %d"), regnum
);
300 /* Return the 'local' register number for stubs, dwarf2, etc.
301 The debugging information enumerates registers starting from 0 for A0
302 to n for An. So, we only have to add the base number for A0. */
305 xtensa_reg_to_regnum (struct gdbarch
*gdbarch
, int regnum
)
309 if (regnum
>= 0 && regnum
< 16)
310 return gdbarch_tdep (gdbarch
)->a0_base
+ regnum
;
313 i
< gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
315 if (regnum
== gdbarch_tdep (gdbarch
)->regmap
[i
].target_number
)
318 internal_error (__FILE__
, __LINE__
,
319 _("invalid dwarf/stabs register number %d"), regnum
);
324 /* Write the bits of a masked register to the various registers.
325 Only the masked areas of these registers are modified; the other
326 fields are untouched. The size of masked registers is always less
327 than or equal to 32 bits. */
330 xtensa_register_write_masked (struct regcache
*regcache
,
331 xtensa_register_t
*reg
, const gdb_byte
*buffer
)
333 unsigned int value
[(MAX_REGISTER_SIZE
+ 3) / 4];
334 const xtensa_mask_t
*mask
= reg
->mask
;
336 int shift
= 0; /* Shift for next mask (mod 32). */
337 int start
, size
; /* Start bit and size of current mask. */
339 unsigned int *ptr
= value
;
340 unsigned int regval
, m
, mem
= 0;
342 int bytesize
= reg
->byte_size
;
343 int bitsize
= bytesize
* 8;
346 DEBUGTRACE ("xtensa_register_write_masked ()\n");
348 /* Copy the masked register to host byte-order. */
349 if (gdbarch_byte_order (get_regcache_arch (regcache
)) == BFD_ENDIAN_BIG
)
350 for (i
= 0; i
< bytesize
; i
++)
353 mem
|= (buffer
[bytesize
- i
- 1] << 24);
358 for (i
= 0; i
< bytesize
; i
++)
361 mem
|= (buffer
[i
] << 24);
366 /* We might have to shift the final value:
367 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
368 bytesize & 3 == x -> shift (4-x) * 8. */
370 *ptr
= mem
>> (((0 - bytesize
) & 3) * 8);
374 /* Write the bits to the masked areas of the other registers. */
375 for (i
= 0; i
< mask
->count
; i
++)
377 start
= mask
->mask
[i
].bit_start
;
378 size
= mask
->mask
[i
].bit_size
;
379 regval
= mem
>> shift
;
381 if ((shift
+= size
) > bitsize
)
382 error (_("size of all masks is larger than the register"));
391 regval
|= mem
<< (size
- shift
);
394 /* Make sure we have a valid register. */
395 r
= mask
->mask
[i
].reg_num
;
396 if (r
>= 0 && size
> 0)
398 /* Don't overwrite the unmasked areas. */
400 regcache_cooked_read_unsigned (regcache
, r
, &old_val
);
401 m
= 0xffffffff >> (32 - size
) << start
;
403 regval
= (regval
& m
) | (old_val
& ~m
);
404 regcache_cooked_write_unsigned (regcache
, r
, regval
);
410 /* Read a tie state or mapped registers. Read the masked areas
411 of the registers and assemble them into a single value. */
414 xtensa_register_read_masked (struct regcache
*regcache
,
415 xtensa_register_t
*reg
, gdb_byte
*buffer
)
417 unsigned int value
[(MAX_REGISTER_SIZE
+ 3) / 4];
418 const xtensa_mask_t
*mask
= reg
->mask
;
423 unsigned int *ptr
= value
;
424 unsigned int regval
, mem
= 0;
426 int bytesize
= reg
->byte_size
;
427 int bitsize
= bytesize
* 8;
430 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
431 reg
->name
== 0 ? "" : reg
->name
);
433 /* Assemble the register from the masked areas of other registers. */
434 for (i
= 0; i
< mask
->count
; i
++)
436 int r
= mask
->mask
[i
].reg_num
;
440 regcache_cooked_read_unsigned (regcache
, r
, &val
);
441 regval
= (unsigned int) val
;
446 start
= mask
->mask
[i
].bit_start
;
447 size
= mask
->mask
[i
].bit_size
;
452 regval
&= (0xffffffff >> (32 - size
));
454 mem
|= regval
<< shift
;
456 if ((shift
+= size
) > bitsize
)
457 error (_("size of all masks is larger than the register"));
468 mem
= regval
>> (size
- shift
);
475 /* Copy value to target byte order. */
479 if (gdbarch_byte_order (get_regcache_arch (regcache
)) == BFD_ENDIAN_BIG
)
480 for (i
= 0; i
< bytesize
; i
++)
484 buffer
[bytesize
- i
- 1] = mem
& 0xff;
488 for (i
= 0; i
< bytesize
; i
++)
492 buffer
[i
] = mem
& 0xff;
498 /* Read pseudo registers. */
501 xtensa_pseudo_register_read (struct gdbarch
*gdbarch
,
502 struct regcache
*regcache
,
506 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
507 regnum
, xtensa_register_name (gdbarch
, regnum
));
509 if (regnum
== gdbarch_num_regs (gdbarch
)
510 + gdbarch_num_pseudo_regs (gdbarch
) - 1)
511 regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ 1;
513 /* Read aliases a0..a15, if this is a Windowed ABI. */
514 if (gdbarch_tdep (gdbarch
)->isa_use_windowed_registers
515 && (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
)
516 && (regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15))
518 gdb_byte
*buf
= (gdb_byte
*) alloca (MAX_REGISTER_SIZE
);
520 regcache_raw_read (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, buf
);
521 regnum
= arreg_number (gdbarch
, regnum
,
522 extract_unsigned_integer (buf
, 4));
525 /* We can always read non-pseudo registers. */
526 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
527 regcache_raw_read (regcache
, regnum
, buffer
);
530 /* We have to find out how to deal with priveleged registers.
531 Let's treat them as pseudo-registers, but we cannot read/write them. */
533 else if (regnum
< gdbarch_tdep (gdbarch
)->a0_base
)
535 buffer
[0] = (gdb_byte
)0;
536 buffer
[1] = (gdb_byte
)0;
537 buffer
[2] = (gdb_byte
)0;
538 buffer
[3] = (gdb_byte
)0;
540 /* Pseudo registers. */
542 && regnum
< gdbarch_num_regs (gdbarch
)
543 + gdbarch_num_pseudo_regs (gdbarch
))
545 xtensa_register_t
*reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
546 xtensa_register_type_t type
= reg
->type
;
547 int flags
= gdbarch_tdep (gdbarch
)->target_flags
;
549 /* We cannot read Unknown or Unmapped registers. */
550 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
552 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
554 warning (_("cannot read register %s"),
555 xtensa_register_name (gdbarch
, regnum
));
560 /* Some targets cannot read TIE register files. */
561 else if (type
== xtRegisterTypeTieRegfile
)
563 /* Use 'fetch' to get register? */
564 if (flags
& xtTargetFlagsUseFetchStore
)
566 warning (_("cannot read register"));
570 /* On some targets (esp. simulators), we can always read the reg. */
571 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
573 warning (_("cannot read register"));
578 /* We can always read mapped registers. */
579 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
581 xtensa_register_read_masked (regcache
, reg
, buffer
);
585 /* Assume that we can read the register. */
586 regcache_raw_read (regcache
, regnum
, buffer
);
589 internal_error (__FILE__
, __LINE__
,
590 _("invalid register number %d"), regnum
);
594 /* Write pseudo registers. */
597 xtensa_pseudo_register_write (struct gdbarch
*gdbarch
,
598 struct regcache
*regcache
,
600 const gdb_byte
*buffer
)
602 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
603 regnum
, xtensa_register_name (gdbarch
, regnum
));
605 if (regnum
== gdbarch_num_regs (gdbarch
)
606 + gdbarch_num_pseudo_regs (gdbarch
) -1)
607 regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ 1;
609 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
610 if (gdbarch_tdep (gdbarch
)->isa_use_windowed_registers
611 && (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
)
612 && (regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15))
614 gdb_byte
*buf
= (gdb_byte
*) alloca (MAX_REGISTER_SIZE
);
617 regcache_raw_read (regcache
,
618 gdbarch_tdep (gdbarch
)->wb_regnum
, buf
);
619 regnum
= arreg_number (gdbarch
, regnum
,
620 extract_unsigned_integer (buf
, 4));
623 /* We can always write 'core' registers.
624 Note: We might have converted Ax->ARy. */
625 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
626 regcache_raw_write (regcache
, regnum
, buffer
);
628 /* We have to find out how to deal with priveleged registers.
629 Let's treat them as pseudo-registers, but we cannot read/write them. */
631 else if (regnum
< gdbarch_tdep (gdbarch
)->a0_base
)
635 /* Pseudo registers. */
637 && regnum
< gdbarch_num_regs (gdbarch
)
638 + gdbarch_num_pseudo_regs (gdbarch
))
640 xtensa_register_t
*reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
641 xtensa_register_type_t type
= reg
->type
;
642 int flags
= gdbarch_tdep (gdbarch
)->target_flags
;
644 /* On most targets, we cannot write registers
645 of type "Unknown" or "Unmapped". */
646 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
648 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
650 warning (_("cannot write register %s"),
651 xtensa_register_name (gdbarch
, regnum
));
656 /* Some targets cannot read TIE register files. */
657 else if (type
== xtRegisterTypeTieRegfile
)
659 /* Use 'store' to get register? */
660 if (flags
& xtTargetFlagsUseFetchStore
)
662 warning (_("cannot write register"));
666 /* On some targets (esp. simulators), we can always write
668 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
670 warning (_("cannot write register"));
675 /* We can always write mapped registers. */
676 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
678 xtensa_register_write_masked (regcache
, reg
, buffer
);
682 /* Assume that we can write the register. */
683 regcache_raw_write (regcache
, regnum
, buffer
);
686 internal_error (__FILE__
, __LINE__
,
687 _("invalid register number %d"), regnum
);
690 static struct reggroup
*xtensa_ar_reggroup
;
691 static struct reggroup
*xtensa_user_reggroup
;
692 static struct reggroup
*xtensa_vectra_reggroup
;
693 static struct reggroup
*xtensa_cp
[XTENSA_MAX_COPROCESSOR
];
696 xtensa_init_reggroups (void)
698 xtensa_ar_reggroup
= reggroup_new ("ar", USER_REGGROUP
);
699 xtensa_user_reggroup
= reggroup_new ("user", USER_REGGROUP
);
700 xtensa_vectra_reggroup
= reggroup_new ("vectra", USER_REGGROUP
);
702 xtensa_cp
[0] = reggroup_new ("cp0", USER_REGGROUP
);
703 xtensa_cp
[1] = reggroup_new ("cp1", USER_REGGROUP
);
704 xtensa_cp
[2] = reggroup_new ("cp2", USER_REGGROUP
);
705 xtensa_cp
[3] = reggroup_new ("cp3", USER_REGGROUP
);
706 xtensa_cp
[4] = reggroup_new ("cp4", USER_REGGROUP
);
707 xtensa_cp
[5] = reggroup_new ("cp5", USER_REGGROUP
);
708 xtensa_cp
[6] = reggroup_new ("cp6", USER_REGGROUP
);
709 xtensa_cp
[7] = reggroup_new ("cp7", USER_REGGROUP
);
713 xtensa_add_reggroups (struct gdbarch
*gdbarch
)
717 /* Predefined groups. */
718 reggroup_add (gdbarch
, all_reggroup
);
719 reggroup_add (gdbarch
, save_reggroup
);
720 reggroup_add (gdbarch
, restore_reggroup
);
721 reggroup_add (gdbarch
, system_reggroup
);
722 reggroup_add (gdbarch
, vector_reggroup
);
723 reggroup_add (gdbarch
, general_reggroup
);
724 reggroup_add (gdbarch
, float_reggroup
);
726 /* Xtensa-specific groups. */
727 reggroup_add (gdbarch
, xtensa_ar_reggroup
);
728 reggroup_add (gdbarch
, xtensa_user_reggroup
);
729 reggroup_add (gdbarch
, xtensa_vectra_reggroup
);
731 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
732 reggroup_add (gdbarch
, xtensa_cp
[i
]);
736 xtensa_coprocessor_register_group (struct reggroup
*group
)
740 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
741 if (group
== xtensa_cp
[i
])
747 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
748 | XTENSA_REGISTER_FLAGS_WRITABLE \
749 | XTENSA_REGISTER_FLAGS_VOLATILE)
751 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
752 | XTENSA_REGISTER_FLAGS_WRITABLE)
755 xtensa_register_reggroup_p (struct gdbarch
*gdbarch
,
757 struct reggroup
*group
)
759 xtensa_register_t
* reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
760 xtensa_register_type_t type
= reg
->type
;
761 xtensa_register_group_t rg
= reg
->group
;
764 /* First, skip registers that are not visible to this target
765 (unknown and unmapped registers when not using ISS). */
767 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
769 if (group
== all_reggroup
)
771 if (group
== xtensa_ar_reggroup
)
772 return rg
& xtRegisterGroupAddrReg
;
773 if (group
== xtensa_user_reggroup
)
774 return rg
& xtRegisterGroupUser
;
775 if (group
== float_reggroup
)
776 return rg
& xtRegisterGroupFloat
;
777 if (group
== general_reggroup
)
778 return rg
& xtRegisterGroupGeneral
;
779 if (group
== float_reggroup
)
780 return rg
& xtRegisterGroupFloat
;
781 if (group
== system_reggroup
)
782 return rg
& xtRegisterGroupState
;
783 if (group
== vector_reggroup
|| group
== xtensa_vectra_reggroup
)
784 return rg
& xtRegisterGroupVectra
;
785 if (group
== save_reggroup
|| group
== restore_reggroup
)
786 return (regnum
< gdbarch_num_regs (gdbarch
)
787 && (reg
->flags
& SAVE_REST_FLAGS
) == SAVE_REST_VALID
);
788 if ((cp_number
= xtensa_coprocessor_register_group (group
)) >= 0)
789 return rg
& (xtRegisterGroupCP0
<< cp_number
);
795 /* Supply register REGNUM from the buffer specified by GREGS and LEN
796 in the general-purpose register set REGSET to register cache
797 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
800 xtensa_supply_gregset (const struct regset
*regset
,
806 const xtensa_elf_gregset_t
*regs
= gregs
;
807 struct gdbarch
*gdbarch
= get_regcache_arch (rc
);
810 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...) \n", regnum
);
812 if (regnum
== gdbarch_pc_regnum (gdbarch
) || regnum
== -1)
813 regcache_raw_supply (rc
, gdbarch_pc_regnum (gdbarch
), (char *) ®s
->pc
);
814 if (regnum
== gdbarch_ps_regnum (gdbarch
) || regnum
== -1)
815 regcache_raw_supply (rc
, gdbarch_ps_regnum (gdbarch
), (char *) ®s
->ps
);
816 if (regnum
== gdbarch_tdep (gdbarch
)->wb_regnum
|| regnum
== -1)
817 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->wb_regnum
,
818 (char *) ®s
->windowbase
);
819 if (regnum
== gdbarch_tdep (gdbarch
)->ws_regnum
|| regnum
== -1)
820 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->ws_regnum
,
821 (char *) ®s
->windowstart
);
822 if (regnum
== gdbarch_tdep (gdbarch
)->lbeg_regnum
|| regnum
== -1)
823 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lbeg_regnum
,
824 (char *) ®s
->lbeg
);
825 if (regnum
== gdbarch_tdep (gdbarch
)->lend_regnum
|| regnum
== -1)
826 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lend_regnum
,
827 (char *) ®s
->lend
);
828 if (regnum
== gdbarch_tdep (gdbarch
)->lcount_regnum
|| regnum
== -1)
829 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lcount_regnum
,
830 (char *) ®s
->lcount
);
831 if (regnum
== gdbarch_tdep (gdbarch
)->sar_regnum
|| regnum
== -1)
832 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->sar_regnum
,
833 (char *) ®s
->sar
);
834 if (regnum
>=gdbarch_tdep (gdbarch
)->ar_base
835 && regnum
< gdbarch_tdep (gdbarch
)->ar_base
836 + gdbarch_tdep (gdbarch
)->num_aregs
)
837 regcache_raw_supply (rc
, regnum
,
838 (char *) ®s
->ar
[regnum
- gdbarch_tdep
839 (gdbarch
)->ar_base
]);
840 else if (regnum
== -1)
842 for (i
= 0; i
< gdbarch_tdep (gdbarch
)->num_aregs
; ++i
)
843 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->ar_base
+ i
,
844 (char *) ®s
->ar
[i
]);
849 /* Xtensa register set. */
855 xtensa_supply_gregset
859 /* Return the appropriate register set for the core
860 section identified by SECT_NAME and SECT_SIZE. */
862 static const struct regset
*
863 xtensa_regset_from_core_section (struct gdbarch
*core_arch
,
864 const char *sect_name
,
867 DEBUGTRACE ("xtensa_regset_from_core_section "
868 "(..., sect_name==\"%s\", sect_size==%x) \n",
869 sect_name
, (unsigned int) sect_size
);
871 if (strcmp (sect_name
, ".reg") == 0
872 && sect_size
>= sizeof(xtensa_elf_gregset_t
))
873 return &xtensa_gregset
;
879 /* Handling frames. */
881 /* Number of registers to save in case of Windowed ABI. */
882 #define XTENSA_NUM_SAVED_AREGS 12
884 /* Frame cache part for Windowed ABI. */
885 typedef struct xtensa_windowed_frame_cache
887 int wb
; /* WINDOWBASE of the previous frame. */
888 int callsize
; /* Call size of this frame. */
889 int ws
; /* WINDOWSTART of the previous frame. It keeps track of
890 life windows only. If there is no bit set for the
891 window, that means it had been already spilled
892 because of window overflow. */
894 /* Spilled A-registers from the previous frame.
895 AREGS[i] == -1, if corresponding AR is alive. */
896 CORE_ADDR aregs
[XTENSA_NUM_SAVED_AREGS
];
897 } xtensa_windowed_frame_cache_t
;
899 /* Call0 ABI Definitions. */
901 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue analysis. */
902 #define C0_NREGS 16 /* Number of A-registers to track. */
903 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
904 #define C0_SP 1 /* Register used as SP. */
905 #define C0_FP 15 /* Register used as FP. */
906 #define C0_RA 0 /* Register used as return address. */
907 #define C0_ARGS 2 /* Register used as first arg/retval. */
908 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
910 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
911 A-register where the current content of the reg came from (in terms
912 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
913 mean that the orignal content of the register was saved to the stack.
914 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
915 know where SP will end up until the entire prologue has been analyzed. */
917 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
918 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
919 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
921 extern xtensa_isa xtensa_default_isa
;
923 typedef struct xtensa_c0reg
925 int fr_reg
; /* original register from which register content
926 is derived, or C0_CONST, or C0_INEXP. */
927 int fr_ofs
; /* constant offset from reg, or immediate value. */
928 int to_stk
; /* offset from original SP to register (4-byte aligned),
929 or C0_NOSTK if register has not been saved. */
933 /* Frame cache part for Call0 ABI. */
934 typedef struct xtensa_call0_frame_cache
936 int c0_frmsz
; /* Stack frame size. */
937 int c0_hasfp
; /* Current frame uses frame pointer. */
938 int fp_regnum
; /* A-register used as FP. */
939 int c0_fp
; /* Actual value of frame pointer. */
940 xtensa_c0reg_t c0_rt
[C0_NREGS
]; /* Register tracking information. */
941 } xtensa_call0_frame_cache_t
;
943 typedef struct xtensa_frame_cache
945 CORE_ADDR base
; /* Stack pointer of this frame. */
946 CORE_ADDR pc
; /* PC at the entry point to the function. */
947 CORE_ADDR ra
; /* The raw return address (without CALLINC). */
948 CORE_ADDR ps
; /* The PS register of this frame. */
949 CORE_ADDR prev_sp
; /* Stack Pointer of the previous frame. */
950 int call0
; /* It's a call0 framework (else windowed). */
953 xtensa_windowed_frame_cache_t wd
; /* call0 == false. */
954 xtensa_call0_frame_cache_t c0
; /* call0 == true. */
956 } xtensa_frame_cache_t
;
959 static struct xtensa_frame_cache
*
960 xtensa_alloc_frame_cache (int windowed
)
962 xtensa_frame_cache_t
*cache
;
965 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
967 cache
= FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t
);
974 cache
->call0
= !windowed
;
977 cache
->c0
.c0_frmsz
= -1;
978 cache
->c0
.c0_hasfp
= 0;
979 cache
->c0
.fp_regnum
= -1;
980 cache
->c0
.c0_fp
= -1;
982 for (i
= 0; i
< C0_NREGS
; i
++)
984 cache
->c0
.c0_rt
[i
].fr_reg
= i
;
985 cache
->c0
.c0_rt
[i
].fr_ofs
= 0;
986 cache
->c0
.c0_rt
[i
].to_stk
= C0_NOSTK
;
993 cache
->wd
.callsize
= -1;
995 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
996 cache
->wd
.aregs
[i
] = -1;
1003 xtensa_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
1005 return address
& ~15;
1010 xtensa_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1015 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1016 host_address_to_string (next_frame
));
1018 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1019 pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1021 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc
);
1027 static struct frame_id
1028 xtensa_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1032 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1034 pc
= get_frame_pc (this_frame
);
1035 fp
= get_frame_register_unsigned
1036 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1038 /* Make dummy frame ID unique by adding a constant. */
1039 return frame_id_build (fp
+ SP_ALIGNMENT
, pc
);
1042 /* Returns the best guess about which register is a frame pointer
1043 for the function containing CURRENT_PC. */
1045 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1048 xtensa_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR current_pc
)
1050 #define RETURN_FP goto done
1052 unsigned int fp_regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ 1;
1053 CORE_ADDR start_addr
;
1055 xtensa_insnbuf ins
, slot
;
1056 char ibuf
[XTENSA_ISA_BSZ
];
1057 CORE_ADDR ia
, bt
, ba
;
1059 int ilen
, islots
, is
;
1061 const char *opcname
;
1063 find_pc_partial_function (current_pc
, NULL
, &start_addr
, NULL
);
1064 if (start_addr
== 0)
1067 if (!xtensa_default_isa
)
1068 xtensa_default_isa
= xtensa_isa_init (0, 0);
1069 isa
= xtensa_default_isa
;
1070 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
1071 ins
= xtensa_insnbuf_alloc (isa
);
1072 slot
= xtensa_insnbuf_alloc (isa
);
1075 for (ia
= start_addr
, bt
= ia
; ia
< current_pc
; ia
+= ilen
)
1077 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
1080 bt
= (ba
+ XTENSA_ISA_BSZ
) < current_pc
1081 ? ba
+ XTENSA_ISA_BSZ
: current_pc
;
1082 read_memory (ba
, ibuf
, bt
- ba
);
1085 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
1086 ifmt
= xtensa_format_decode (isa
, ins
);
1087 if (ifmt
== XTENSA_UNDEFINED
)
1089 ilen
= xtensa_format_length (isa
, ifmt
);
1090 if (ilen
== XTENSA_UNDEFINED
)
1092 islots
= xtensa_format_num_slots (isa
, ifmt
);
1093 if (islots
== XTENSA_UNDEFINED
)
1096 for (is
= 0; is
< islots
; ++is
)
1098 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
1101 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
1102 if (opc
== XTENSA_UNDEFINED
)
1105 opcname
= xtensa_opcode_name (isa
, opc
);
1107 if (strcasecmp (opcname
, "mov.n") == 0
1108 || strcasecmp (opcname
, "or") == 0)
1110 unsigned int register_operand
;
1112 /* Possible candidate for setting frame pointer
1113 from A1. This is what we are looking for. */
1115 if (xtensa_operand_get_field (isa
, opc
, 1, ifmt
,
1116 is
, slot
, ®ister_operand
) != 0)
1118 if (xtensa_operand_decode (isa
, opc
, 1, ®ister_operand
) != 0)
1120 if (register_operand
== 1) /* Mov{.n} FP A1. */
1122 if (xtensa_operand_get_field (isa
, opc
, 0, ifmt
, is
, slot
,
1123 ®ister_operand
) != 0)
1125 if (xtensa_operand_decode (isa
, opc
, 0,
1126 ®ister_operand
) != 0)
1129 fp_regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ register_operand
;
1135 /* We have problems decoding the memory. */
1137 || strcasecmp (opcname
, "ill") == 0
1138 || strcasecmp (opcname
, "ill.n") == 0
1139 /* Hit planted breakpoint. */
1140 || strcasecmp (opcname
, "break") == 0
1141 || strcasecmp (opcname
, "break.n") == 0
1142 /* Flow control instructions finish prologue. */
1143 || xtensa_opcode_is_branch (isa
, opc
) > 0
1144 || xtensa_opcode_is_jump (isa
, opc
) > 0
1145 || xtensa_opcode_is_loop (isa
, opc
) > 0
1146 || xtensa_opcode_is_call (isa
, opc
) > 0
1147 || strcasecmp (opcname
, "simcall") == 0
1148 || strcasecmp (opcname
, "syscall") == 0)
1149 /* Can not continue analysis. */
1154 xtensa_insnbuf_free(isa
, slot
);
1155 xtensa_insnbuf_free(isa
, ins
);
1159 /* The key values to identify the frame using "cache" are
1161 cache->base = SP (or best guess about FP) of this frame;
1162 cache->pc = entry-PC (entry point of the frame function);
1163 cache->prev_sp = SP of the previous frame.
1167 call0_frame_cache (struct frame_info
*this_frame
,
1168 xtensa_frame_cache_t
*cache
,
1169 CORE_ADDR pc
, CORE_ADDR litbase
);
1171 static struct xtensa_frame_cache
*
1172 xtensa_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1174 xtensa_frame_cache_t
*cache
;
1175 CORE_ADDR ra
, wb
, ws
, pc
, sp
, ps
;
1176 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1177 unsigned int fp_regnum
;
1184 ps
= get_frame_register_unsigned (this_frame
, gdbarch_ps_regnum (gdbarch
));
1185 windowed
= windowing_enabled (ps
);
1187 /* Get pristine xtensa-frame. */
1188 cache
= xtensa_alloc_frame_cache (windowed
);
1189 *this_cache
= cache
;
1191 pc
= get_frame_register_unsigned (this_frame
, gdbarch_pc_regnum (gdbarch
));
1195 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1196 wb
= get_frame_register_unsigned (this_frame
,
1197 gdbarch_tdep (gdbarch
)->wb_regnum
);
1198 ws
= get_frame_register_unsigned (this_frame
,
1199 gdbarch_tdep (gdbarch
)->ws_regnum
);
1201 op1
= read_memory_integer (pc
, 1);
1202 if (XTENSA_IS_ENTRY (gdbarch
, op1
))
1204 int callinc
= CALLINC (ps
);
1205 ra
= get_frame_register_unsigned
1206 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ callinc
* 4);
1208 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1209 cache
->wd
.callsize
= 0;
1212 cache
->prev_sp
= get_frame_register_unsigned
1213 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1215 /* This only can be the outermost frame since we are
1216 just about to execute ENTRY. SP hasn't been set yet.
1217 We can assume any frame size, because it does not
1218 matter, and, let's fake frame base in cache. */
1219 cache
->base
= cache
->prev_sp
+ 16;
1222 cache
->ra
= (cache
->pc
& 0xc0000000) | (ra
& 0x3fffffff);
1223 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1224 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1230 fp_regnum
= xtensa_scan_prologue (gdbarch
, pc
);
1231 ra
= get_frame_register_unsigned (this_frame
,
1232 gdbarch_tdep (gdbarch
)->a0_base
);
1233 cache
->wd
.callsize
= WINSIZE (ra
);
1234 cache
->wd
.wb
= (wb
- cache
->wd
.callsize
/ 4)
1235 & (gdbarch_tdep (gdbarch
)->num_aregs
/ 4 - 1);
1236 cache
->wd
.ws
= ws
& ~(1 << wb
);
1238 cache
->pc
= get_frame_func (this_frame
);
1239 cache
->ra
= (pc
& 0xc0000000) | (ra
& 0x3fffffff);
1240 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1241 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1244 if (cache
->wd
.ws
== 0)
1249 sp
= get_frame_register_unsigned
1250 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1) - 16;
1252 for (i
= 0; i
< 4; i
++, sp
+= 4)
1254 cache
->wd
.aregs
[i
] = sp
;
1257 if (cache
->wd
.callsize
> 4)
1259 /* Set A4...A7/A11. */
1260 /* Get the SP of the frame previous to the previous one.
1261 To achieve this, we have to dereference SP twice. */
1262 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4);
1263 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4);
1264 sp
-= cache
->wd
.callsize
* 4;
1266 for ( i
= 4; i
< cache
->wd
.callsize
; i
++, sp
+= 4)
1268 cache
->wd
.aregs
[i
] = sp
;
1273 if ((cache
->prev_sp
== 0) && ( ra
!= 0 ))
1274 /* If RA is equal to 0 this frame is an outermost frame. Leave
1275 cache->prev_sp unchanged marking the boundary of the frame stack. */
1277 if ((cache
->wd
.ws
& (1 << cache
->wd
.wb
)) == 0)
1279 /* Register window overflow already happened.
1280 We can read caller's SP from the proper spill loction. */
1281 sp
= get_frame_register_unsigned
1282 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1283 cache
->prev_sp
= read_memory_integer (sp
- 12, 4);
1287 /* Read caller's frame SP directly from the previous window. */
1288 int regnum
= arreg_number
1289 (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ 1,
1292 cache
->prev_sp
= get_frame_register_unsigned (this_frame
, regnum
);
1296 else /* Call0 framework. */
1298 unsigned int litbase_regnum
= gdbarch_tdep (gdbarch
)->litbase_regnum
;
1299 CORE_ADDR litbase
= (litbase_regnum
== -1)
1300 ? 0 : get_frame_register_unsigned (this_frame
, litbase_regnum
);
1302 call0_frame_cache (this_frame
, cache
, pc
, litbase
);
1303 fp_regnum
= cache
->c0
.fp_regnum
;
1306 cache
->base
= get_frame_register_unsigned (this_frame
, fp_regnum
);
1312 xtensa_frame_this_id (struct frame_info
*this_frame
,
1314 struct frame_id
*this_id
)
1316 struct xtensa_frame_cache
*cache
=
1317 xtensa_frame_cache (this_frame
, this_cache
);
1319 if (cache
->prev_sp
== 0)
1322 (*this_id
) = frame_id_build (cache
->prev_sp
, cache
->pc
);
1325 static struct value
*
1326 xtensa_frame_prev_register (struct frame_info
*this_frame
,
1330 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1331 struct xtensa_frame_cache
*cache
;
1332 ULONGEST saved_reg
= 0;
1335 if (*this_cache
== NULL
)
1336 *this_cache
= xtensa_frame_cache (this_frame
, this_cache
);
1337 cache
= *this_cache
;
1339 if (regnum
==gdbarch_pc_regnum (gdbarch
))
1340 saved_reg
= cache
->ra
;
1341 else if (regnum
== gdbarch_tdep (gdbarch
)->a0_base
+ 1)
1342 saved_reg
= cache
->prev_sp
;
1343 else if (!cache
->call0
)
1345 if (regnum
== gdbarch_tdep (gdbarch
)->ws_regnum
)
1346 saved_reg
= cache
->wd
.ws
;
1347 else if (regnum
== gdbarch_tdep (gdbarch
)->wb_regnum
)
1348 saved_reg
= cache
->wd
.wb
;
1349 else if (regnum
== gdbarch_ps_regnum (gdbarch
))
1350 saved_reg
= cache
->ps
;
1358 return frame_unwind_got_constant (this_frame
, regnum
, saved_reg
);
1360 if (!cache
->call0
) /* Windowed ABI. */
1362 /* Convert A-register numbers to AR-register numbers,
1363 if we deal with A-register. */
1364 if (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
1365 && regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15)
1366 regnum
= arreg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1368 /* Check, if we deal with AR-register saved on stack. */
1369 if (regnum
>= gdbarch_tdep (gdbarch
)->ar_base
1370 && regnum
<= (gdbarch_tdep (gdbarch
)->ar_base
1371 + gdbarch_tdep (gdbarch
)->num_aregs
))
1373 int areg
= areg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1376 && areg
< XTENSA_NUM_SAVED_AREGS
1377 && cache
->wd
.aregs
[areg
] != -1)
1378 return frame_unwind_got_memory (this_frame
, regnum
,
1379 cache
->wd
.aregs
[areg
]);
1382 else /* Call0 ABI. */
1384 int reg
= (regnum
>= gdbarch_tdep (gdbarch
)->ar_base
1385 && regnum
<= (gdbarch_tdep (gdbarch
)->ar_base
1387 ? regnum
- gdbarch_tdep (gdbarch
)->ar_base
: regnum
;
1394 /* If register was saved in the prologue, retrieve it. */
1395 stkofs
= cache
->c0
.c0_rt
[reg
].to_stk
;
1396 if (stkofs
!= C0_NOSTK
)
1398 /* Determine SP on entry based on FP. */
1399 spe
= cache
->c0
.c0_fp
1400 - cache
->c0
.c0_rt
[cache
->c0
.fp_regnum
].fr_ofs
;
1402 return frame_unwind_got_memory (this_frame
, regnum
, spe
+ stkofs
);
1407 /* All other registers have been either saved to
1408 the stack or are still alive in the processor. */
1410 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1414 static const struct frame_unwind
1418 xtensa_frame_this_id
,
1419 xtensa_frame_prev_register
,
1421 default_frame_sniffer
1425 xtensa_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1427 struct xtensa_frame_cache
*cache
=
1428 xtensa_frame_cache (this_frame
, this_cache
);
1433 static const struct frame_base
1437 xtensa_frame_base_address
,
1438 xtensa_frame_base_address
,
1439 xtensa_frame_base_address
1444 xtensa_extract_return_value (struct type
*type
,
1445 struct regcache
*regcache
,
1448 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1449 bfd_byte
*valbuf
= dst
;
1450 int len
= TYPE_LENGTH (type
);
1455 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1457 gdb_assert(len
> 0);
1459 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1461 /* First, we have to find the caller window in the register file. */
1462 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1463 callsize
= extract_call_winsize (gdbarch
, pc
);
1465 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1466 if (len
> (callsize
> 8 ? 8 : 16))
1467 internal_error (__FILE__
, __LINE__
,
1468 _("cannot extract return value of %d bytes long"), len
);
1470 /* Get the register offset of the return
1471 register (A2) in the caller window. */
1472 regcache_raw_read_unsigned
1473 (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, &wb
);
1474 areg
= arreg_number (gdbarch
,
1475 gdbarch_tdep (gdbarch
)->a0_base
+ 2 + callsize
, wb
);
1479 /* No windowing hardware - Call0 ABI. */
1480 areg
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_ARGS
;
1483 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg
, len
);
1485 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1488 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1491 regcache_raw_read_part (regcache
, areg
, offset
, len
, valbuf
);
1493 regcache_raw_read (regcache
, areg
, valbuf
);
1499 xtensa_store_return_value (struct type
*type
,
1500 struct regcache
*regcache
,
1503 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1504 const bfd_byte
*valbuf
= dst
;
1508 int len
= TYPE_LENGTH (type
);
1511 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1513 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1515 regcache_raw_read_unsigned
1516 (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, &wb
);
1517 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1518 callsize
= extract_call_winsize (gdbarch
, pc
);
1520 if (len
> (callsize
> 8 ? 8 : 16))
1521 internal_error (__FILE__
, __LINE__
,
1522 _("unimplemented for this length: %d"),
1523 TYPE_LENGTH (type
));
1524 areg
= arreg_number (gdbarch
,
1525 gdbarch_tdep (gdbarch
)->a0_base
+ 2 + callsize
, wb
);
1527 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1528 callsize
, (int) wb
);
1532 areg
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_ARGS
;
1535 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1538 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1541 regcache_raw_write_part (regcache
, areg
, offset
, len
, valbuf
);
1543 regcache_raw_write (regcache
, areg
, valbuf
);
1548 static enum return_value_convention
1549 xtensa_return_value (struct gdbarch
*gdbarch
,
1550 struct type
*func_type
,
1551 struct type
*valtype
,
1552 struct regcache
*regcache
,
1554 const gdb_byte
*writebuf
)
1556 /* Structures up to 16 bytes are returned in registers. */
1558 int struct_return
= ((TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
1559 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
1560 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
1561 && TYPE_LENGTH (valtype
) > 16);
1564 return RETURN_VALUE_STRUCT_CONVENTION
;
1566 DEBUGTRACE ("xtensa_return_value(...)\n");
1568 if (writebuf
!= NULL
)
1570 xtensa_store_return_value (valtype
, regcache
, writebuf
);
1573 if (readbuf
!= NULL
)
1575 gdb_assert (!struct_return
);
1576 xtensa_extract_return_value (valtype
, regcache
, readbuf
);
1578 return RETURN_VALUE_REGISTER_CONVENTION
;
1585 xtensa_push_dummy_call (struct gdbarch
*gdbarch
,
1586 struct value
*function
,
1587 struct regcache
*regcache
,
1590 struct value
**args
,
1593 CORE_ADDR struct_addr
)
1596 int size
, onstack_size
;
1597 gdb_byte
*buf
= (gdb_byte
*) alloca (16);
1599 struct argument_info
1601 const bfd_byte
*contents
;
1603 int onstack
; /* onstack == 0 => in reg */
1604 int align
; /* alignment */
1607 int offset
; /* stack offset if on stack */
1608 int regno
; /* regno if in register */
1612 struct argument_info
*arg_info
=
1613 (struct argument_info
*) alloca (nargs
* sizeof (struct argument_info
));
1617 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1619 if (xtensa_debug_level
> 3)
1622 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs
);
1623 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1624 "struct_addr=0x%x\n",
1625 (int) sp
, (int) struct_return
, (int) struct_addr
);
1627 for (i
= 0; i
< nargs
; i
++)
1629 struct value
*arg
= args
[i
];
1630 struct type
*arg_type
= check_typedef (value_type (arg
));
1631 fprintf_unfiltered (gdb_stdlog
, "%2d: 0x%lx %3d ",
1632 i
, (unsigned long) arg
, TYPE_LENGTH (arg_type
));
1633 switch (TYPE_CODE (arg_type
))
1636 fprintf_unfiltered (gdb_stdlog
, "int");
1638 case TYPE_CODE_STRUCT
:
1639 fprintf_unfiltered (gdb_stdlog
, "struct");
1642 fprintf_unfiltered (gdb_stdlog
, "%3d", TYPE_CODE (arg_type
));
1645 fprintf_unfiltered (gdb_stdlog
, " 0x%lx\n",
1646 (unsigned long) value_contents (arg
));
1650 /* First loop: collect information.
1651 Cast into type_long. (This shouldn't happen often for C because
1652 GDB already does this earlier.) It's possible that GDB could
1653 do it all the time but it's harmless to leave this code here. */
1660 size
= REGISTER_SIZE
;
1662 for (i
= 0; i
< nargs
; i
++)
1664 struct argument_info
*info
= &arg_info
[i
];
1665 struct value
*arg
= args
[i
];
1666 struct type
*arg_type
= check_typedef (value_type (arg
));
1668 switch (TYPE_CODE (arg_type
))
1671 case TYPE_CODE_BOOL
:
1672 case TYPE_CODE_CHAR
:
1673 case TYPE_CODE_RANGE
:
1674 case TYPE_CODE_ENUM
:
1676 /* Cast argument to long if necessary as the mask does it too. */
1677 if (TYPE_LENGTH (arg_type
)
1678 < TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
))
1680 arg_type
= builtin_type (gdbarch
)->builtin_long
;
1681 arg
= value_cast (arg_type
, arg
);
1683 /* Aligment is equal to the type length for the basic types. */
1684 info
->align
= TYPE_LENGTH (arg_type
);
1689 /* Align doubles correctly. */
1690 if (TYPE_LENGTH (arg_type
)
1691 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
))
1692 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
);
1694 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
);
1697 case TYPE_CODE_STRUCT
:
1699 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
);
1702 info
->length
= TYPE_LENGTH (arg_type
);
1703 info
->contents
= value_contents (arg
);
1705 /* Align size and onstack_size. */
1706 size
= (size
+ info
->align
- 1) & ~(info
->align
- 1);
1707 onstack_size
= (onstack_size
+ info
->align
- 1) & ~(info
->align
- 1);
1709 if (size
+ info
->length
> REGISTER_SIZE
* ARG_NOF (gdbarch
))
1712 info
->u
.offset
= onstack_size
;
1713 onstack_size
+= info
->length
;
1718 info
->u
.regno
= ARG_1ST (gdbarch
) + size
/ REGISTER_SIZE
;
1720 size
+= info
->length
;
1723 /* Adjust the stack pointer and align it. */
1724 sp
= align_down (sp
- onstack_size
, SP_ALIGNMENT
);
1726 /* Simulate MOVSP, if Windowed ABI. */
1727 if ((gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1730 read_memory (osp
- 16, buf
, 16);
1731 write_memory (sp
- 16, buf
, 16);
1734 /* Second Loop: Load arguments. */
1738 store_unsigned_integer (buf
, REGISTER_SIZE
, struct_addr
);
1739 regcache_cooked_write (regcache
, ARG_1ST (gdbarch
), buf
);
1742 for (i
= 0; i
< nargs
; i
++)
1744 struct argument_info
*info
= &arg_info
[i
];
1748 int n
= info
->length
;
1749 CORE_ADDR offset
= sp
+ info
->u
.offset
;
1751 /* Odd-sized structs are aligned to the lower side of a memory
1752 word in big-endian mode and require a shift. This only
1753 applies for structures smaller than one word. */
1755 if (n
< REGISTER_SIZE
1756 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1757 offset
+= (REGISTER_SIZE
- n
);
1759 write_memory (offset
, info
->contents
, info
->length
);
1764 int n
= info
->length
;
1765 const bfd_byte
*cp
= info
->contents
;
1766 int r
= info
->u
.regno
;
1768 /* Odd-sized structs are aligned to the lower side of registers in
1769 big-endian mode and require a shift. The odd-sized leftover will
1770 be at the end. Note that this is only true for structures smaller
1771 than REGISTER_SIZE; for larger odd-sized structures the excess
1772 will be left-aligned in the register on both endiannesses. */
1774 if (n
< REGISTER_SIZE
1775 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1777 ULONGEST v
= extract_unsigned_integer (cp
, REGISTER_SIZE
);
1778 v
= v
>> ((REGISTER_SIZE
- n
) * TARGET_CHAR_BIT
);
1780 store_unsigned_integer (buf
, REGISTER_SIZE
, v
);
1781 regcache_cooked_write (regcache
, r
, buf
);
1783 cp
+= REGISTER_SIZE
;
1790 regcache_cooked_write (regcache
, r
, cp
);
1792 cp
+= REGISTER_SIZE
;
1799 /* Set the return address of dummy frame to the dummy address.
1800 The return address for the current function (in A0) is
1801 saved in the dummy frame, so we can savely overwrite A0 here. */
1803 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1805 ra
= (bp_addr
& 0x3fffffff) | 0x40000000;
1806 regcache_raw_read (regcache
, gdbarch_ps_regnum (gdbarch
), buf
);
1807 ps
= extract_unsigned_integer (buf
, 4) & ~0x00030000;
1808 regcache_cooked_write_unsigned
1809 (regcache
, gdbarch_tdep (gdbarch
)->a0_base
+ 4, ra
);
1810 regcache_cooked_write_unsigned (regcache
,
1811 gdbarch_ps_regnum (gdbarch
),
1814 /* All the registers have been saved. After executing
1815 dummy call, they all will be restored. So it's safe
1816 to modify WINDOWSTART register to make it look like there
1817 is only one register window corresponding to WINDOWEBASE. */
1819 regcache_raw_read (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, buf
);
1820 regcache_cooked_write_unsigned (regcache
,
1821 gdbarch_tdep (gdbarch
)->ws_regnum
,
1822 1 << extract_unsigned_integer (buf
, 4));
1826 /* Simulate CALL0: write RA into A0 register. */
1827 regcache_cooked_write_unsigned
1828 (regcache
, gdbarch_tdep (gdbarch
)->a0_base
, bp_addr
);
1831 /* Set new stack pointer and return it. */
1832 regcache_cooked_write_unsigned (regcache
,
1833 gdbarch_tdep (gdbarch
)->a0_base
+ 1, sp
);
1834 /* Make dummy frame ID unique by adding a constant. */
1835 return sp
+ SP_ALIGNMENT
;
1839 /* Return a breakpoint for the current location of PC. We always use
1840 the density version if we have density instructions (regardless of the
1841 current instruction at PC), and use regular instructions otherwise. */
1843 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1844 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1845 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1846 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1848 static const unsigned char *
1849 xtensa_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
1852 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
1853 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
1854 static unsigned char density_big_breakpoint
[] = DENSITY_BIG_BREAKPOINT
;
1855 static unsigned char density_little_breakpoint
[] = DENSITY_LITTLE_BREAKPOINT
;
1857 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr
);
1859 if (gdbarch_tdep (gdbarch
)->isa_use_density_instructions
)
1861 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1863 *lenptr
= sizeof (density_big_breakpoint
);
1864 return density_big_breakpoint
;
1868 *lenptr
= sizeof (density_little_breakpoint
);
1869 return density_little_breakpoint
;
1874 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1876 *lenptr
= sizeof (big_breakpoint
);
1877 return big_breakpoint
;
1881 *lenptr
= sizeof (little_breakpoint
);
1882 return little_breakpoint
;
1887 /* Call0 ABI support routines. */
1889 /* Call0 opcode class. Opcodes are preclassified according to what they
1890 mean for Call0 prologue analysis, and their number of significant operands.
1891 The purpose of this is to simplify prologue analysis by separating
1892 instruction decoding (libisa) from the semantics of prologue analysis. */
1895 c0opc_illegal
, /* Unknown to libisa (invalid) or 'ill' opcode. */
1896 c0opc_uninteresting
, /* Not interesting for Call0 prologue analysis. */
1897 c0opc_flow
, /* Flow control insn. */
1898 c0opc_entry
, /* ENTRY indicates non-Call0 prologue. */
1899 c0opc_break
, /* Debugger software breakpoints. */
1900 c0opc_add
, /* Adding two registers. */
1901 c0opc_addi
, /* Adding a register and an immediate. */
1902 c0opc_sub
, /* Subtracting a register from a register. */
1903 c0opc_mov
, /* Moving a register to a register. */
1904 c0opc_movi
, /* Moving an immediate to a register. */
1905 c0opc_l32r
, /* Loading a literal. */
1906 c0opc_s32i
, /* Storing word at fixed offset from a base register. */
1907 c0opc_NrOf
/* Number of opcode classifications. */
1911 /* Classify an opcode based on what it means for Call0 prologue analysis. */
1913 static xtensa_insn_kind
1914 call0_classify_opcode (xtensa_isa isa
, xtensa_opcode opc
)
1916 const char *opcname
;
1917 xtensa_insn_kind opclass
= c0opc_uninteresting
;
1919 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc
);
1921 /* Get opcode name and handle special classifications. */
1923 opcname
= xtensa_opcode_name (isa
, opc
);
1926 || strcasecmp (opcname
, "ill") == 0
1927 || strcasecmp (opcname
, "ill.n") == 0)
1928 opclass
= c0opc_illegal
;
1929 else if (strcasecmp (opcname
, "break") == 0
1930 || strcasecmp (opcname
, "break.n") == 0)
1931 opclass
= c0opc_break
;
1932 else if (strcasecmp (opcname
, "entry") == 0)
1933 opclass
= c0opc_entry
;
1934 else if (xtensa_opcode_is_branch (isa
, opc
) > 0
1935 || xtensa_opcode_is_jump (isa
, opc
) > 0
1936 || xtensa_opcode_is_loop (isa
, opc
) > 0
1937 || xtensa_opcode_is_call (isa
, opc
) > 0
1938 || strcasecmp (opcname
, "simcall") == 0
1939 || strcasecmp (opcname
, "syscall") == 0)
1940 opclass
= c0opc_flow
;
1942 /* Also, classify specific opcodes that need to be tracked. */
1943 else if (strcasecmp (opcname
, "add") == 0
1944 || strcasecmp (opcname
, "add.n") == 0)
1945 opclass
= c0opc_add
;
1946 else if (strcasecmp (opcname
, "addi") == 0
1947 || strcasecmp (opcname
, "addi.n") == 0
1948 || strcasecmp (opcname
, "addmi") == 0)
1949 opclass
= c0opc_addi
;
1950 else if (strcasecmp (opcname
, "sub") == 0)
1951 opclass
= c0opc_sub
;
1952 else if (strcasecmp (opcname
, "mov.n") == 0
1953 || strcasecmp (opcname
, "or") == 0) /* Could be 'mov' asm macro. */
1954 opclass
= c0opc_mov
;
1955 else if (strcasecmp (opcname
, "movi") == 0
1956 || strcasecmp (opcname
, "movi.n") == 0)
1957 opclass
= c0opc_movi
;
1958 else if (strcasecmp (opcname
, "l32r") == 0)
1959 opclass
= c0opc_l32r
;
1960 else if (strcasecmp (opcname
, "s32i") == 0
1961 || strcasecmp (opcname
, "s32i.n") == 0)
1962 opclass
= c0opc_s32i
;
1967 /* Tracks register movement/mutation for a given operation, which may
1968 be within a bundle. Updates the destination register tracking info
1969 accordingly. The pc is needed only for pc-relative load instructions
1970 (eg. l32r). The SP register number is needed to identify stores to
1974 call0_track_op (xtensa_c0reg_t dst
[], xtensa_c0reg_t src
[],
1975 xtensa_insn_kind opclass
, int nods
, unsigned odv
[],
1976 CORE_ADDR pc
, CORE_ADDR litbase
, int spreg
)
1978 unsigned litaddr
, litval
;
1983 /* 3 operands: dst, src, imm. */
1984 gdb_assert (nods
== 3);
1985 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
1986 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ odv
[2];
1989 /* 3 operands: dst, src1, src2. */
1990 gdb_assert (nods
== 3);
1991 if (src
[odv
[1]].fr_reg
== C0_CONST
)
1993 dst
[odv
[0]].fr_reg
= src
[odv
[2]].fr_reg
;
1994 dst
[odv
[0]].fr_ofs
= src
[odv
[2]].fr_ofs
+ src
[odv
[1]].fr_ofs
;
1996 else if (src
[odv
[2]].fr_reg
== C0_CONST
)
1998 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
1999 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ src
[odv
[2]].fr_ofs
;
2001 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2004 /* 3 operands: dst, src1, src2. */
2005 gdb_assert (nods
== 3);
2006 if (src
[odv
[2]].fr_reg
== C0_CONST
)
2008 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2009 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
- src
[odv
[2]].fr_ofs
;
2011 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2014 /* 2 operands: dst, src [, src]. */
2015 gdb_assert (nods
== 2);
2016 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2017 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
;
2020 /* 2 operands: dst, imm. */
2021 gdb_assert (nods
== 2);
2022 dst
[odv
[0]].fr_reg
= C0_CONST
;
2023 dst
[odv
[0]].fr_ofs
= odv
[1];
2026 /* 2 operands: dst, literal offset. */
2027 gdb_assert (nods
== 2);
2028 litaddr
= litbase
& 1
2029 ? (litbase
& ~1) + (signed)odv
[1]
2030 : (pc
+ 3 + (signed)odv
[1]) & ~3;
2031 litval
= read_memory_integer(litaddr
, 4);
2032 dst
[odv
[0]].fr_reg
= C0_CONST
;
2033 dst
[odv
[0]].fr_ofs
= litval
;
2036 /* 3 operands: value, base, offset. */
2037 gdb_assert (nods
== 3 && spreg
>= 0 && spreg
< C0_NREGS
);
2038 if (src
[odv
[1]].fr_reg
== spreg
/* Store to stack frame. */
2039 && (src
[odv
[1]].fr_ofs
& 3) == 0 /* Alignment preserved. */
2040 && src
[odv
[0]].fr_reg
>= 0 /* Value is from a register. */
2041 && src
[odv
[0]].fr_ofs
== 0 /* Value hasn't been modified. */
2042 && src
[src
[odv
[0]].fr_reg
].to_stk
== C0_NOSTK
) /* First time. */
2044 /* ISA encoding guarantees alignment. But, check it anyway. */
2045 gdb_assert ((odv
[2] & 3) == 0);
2046 dst
[src
[odv
[0]].fr_reg
].to_stk
= src
[odv
[1]].fr_ofs
+ odv
[2];
2054 /* Analyze prologue of the function at start address to determine if it uses
2055 the Call0 ABI, and if so track register moves and linear modifications
2056 in the prologue up to the PC or just beyond the prologue, whichever is first.
2057 An 'entry' instruction indicates non-Call0 ABI and the end of the prologue.
2058 The prologue may overlap non-prologue instructions but is guaranteed to end
2059 by the first flow-control instruction (jump, branch, call or return).
2060 Since an optimized function may move information around and change the
2061 stack frame arbitrarily during the prologue, the information is guaranteed
2062 valid only at the point in the function indicated by the PC.
2063 May be used to skip the prologue or identify the ABI, w/o tracking.
2065 Returns: Address of first instruction after prologue, or PC (whichever
2066 is first), or 0, if decoding failed (in libisa).
2068 start Start address of function/prologue.
2069 pc Program counter to stop at. Use 0 to continue to end of prologue.
2070 If 0, avoids infinite run-on in corrupt code memory by bounding
2071 the scan to the end of the function if that can be determined.
2072 nregs Number of general registers to track (size of rt[] array).
2074 rt[] Array[nregs] of xtensa_c0reg structures for register tracking info.
2075 If NULL, registers are not tracked.
2077 call0 If != NULL, *call0 is set non-zero if Call0 ABI used, else 0
2078 (more accurately, non-zero until 'entry' insn is encountered).
2080 Note that these may produce useful results even if decoding fails
2081 because they begin with default assumptions that analysis may change. */
2084 call0_analyze_prologue (CORE_ADDR start
, CORE_ADDR pc
, CORE_ADDR litbase
,
2085 int nregs
, xtensa_c0reg_t rt
[], int *call0
)
2087 CORE_ADDR ia
; /* Current insn address in prologue. */
2088 CORE_ADDR ba
= 0; /* Current address at base of insn buffer. */
2089 CORE_ADDR bt
; /* Current address at top+1 of insn buffer. */
2090 char ibuf
[XTENSA_ISA_BSZ
];/* Instruction buffer for decoding prologue. */
2091 xtensa_isa isa
; /* libisa ISA handle. */
2092 xtensa_insnbuf ins
, slot
; /* libisa handle to decoded insn, slot. */
2093 xtensa_format ifmt
; /* libisa instruction format. */
2094 int ilen
, islots
, is
; /* Instruction length, nbr slots, current slot. */
2095 xtensa_opcode opc
; /* Opcode in current slot. */
2096 xtensa_insn_kind opclass
; /* Opcode class for Call0 prologue analysis. */
2097 int nods
; /* Opcode number of operands. */
2098 unsigned odv
[C0_MAXOPDS
]; /* Operand values in order provided by libisa. */
2099 xtensa_c0reg_t
*rtmp
; /* Register tracking info snapshot. */
2100 int j
; /* General loop counter. */
2101 int fail
= 0; /* Set non-zero and exit, if decoding fails. */
2102 CORE_ADDR body_pc
; /* The PC for the first non-prologue insn. */
2103 CORE_ADDR end_pc
; /* The PC for the lust function insn. */
2105 struct symtab_and_line prologue_sal
;
2107 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2108 (int)start
, (int)pc
);
2110 /* Try to limit the scan to the end of the function if a non-zero pc
2111 arg was not supplied to avoid probing beyond the end of valid memory.
2112 If memory is full of garbage that classifies as c0opc_uninteresting.
2113 If this fails (eg. if no symbols) pc ends up 0 as it was.
2114 Intialize the Call0 frame and register tracking info.
2115 Assume it's Call0 until an 'entry' instruction is encountered.
2116 Assume we may be in the prologue until we hit a flow control instr. */
2122 /* Find out, if we have an information about the prologue from DWARF. */
2123 prologue_sal
= find_pc_line (start
, 0);
2124 if (prologue_sal
.line
!= 0) /* Found debug info. */
2125 body_pc
= prologue_sal
.end
;
2127 /* If we are going to analyze the prologue in general without knowing about
2128 the current PC, make the best assumtion for the end of the prologue. */
2131 find_pc_partial_function (start
, 0, NULL
, &end_pc
);
2132 body_pc
= min (end_pc
, body_pc
);
2135 body_pc
= min (pc
, body_pc
);
2142 rtmp
= (xtensa_c0reg_t
*) alloca(nregs
* sizeof(xtensa_c0reg_t
));
2143 /* rt is already initialized in xtensa_alloc_frame_cache(). */
2147 if (!xtensa_default_isa
)
2148 xtensa_default_isa
= xtensa_isa_init (0, 0);
2149 isa
= xtensa_default_isa
;
2150 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2151 ins
= xtensa_insnbuf_alloc (isa
);
2152 slot
= xtensa_insnbuf_alloc (isa
);
2154 for (ia
= start
, bt
= ia
; ia
< body_pc
; ia
+= ilen
)
2156 /* (Re)fill instruction buffer from memory if necessary, but do not
2157 read memory beyond PC to be sure we stay within text section
2158 (this protection only works if a non-zero pc is supplied). */
2160 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2163 bt
= (ba
+ XTENSA_ISA_BSZ
) < body_pc
? ba
+ XTENSA_ISA_BSZ
: body_pc
;
2164 read_memory (ba
, ibuf
, bt
- ba
);
2167 /* Decode format information. */
2169 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2170 ifmt
= xtensa_format_decode (isa
, ins
);
2171 if (ifmt
== XTENSA_UNDEFINED
)
2176 ilen
= xtensa_format_length (isa
, ifmt
);
2177 if (ilen
== XTENSA_UNDEFINED
)
2182 islots
= xtensa_format_num_slots (isa
, ifmt
);
2183 if (islots
== XTENSA_UNDEFINED
)
2189 /* Analyze a bundle or a single instruction, using a snapshot of
2190 the register tracking info as input for the entire bundle so that
2191 register changes do not take effect within this bundle. */
2193 for (j
= 0; j
< nregs
; ++j
)
2196 for (is
= 0; is
< islots
; ++is
)
2198 /* Decode a slot and classify the opcode. */
2200 fail
= xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
);
2204 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2205 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2207 if (opc
== XTENSA_UNDEFINED
)
2208 opclass
= c0opc_illegal
;
2210 opclass
= call0_classify_opcode (isa
, opc
);
2212 /* Decide whether to track this opcode, ignore it, or bail out. */
2221 case c0opc_uninteresting
:
2230 ia
+= ilen
; /* Skip over 'entry' insn. */
2238 /* Only expected opcodes should get this far. */
2242 /* Extract and decode the operands. */
2243 nods
= xtensa_opcode_num_operands (isa
, opc
);
2244 if (nods
== XTENSA_UNDEFINED
)
2250 for (j
= 0; j
< nods
&& j
< C0_MAXOPDS
; ++j
)
2252 fail
= xtensa_operand_get_field (isa
, opc
, j
, ifmt
,
2257 fail
= xtensa_operand_decode (isa
, opc
, j
, &odv
[j
]);
2262 /* Check operands to verify use of 'mov' assembler macro. */
2263 if (opclass
== c0opc_mov
&& nods
== 3)
2265 if (odv
[2] == odv
[1])
2269 opclass
= c0opc_uninteresting
;
2274 /* Track register movement and modification for this operation. */
2275 call0_track_op (rt
, rtmp
, opclass
, nods
, odv
, ia
, litbase
, 1);
2279 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2280 (unsigned)ia
, fail
? "failed" : "succeeded");
2281 xtensa_insnbuf_free(isa
, slot
);
2282 xtensa_insnbuf_free(isa
, ins
);
2283 return fail
? 0 : ia
;
2286 /* Initialize frame cache for the current frame in CALL0 ABI. */
2289 call0_frame_cache (struct frame_info
*this_frame
,
2290 xtensa_frame_cache_t
*cache
, CORE_ADDR pc
, CORE_ADDR litbase
)
2292 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2293 CORE_ADDR start_pc
; /* The beginning of the function. */
2294 CORE_ADDR body_pc
=UINT_MAX
; /* PC, where prologue analysis stopped. */
2295 CORE_ADDR sp
, fp
, ra
;
2296 int fp_regnum
, c0_hasfp
, c0_frmsz
, prev_sp
, to_stk
;
2298 /* Find the beginning of the prologue of the function containing the PC
2299 and analyze it up to the PC or the end of the prologue. */
2301 if (find_pc_partial_function (pc
, NULL
, &start_pc
, NULL
))
2303 body_pc
= call0_analyze_prologue (start_pc
, pc
, litbase
, C0_NREGS
,
2304 &cache
->c0
.c0_rt
[0],
2308 sp
= get_frame_register_unsigned
2309 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
2310 fp
= sp
; /* Assume FP == SP until proven otherwise. */
2312 /* Get the frame information and FP (if used) at the current PC.
2313 If PC is in the prologue, the prologue analysis is more reliable
2314 than DWARF info. We don't not know for sure if PC is in the prologue,
2315 but we know no calls have yet taken place, so we can almost
2316 certainly rely on the prologue analysis. */
2320 /* Prologue analysis was successful up to the PC.
2321 It includes the cases when PC == START_PC. */
2322 c0_hasfp
= cache
->c0
.c0_rt
[C0_FP
].fr_reg
== C0_SP
;
2323 /* c0_hasfp == true means there is a frame pointer because
2324 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2325 was derived from SP. Otherwise, it would be C0_FP. */
2326 fp_regnum
= c0_hasfp
? C0_FP
: C0_SP
;
2327 c0_frmsz
= - cache
->c0
.c0_rt
[fp_regnum
].fr_ofs
;
2328 fp_regnum
+= gdbarch_tdep (gdbarch
)->a0_base
;
2330 else /* No data from the prologue analysis. */
2333 fp_regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_SP
;
2338 prev_sp
= fp
+ c0_frmsz
;
2340 /* Frame size from debug info or prologue tracking does not account for
2341 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2344 fp
= get_frame_register_unsigned (this_frame
, fp_regnum
);
2346 /* Recalculate previous SP. */
2347 prev_sp
= fp
+ c0_frmsz
;
2348 /* Update the stack frame size. */
2349 c0_frmsz
+= fp
- sp
;
2352 /* Get the return address (RA) from the stack if saved,
2353 or try to get it from a register. */
2355 to_stk
= cache
->c0
.c0_rt
[C0_RA
].to_stk
;
2356 if (to_stk
!= C0_NOSTK
)
2358 read_memory_integer (sp
+ c0_frmsz
+ cache
->c0
.c0_rt
[C0_RA
].to_stk
, 4);
2360 else if (cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_CONST
2361 && cache
->c0
.c0_rt
[C0_RA
].fr_ofs
== 0)
2363 /* Special case for terminating backtrace at a function that wants to
2364 be seen as the outermost. Such a function will clear it's RA (A0)
2365 register to 0 in the prologue instead of saving its original value. */
2370 /* RA was copied to another register or (before any function call) may
2371 still be in the original RA register. This is not always reliable:
2372 even in a leaf function, register tracking stops after prologue, and
2373 even in prologue, non-prologue instructions (not tracked) may overwrite
2374 RA or any register it was copied to. If likely in prologue or before
2375 any call, use retracking info and hope for the best (compiler should
2376 have saved RA in stack if not in a leaf function). If not in prologue,
2382 (i
== C0_RA
|| cache
->c0
.c0_rt
[i
].fr_reg
!= C0_RA
);
2384 if (i
>= C0_NREGS
&& cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_RA
)
2388 ra
= get_frame_register_unsigned
2390 gdbarch_tdep (gdbarch
)->a0_base
+ cache
->c0
.c0_rt
[i
].fr_reg
);
2395 cache
->pc
= start_pc
;
2397 /* RA == 0 marks the outermost frame. Do not go past it. */
2398 cache
->prev_sp
= (ra
!= 0) ? prev_sp
: 0;
2399 cache
->c0
.fp_regnum
= fp_regnum
;
2400 cache
->c0
.c0_frmsz
= c0_frmsz
;
2401 cache
->c0
.c0_hasfp
= c0_hasfp
;
2402 cache
->c0
.c0_fp
= fp
;
2406 /* Skip function prologue.
2408 Return the pc of the first instruction after prologue. GDB calls this to
2409 find the address of the first line of the function or (if there is no line
2410 number information) to skip the prologue for planting breakpoints on
2411 function entries. Use debug info (if present) or prologue analysis to skip
2412 the prologue to achieve reliable debugging behavior. For windowed ABI,
2413 only the 'entry' instruction is skipped. It is not strictly necessary to
2414 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2415 backtrace at any point in the prologue, however certain potential hazards
2416 are avoided and a more "normal" debugging experience is ensured by
2417 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2418 For example, if we don't skip the prologue:
2419 - Some args may not yet have been saved to the stack where the debug
2420 info expects to find them (true anyway when only 'entry' is skipped);
2421 - Software breakpoints ('break' instrs) may not have been unplanted
2422 when the prologue analysis is done on initializing the frame cache,
2423 and breaks in the prologue will throw off the analysis.
2425 If we have debug info ( line-number info, in particular ) we simply skip
2426 the code associated with the first function line effectively skipping
2427 the prologue code. It works even in cases like
2430 { int local_var = 1;
2434 because, for this source code, both Xtensa compilers will generate two
2435 separate entries ( with the same line number ) in dwarf line-number
2436 section to make sure there is a boundary between the prologue code and
2437 the rest of the function.
2439 If there is no debug info, we need to analyze the code. */
2441 /* #define DONT_SKIP_PROLOGUE */
2444 xtensa_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
2446 struct symtab_and_line prologue_sal
;
2449 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc
);
2451 #if DONT_SKIP_PROLOGUE
2455 /* Try to find first body line from debug info. */
2457 prologue_sal
= find_pc_line (start_pc
, 0);
2458 if (prologue_sal
.line
!= 0) /* Found debug info. */
2460 /* In Call0, it is possible to have a function with only one instruction
2461 ('ret') resulting from a 1-line optimized function that does nothing.
2462 In that case, prologue_sal.end may actually point to the start of the
2463 next function in the text section, causing a breakpoint to be set at
2464 the wrong place. Check if the end address is in a different function,
2465 and if so return the start PC. We know we have symbol info. */
2469 find_pc_partial_function (prologue_sal
.end
, NULL
, &end_func
, NULL
);
2470 if (end_func
!= start_pc
)
2473 return prologue_sal
.end
;
2476 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
2477 body_pc
= call0_analyze_prologue(start_pc
, 0, 0, 0, NULL
, NULL
);
2478 return body_pc
!= 0 ? body_pc
: start_pc
;
2481 /* Verify the current configuration. */
2483 xtensa_verify_config (struct gdbarch
*gdbarch
)
2485 struct ui_file
*log
;
2486 struct cleanup
*cleanups
;
2487 struct gdbarch_tdep
*tdep
;
2491 tdep
= gdbarch_tdep (gdbarch
);
2492 log
= mem_fileopen ();
2493 cleanups
= make_cleanup_ui_file_delete (log
);
2495 /* Verify that we got a reasonable number of AREGS. */
2496 if ((tdep
->num_aregs
& -tdep
->num_aregs
) != tdep
->num_aregs
)
2497 fprintf_unfiltered (log
, _("\
2498 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
2501 /* Verify that certain registers exist. */
2503 if (tdep
->pc_regnum
== -1)
2504 fprintf_unfiltered (log
, _("\n\tpc_regnum: No PC register"));
2505 if (tdep
->isa_use_exceptions
&& tdep
->ps_regnum
== -1)
2506 fprintf_unfiltered (log
, _("\n\tps_regnum: No PS register"));
2508 if (tdep
->isa_use_windowed_registers
)
2510 if (tdep
->wb_regnum
== -1)
2511 fprintf_unfiltered (log
, _("\n\twb_regnum: No WB register"));
2512 if (tdep
->ws_regnum
== -1)
2513 fprintf_unfiltered (log
, _("\n\tws_regnum: No WS register"));
2514 if (tdep
->ar_base
== -1)
2515 fprintf_unfiltered (log
, _("\n\tar_base: No AR registers"));
2518 if (tdep
->a0_base
== -1)
2519 fprintf_unfiltered (log
, _("\n\ta0_base: No Ax registers"));
2521 buf
= ui_file_xstrdup (log
, &dummy
);
2522 make_cleanup (xfree
, buf
);
2523 if (strlen (buf
) > 0)
2524 internal_error (__FILE__
, __LINE__
,
2525 _("the following are invalid: %s"), buf
);
2526 do_cleanups (cleanups
);
2530 /* Derive specific register numbers from the array of registers. */
2533 xtensa_derive_tdep (struct gdbarch_tdep
*tdep
)
2535 xtensa_register_t
* rmap
;
2536 int n
, max_size
= 4;
2539 tdep
->num_nopriv_regs
= 0;
2541 /* Special registers 0..255 (core). */
2542 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
2544 for (rmap
= tdep
->regmap
, n
= 0; rmap
->target_number
!= -1; n
++, rmap
++)
2546 if (rmap
->target_number
== 0x0020)
2547 tdep
->pc_regnum
= n
;
2548 else if (rmap
->target_number
== 0x0100)
2550 else if (rmap
->target_number
== 0x0000)
2552 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(72))
2553 tdep
->wb_regnum
= n
;
2554 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(73))
2555 tdep
->ws_regnum
= n
;
2556 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(233))
2557 tdep
->debugcause_regnum
= n
;
2558 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(232))
2559 tdep
->exccause_regnum
= n
;
2560 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(238))
2561 tdep
->excvaddr_regnum
= n
;
2562 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(0))
2563 tdep
->lbeg_regnum
= n
;
2564 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(1))
2565 tdep
->lend_regnum
= n
;
2566 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(2))
2567 tdep
->lcount_regnum
= n
;
2568 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(3))
2569 tdep
->sar_regnum
= n
;
2570 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(5))
2571 tdep
->litbase_regnum
= n
;
2572 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(230))
2573 tdep
->ps_regnum
= n
;
2575 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(226))
2576 tdep
->interrupt_regnum
= n
;
2577 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(227))
2578 tdep
->interrupt2_regnum
= n
;
2579 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(224))
2580 tdep
->cpenable_regnum
= n
;
2583 if (rmap
->byte_size
> max_size
)
2584 max_size
= rmap
->byte_size
;
2585 if (rmap
->mask
!= 0 && tdep
->num_regs
== 0)
2587 /* Find out out how to deal with priveleged registers.
2589 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
2590 && tdep->num_nopriv_regs == 0)
2591 tdep->num_nopriv_regs = n;
2593 if ((rmap
->flags
& XTENSA_REGISTER_FLAGS_PRIVILEGED
) != 0
2594 && tdep
->num_regs
== 0)
2598 /* Number of pseudo registers. */
2599 tdep
->num_pseudo_regs
= n
- tdep
->num_regs
;
2601 /* Empirically determined maximum sizes. */
2602 tdep
->max_register_raw_size
= max_size
;
2603 tdep
->max_register_virtual_size
= max_size
;
2606 /* Module "constructor" function. */
2608 extern struct gdbarch_tdep xtensa_tdep
;
2610 static struct gdbarch
*
2611 xtensa_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2613 struct gdbarch_tdep
*tdep
;
2614 struct gdbarch
*gdbarch
;
2615 struct xtensa_abi_handler
*abi_handler
;
2617 DEBUGTRACE ("gdbarch_init()\n");
2619 /* We have to set the byte order before we call gdbarch_alloc. */
2620 info
.byte_order
= XCHAL_HAVE_BE
? BFD_ENDIAN_BIG
: BFD_ENDIAN_LITTLE
;
2622 tdep
= &xtensa_tdep
;
2623 gdbarch
= gdbarch_alloc (&info
, tdep
);
2624 xtensa_derive_tdep (tdep
);
2626 /* Verify our configuration. */
2627 xtensa_verify_config (gdbarch
);
2629 /* Pseudo-Register read/write. */
2630 set_gdbarch_pseudo_register_read (gdbarch
, xtensa_pseudo_register_read
);
2631 set_gdbarch_pseudo_register_write (gdbarch
, xtensa_pseudo_register_write
);
2633 /* Set target information. */
2634 set_gdbarch_num_regs (gdbarch
, tdep
->num_regs
);
2635 set_gdbarch_num_pseudo_regs (gdbarch
, tdep
->num_pseudo_regs
);
2636 set_gdbarch_sp_regnum (gdbarch
, tdep
->a0_base
+ 1);
2637 set_gdbarch_pc_regnum (gdbarch
, tdep
->pc_regnum
);
2638 set_gdbarch_ps_regnum (gdbarch
, tdep
->ps_regnum
);
2640 /* Renumber registers for known formats (stabs and dwarf2). */
2641 set_gdbarch_stab_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
2642 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
2644 /* We provide our own function to get register information. */
2645 set_gdbarch_register_name (gdbarch
, xtensa_register_name
);
2646 set_gdbarch_register_type (gdbarch
, xtensa_register_type
);
2648 /* To call functions from GDB using dummy frame */
2649 set_gdbarch_push_dummy_call (gdbarch
, xtensa_push_dummy_call
);
2651 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2653 set_gdbarch_return_value (gdbarch
, xtensa_return_value
);
2655 /* Advance PC across any prologue instructions to reach "real" code. */
2656 set_gdbarch_skip_prologue (gdbarch
, xtensa_skip_prologue
);
2658 /* Stack grows downward. */
2659 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2661 /* Set breakpoints. */
2662 set_gdbarch_breakpoint_from_pc (gdbarch
, xtensa_breakpoint_from_pc
);
2664 /* After breakpoint instruction or illegal instruction, pc still
2665 points at break instruction, so don't decrement. */
2666 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
2668 /* We don't skip args. */
2669 set_gdbarch_frame_args_skip (gdbarch
, 0);
2671 set_gdbarch_unwind_pc (gdbarch
, xtensa_unwind_pc
);
2673 set_gdbarch_frame_align (gdbarch
, xtensa_frame_align
);
2675 set_gdbarch_dummy_id (gdbarch
, xtensa_dummy_id
);
2677 /* Frame handling. */
2678 frame_base_set_default (gdbarch
, &xtensa_frame_base
);
2679 frame_unwind_append_unwinder (gdbarch
, &xtensa_unwind
);
2680 dwarf2_append_unwinders (gdbarch
);
2682 set_gdbarch_print_insn (gdbarch
, print_insn_xtensa
);
2684 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
2686 xtensa_add_reggroups (gdbarch
);
2687 set_gdbarch_register_reggroup_p (gdbarch
, xtensa_register_reggroup_p
);
2689 set_gdbarch_regset_from_core_section (gdbarch
,
2690 xtensa_regset_from_core_section
);
2692 set_solib_svr4_fetch_link_map_offsets
2693 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
2699 xtensa_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
2701 error (_("xtensa_dump_tdep(): not implemented"));
2704 /* Provide a prototype to silence -Wmissing-prototypes. */
2705 extern initialize_file_ftype _initialize_xtensa_tdep
;
2708 _initialize_xtensa_tdep (void)
2710 struct cmd_list_element
*c
;
2712 gdbarch_register (bfd_arch_xtensa
, xtensa_gdbarch_init
, xtensa_dump_tdep
);
2713 xtensa_init_reggroups ();
2715 add_setshow_zinteger_cmd ("xtensa",
2717 &xtensa_debug_level
, _("\
2718 Set Xtensa debugging."), _("\
2719 Show Xtensa debugging."), _("\
2720 When non-zero, Xtensa-specific debugging is enabled. \
2721 Can be 1, 2, 3, or 4 indicating the level of debugging."),
2724 &setdebuglist
, &showdebuglist
);