1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003-2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "solib-svr4.h"
33 #include "reggroups.h"
36 #include "dummy-frame.h"
38 #include "dwarf2-frame.h"
39 #include "dwarf2loc.h"
40 #include "frame-base.h"
41 #include "frame-unwind.h"
43 #include "arch-utils.h"
51 #include "xtensa-isa.h"
52 #include "xtensa-tdep.h"
53 #include "xtensa-config.h"
57 static unsigned int xtensa_debug_level
= 0;
59 #define DEBUGWARN(args...) \
60 if (xtensa_debug_level > 0) \
61 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
63 #define DEBUGINFO(args...) \
64 if (xtensa_debug_level > 1) \
65 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
67 #define DEBUGTRACE(args...) \
68 if (xtensa_debug_level > 2) \
69 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
71 #define DEBUGVERB(args...) \
72 if (xtensa_debug_level > 3) \
73 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
76 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
77 #define SP_ALIGNMENT 16
80 /* On Windowed ABI, we use a6 through a11 for passing arguments
81 to a function called by GDB because CALL4 is used. */
82 #define ARGS_NUM_REGS 6
83 #define REGISTER_SIZE 4
86 /* Extract the call size from the return address or PS register. */
87 #define PS_CALLINC_SHIFT 16
88 #define PS_CALLINC_MASK 0x00030000
89 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
90 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
92 /* On TX, hardware can be configured without Exception Option.
93 There is no PS register in this case. Inside XT-GDB, let us treat
94 it as a virtual read-only register always holding the same value. */
97 /* ABI-independent macros. */
98 #define ARG_NOF(gdbarch) \
99 (gdbarch_tdep (gdbarch)->call_abi \
100 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
101 #define ARG_1ST(gdbarch) \
102 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
103 ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \
104 : (gdbarch_tdep (gdbarch)->a0_base + 6))
106 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
107 indicates that the instruction is an ENTRY instruction. */
109 #define XTENSA_IS_ENTRY(gdbarch, op1) \
110 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
111 ? ((op1) == 0x6c) : ((op1) == 0x36))
113 #define XTENSA_ENTRY_LENGTH 3
115 /* windowing_enabled() returns true, if windowing is enabled.
116 WOE must be set to 1; EXCM to 0.
117 Note: We assume that EXCM is always 0 for XEA1. */
119 #define PS_WOE (1<<18)
120 #define PS_EXC (1<<4)
122 /* Big enough to hold the size of the largest register in bytes. */
123 #define XTENSA_MAX_REGISTER_SIZE 64
126 windowing_enabled (struct gdbarch
*gdbarch
, unsigned int ps
)
128 /* If we know CALL0 ABI is set explicitly, say it is Call0. */
129 if (gdbarch_tdep (gdbarch
)->call_abi
== CallAbiCall0Only
)
132 return ((ps
& PS_EXC
) == 0 && (ps
& PS_WOE
) != 0);
135 /* Convert a live A-register number to the corresponding AR-register
138 arreg_number (struct gdbarch
*gdbarch
, int a_regnum
, ULONGEST wb
)
140 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
143 arreg
= a_regnum
- tdep
->a0_base
;
144 arreg
+= (wb
& ((tdep
->num_aregs
- 1) >> 2)) << WB_SHIFT
;
145 arreg
&= tdep
->num_aregs
- 1;
147 return arreg
+ tdep
->ar_base
;
150 /* Convert a live AR-register number to the corresponding A-register order
151 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
153 areg_number (struct gdbarch
*gdbarch
, int ar_regnum
, unsigned int wb
)
155 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
158 areg
= ar_regnum
- tdep
->ar_base
;
159 if (areg
< 0 || areg
>= tdep
->num_aregs
)
161 areg
= (areg
- wb
* 4) & (tdep
->num_aregs
- 1);
162 return (areg
> 15) ? -1 : areg
;
165 /* Read Xtensa register directly from the hardware. */
167 xtensa_read_register (int regnum
)
171 regcache_raw_read_unsigned (get_current_regcache (), regnum
, &value
);
172 return (unsigned long) value
;
175 /* Write Xtensa register directly to the hardware. */
177 xtensa_write_register (int regnum
, ULONGEST value
)
179 regcache_raw_write_unsigned (get_current_regcache (), regnum
, value
);
182 /* Return the window size of the previous call to the function from which we
185 This function is used to extract the return value after a called function
186 has returned to the caller. On Xtensa, the register that holds the return
187 value (from the perspective of the caller) depends on what call
188 instruction was used. For now, we are assuming that the call instruction
189 precedes the current address, so we simply analyze the call instruction.
190 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
191 method to call the inferior function. */
194 extract_call_winsize (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
196 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
201 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc
);
203 /* Read the previous instruction (should be a call[x]{4|8|12}. */
204 read_memory (pc
-3, buf
, 3);
205 insn
= extract_unsigned_integer (buf
, 3, byte_order
);
207 /* Decode call instruction:
209 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
210 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
212 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
213 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
215 if (byte_order
== BFD_ENDIAN_LITTLE
)
217 if (((insn
& 0xf) == 0x5) || ((insn
& 0xcf) == 0xc0))
218 winsize
= (insn
& 0x30) >> 2; /* 0, 4, 8, 12. */
222 if (((insn
>> 20) == 0x5) || (((insn
>> 16) & 0xf3) == 0x03))
223 winsize
= (insn
>> 16) & 0xc; /* 0, 4, 8, 12. */
229 /* REGISTER INFORMATION */
231 /* Find register by name. */
233 xtensa_find_register_by_name (struct gdbarch
*gdbarch
, const char *name
)
237 for (i
= 0; i
< gdbarch_num_regs (gdbarch
)
238 + gdbarch_num_pseudo_regs (gdbarch
);
241 if (strcasecmp (gdbarch_tdep (gdbarch
)->regmap
[i
].name
, name
) == 0)
247 /* Returns the name of a register. */
249 xtensa_register_name (struct gdbarch
*gdbarch
, int regnum
)
251 /* Return the name stored in the register map. */
252 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
)
253 + gdbarch_num_pseudo_regs (gdbarch
))
254 return gdbarch_tdep (gdbarch
)->regmap
[regnum
].name
;
256 internal_error (__FILE__
, __LINE__
, _("invalid register %d"), regnum
);
260 /* Return the type of a register. Create a new type, if necessary. */
263 xtensa_register_type (struct gdbarch
*gdbarch
, int regnum
)
265 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
267 /* Return signed integer for ARx and Ax registers. */
268 if ((regnum
>= tdep
->ar_base
269 && regnum
< tdep
->ar_base
+ tdep
->num_aregs
)
270 || (regnum
>= tdep
->a0_base
271 && regnum
< tdep
->a0_base
+ 16))
272 return builtin_type (gdbarch
)->builtin_int
;
274 if (regnum
== gdbarch_pc_regnum (gdbarch
)
275 || regnum
== tdep
->a0_base
+ 1)
276 return builtin_type (gdbarch
)->builtin_data_ptr
;
278 /* Return the stored type for all other registers. */
279 else if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
)
280 + gdbarch_num_pseudo_regs (gdbarch
))
282 xtensa_register_t
* reg
= &tdep
->regmap
[regnum
];
284 /* Set ctype for this register (only the first time). */
288 struct ctype_cache
*tp
;
289 int size
= reg
->byte_size
;
291 /* We always use the memory representation,
292 even if the register width is smaller. */
296 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint8
;
300 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint16
;
304 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint32
;
308 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint64
;
312 reg
->ctype
= builtin_type (gdbarch
)->builtin_uint128
;
316 for (tp
= tdep
->type_entries
; tp
!= NULL
; tp
= tp
->next
)
317 if (tp
->size
== size
)
322 char *name
= xstrprintf ("int%d", size
* 8);
324 tp
= XNEW (struct ctype_cache
);
325 tp
->next
= tdep
->type_entries
;
326 tdep
->type_entries
= tp
;
329 = arch_integer_type (gdbarch
, size
* 8, 1, name
);
333 reg
->ctype
= tp
->virtual_type
;
339 internal_error (__FILE__
, __LINE__
, _("invalid register number %d"), regnum
);
344 /* Return the 'local' register number for stubs, dwarf2, etc.
345 The debugging information enumerates registers starting from 0 for A0
346 to n for An. So, we only have to add the base number for A0. */
349 xtensa_reg_to_regnum (struct gdbarch
*gdbarch
, int regnum
)
353 if (regnum
>= 0 && regnum
< 16)
354 return gdbarch_tdep (gdbarch
)->a0_base
+ regnum
;
357 i
< gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
359 if (regnum
== gdbarch_tdep (gdbarch
)->regmap
[i
].target_number
)
366 /* Write the bits of a masked register to the various registers.
367 Only the masked areas of these registers are modified; the other
368 fields are untouched. The size of masked registers is always less
369 than or equal to 32 bits. */
372 xtensa_register_write_masked (struct regcache
*regcache
,
373 xtensa_register_t
*reg
, const gdb_byte
*buffer
)
375 unsigned int value
[(XTENSA_MAX_REGISTER_SIZE
+ 3) / 4];
376 const xtensa_mask_t
*mask
= reg
->mask
;
378 int shift
= 0; /* Shift for next mask (mod 32). */
379 int start
, size
; /* Start bit and size of current mask. */
381 unsigned int *ptr
= value
;
382 unsigned int regval
, m
, mem
= 0;
384 int bytesize
= reg
->byte_size
;
385 int bitsize
= bytesize
* 8;
388 DEBUGTRACE ("xtensa_register_write_masked ()\n");
390 /* Copy the masked register to host byte-order. */
391 if (gdbarch_byte_order (regcache
->arch ()) == BFD_ENDIAN_BIG
)
392 for (i
= 0; i
< bytesize
; i
++)
395 mem
|= (buffer
[bytesize
- i
- 1] << 24);
400 for (i
= 0; i
< bytesize
; i
++)
403 mem
|= (buffer
[i
] << 24);
408 /* We might have to shift the final value:
409 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
410 bytesize & 3 == x -> shift (4-x) * 8. */
412 *ptr
= mem
>> (((0 - bytesize
) & 3) * 8);
416 /* Write the bits to the masked areas of the other registers. */
417 for (i
= 0; i
< mask
->count
; i
++)
419 start
= mask
->mask
[i
].bit_start
;
420 size
= mask
->mask
[i
].bit_size
;
421 regval
= mem
>> shift
;
423 if ((shift
+= size
) > bitsize
)
424 error (_("size of all masks is larger than the register"));
433 regval
|= mem
<< (size
- shift
);
436 /* Make sure we have a valid register. */
437 r
= mask
->mask
[i
].reg_num
;
438 if (r
>= 0 && size
> 0)
440 /* Don't overwrite the unmasked areas. */
442 regcache_cooked_read_unsigned (regcache
, r
, &old_val
);
443 m
= 0xffffffff >> (32 - size
) << start
;
445 regval
= (regval
& m
) | (old_val
& ~m
);
446 regcache_cooked_write_unsigned (regcache
, r
, regval
);
452 /* Read a tie state or mapped registers. Read the masked areas
453 of the registers and assemble them into a single value. */
455 static enum register_status
456 xtensa_register_read_masked (struct regcache
*regcache
,
457 xtensa_register_t
*reg
, gdb_byte
*buffer
)
459 unsigned int value
[(XTENSA_MAX_REGISTER_SIZE
+ 3) / 4];
460 const xtensa_mask_t
*mask
= reg
->mask
;
465 unsigned int *ptr
= value
;
466 unsigned int regval
, mem
= 0;
468 int bytesize
= reg
->byte_size
;
469 int bitsize
= bytesize
* 8;
472 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
473 reg
->name
== 0 ? "" : reg
->name
);
475 /* Assemble the register from the masked areas of other registers. */
476 for (i
= 0; i
< mask
->count
; i
++)
478 int r
= mask
->mask
[i
].reg_num
;
481 enum register_status status
;
484 status
= regcache_cooked_read_unsigned (regcache
, r
, &val
);
485 if (status
!= REG_VALID
)
487 regval
= (unsigned int) val
;
492 start
= mask
->mask
[i
].bit_start
;
493 size
= mask
->mask
[i
].bit_size
;
498 regval
&= (0xffffffff >> (32 - size
));
500 mem
|= regval
<< shift
;
502 if ((shift
+= size
) > bitsize
)
503 error (_("size of all masks is larger than the register"));
514 mem
= regval
>> (size
- shift
);
521 /* Copy value to target byte order. */
525 if (gdbarch_byte_order (regcache
->arch ()) == BFD_ENDIAN_BIG
)
526 for (i
= 0; i
< bytesize
; i
++)
530 buffer
[bytesize
- i
- 1] = mem
& 0xff;
534 for (i
= 0; i
< bytesize
; i
++)
538 buffer
[i
] = mem
& 0xff;
546 /* Read pseudo registers. */
548 static enum register_status
549 xtensa_pseudo_register_read (struct gdbarch
*gdbarch
,
550 struct regcache
*regcache
,
554 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
555 regnum
, xtensa_register_name (gdbarch
, regnum
));
557 /* Read aliases a0..a15, if this is a Windowed ABI. */
558 if (gdbarch_tdep (gdbarch
)->isa_use_windowed_registers
559 && (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
)
560 && (regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15))
563 enum register_status status
;
565 status
= regcache_raw_read_unsigned (regcache
,
566 gdbarch_tdep (gdbarch
)->wb_regnum
,
568 if (status
!= REG_VALID
)
570 regnum
= arreg_number (gdbarch
, regnum
, value
);
573 /* We can always read non-pseudo registers. */
574 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
575 return regcache_raw_read (regcache
, regnum
, buffer
);
577 /* We have to find out how to deal with priveleged registers.
578 Let's treat them as pseudo-registers, but we cannot read/write them. */
580 else if (gdbarch_tdep (gdbarch
)->call_abi
== CallAbiCall0Only
581 || regnum
< gdbarch_tdep (gdbarch
)->a0_base
)
583 buffer
[0] = (gdb_byte
)0;
584 buffer
[1] = (gdb_byte
)0;
585 buffer
[2] = (gdb_byte
)0;
586 buffer
[3] = (gdb_byte
)0;
589 /* Pseudo registers. */
591 && regnum
< gdbarch_num_regs (gdbarch
)
592 + gdbarch_num_pseudo_regs (gdbarch
))
594 xtensa_register_t
*reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
595 xtensa_register_type_t type
= reg
->type
;
596 int flags
= gdbarch_tdep (gdbarch
)->target_flags
;
598 /* We cannot read Unknown or Unmapped registers. */
599 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
601 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
603 warning (_("cannot read register %s"),
604 xtensa_register_name (gdbarch
, regnum
));
609 /* Some targets cannot read TIE register files. */
610 else if (type
== xtRegisterTypeTieRegfile
)
612 /* Use 'fetch' to get register? */
613 if (flags
& xtTargetFlagsUseFetchStore
)
615 warning (_("cannot read register"));
619 /* On some targets (esp. simulators), we can always read the reg. */
620 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
622 warning (_("cannot read register"));
627 /* We can always read mapped registers. */
628 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
629 return xtensa_register_read_masked (regcache
, reg
, buffer
);
631 /* Assume that we can read the register. */
632 return regcache_raw_read (regcache
, regnum
, buffer
);
635 internal_error (__FILE__
, __LINE__
,
636 _("invalid register number %d"), regnum
);
640 /* Write pseudo registers. */
643 xtensa_pseudo_register_write (struct gdbarch
*gdbarch
,
644 struct regcache
*regcache
,
646 const gdb_byte
*buffer
)
648 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
649 regnum
, xtensa_register_name (gdbarch
, regnum
));
651 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
652 if (gdbarch_tdep (gdbarch
)->isa_use_windowed_registers
653 && (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
)
654 && (regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15))
657 regcache_raw_read_unsigned (regcache
,
658 gdbarch_tdep (gdbarch
)->wb_regnum
, &value
);
659 regnum
= arreg_number (gdbarch
, regnum
, value
);
662 /* We can always write 'core' registers.
663 Note: We might have converted Ax->ARy. */
664 if (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
))
665 regcache_raw_write (regcache
, regnum
, buffer
);
667 /* We have to find out how to deal with priveleged registers.
668 Let's treat them as pseudo-registers, but we cannot read/write them. */
670 else if (regnum
< gdbarch_tdep (gdbarch
)->a0_base
)
674 /* Pseudo registers. */
676 && regnum
< gdbarch_num_regs (gdbarch
)
677 + gdbarch_num_pseudo_regs (gdbarch
))
679 xtensa_register_t
*reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
680 xtensa_register_type_t type
= reg
->type
;
681 int flags
= gdbarch_tdep (gdbarch
)->target_flags
;
683 /* On most targets, we cannot write registers
684 of type "Unknown" or "Unmapped". */
685 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
687 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
689 warning (_("cannot write register %s"),
690 xtensa_register_name (gdbarch
, regnum
));
695 /* Some targets cannot read TIE register files. */
696 else if (type
== xtRegisterTypeTieRegfile
)
698 /* Use 'store' to get register? */
699 if (flags
& xtTargetFlagsUseFetchStore
)
701 warning (_("cannot write register"));
705 /* On some targets (esp. simulators), we can always write
707 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
709 warning (_("cannot write register"));
714 /* We can always write mapped registers. */
715 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
717 xtensa_register_write_masked (regcache
, reg
, buffer
);
721 /* Assume that we can write the register. */
722 regcache_raw_write (regcache
, regnum
, buffer
);
725 internal_error (__FILE__
, __LINE__
,
726 _("invalid register number %d"), regnum
);
729 static struct reggroup
*xtensa_ar_reggroup
;
730 static struct reggroup
*xtensa_user_reggroup
;
731 static struct reggroup
*xtensa_vectra_reggroup
;
732 static struct reggroup
*xtensa_cp
[XTENSA_MAX_COPROCESSOR
];
735 xtensa_init_reggroups (void)
739 xtensa_ar_reggroup
= reggroup_new ("ar", USER_REGGROUP
);
740 xtensa_user_reggroup
= reggroup_new ("user", USER_REGGROUP
);
741 xtensa_vectra_reggroup
= reggroup_new ("vectra", USER_REGGROUP
);
743 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
744 xtensa_cp
[i
] = reggroup_new (xstrprintf ("cp%d", i
), USER_REGGROUP
);
748 xtensa_add_reggroups (struct gdbarch
*gdbarch
)
752 /* Predefined groups. */
753 reggroup_add (gdbarch
, all_reggroup
);
754 reggroup_add (gdbarch
, save_reggroup
);
755 reggroup_add (gdbarch
, restore_reggroup
);
756 reggroup_add (gdbarch
, system_reggroup
);
757 reggroup_add (gdbarch
, vector_reggroup
);
758 reggroup_add (gdbarch
, general_reggroup
);
759 reggroup_add (gdbarch
, float_reggroup
);
761 /* Xtensa-specific groups. */
762 reggroup_add (gdbarch
, xtensa_ar_reggroup
);
763 reggroup_add (gdbarch
, xtensa_user_reggroup
);
764 reggroup_add (gdbarch
, xtensa_vectra_reggroup
);
766 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
767 reggroup_add (gdbarch
, xtensa_cp
[i
]);
771 xtensa_coprocessor_register_group (struct reggroup
*group
)
775 for (i
= 0; i
< XTENSA_MAX_COPROCESSOR
; i
++)
776 if (group
== xtensa_cp
[i
])
782 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
783 | XTENSA_REGISTER_FLAGS_WRITABLE \
784 | XTENSA_REGISTER_FLAGS_VOLATILE)
786 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
787 | XTENSA_REGISTER_FLAGS_WRITABLE)
790 xtensa_register_reggroup_p (struct gdbarch
*gdbarch
,
792 struct reggroup
*group
)
794 xtensa_register_t
* reg
= &gdbarch_tdep (gdbarch
)->regmap
[regnum
];
795 xtensa_register_type_t type
= reg
->type
;
796 xtensa_register_group_t rg
= reg
->group
;
799 if (group
== save_reggroup
)
800 /* Every single register should be included into the list of registers
801 to be watched for changes while using -data-list-changed-registers. */
804 /* First, skip registers that are not visible to this target
805 (unknown and unmapped registers when not using ISS). */
807 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
809 if (group
== all_reggroup
)
811 if (group
== xtensa_ar_reggroup
)
812 return rg
& xtRegisterGroupAddrReg
;
813 if (group
== xtensa_user_reggroup
)
814 return rg
& xtRegisterGroupUser
;
815 if (group
== float_reggroup
)
816 return rg
& xtRegisterGroupFloat
;
817 if (group
== general_reggroup
)
818 return rg
& xtRegisterGroupGeneral
;
819 if (group
== system_reggroup
)
820 return rg
& xtRegisterGroupState
;
821 if (group
== vector_reggroup
|| group
== xtensa_vectra_reggroup
)
822 return rg
& xtRegisterGroupVectra
;
823 if (group
== restore_reggroup
)
824 return (regnum
< gdbarch_num_regs (gdbarch
)
825 && (reg
->flags
& SAVE_REST_FLAGS
) == SAVE_REST_VALID
);
826 cp_number
= xtensa_coprocessor_register_group (group
);
828 return rg
& (xtRegisterGroupCP0
<< cp_number
);
834 /* Supply register REGNUM from the buffer specified by GREGS and LEN
835 in the general-purpose register set REGSET to register cache
836 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
839 xtensa_supply_gregset (const struct regset
*regset
,
845 const xtensa_elf_gregset_t
*regs
= (const xtensa_elf_gregset_t
*) gregs
;
846 struct gdbarch
*gdbarch
= rc
->arch ();
849 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum
);
851 if (regnum
== gdbarch_pc_regnum (gdbarch
) || regnum
== -1)
852 regcache_raw_supply (rc
, gdbarch_pc_regnum (gdbarch
), (char *) ®s
->pc
);
853 if (regnum
== gdbarch_ps_regnum (gdbarch
) || regnum
== -1)
854 regcache_raw_supply (rc
, gdbarch_ps_regnum (gdbarch
), (char *) ®s
->ps
);
855 if (regnum
== gdbarch_tdep (gdbarch
)->wb_regnum
|| regnum
== -1)
856 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->wb_regnum
,
857 (char *) ®s
->windowbase
);
858 if (regnum
== gdbarch_tdep (gdbarch
)->ws_regnum
|| regnum
== -1)
859 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->ws_regnum
,
860 (char *) ®s
->windowstart
);
861 if (regnum
== gdbarch_tdep (gdbarch
)->lbeg_regnum
|| regnum
== -1)
862 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lbeg_regnum
,
863 (char *) ®s
->lbeg
);
864 if (regnum
== gdbarch_tdep (gdbarch
)->lend_regnum
|| regnum
== -1)
865 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lend_regnum
,
866 (char *) ®s
->lend
);
867 if (regnum
== gdbarch_tdep (gdbarch
)->lcount_regnum
|| regnum
== -1)
868 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->lcount_regnum
,
869 (char *) ®s
->lcount
);
870 if (regnum
== gdbarch_tdep (gdbarch
)->sar_regnum
|| regnum
== -1)
871 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->sar_regnum
,
872 (char *) ®s
->sar
);
873 if (regnum
>=gdbarch_tdep (gdbarch
)->ar_base
874 && regnum
< gdbarch_tdep (gdbarch
)->ar_base
875 + gdbarch_tdep (gdbarch
)->num_aregs
)
876 regcache_raw_supply (rc
, regnum
,
877 (char *) ®s
->ar
[regnum
- gdbarch_tdep
878 (gdbarch
)->ar_base
]);
879 else if (regnum
== -1)
881 for (i
= 0; i
< gdbarch_tdep (gdbarch
)->num_aregs
; ++i
)
882 regcache_raw_supply (rc
, gdbarch_tdep (gdbarch
)->ar_base
+ i
,
883 (char *) ®s
->ar
[i
]);
888 /* Xtensa register set. */
894 xtensa_supply_gregset
898 /* Iterate over supported core file register note sections. */
901 xtensa_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
902 iterate_over_regset_sections_cb
*cb
,
904 const struct regcache
*regcache
)
906 DEBUGTRACE ("xtensa_iterate_over_regset_sections\n");
908 cb (".reg", sizeof (xtensa_elf_gregset_t
), &xtensa_gregset
,
913 /* Handling frames. */
915 /* Number of registers to save in case of Windowed ABI. */
916 #define XTENSA_NUM_SAVED_AREGS 12
918 /* Frame cache part for Windowed ABI. */
919 typedef struct xtensa_windowed_frame_cache
921 int wb
; /* WINDOWBASE of the previous frame. */
922 int callsize
; /* Call size of this frame. */
923 int ws
; /* WINDOWSTART of the previous frame. It keeps track of
924 life windows only. If there is no bit set for the
925 window, that means it had been already spilled
926 because of window overflow. */
928 /* Addresses of spilled A-registers.
929 AREGS[i] == -1, if corresponding AR is alive. */
930 CORE_ADDR aregs
[XTENSA_NUM_SAVED_AREGS
];
931 } xtensa_windowed_frame_cache_t
;
933 /* Call0 ABI Definitions. */
935 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue
937 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
938 #define C0_SP 1 /* Register used as SP. */
939 #define C0_FP 15 /* Register used as FP. */
940 #define C0_RA 0 /* Register used as return address. */
941 #define C0_ARGS 2 /* Register used as first arg/retval. */
942 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
944 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
945 A-register where the current content of the reg came from (in terms
946 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
947 mean that the orignal content of the register was saved to the stack.
948 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
949 know where SP will end up until the entire prologue has been analyzed. */
951 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
952 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
953 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
955 extern xtensa_isa xtensa_default_isa
;
957 typedef struct xtensa_c0reg
959 int fr_reg
; /* original register from which register content
960 is derived, or C0_CONST, or C0_INEXP. */
961 int fr_ofs
; /* constant offset from reg, or immediate value. */
962 int to_stk
; /* offset from original SP to register (4-byte aligned),
963 or C0_NOSTK if register has not been saved. */
966 /* Frame cache part for Call0 ABI. */
967 typedef struct xtensa_call0_frame_cache
969 int c0_frmsz
; /* Stack frame size. */
970 int c0_hasfp
; /* Current frame uses frame pointer. */
971 int fp_regnum
; /* A-register used as FP. */
972 int c0_fp
; /* Actual value of frame pointer. */
973 int c0_fpalign
; /* Dinamic adjustment for the stack
974 pointer. It's an AND mask. Zero,
975 if alignment was not adjusted. */
976 int c0_old_sp
; /* In case of dynamic adjustment, it is
977 a register holding unaligned sp.
978 C0_INEXP, when undefined. */
979 int c0_sp_ofs
; /* If "c0_old_sp" was spilled it's a
980 stack offset. C0_NOSTK otherwise. */
982 xtensa_c0reg_t c0_rt
[C0_NREGS
]; /* Register tracking information. */
983 } xtensa_call0_frame_cache_t
;
985 typedef struct xtensa_frame_cache
987 CORE_ADDR base
; /* Stack pointer of this frame. */
988 CORE_ADDR pc
; /* PC of this frame at the function entry point. */
989 CORE_ADDR ra
; /* The raw return address of this frame. */
990 CORE_ADDR ps
; /* The PS register of the previous (older) frame. */
991 CORE_ADDR prev_sp
; /* Stack Pointer of the previous (older) frame. */
992 int call0
; /* It's a call0 framework (else windowed). */
995 xtensa_windowed_frame_cache_t wd
; /* call0 == false. */
996 xtensa_call0_frame_cache_t c0
; /* call0 == true. */
998 } xtensa_frame_cache_t
;
1001 static struct xtensa_frame_cache
*
1002 xtensa_alloc_frame_cache (int windowed
)
1004 xtensa_frame_cache_t
*cache
;
1007 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
1009 cache
= FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t
);
1016 cache
->call0
= !windowed
;
1019 cache
->c0
.c0_frmsz
= -1;
1020 cache
->c0
.c0_hasfp
= 0;
1021 cache
->c0
.fp_regnum
= -1;
1022 cache
->c0
.c0_fp
= -1;
1023 cache
->c0
.c0_fpalign
= 0;
1024 cache
->c0
.c0_old_sp
= C0_INEXP
;
1025 cache
->c0
.c0_sp_ofs
= C0_NOSTK
;
1027 for (i
= 0; i
< C0_NREGS
; i
++)
1029 cache
->c0
.c0_rt
[i
].fr_reg
= i
;
1030 cache
->c0
.c0_rt
[i
].fr_ofs
= 0;
1031 cache
->c0
.c0_rt
[i
].to_stk
= C0_NOSTK
;
1038 cache
->wd
.callsize
= -1;
1040 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
1041 cache
->wd
.aregs
[i
] = -1;
1048 xtensa_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
1050 return address
& ~15;
1055 xtensa_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1060 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1061 host_address_to_string (next_frame
));
1063 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1064 pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1066 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc
);
1072 static struct frame_id
1073 xtensa_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1077 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1079 pc
= get_frame_pc (this_frame
);
1080 fp
= get_frame_register_unsigned
1081 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1083 /* Make dummy frame ID unique by adding a constant. */
1084 return frame_id_build (fp
+ SP_ALIGNMENT
, pc
);
1087 /* Returns true, if instruction to execute next is unique to Xtensa Window
1088 Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */
1091 xtensa_window_interrupt_insn (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1093 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1094 unsigned int insn
= read_memory_integer (pc
, 4, byte_order
);
1097 if (byte_order
== BFD_ENDIAN_BIG
)
1099 /* Check, if this is L32E or S32E. */
1100 code
= insn
& 0xf000ff00;
1101 if ((code
== 0x00009000) || (code
== 0x00009400))
1103 /* Check, if this is RFWU or RFWO. */
1104 code
= insn
& 0xffffff00;
1105 return ((code
== 0x00430000) || (code
== 0x00530000));
1109 /* Check, if this is L32E or S32E. */
1110 code
= insn
& 0x00ff000f;
1111 if ((code
== 0x090000) || (code
== 0x490000))
1113 /* Check, if this is RFWU or RFWO. */
1114 code
= insn
& 0x00ffffff;
1115 return ((code
== 0x00003400) || (code
== 0x00003500));
1119 /* Returns the best guess about which register is a frame pointer
1120 for the function containing CURRENT_PC. */
1122 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1123 #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */
1126 xtensa_scan_prologue (struct gdbarch
*gdbarch
, CORE_ADDR current_pc
)
1128 #define RETURN_FP goto done
1130 unsigned int fp_regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ 1;
1131 CORE_ADDR start_addr
;
1133 xtensa_insnbuf ins
, slot
;
1134 gdb_byte ibuf
[XTENSA_ISA_BSZ
];
1135 CORE_ADDR ia
, bt
, ba
;
1137 int ilen
, islots
, is
;
1139 const char *opcname
;
1141 find_pc_partial_function (current_pc
, NULL
, &start_addr
, NULL
);
1142 if (start_addr
== 0)
1145 isa
= xtensa_default_isa
;
1146 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
1147 ins
= xtensa_insnbuf_alloc (isa
);
1148 slot
= xtensa_insnbuf_alloc (isa
);
1151 for (ia
= start_addr
, bt
= ia
; ia
< current_pc
; ia
+= ilen
)
1153 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
1156 bt
= (ba
+ XTENSA_ISA_BSZ
) < current_pc
1157 ? ba
+ XTENSA_ISA_BSZ
: current_pc
;
1158 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0)
1162 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
1163 ifmt
= xtensa_format_decode (isa
, ins
);
1164 if (ifmt
== XTENSA_UNDEFINED
)
1166 ilen
= xtensa_format_length (isa
, ifmt
);
1167 if (ilen
== XTENSA_UNDEFINED
)
1169 islots
= xtensa_format_num_slots (isa
, ifmt
);
1170 if (islots
== XTENSA_UNDEFINED
)
1173 for (is
= 0; is
< islots
; ++is
)
1175 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
1178 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
1179 if (opc
== XTENSA_UNDEFINED
)
1182 opcname
= xtensa_opcode_name (isa
, opc
);
1184 if (strcasecmp (opcname
, "mov.n") == 0
1185 || strcasecmp (opcname
, "or") == 0)
1187 unsigned int register_operand
;
1189 /* Possible candidate for setting frame pointer
1190 from A1. This is what we are looking for. */
1192 if (xtensa_operand_get_field (isa
, opc
, 1, ifmt
,
1193 is
, slot
, ®ister_operand
) != 0)
1195 if (xtensa_operand_decode (isa
, opc
, 1, ®ister_operand
) != 0)
1197 if (register_operand
== 1) /* Mov{.n} FP A1. */
1199 if (xtensa_operand_get_field (isa
, opc
, 0, ifmt
, is
, slot
,
1200 ®ister_operand
) != 0)
1202 if (xtensa_operand_decode (isa
, opc
, 0,
1203 ®ister_operand
) != 0)
1207 = gdbarch_tdep (gdbarch
)->a0_base
+ register_operand
;
1213 /* We have problems decoding the memory. */
1215 || strcasecmp (opcname
, "ill") == 0
1216 || strcasecmp (opcname
, "ill.n") == 0
1217 /* Hit planted breakpoint. */
1218 || strcasecmp (opcname
, "break") == 0
1219 || strcasecmp (opcname
, "break.n") == 0
1220 /* Flow control instructions finish prologue. */
1221 || xtensa_opcode_is_branch (isa
, opc
) > 0
1222 || xtensa_opcode_is_jump (isa
, opc
) > 0
1223 || xtensa_opcode_is_loop (isa
, opc
) > 0
1224 || xtensa_opcode_is_call (isa
, opc
) > 0
1225 || strcasecmp (opcname
, "simcall") == 0
1226 || strcasecmp (opcname
, "syscall") == 0)
1227 /* Can not continue analysis. */
1232 xtensa_insnbuf_free(isa
, slot
);
1233 xtensa_insnbuf_free(isa
, ins
);
1237 /* The key values to identify the frame using "cache" are
1239 cache->base = SP (or best guess about FP) of this frame;
1240 cache->pc = entry-PC (entry point of the frame function);
1241 cache->prev_sp = SP of the previous frame. */
1244 call0_frame_cache (struct frame_info
*this_frame
,
1245 xtensa_frame_cache_t
*cache
, CORE_ADDR pc
);
1248 xtensa_window_interrupt_frame_cache (struct frame_info
*this_frame
,
1249 xtensa_frame_cache_t
*cache
,
1252 static struct xtensa_frame_cache
*
1253 xtensa_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1255 xtensa_frame_cache_t
*cache
;
1256 CORE_ADDR ra
, wb
, ws
, pc
, sp
, ps
;
1257 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1258 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1259 unsigned int fp_regnum
;
1260 int windowed
, ps_regnum
;
1263 return (struct xtensa_frame_cache
*) *this_cache
;
1265 pc
= get_frame_register_unsigned (this_frame
, gdbarch_pc_regnum (gdbarch
));
1266 ps_regnum
= gdbarch_ps_regnum (gdbarch
);
1267 ps
= (ps_regnum
>= 0
1268 ? get_frame_register_unsigned (this_frame
, ps_regnum
) : TX_PS
);
1270 windowed
= windowing_enabled (gdbarch
, ps
);
1272 /* Get pristine xtensa-frame. */
1273 cache
= xtensa_alloc_frame_cache (windowed
);
1274 *this_cache
= cache
;
1280 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1281 wb
= get_frame_register_unsigned (this_frame
,
1282 gdbarch_tdep (gdbarch
)->wb_regnum
);
1283 ws
= get_frame_register_unsigned (this_frame
,
1284 gdbarch_tdep (gdbarch
)->ws_regnum
);
1286 if (safe_read_memory_integer (pc
, 1, byte_order
, &op1
)
1287 && XTENSA_IS_ENTRY (gdbarch
, op1
))
1289 int callinc
= CALLINC (ps
);
1290 ra
= get_frame_register_unsigned
1291 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ callinc
* 4);
1293 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1294 cache
->wd
.callsize
= 0;
1297 cache
->prev_sp
= get_frame_register_unsigned
1298 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1300 /* This only can be the outermost frame since we are
1301 just about to execute ENTRY. SP hasn't been set yet.
1302 We can assume any frame size, because it does not
1303 matter, and, let's fake frame base in cache. */
1304 cache
->base
= cache
->prev_sp
- 16;
1307 cache
->ra
= (cache
->pc
& 0xc0000000) | (ra
& 0x3fffffff);
1308 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1309 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1315 fp_regnum
= xtensa_scan_prologue (gdbarch
, pc
);
1316 ra
= get_frame_register_unsigned (this_frame
,
1317 gdbarch_tdep (gdbarch
)->a0_base
);
1318 cache
->wd
.callsize
= WINSIZE (ra
);
1319 cache
->wd
.wb
= (wb
- cache
->wd
.callsize
/ 4)
1320 & (gdbarch_tdep (gdbarch
)->num_aregs
/ 4 - 1);
1321 cache
->wd
.ws
= ws
& ~(1 << wb
);
1323 cache
->pc
= get_frame_func (this_frame
);
1324 cache
->ra
= (pc
& 0xc0000000) | (ra
& 0x3fffffff);
1325 cache
->ps
= (ps
& ~PS_CALLINC_MASK
)
1326 | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
1329 if (cache
->wd
.ws
== 0)
1334 sp
= get_frame_register_unsigned
1335 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1) - 16;
1337 for (i
= 0; i
< 4; i
++, sp
+= 4)
1339 cache
->wd
.aregs
[i
] = sp
;
1342 if (cache
->wd
.callsize
> 4)
1344 /* Set A4...A7/A11. */
1345 /* Get the SP of the frame previous to the previous one.
1346 To achieve this, we have to dereference SP twice. */
1347 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4, byte_order
);
1348 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4, byte_order
);
1349 sp
-= cache
->wd
.callsize
* 4;
1351 for ( i
= 4; i
< cache
->wd
.callsize
; i
++, sp
+= 4)
1353 cache
->wd
.aregs
[i
] = sp
;
1358 if ((cache
->prev_sp
== 0) && ( ra
!= 0 ))
1359 /* If RA is equal to 0 this frame is an outermost frame. Leave
1360 cache->prev_sp unchanged marking the boundary of the frame stack. */
1362 if ((cache
->wd
.ws
& (1 << cache
->wd
.wb
)) == 0)
1364 /* Register window overflow already happened.
1365 We can read caller's SP from the proper spill loction. */
1366 sp
= get_frame_register_unsigned
1367 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
1368 cache
->prev_sp
= read_memory_integer (sp
- 12, 4, byte_order
);
1372 /* Read caller's frame SP directly from the previous window. */
1373 int regnum
= arreg_number
1374 (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ 1,
1377 cache
->prev_sp
= xtensa_read_register (regnum
);
1381 else if (xtensa_window_interrupt_insn (gdbarch
, pc
))
1383 /* Execution stopped inside Xtensa Window Interrupt Handler. */
1385 xtensa_window_interrupt_frame_cache (this_frame
, cache
, pc
);
1386 /* Everything was set already, including cache->base. */
1389 else /* Call0 framework. */
1391 call0_frame_cache (this_frame
, cache
, pc
);
1392 fp_regnum
= cache
->c0
.fp_regnum
;
1395 cache
->base
= get_frame_register_unsigned (this_frame
, fp_regnum
);
1400 static int xtensa_session_once_reported
= 1;
1402 /* Report a problem with prologue analysis while doing backtracing.
1403 But, do it only once to avoid annoyng repeated messages. */
1408 if (xtensa_session_once_reported
== 0)
1410 \nUnrecognised function prologue. Stack trace cannot be resolved. \
1411 This message will not be repeated in this session.\n"));
1413 xtensa_session_once_reported
= 1;
1418 xtensa_frame_this_id (struct frame_info
*this_frame
,
1420 struct frame_id
*this_id
)
1422 struct xtensa_frame_cache
*cache
=
1423 xtensa_frame_cache (this_frame
, this_cache
);
1425 if (cache
->prev_sp
== 0)
1428 (*this_id
) = frame_id_build (cache
->prev_sp
, cache
->pc
);
1431 static struct value
*
1432 xtensa_frame_prev_register (struct frame_info
*this_frame
,
1436 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1437 struct xtensa_frame_cache
*cache
;
1438 ULONGEST saved_reg
= 0;
1441 if (*this_cache
== NULL
)
1442 *this_cache
= xtensa_frame_cache (this_frame
, this_cache
);
1443 cache
= (struct xtensa_frame_cache
*) *this_cache
;
1445 if (regnum
==gdbarch_pc_regnum (gdbarch
))
1446 saved_reg
= cache
->ra
;
1447 else if (regnum
== gdbarch_tdep (gdbarch
)->a0_base
+ 1)
1448 saved_reg
= cache
->prev_sp
;
1449 else if (!cache
->call0
)
1451 if (regnum
== gdbarch_tdep (gdbarch
)->ws_regnum
)
1452 saved_reg
= cache
->wd
.ws
;
1453 else if (regnum
== gdbarch_tdep (gdbarch
)->wb_regnum
)
1454 saved_reg
= cache
->wd
.wb
;
1455 else if (regnum
== gdbarch_ps_regnum (gdbarch
))
1456 saved_reg
= cache
->ps
;
1464 return frame_unwind_got_constant (this_frame
, regnum
, saved_reg
);
1466 if (!cache
->call0
) /* Windowed ABI. */
1468 /* Convert A-register numbers to AR-register numbers,
1469 if we deal with A-register. */
1470 if (regnum
>= gdbarch_tdep (gdbarch
)->a0_base
1471 && regnum
<= gdbarch_tdep (gdbarch
)->a0_base
+ 15)
1472 regnum
= arreg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1474 /* Check, if we deal with AR-register saved on stack. */
1475 if (regnum
>= gdbarch_tdep (gdbarch
)->ar_base
1476 && regnum
<= (gdbarch_tdep (gdbarch
)->ar_base
1477 + gdbarch_tdep (gdbarch
)->num_aregs
))
1479 int areg
= areg_number (gdbarch
, regnum
, cache
->wd
.wb
);
1482 && areg
< XTENSA_NUM_SAVED_AREGS
1483 && cache
->wd
.aregs
[areg
] != -1)
1484 return frame_unwind_got_memory (this_frame
, regnum
,
1485 cache
->wd
.aregs
[areg
]);
1488 else /* Call0 ABI. */
1490 int reg
= (regnum
>= gdbarch_tdep (gdbarch
)->ar_base
1491 && regnum
<= (gdbarch_tdep (gdbarch
)->ar_base
1493 ? regnum
- gdbarch_tdep (gdbarch
)->ar_base
: regnum
;
1500 /* If register was saved in the prologue, retrieve it. */
1501 stkofs
= cache
->c0
.c0_rt
[reg
].to_stk
;
1502 if (stkofs
!= C0_NOSTK
)
1504 /* Determine SP on entry based on FP. */
1505 spe
= cache
->c0
.c0_fp
1506 - cache
->c0
.c0_rt
[cache
->c0
.fp_regnum
].fr_ofs
;
1508 return frame_unwind_got_memory (this_frame
, regnum
,
1514 /* All other registers have been either saved to
1515 the stack or are still alive in the processor. */
1517 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1521 static const struct frame_unwind
1525 default_frame_unwind_stop_reason
,
1526 xtensa_frame_this_id
,
1527 xtensa_frame_prev_register
,
1529 default_frame_sniffer
1533 xtensa_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1535 struct xtensa_frame_cache
*cache
=
1536 xtensa_frame_cache (this_frame
, this_cache
);
1541 static const struct frame_base
1545 xtensa_frame_base_address
,
1546 xtensa_frame_base_address
,
1547 xtensa_frame_base_address
1552 xtensa_extract_return_value (struct type
*type
,
1553 struct regcache
*regcache
,
1556 struct gdbarch
*gdbarch
= regcache
->arch ();
1557 bfd_byte
*valbuf
= (bfd_byte
*) dst
;
1558 int len
= TYPE_LENGTH (type
);
1563 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1565 gdb_assert(len
> 0);
1567 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1569 /* First, we have to find the caller window in the register file. */
1570 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1571 callsize
= extract_call_winsize (gdbarch
, pc
);
1573 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1574 if (len
> (callsize
> 8 ? 8 : 16))
1575 internal_error (__FILE__
, __LINE__
,
1576 _("cannot extract return value of %d bytes long"),
1579 /* Get the register offset of the return
1580 register (A2) in the caller window. */
1581 regcache_raw_read_unsigned
1582 (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, &wb
);
1583 areg
= arreg_number (gdbarch
,
1584 gdbarch_tdep (gdbarch
)->a0_base
+ 2 + callsize
, wb
);
1588 /* No windowing hardware - Call0 ABI. */
1589 areg
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_ARGS
;
1592 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg
, len
);
1594 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1597 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1600 regcache_raw_read_part (regcache
, areg
, offset
, len
, valbuf
);
1602 regcache_raw_read (regcache
, areg
, valbuf
);
1608 xtensa_store_return_value (struct type
*type
,
1609 struct regcache
*regcache
,
1612 struct gdbarch
*gdbarch
= regcache
->arch ();
1613 const bfd_byte
*valbuf
= (const bfd_byte
*) dst
;
1617 int len
= TYPE_LENGTH (type
);
1620 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1622 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1624 regcache_raw_read_unsigned
1625 (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, &wb
);
1626 regcache_raw_read_unsigned (regcache
, gdbarch_pc_regnum (gdbarch
), &pc
);
1627 callsize
= extract_call_winsize (gdbarch
, pc
);
1629 if (len
> (callsize
> 8 ? 8 : 16))
1630 internal_error (__FILE__
, __LINE__
,
1631 _("unimplemented for this length: %d"),
1632 TYPE_LENGTH (type
));
1633 areg
= arreg_number (gdbarch
,
1634 gdbarch_tdep (gdbarch
)->a0_base
+ 2 + callsize
, wb
);
1636 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1637 callsize
, (int) wb
);
1641 areg
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_ARGS
;
1644 if (len
< 4 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1647 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1650 regcache_raw_write_part (regcache
, areg
, offset
, len
, valbuf
);
1652 regcache_raw_write (regcache
, areg
, valbuf
);
1657 static enum return_value_convention
1658 xtensa_return_value (struct gdbarch
*gdbarch
,
1659 struct value
*function
,
1660 struct type
*valtype
,
1661 struct regcache
*regcache
,
1663 const gdb_byte
*writebuf
)
1665 /* Structures up to 16 bytes are returned in registers. */
1667 int struct_return
= ((TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
1668 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
1669 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
1670 && TYPE_LENGTH (valtype
) > 16);
1673 return RETURN_VALUE_STRUCT_CONVENTION
;
1675 DEBUGTRACE ("xtensa_return_value(...)\n");
1677 if (writebuf
!= NULL
)
1679 xtensa_store_return_value (valtype
, regcache
, writebuf
);
1682 if (readbuf
!= NULL
)
1684 gdb_assert (!struct_return
);
1685 xtensa_extract_return_value (valtype
, regcache
, readbuf
);
1687 return RETURN_VALUE_REGISTER_CONVENTION
;
1694 xtensa_push_dummy_call (struct gdbarch
*gdbarch
,
1695 struct value
*function
,
1696 struct regcache
*regcache
,
1699 struct value
**args
,
1702 CORE_ADDR struct_addr
)
1704 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1706 int size
, onstack_size
;
1707 gdb_byte
*buf
= (gdb_byte
*) alloca (16);
1709 struct argument_info
1711 const bfd_byte
*contents
;
1713 int onstack
; /* onstack == 0 => in reg */
1714 int align
; /* alignment */
1717 int offset
; /* stack offset if on stack. */
1718 int regno
; /* regno if in register. */
1722 struct argument_info
*arg_info
=
1723 (struct argument_info
*) alloca (nargs
* sizeof (struct argument_info
));
1727 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1729 if (xtensa_debug_level
> 3)
1732 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs
);
1733 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1734 "struct_addr=0x%x\n",
1735 (int) sp
, (int) struct_return
, (int) struct_addr
);
1737 for (i
= 0; i
< nargs
; i
++)
1739 struct value
*arg
= args
[i
];
1740 struct type
*arg_type
= check_typedef (value_type (arg
));
1741 fprintf_unfiltered (gdb_stdlog
, "%2d: %s %3d ", i
,
1742 host_address_to_string (arg
),
1743 TYPE_LENGTH (arg_type
));
1744 switch (TYPE_CODE (arg_type
))
1747 fprintf_unfiltered (gdb_stdlog
, "int");
1749 case TYPE_CODE_STRUCT
:
1750 fprintf_unfiltered (gdb_stdlog
, "struct");
1753 fprintf_unfiltered (gdb_stdlog
, "%3d", TYPE_CODE (arg_type
));
1756 fprintf_unfiltered (gdb_stdlog
, " %s\n",
1757 host_address_to_string (value_contents (arg
)));
1761 /* First loop: collect information.
1762 Cast into type_long. (This shouldn't happen often for C because
1763 GDB already does this earlier.) It's possible that GDB could
1764 do it all the time but it's harmless to leave this code here. */
1771 size
= REGISTER_SIZE
;
1773 for (i
= 0; i
< nargs
; i
++)
1775 struct argument_info
*info
= &arg_info
[i
];
1776 struct value
*arg
= args
[i
];
1777 struct type
*arg_type
= check_typedef (value_type (arg
));
1779 switch (TYPE_CODE (arg_type
))
1782 case TYPE_CODE_BOOL
:
1783 case TYPE_CODE_CHAR
:
1784 case TYPE_CODE_RANGE
:
1785 case TYPE_CODE_ENUM
:
1787 /* Cast argument to long if necessary as the mask does it too. */
1788 if (TYPE_LENGTH (arg_type
)
1789 < TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
))
1791 arg_type
= builtin_type (gdbarch
)->builtin_long
;
1792 arg
= value_cast (arg_type
, arg
);
1794 /* Aligment is equal to the type length for the basic types. */
1795 info
->align
= TYPE_LENGTH (arg_type
);
1800 /* Align doubles correctly. */
1801 if (TYPE_LENGTH (arg_type
)
1802 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
))
1803 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
);
1805 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
);
1808 case TYPE_CODE_STRUCT
:
1810 info
->align
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_long
);
1813 info
->length
= TYPE_LENGTH (arg_type
);
1814 info
->contents
= value_contents (arg
);
1816 /* Align size and onstack_size. */
1817 size
= (size
+ info
->align
- 1) & ~(info
->align
- 1);
1818 onstack_size
= (onstack_size
+ info
->align
- 1) & ~(info
->align
- 1);
1820 if (size
+ info
->length
> REGISTER_SIZE
* ARG_NOF (gdbarch
))
1823 info
->u
.offset
= onstack_size
;
1824 onstack_size
+= info
->length
;
1829 info
->u
.regno
= ARG_1ST (gdbarch
) + size
/ REGISTER_SIZE
;
1831 size
+= info
->length
;
1834 /* Adjust the stack pointer and align it. */
1835 sp
= align_down (sp
- onstack_size
, SP_ALIGNMENT
);
1837 /* Simulate MOVSP, if Windowed ABI. */
1838 if ((gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1841 read_memory (osp
- 16, buf
, 16);
1842 write_memory (sp
- 16, buf
, 16);
1845 /* Second Loop: Load arguments. */
1849 store_unsigned_integer (buf
, REGISTER_SIZE
, byte_order
, struct_addr
);
1850 regcache_cooked_write (regcache
, ARG_1ST (gdbarch
), buf
);
1853 for (i
= 0; i
< nargs
; i
++)
1855 struct argument_info
*info
= &arg_info
[i
];
1859 int n
= info
->length
;
1860 CORE_ADDR offset
= sp
+ info
->u
.offset
;
1862 /* Odd-sized structs are aligned to the lower side of a memory
1863 word in big-endian mode and require a shift. This only
1864 applies for structures smaller than one word. */
1866 if (n
< REGISTER_SIZE
1867 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1868 offset
+= (REGISTER_SIZE
- n
);
1870 write_memory (offset
, info
->contents
, info
->length
);
1875 int n
= info
->length
;
1876 const bfd_byte
*cp
= info
->contents
;
1877 int r
= info
->u
.regno
;
1879 /* Odd-sized structs are aligned to the lower side of registers in
1880 big-endian mode and require a shift. The odd-sized leftover will
1881 be at the end. Note that this is only true for structures smaller
1882 than REGISTER_SIZE; for larger odd-sized structures the excess
1883 will be left-aligned in the register on both endiannesses. */
1885 if (n
< REGISTER_SIZE
&& byte_order
== BFD_ENDIAN_BIG
)
1888 v
= extract_unsigned_integer (cp
, REGISTER_SIZE
, byte_order
);
1889 v
= v
>> ((REGISTER_SIZE
- n
) * TARGET_CHAR_BIT
);
1891 store_unsigned_integer (buf
, REGISTER_SIZE
, byte_order
, v
);
1892 regcache_cooked_write (regcache
, r
, buf
);
1894 cp
+= REGISTER_SIZE
;
1901 regcache_cooked_write (regcache
, r
, cp
);
1903 cp
+= REGISTER_SIZE
;
1910 /* Set the return address of dummy frame to the dummy address.
1911 The return address for the current function (in A0) is
1912 saved in the dummy frame, so we can savely overwrite A0 here. */
1914 if (gdbarch_tdep (gdbarch
)->call_abi
!= CallAbiCall0Only
)
1918 ra
= (bp_addr
& 0x3fffffff) | 0x40000000;
1919 regcache_raw_read_unsigned (regcache
, gdbarch_ps_regnum (gdbarch
), &val
);
1920 ps
= (unsigned long) val
& ~0x00030000;
1921 regcache_cooked_write_unsigned
1922 (regcache
, gdbarch_tdep (gdbarch
)->a0_base
+ 4, ra
);
1923 regcache_cooked_write_unsigned (regcache
,
1924 gdbarch_ps_regnum (gdbarch
),
1927 /* All the registers have been saved. After executing
1928 dummy call, they all will be restored. So it's safe
1929 to modify WINDOWSTART register to make it look like there
1930 is only one register window corresponding to WINDOWEBASE. */
1932 regcache_raw_read (regcache
, gdbarch_tdep (gdbarch
)->wb_regnum
, buf
);
1933 regcache_cooked_write_unsigned
1934 (regcache
, gdbarch_tdep (gdbarch
)->ws_regnum
,
1935 1 << extract_unsigned_integer (buf
, 4, byte_order
));
1939 /* Simulate CALL0: write RA into A0 register. */
1940 regcache_cooked_write_unsigned
1941 (regcache
, gdbarch_tdep (gdbarch
)->a0_base
, bp_addr
);
1944 /* Set new stack pointer and return it. */
1945 regcache_cooked_write_unsigned (regcache
,
1946 gdbarch_tdep (gdbarch
)->a0_base
+ 1, sp
);
1947 /* Make dummy frame ID unique by adding a constant. */
1948 return sp
+ SP_ALIGNMENT
;
1951 /* Implement the breakpoint_kind_from_pc gdbarch method. */
1954 xtensa_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
1956 if (gdbarch_tdep (gdbarch
)->isa_use_density_instructions
)
1962 /* Return a breakpoint for the current location of PC. We always use
1963 the density version if we have density instructions (regardless of the
1964 current instruction at PC), and use regular instructions otherwise. */
1966 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1967 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1968 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1969 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1971 /* Implement the sw_breakpoint_from_kind gdbarch method. */
1973 static const gdb_byte
*
1974 xtensa_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
1980 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
1981 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
1983 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1984 return big_breakpoint
;
1986 return little_breakpoint
;
1990 static unsigned char density_big_breakpoint
[] = DENSITY_BIG_BREAKPOINT
;
1991 static unsigned char density_little_breakpoint
[]
1992 = DENSITY_LITTLE_BREAKPOINT
;
1994 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1995 return density_big_breakpoint
;
1997 return density_little_breakpoint
;
2001 /* Call0 ABI support routines. */
2003 /* Return true, if PC points to "ret" or "ret.n". */
2006 call0_ret (CORE_ADDR start_pc
, CORE_ADDR finish_pc
)
2008 #define RETURN_RET goto done
2010 xtensa_insnbuf ins
, slot
;
2011 gdb_byte ibuf
[XTENSA_ISA_BSZ
];
2012 CORE_ADDR ia
, bt
, ba
;
2014 int ilen
, islots
, is
;
2016 const char *opcname
;
2019 isa
= xtensa_default_isa
;
2020 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2021 ins
= xtensa_insnbuf_alloc (isa
);
2022 slot
= xtensa_insnbuf_alloc (isa
);
2025 for (ia
= start_pc
, bt
= ia
; ia
< finish_pc
; ia
+= ilen
)
2027 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2030 bt
= (ba
+ XTENSA_ISA_BSZ
) < finish_pc
2031 ? ba
+ XTENSA_ISA_BSZ
: finish_pc
;
2032 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0 )
2036 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2037 ifmt
= xtensa_format_decode (isa
, ins
);
2038 if (ifmt
== XTENSA_UNDEFINED
)
2040 ilen
= xtensa_format_length (isa
, ifmt
);
2041 if (ilen
== XTENSA_UNDEFINED
)
2043 islots
= xtensa_format_num_slots (isa
, ifmt
);
2044 if (islots
== XTENSA_UNDEFINED
)
2047 for (is
= 0; is
< islots
; ++is
)
2049 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
2052 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2053 if (opc
== XTENSA_UNDEFINED
)
2056 opcname
= xtensa_opcode_name (isa
, opc
);
2058 if ((strcasecmp (opcname
, "ret.n") == 0)
2059 || (strcasecmp (opcname
, "ret") == 0))
2067 xtensa_insnbuf_free(isa
, slot
);
2068 xtensa_insnbuf_free(isa
, ins
);
2072 /* Call0 opcode class. Opcodes are preclassified according to what they
2073 mean for Call0 prologue analysis, and their number of significant operands.
2074 The purpose of this is to simplify prologue analysis by separating
2075 instruction decoding (libisa) from the semantics of prologue analysis. */
2079 c0opc_illegal
, /* Unknown to libisa (invalid) or 'ill' opcode. */
2080 c0opc_uninteresting
, /* Not interesting for Call0 prologue analysis. */
2081 c0opc_flow
, /* Flow control insn. */
2082 c0opc_entry
, /* ENTRY indicates non-Call0 prologue. */
2083 c0opc_break
, /* Debugger software breakpoints. */
2084 c0opc_add
, /* Adding two registers. */
2085 c0opc_addi
, /* Adding a register and an immediate. */
2086 c0opc_and
, /* Bitwise "and"-ing two registers. */
2087 c0opc_sub
, /* Subtracting a register from a register. */
2088 c0opc_mov
, /* Moving a register to a register. */
2089 c0opc_movi
, /* Moving an immediate to a register. */
2090 c0opc_l32r
, /* Loading a literal. */
2091 c0opc_s32i
, /* Storing word at fixed offset from a base register. */
2092 c0opc_rwxsr
, /* RSR, WRS, or XSR instructions. */
2093 c0opc_l32e
, /* L32E instruction. */
2094 c0opc_s32e
, /* S32E instruction. */
2095 c0opc_rfwo
, /* RFWO instruction. */
2096 c0opc_rfwu
, /* RFWU instruction. */
2097 c0opc_NrOf
/* Number of opcode classifications. */
2100 /* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */
2103 rwx_special_register (const char *opcname
)
2105 char ch
= *opcname
++;
2107 if ((ch
!= 'r') && (ch
!= 'w') && (ch
!= 'x'))
2109 if (*opcname
++ != 's')
2111 if (*opcname
++ != 'r')
2113 if (*opcname
++ != '.')
2119 /* Classify an opcode based on what it means for Call0 prologue analysis. */
2121 static xtensa_insn_kind
2122 call0_classify_opcode (xtensa_isa isa
, xtensa_opcode opc
)
2124 const char *opcname
;
2125 xtensa_insn_kind opclass
= c0opc_uninteresting
;
2127 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc
);
2129 /* Get opcode name and handle special classifications. */
2131 opcname
= xtensa_opcode_name (isa
, opc
);
2134 || strcasecmp (opcname
, "ill") == 0
2135 || strcasecmp (opcname
, "ill.n") == 0)
2136 opclass
= c0opc_illegal
;
2137 else if (strcasecmp (opcname
, "break") == 0
2138 || strcasecmp (opcname
, "break.n") == 0)
2139 opclass
= c0opc_break
;
2140 else if (strcasecmp (opcname
, "entry") == 0)
2141 opclass
= c0opc_entry
;
2142 else if (strcasecmp (opcname
, "rfwo") == 0)
2143 opclass
= c0opc_rfwo
;
2144 else if (strcasecmp (opcname
, "rfwu") == 0)
2145 opclass
= c0opc_rfwu
;
2146 else if (xtensa_opcode_is_branch (isa
, opc
) > 0
2147 || xtensa_opcode_is_jump (isa
, opc
) > 0
2148 || xtensa_opcode_is_loop (isa
, opc
) > 0
2149 || xtensa_opcode_is_call (isa
, opc
) > 0
2150 || strcasecmp (opcname
, "simcall") == 0
2151 || strcasecmp (opcname
, "syscall") == 0)
2152 opclass
= c0opc_flow
;
2154 /* Also, classify specific opcodes that need to be tracked. */
2155 else if (strcasecmp (opcname
, "add") == 0
2156 || strcasecmp (opcname
, "add.n") == 0)
2157 opclass
= c0opc_add
;
2158 else if (strcasecmp (opcname
, "and") == 0)
2159 opclass
= c0opc_and
;
2160 else if (strcasecmp (opcname
, "addi") == 0
2161 || strcasecmp (opcname
, "addi.n") == 0
2162 || strcasecmp (opcname
, "addmi") == 0)
2163 opclass
= c0opc_addi
;
2164 else if (strcasecmp (opcname
, "sub") == 0)
2165 opclass
= c0opc_sub
;
2166 else if (strcasecmp (opcname
, "mov.n") == 0
2167 || strcasecmp (opcname
, "or") == 0) /* Could be 'mov' asm macro. */
2168 opclass
= c0opc_mov
;
2169 else if (strcasecmp (opcname
, "movi") == 0
2170 || strcasecmp (opcname
, "movi.n") == 0)
2171 opclass
= c0opc_movi
;
2172 else if (strcasecmp (opcname
, "l32r") == 0)
2173 opclass
= c0opc_l32r
;
2174 else if (strcasecmp (opcname
, "s32i") == 0
2175 || strcasecmp (opcname
, "s32i.n") == 0)
2176 opclass
= c0opc_s32i
;
2177 else if (strcasecmp (opcname
, "l32e") == 0)
2178 opclass
= c0opc_l32e
;
2179 else if (strcasecmp (opcname
, "s32e") == 0)
2180 opclass
= c0opc_s32e
;
2181 else if (rwx_special_register (opcname
))
2182 opclass
= c0opc_rwxsr
;
2187 /* Tracks register movement/mutation for a given operation, which may
2188 be within a bundle. Updates the destination register tracking info
2189 accordingly. The pc is needed only for pc-relative load instructions
2190 (eg. l32r). The SP register number is needed to identify stores to
2191 the stack frame. Returns 0, if analysis was succesfull, non-zero
2195 call0_track_op (struct gdbarch
*gdbarch
, xtensa_c0reg_t dst
[], xtensa_c0reg_t src
[],
2196 xtensa_insn_kind opclass
, int nods
, unsigned odv
[],
2197 CORE_ADDR pc
, int spreg
, xtensa_frame_cache_t
*cache
)
2199 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2200 unsigned litbase
, litaddr
, litval
;
2205 /* 3 operands: dst, src, imm. */
2206 gdb_assert (nods
== 3);
2207 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2208 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ odv
[2];
2211 /* 3 operands: dst, src1, src2. */
2212 gdb_assert (nods
== 3);
2213 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2215 dst
[odv
[0]].fr_reg
= src
[odv
[2]].fr_reg
;
2216 dst
[odv
[0]].fr_ofs
= src
[odv
[2]].fr_ofs
+ src
[odv
[1]].fr_ofs
;
2218 else if (src
[odv
[2]].fr_reg
== C0_CONST
)
2220 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2221 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
+ src
[odv
[2]].fr_ofs
;
2223 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2226 /* 3 operands: dst, src1, src2. */
2227 gdb_assert (nods
== 3);
2228 if (cache
->c0
.c0_fpalign
== 0)
2230 /* Handle dynamic stack alignment. */
2231 if ((src
[odv
[0]].fr_reg
== spreg
) && (src
[odv
[1]].fr_reg
== spreg
))
2233 if (src
[odv
[2]].fr_reg
== C0_CONST
)
2234 cache
->c0
.c0_fpalign
= src
[odv
[2]].fr_ofs
;
2237 else if ((src
[odv
[0]].fr_reg
== spreg
)
2238 && (src
[odv
[2]].fr_reg
== spreg
))
2240 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2241 cache
->c0
.c0_fpalign
= src
[odv
[1]].fr_ofs
;
2244 /* else fall through. */
2246 if (src
[odv
[1]].fr_reg
== C0_CONST
)
2248 dst
[odv
[0]].fr_reg
= src
[odv
[2]].fr_reg
;
2249 dst
[odv
[0]].fr_ofs
= src
[odv
[2]].fr_ofs
& src
[odv
[1]].fr_ofs
;
2251 else if (src
[odv
[2]].fr_reg
== C0_CONST
)
2253 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2254 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
& src
[odv
[2]].fr_ofs
;
2256 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2259 /* 3 operands: dst, src1, src2. */
2260 gdb_assert (nods
== 3);
2261 if (src
[odv
[2]].fr_reg
== C0_CONST
)
2263 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2264 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
- src
[odv
[2]].fr_ofs
;
2266 else dst
[odv
[0]].fr_reg
= C0_INEXP
;
2269 /* 2 operands: dst, src [, src]. */
2270 gdb_assert (nods
== 2);
2271 /* First, check if it's a special case of saving unaligned SP
2272 to a spare register in case of dynamic stack adjustment.
2273 But, only do it one time. The second time could be initializing
2274 frame pointer. We don't want to overwrite the first one. */
2275 if ((odv
[1] == spreg
) && (cache
->c0
.c0_old_sp
== C0_INEXP
))
2276 cache
->c0
.c0_old_sp
= odv
[0];
2278 dst
[odv
[0]].fr_reg
= src
[odv
[1]].fr_reg
;
2279 dst
[odv
[0]].fr_ofs
= src
[odv
[1]].fr_ofs
;
2282 /* 2 operands: dst, imm. */
2283 gdb_assert (nods
== 2);
2284 dst
[odv
[0]].fr_reg
= C0_CONST
;
2285 dst
[odv
[0]].fr_ofs
= odv
[1];
2288 /* 2 operands: dst, literal offset. */
2289 gdb_assert (nods
== 2);
2290 /* litbase = xtensa_get_litbase (pc); can be also used. */
2291 litbase
= (gdbarch_tdep (gdbarch
)->litbase_regnum
== -1)
2292 ? 0 : xtensa_read_register
2293 (gdbarch_tdep (gdbarch
)->litbase_regnum
);
2294 litaddr
= litbase
& 1
2295 ? (litbase
& ~1) + (signed)odv
[1]
2296 : (pc
+ 3 + (signed)odv
[1]) & ~3;
2297 litval
= read_memory_integer (litaddr
, 4, byte_order
);
2298 dst
[odv
[0]].fr_reg
= C0_CONST
;
2299 dst
[odv
[0]].fr_ofs
= litval
;
2302 /* 3 operands: value, base, offset. */
2303 gdb_assert (nods
== 3 && spreg
>= 0 && spreg
< C0_NREGS
);
2304 /* First, check if it's a spill for saved unaligned SP,
2305 when dynamic stack adjustment was applied to this frame. */
2306 if ((cache
->c0
.c0_fpalign
!= 0) /* Dynamic stack adjustment. */
2307 && (odv
[1] == spreg
) /* SP usage indicates spill. */
2308 && (odv
[0] == cache
->c0
.c0_old_sp
)) /* Old SP register spilled. */
2309 cache
->c0
.c0_sp_ofs
= odv
[2];
2311 if (src
[odv
[1]].fr_reg
== spreg
/* Store to stack frame. */
2312 && (src
[odv
[1]].fr_ofs
& 3) == 0 /* Alignment preserved. */
2313 && src
[odv
[0]].fr_reg
>= 0 /* Value is from a register. */
2314 && src
[odv
[0]].fr_ofs
== 0 /* Value hasn't been modified. */
2315 && src
[src
[odv
[0]].fr_reg
].to_stk
== C0_NOSTK
) /* First time. */
2317 /* ISA encoding guarantees alignment. But, check it anyway. */
2318 gdb_assert ((odv
[2] & 3) == 0);
2319 dst
[src
[odv
[0]].fr_reg
].to_stk
= src
[odv
[1]].fr_ofs
+ odv
[2];
2322 /* If we end up inside Window Overflow / Underflow interrupt handler
2323 report an error because these handlers should have been handled
2324 already in a different way. */
2336 /* Analyze prologue of the function at start address to determine if it uses
2337 the Call0 ABI, and if so track register moves and linear modifications
2338 in the prologue up to the PC or just beyond the prologue, whichever is
2339 first. An 'entry' instruction indicates non-Call0 ABI and the end of the
2340 prologue. The prologue may overlap non-prologue instructions but is
2341 guaranteed to end by the first flow-control instruction (jump, branch,
2342 call or return). Since an optimized function may move information around
2343 and change the stack frame arbitrarily during the prologue, the information
2344 is guaranteed valid only at the point in the function indicated by the PC.
2345 May be used to skip the prologue or identify the ABI, w/o tracking.
2347 Returns: Address of first instruction after prologue, or PC (whichever
2348 is first), or 0, if decoding failed (in libisa).
2350 start Start address of function/prologue.
2351 pc Program counter to stop at. Use 0 to continue to end of prologue.
2352 If 0, avoids infinite run-on in corrupt code memory by bounding
2353 the scan to the end of the function if that can be determined.
2354 nregs Number of general registers to track.
2356 cache Xtensa frame cache.
2358 Note that these may produce useful results even if decoding fails
2359 because they begin with default assumptions that analysis may change. */
2362 call0_analyze_prologue (struct gdbarch
*gdbarch
,
2363 CORE_ADDR start
, CORE_ADDR pc
,
2364 int nregs
, xtensa_frame_cache_t
*cache
)
2366 CORE_ADDR ia
; /* Current insn address in prologue. */
2367 CORE_ADDR ba
= 0; /* Current address at base of insn buffer. */
2368 CORE_ADDR bt
; /* Current address at top+1 of insn buffer. */
2369 gdb_byte ibuf
[XTENSA_ISA_BSZ
];/* Instruction buffer for decoding prologue. */
2370 xtensa_isa isa
; /* libisa ISA handle. */
2371 xtensa_insnbuf ins
, slot
; /* libisa handle to decoded insn, slot. */
2372 xtensa_format ifmt
; /* libisa instruction format. */
2373 int ilen
, islots
, is
; /* Instruction length, nbr slots, current slot. */
2374 xtensa_opcode opc
; /* Opcode in current slot. */
2375 xtensa_insn_kind opclass
; /* Opcode class for Call0 prologue analysis. */
2376 int nods
; /* Opcode number of operands. */
2377 unsigned odv
[C0_MAXOPDS
]; /* Operand values in order provided by libisa. */
2378 xtensa_c0reg_t
*rtmp
; /* Register tracking info snapshot. */
2379 int j
; /* General loop counter. */
2380 int fail
= 0; /* Set non-zero and exit, if decoding fails. */
2381 CORE_ADDR body_pc
; /* The PC for the first non-prologue insn. */
2382 CORE_ADDR end_pc
; /* The PC for the lust function insn. */
2384 struct symtab_and_line prologue_sal
;
2386 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2387 (int)start
, (int)pc
);
2389 /* Try to limit the scan to the end of the function if a non-zero pc
2390 arg was not supplied to avoid probing beyond the end of valid memory.
2391 If memory is full of garbage that classifies as c0opc_uninteresting.
2392 If this fails (eg. if no symbols) pc ends up 0 as it was.
2393 Initialize the Call0 frame and register tracking info.
2394 Assume it's Call0 until an 'entry' instruction is encountered.
2395 Assume we may be in the prologue until we hit a flow control instr. */
2401 /* Find out, if we have an information about the prologue from DWARF. */
2402 prologue_sal
= find_pc_line (start
, 0);
2403 if (prologue_sal
.line
!= 0) /* Found debug info. */
2404 body_pc
= prologue_sal
.end
;
2406 /* If we are going to analyze the prologue in general without knowing about
2407 the current PC, make the best assumtion for the end of the prologue. */
2410 find_pc_partial_function (start
, 0, NULL
, &end_pc
);
2411 body_pc
= std::min (end_pc
, body_pc
);
2414 body_pc
= std::min (pc
, body_pc
);
2417 rtmp
= (xtensa_c0reg_t
*) alloca(nregs
* sizeof(xtensa_c0reg_t
));
2419 isa
= xtensa_default_isa
;
2420 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2421 ins
= xtensa_insnbuf_alloc (isa
);
2422 slot
= xtensa_insnbuf_alloc (isa
);
2424 for (ia
= start
, bt
= ia
; ia
< body_pc
; ia
+= ilen
)
2426 /* (Re)fill instruction buffer from memory if necessary, but do not
2427 read memory beyond PC to be sure we stay within text section
2428 (this protection only works if a non-zero pc is supplied). */
2430 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2433 bt
= (ba
+ XTENSA_ISA_BSZ
) < body_pc
? ba
+ XTENSA_ISA_BSZ
: body_pc
;
2434 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0 )
2435 error (_("Unable to read target memory ..."));
2438 /* Decode format information. */
2440 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2441 ifmt
= xtensa_format_decode (isa
, ins
);
2442 if (ifmt
== XTENSA_UNDEFINED
)
2447 ilen
= xtensa_format_length (isa
, ifmt
);
2448 if (ilen
== XTENSA_UNDEFINED
)
2453 islots
= xtensa_format_num_slots (isa
, ifmt
);
2454 if (islots
== XTENSA_UNDEFINED
)
2460 /* Analyze a bundle or a single instruction, using a snapshot of
2461 the register tracking info as input for the entire bundle so that
2462 register changes do not take effect within this bundle. */
2464 for (j
= 0; j
< nregs
; ++j
)
2465 rtmp
[j
] = cache
->c0
.c0_rt
[j
];
2467 for (is
= 0; is
< islots
; ++is
)
2469 /* Decode a slot and classify the opcode. */
2471 fail
= xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
);
2475 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2476 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2478 if (opc
== XTENSA_UNDEFINED
)
2479 opclass
= c0opc_illegal
;
2481 opclass
= call0_classify_opcode (isa
, opc
);
2483 /* Decide whether to track this opcode, ignore it, or bail out. */
2492 case c0opc_uninteresting
:
2495 case c0opc_flow
: /* Flow control instructions stop analysis. */
2496 case c0opc_rwxsr
: /* RSR, WSR, XSR instructions stop analysis. */
2501 ia
+= ilen
; /* Skip over 'entry' insn. */
2508 /* Only expected opcodes should get this far. */
2510 /* Extract and decode the operands. */
2511 nods
= xtensa_opcode_num_operands (isa
, opc
);
2512 if (nods
== XTENSA_UNDEFINED
)
2518 for (j
= 0; j
< nods
&& j
< C0_MAXOPDS
; ++j
)
2520 fail
= xtensa_operand_get_field (isa
, opc
, j
, ifmt
,
2525 fail
= xtensa_operand_decode (isa
, opc
, j
, &odv
[j
]);
2530 /* Check operands to verify use of 'mov' assembler macro. */
2531 if (opclass
== c0opc_mov
&& nods
== 3)
2533 if (odv
[2] == odv
[1])
2536 if ((odv
[0] == 1) && (odv
[1] != 1))
2537 /* OR A1, An, An , where n != 1.
2538 This means we are inside epilogue already. */
2543 opclass
= c0opc_uninteresting
;
2548 /* Track register movement and modification for this operation. */
2549 fail
= call0_track_op (gdbarch
, cache
->c0
.c0_rt
, rtmp
,
2550 opclass
, nods
, odv
, ia
, 1, cache
);
2556 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2557 (unsigned)ia
, fail
? "failed" : "succeeded");
2558 xtensa_insnbuf_free(isa
, slot
);
2559 xtensa_insnbuf_free(isa
, ins
);
2560 return fail
? XTENSA_ISA_BADPC
: ia
;
2563 /* Initialize frame cache for the current frame in CALL0 ABI. */
2566 call0_frame_cache (struct frame_info
*this_frame
,
2567 xtensa_frame_cache_t
*cache
, CORE_ADDR pc
)
2569 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2570 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2571 CORE_ADDR start_pc
; /* The beginning of the function. */
2572 CORE_ADDR body_pc
=UINT_MAX
; /* PC, where prologue analysis stopped. */
2573 CORE_ADDR sp
, fp
, ra
;
2574 int fp_regnum
= C0_SP
, c0_hasfp
= 0, c0_frmsz
= 0, prev_sp
= 0, to_stk
;
2576 sp
= get_frame_register_unsigned
2577 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ 1);
2578 fp
= sp
; /* Assume FP == SP until proven otherwise. */
2580 /* Find the beginning of the prologue of the function containing the PC
2581 and analyze it up to the PC or the end of the prologue. */
2583 if (find_pc_partial_function (pc
, NULL
, &start_pc
, NULL
))
2585 body_pc
= call0_analyze_prologue (gdbarch
, start_pc
, pc
, C0_NREGS
, cache
);
2587 if (body_pc
== XTENSA_ISA_BADPC
)
2591 goto finish_frame_analysis
;
2595 /* Get the frame information and FP (if used) at the current PC.
2596 If PC is in the prologue, the prologue analysis is more reliable
2597 than DWARF info. We don't not know for sure, if PC is in the prologue,
2598 but we do know no calls have yet taken place, so we can almost
2599 certainly rely on the prologue analysis. */
2603 /* Prologue analysis was successful up to the PC.
2604 It includes the cases when PC == START_PC. */
2605 c0_hasfp
= cache
->c0
.c0_rt
[C0_FP
].fr_reg
== C0_SP
;
2606 /* c0_hasfp == true means there is a frame pointer because
2607 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2608 was derived from SP. Otherwise, it would be C0_FP. */
2609 fp_regnum
= c0_hasfp
? C0_FP
: C0_SP
;
2610 c0_frmsz
= - cache
->c0
.c0_rt
[fp_regnum
].fr_ofs
;
2611 fp_regnum
+= gdbarch_tdep (gdbarch
)->a0_base
;
2613 else /* No data from the prologue analysis. */
2616 fp_regnum
= gdbarch_tdep (gdbarch
)->a0_base
+ C0_SP
;
2621 if (cache
->c0
.c0_fpalign
)
2623 /* This frame has a special prologue with a dynamic stack adjustment
2624 to force an alignment, which is bigger than standard 16 bytes. */
2626 CORE_ADDR unaligned_sp
;
2628 if (cache
->c0
.c0_old_sp
== C0_INEXP
)
2629 /* This can't be. Prologue code should be consistent.
2630 Unaligned stack pointer should be saved in a spare register. */
2634 goto finish_frame_analysis
;
2637 if (cache
->c0
.c0_sp_ofs
== C0_NOSTK
)
2638 /* Saved unaligned value of SP is kept in a register. */
2639 unaligned_sp
= get_frame_register_unsigned
2640 (this_frame
, gdbarch_tdep (gdbarch
)->a0_base
+ cache
->c0
.c0_old_sp
);
2642 /* Get the value from stack. */
2643 unaligned_sp
= (CORE_ADDR
)
2644 read_memory_integer (fp
+ cache
->c0
.c0_sp_ofs
, 4, byte_order
);
2646 prev_sp
= unaligned_sp
+ c0_frmsz
;
2649 prev_sp
= fp
+ c0_frmsz
;
2651 /* Frame size from debug info or prologue tracking does not account for
2652 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2655 fp
= get_frame_register_unsigned (this_frame
, fp_regnum
);
2657 /* Update the stack frame size. */
2658 c0_frmsz
+= fp
- sp
;
2661 /* Get the return address (RA) from the stack if saved,
2662 or try to get it from a register. */
2664 to_stk
= cache
->c0
.c0_rt
[C0_RA
].to_stk
;
2665 if (to_stk
!= C0_NOSTK
)
2667 read_memory_integer (sp
+ c0_frmsz
+ cache
->c0
.c0_rt
[C0_RA
].to_stk
,
2670 else if (cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_CONST
2671 && cache
->c0
.c0_rt
[C0_RA
].fr_ofs
== 0)
2673 /* Special case for terminating backtrace at a function that wants to
2674 be seen as the outermost one. Such a function will clear it's RA (A0)
2675 register to 0 in the prologue instead of saving its original value. */
2680 /* RA was copied to another register or (before any function call) may
2681 still be in the original RA register. This is not always reliable:
2682 even in a leaf function, register tracking stops after prologue, and
2683 even in prologue, non-prologue instructions (not tracked) may overwrite
2684 RA or any register it was copied to. If likely in prologue or before
2685 any call, use retracking info and hope for the best (compiler should
2686 have saved RA in stack if not in a leaf function). If not in prologue,
2692 && (i
== C0_RA
|| cache
->c0
.c0_rt
[i
].fr_reg
!= C0_RA
);
2694 if (i
>= C0_NREGS
&& cache
->c0
.c0_rt
[C0_RA
].fr_reg
== C0_RA
)
2698 ra
= get_frame_register_unsigned
2700 gdbarch_tdep (gdbarch
)->a0_base
+ cache
->c0
.c0_rt
[i
].fr_reg
);
2705 finish_frame_analysis
:
2706 cache
->pc
= start_pc
;
2708 /* RA == 0 marks the outermost frame. Do not go past it. */
2709 cache
->prev_sp
= (ra
!= 0) ? prev_sp
: 0;
2710 cache
->c0
.fp_regnum
= fp_regnum
;
2711 cache
->c0
.c0_frmsz
= c0_frmsz
;
2712 cache
->c0
.c0_hasfp
= c0_hasfp
;
2713 cache
->c0
.c0_fp
= fp
;
2716 static CORE_ADDR a0_saved
;
2717 static CORE_ADDR a7_saved
;
2718 static CORE_ADDR a11_saved
;
2719 static int a0_was_saved
;
2720 static int a7_was_saved
;
2721 static int a11_was_saved
;
2723 /* Simulate L32E instruction: AT <-- ref (AS + offset). */
2725 execute_l32e (struct gdbarch
*gdbarch
, int at
, int as
, int offset
, CORE_ADDR wb
)
2727 int atreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ at
, wb
);
2728 int asreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ as
, wb
);
2729 CORE_ADDR addr
= xtensa_read_register (asreg
) + offset
;
2730 unsigned int spilled_value
2731 = read_memory_unsigned_integer (addr
, 4, gdbarch_byte_order (gdbarch
));
2733 if ((at
== 0) && !a0_was_saved
)
2735 a0_saved
= xtensa_read_register (atreg
);
2738 else if ((at
== 7) && !a7_was_saved
)
2740 a7_saved
= xtensa_read_register (atreg
);
2743 else if ((at
== 11) && !a11_was_saved
)
2745 a11_saved
= xtensa_read_register (atreg
);
2749 xtensa_write_register (atreg
, spilled_value
);
2752 /* Simulate S32E instruction: AT --> ref (AS + offset). */
2754 execute_s32e (struct gdbarch
*gdbarch
, int at
, int as
, int offset
, CORE_ADDR wb
)
2756 int atreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ at
, wb
);
2757 int asreg
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
+ as
, wb
);
2758 CORE_ADDR addr
= xtensa_read_register (asreg
) + offset
;
2759 ULONGEST spilled_value
= xtensa_read_register (atreg
);
2761 write_memory_unsigned_integer (addr
, 4,
2762 gdbarch_byte_order (gdbarch
),
2766 #define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200
2772 xtNoExceptionHandler
2773 } xtensa_exception_handler_t
;
2775 /* Execute instruction stream from current PC until hitting RFWU or RFWO.
2776 Return type of Xtensa Window Interrupt Handler on success. */
2777 static xtensa_exception_handler_t
2778 execute_code (struct gdbarch
*gdbarch
, CORE_ADDR current_pc
, CORE_ADDR wb
)
2781 xtensa_insnbuf ins
, slot
;
2782 gdb_byte ibuf
[XTENSA_ISA_BSZ
];
2783 CORE_ADDR ia
, bt
, ba
;
2785 int ilen
, islots
, is
;
2788 void (*func
) (struct gdbarch
*, int, int, int, CORE_ADDR
);
2790 uint32_t at
, as
, offset
;
2792 /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */
2793 int WindowUnderflow12
= (current_pc
& 0x1ff) >= 0x140;
2795 isa
= xtensa_default_isa
;
2796 gdb_assert (XTENSA_ISA_BSZ
>= xtensa_isa_maxlength (isa
));
2797 ins
= xtensa_insnbuf_alloc (isa
);
2798 slot
= xtensa_insnbuf_alloc (isa
);
2807 while (insn_num
++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN
)
2809 if (ia
+ xtensa_isa_maxlength (isa
) > bt
)
2812 bt
= (ba
+ XTENSA_ISA_BSZ
);
2813 if (target_read_memory (ba
, ibuf
, bt
- ba
) != 0)
2814 return xtNoExceptionHandler
;
2816 xtensa_insnbuf_from_chars (isa
, ins
, &ibuf
[ia
-ba
], 0);
2817 ifmt
= xtensa_format_decode (isa
, ins
);
2818 if (ifmt
== XTENSA_UNDEFINED
)
2819 return xtNoExceptionHandler
;
2820 ilen
= xtensa_format_length (isa
, ifmt
);
2821 if (ilen
== XTENSA_UNDEFINED
)
2822 return xtNoExceptionHandler
;
2823 islots
= xtensa_format_num_slots (isa
, ifmt
);
2824 if (islots
== XTENSA_UNDEFINED
)
2825 return xtNoExceptionHandler
;
2826 for (is
= 0; is
< islots
; ++is
)
2828 if (xtensa_format_get_slot (isa
, ifmt
, is
, ins
, slot
))
2829 return xtNoExceptionHandler
;
2830 opc
= xtensa_opcode_decode (isa
, ifmt
, is
, slot
);
2831 if (opc
== XTENSA_UNDEFINED
)
2832 return xtNoExceptionHandler
;
2833 switch (call0_classify_opcode (isa
, opc
))
2839 /* We expect none of them here. */
2840 return xtNoExceptionHandler
;
2842 func
= execute_l32e
;
2845 func
= execute_s32e
;
2847 case c0opc_rfwo
: /* RFWO. */
2848 /* Here, we return from WindowOverflow handler and,
2849 if we stopped at the very beginning, which means
2850 A0 was saved, we have to restore it now. */
2853 int arreg
= arreg_number (gdbarch
,
2854 gdbarch_tdep (gdbarch
)->a0_base
,
2856 xtensa_write_register (arreg
, a0_saved
);
2858 return xtWindowOverflow
;
2859 case c0opc_rfwu
: /* RFWU. */
2860 /* Here, we return from WindowUnderflow handler.
2861 Let's see if either A7 or A11 has to be restored. */
2862 if (WindowUnderflow12
)
2866 int arreg
= arreg_number (gdbarch
,
2867 gdbarch_tdep (gdbarch
)->a0_base
+ 11,
2869 xtensa_write_register (arreg
, a11_saved
);
2872 else if (a7_was_saved
)
2874 int arreg
= arreg_number (gdbarch
,
2875 gdbarch_tdep (gdbarch
)->a0_base
+ 7,
2877 xtensa_write_register (arreg
, a7_saved
);
2879 return xtWindowUnderflow
;
2880 default: /* Simply skip this insns. */
2884 /* Decode arguments for L32E / S32E and simulate their execution. */
2885 if ( xtensa_opcode_num_operands (isa
, opc
) != 3 )
2886 return xtNoExceptionHandler
;
2887 if (xtensa_operand_get_field (isa
, opc
, 0, ifmt
, is
, slot
, &at
))
2888 return xtNoExceptionHandler
;
2889 if (xtensa_operand_decode (isa
, opc
, 0, &at
))
2890 return xtNoExceptionHandler
;
2891 if (xtensa_operand_get_field (isa
, opc
, 1, ifmt
, is
, slot
, &as
))
2892 return xtNoExceptionHandler
;
2893 if (xtensa_operand_decode (isa
, opc
, 1, &as
))
2894 return xtNoExceptionHandler
;
2895 if (xtensa_operand_get_field (isa
, opc
, 2, ifmt
, is
, slot
, &offset
))
2896 return xtNoExceptionHandler
;
2897 if (xtensa_operand_decode (isa
, opc
, 2, &offset
))
2898 return xtNoExceptionHandler
;
2900 (*func
) (gdbarch
, at
, as
, offset
, wb
);
2905 return xtNoExceptionHandler
;
2908 /* Handle Window Overflow / Underflow exception frames. */
2911 xtensa_window_interrupt_frame_cache (struct frame_info
*this_frame
,
2912 xtensa_frame_cache_t
*cache
,
2915 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2916 CORE_ADDR ps
, wb
, ws
, ra
;
2917 int epc1_regnum
, i
, regnum
;
2918 xtensa_exception_handler_t eh_type
;
2920 /* Read PS, WB, and WS from the hardware. Note that PS register
2921 must be present, if Windowed ABI is supported. */
2922 ps
= xtensa_read_register (gdbarch_ps_regnum (gdbarch
));
2923 wb
= xtensa_read_register (gdbarch_tdep (gdbarch
)->wb_regnum
);
2924 ws
= xtensa_read_register (gdbarch_tdep (gdbarch
)->ws_regnum
);
2926 /* Execute all the remaining instructions from Window Interrupt Handler
2927 by simulating them on the remote protocol level. On return, set the
2928 type of Xtensa Window Interrupt Handler, or report an error. */
2929 eh_type
= execute_code (gdbarch
, pc
, wb
);
2930 if (eh_type
== xtNoExceptionHandler
)
2932 Unable to decode Xtensa Window Interrupt Handler's code."));
2934 cache
->ps
= ps
^ PS_EXC
; /* Clear the exception bit in PS. */
2935 cache
->call0
= 0; /* It's Windowed ABI. */
2937 /* All registers for the cached frame will be alive. */
2938 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
2939 cache
->wd
.aregs
[i
] = -1;
2941 if (eh_type
== xtWindowOverflow
)
2942 cache
->wd
.ws
= ws
^ (1 << wb
);
2943 else /* eh_type == xtWindowUnderflow. */
2944 cache
->wd
.ws
= ws
| (1 << wb
);
2946 cache
->wd
.wb
= (ps
& 0xf00) >> 8; /* Set WB to OWB. */
2947 regnum
= arreg_number (gdbarch
, gdbarch_tdep (gdbarch
)->a0_base
,
2949 ra
= xtensa_read_register (regnum
);
2950 cache
->wd
.callsize
= WINSIZE (ra
);
2951 cache
->prev_sp
= xtensa_read_register (regnum
+ 1);
2952 /* Set regnum to a frame pointer of the frame being cached. */
2953 regnum
= xtensa_scan_prologue (gdbarch
, pc
);
2954 regnum
= arreg_number (gdbarch
,
2955 gdbarch_tdep (gdbarch
)->a0_base
+ regnum
,
2957 cache
->base
= get_frame_register_unsigned (this_frame
, regnum
);
2959 /* Read PC of interrupted function from EPC1 register. */
2960 epc1_regnum
= xtensa_find_register_by_name (gdbarch
,"epc1");
2961 if (epc1_regnum
< 0)
2962 error(_("Unable to read Xtensa register EPC1"));
2963 cache
->ra
= xtensa_read_register (epc1_regnum
);
2964 cache
->pc
= get_frame_func (this_frame
);
2968 /* Skip function prologue.
2970 Return the pc of the first instruction after prologue. GDB calls this to
2971 find the address of the first line of the function or (if there is no line
2972 number information) to skip the prologue for planting breakpoints on
2973 function entries. Use debug info (if present) or prologue analysis to skip
2974 the prologue to achieve reliable debugging behavior. For windowed ABI,
2975 only the 'entry' instruction is skipped. It is not strictly necessary to
2976 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2977 backtrace at any point in the prologue, however certain potential hazards
2978 are avoided and a more "normal" debugging experience is ensured by
2979 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2980 For example, if we don't skip the prologue:
2981 - Some args may not yet have been saved to the stack where the debug
2982 info expects to find them (true anyway when only 'entry' is skipped);
2983 - Software breakpoints ('break' instrs) may not have been unplanted
2984 when the prologue analysis is done on initializing the frame cache,
2985 and breaks in the prologue will throw off the analysis.
2987 If we have debug info ( line-number info, in particular ) we simply skip
2988 the code associated with the first function line effectively skipping
2989 the prologue code. It works even in cases like
2992 { int local_var = 1;
2996 because, for this source code, both Xtensa compilers will generate two
2997 separate entries ( with the same line number ) in dwarf line-number
2998 section to make sure there is a boundary between the prologue code and
2999 the rest of the function.
3001 If there is no debug info, we need to analyze the code. */
3003 /* #define DONT_SKIP_PROLOGUE */
3006 xtensa_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
3008 struct symtab_and_line prologue_sal
;
3011 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc
);
3013 #if DONT_SKIP_PROLOGUE
3017 /* Try to find first body line from debug info. */
3019 prologue_sal
= find_pc_line (start_pc
, 0);
3020 if (prologue_sal
.line
!= 0) /* Found debug info. */
3022 /* In Call0, it is possible to have a function with only one instruction
3023 ('ret') resulting from a one-line optimized function that does nothing.
3024 In that case, prologue_sal.end may actually point to the start of the
3025 next function in the text section, causing a breakpoint to be set at
3026 the wrong place. Check, if the end address is within a different
3027 function, and if so return the start PC. We know we have symbol
3032 if ((gdbarch_tdep (gdbarch
)->call_abi
== CallAbiCall0Only
)
3033 && call0_ret (start_pc
, prologue_sal
.end
))
3036 find_pc_partial_function (prologue_sal
.end
, NULL
, &end_func
, NULL
);
3037 if (end_func
!= start_pc
)
3040 return prologue_sal
.end
;
3043 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
3044 body_pc
= call0_analyze_prologue (gdbarch
, start_pc
, 0, 0,
3045 xtensa_alloc_frame_cache (0));
3046 return body_pc
!= 0 ? body_pc
: start_pc
;
3049 /* Verify the current configuration. */
3051 xtensa_verify_config (struct gdbarch
*gdbarch
)
3053 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3056 /* Verify that we got a reasonable number of AREGS. */
3057 if ((tdep
->num_aregs
& -tdep
->num_aregs
) != tdep
->num_aregs
)
3059 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
3062 /* Verify that certain registers exist. */
3064 if (tdep
->pc_regnum
== -1)
3065 log
.printf (_("\n\tpc_regnum: No PC register"));
3066 if (tdep
->isa_use_exceptions
&& tdep
->ps_regnum
== -1)
3067 log
.printf (_("\n\tps_regnum: No PS register"));
3069 if (tdep
->isa_use_windowed_registers
)
3071 if (tdep
->wb_regnum
== -1)
3072 log
.printf (_("\n\twb_regnum: No WB register"));
3073 if (tdep
->ws_regnum
== -1)
3074 log
.printf (_("\n\tws_regnum: No WS register"));
3075 if (tdep
->ar_base
== -1)
3076 log
.printf (_("\n\tar_base: No AR registers"));
3079 if (tdep
->a0_base
== -1)
3080 log
.printf (_("\n\ta0_base: No Ax registers"));
3083 internal_error (__FILE__
, __LINE__
,
3084 _("the following are invalid: %s"), log
.c_str ());
3088 /* Derive specific register numbers from the array of registers. */
3091 xtensa_derive_tdep (struct gdbarch_tdep
*tdep
)
3093 xtensa_register_t
* rmap
;
3094 int n
, max_size
= 4;
3097 tdep
->num_nopriv_regs
= 0;
3099 /* Special registers 0..255 (core). */
3100 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
3101 /* User registers 0..255. */
3102 #define XTENSA_DBREGN_UREG(n) (0x0300+(n))
3104 for (rmap
= tdep
->regmap
, n
= 0; rmap
->target_number
!= -1; n
++, rmap
++)
3106 if (rmap
->target_number
== 0x0020)
3107 tdep
->pc_regnum
= n
;
3108 else if (rmap
->target_number
== 0x0100)
3110 else if (rmap
->target_number
== 0x0000)
3112 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(72))
3113 tdep
->wb_regnum
= n
;
3114 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(73))
3115 tdep
->ws_regnum
= n
;
3116 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(233))
3117 tdep
->debugcause_regnum
= n
;
3118 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(232))
3119 tdep
->exccause_regnum
= n
;
3120 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(238))
3121 tdep
->excvaddr_regnum
= n
;
3122 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(0))
3123 tdep
->lbeg_regnum
= n
;
3124 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(1))
3125 tdep
->lend_regnum
= n
;
3126 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(2))
3127 tdep
->lcount_regnum
= n
;
3128 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(3))
3129 tdep
->sar_regnum
= n
;
3130 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(5))
3131 tdep
->litbase_regnum
= n
;
3132 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(230))
3133 tdep
->ps_regnum
= n
;
3134 else if (rmap
->target_number
== XTENSA_DBREGN_UREG(231))
3135 tdep
->threadptr_regnum
= n
;
3137 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(226))
3138 tdep
->interrupt_regnum
= n
;
3139 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(227))
3140 tdep
->interrupt2_regnum
= n
;
3141 else if (rmap
->target_number
== XTENSA_DBREGN_SREG(224))
3142 tdep
->cpenable_regnum
= n
;
3145 if (rmap
->byte_size
> max_size
)
3146 max_size
= rmap
->byte_size
;
3147 if (rmap
->mask
!= 0 && tdep
->num_regs
== 0)
3149 /* Find out out how to deal with priveleged registers.
3151 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
3152 && tdep->num_nopriv_regs == 0)
3153 tdep->num_nopriv_regs = n;
3155 if ((rmap
->flags
& XTENSA_REGISTER_FLAGS_PRIVILEGED
) != 0
3156 && tdep
->num_regs
== 0)
3160 /* Number of pseudo registers. */
3161 tdep
->num_pseudo_regs
= n
- tdep
->num_regs
;
3163 /* Empirically determined maximum sizes. */
3164 tdep
->max_register_raw_size
= max_size
;
3165 tdep
->max_register_virtual_size
= max_size
;
3168 /* Module "constructor" function. */
3170 extern struct gdbarch_tdep xtensa_tdep
;
3172 static struct gdbarch
*
3173 xtensa_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3175 struct gdbarch_tdep
*tdep
;
3176 struct gdbarch
*gdbarch
;
3178 DEBUGTRACE ("gdbarch_init()\n");
3180 if (!xtensa_default_isa
)
3181 xtensa_default_isa
= xtensa_isa_init (0, 0);
3183 /* We have to set the byte order before we call gdbarch_alloc. */
3184 info
.byte_order
= XCHAL_HAVE_BE
? BFD_ENDIAN_BIG
: BFD_ENDIAN_LITTLE
;
3186 tdep
= &xtensa_tdep
;
3187 gdbarch
= gdbarch_alloc (&info
, tdep
);
3188 xtensa_derive_tdep (tdep
);
3190 /* Verify our configuration. */
3191 xtensa_verify_config (gdbarch
);
3192 xtensa_session_once_reported
= 0;
3194 set_gdbarch_wchar_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
3195 set_gdbarch_wchar_signed (gdbarch
, 0);
3197 /* Pseudo-Register read/write. */
3198 set_gdbarch_pseudo_register_read (gdbarch
, xtensa_pseudo_register_read
);
3199 set_gdbarch_pseudo_register_write (gdbarch
, xtensa_pseudo_register_write
);
3201 /* Set target information. */
3202 set_gdbarch_num_regs (gdbarch
, tdep
->num_regs
);
3203 set_gdbarch_num_pseudo_regs (gdbarch
, tdep
->num_pseudo_regs
);
3204 set_gdbarch_sp_regnum (gdbarch
, tdep
->a0_base
+ 1);
3205 set_gdbarch_pc_regnum (gdbarch
, tdep
->pc_regnum
);
3206 set_gdbarch_ps_regnum (gdbarch
, tdep
->ps_regnum
);
3208 /* Renumber registers for known formats (stabs and dwarf2). */
3209 set_gdbarch_stab_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
3210 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
3212 /* We provide our own function to get register information. */
3213 set_gdbarch_register_name (gdbarch
, xtensa_register_name
);
3214 set_gdbarch_register_type (gdbarch
, xtensa_register_type
);
3216 /* To call functions from GDB using dummy frame. */
3217 set_gdbarch_push_dummy_call (gdbarch
, xtensa_push_dummy_call
);
3219 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
3221 set_gdbarch_return_value (gdbarch
, xtensa_return_value
);
3223 /* Advance PC across any prologue instructions to reach "real" code. */
3224 set_gdbarch_skip_prologue (gdbarch
, xtensa_skip_prologue
);
3226 /* Stack grows downward. */
3227 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3229 /* Set breakpoints. */
3230 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
3231 xtensa_breakpoint_kind_from_pc
);
3232 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
3233 xtensa_sw_breakpoint_from_kind
);
3235 /* After breakpoint instruction or illegal instruction, pc still
3236 points at break instruction, so don't decrement. */
3237 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
3239 /* We don't skip args. */
3240 set_gdbarch_frame_args_skip (gdbarch
, 0);
3242 set_gdbarch_unwind_pc (gdbarch
, xtensa_unwind_pc
);
3244 set_gdbarch_frame_align (gdbarch
, xtensa_frame_align
);
3246 set_gdbarch_dummy_id (gdbarch
, xtensa_dummy_id
);
3248 /* Frame handling. */
3249 frame_base_set_default (gdbarch
, &xtensa_frame_base
);
3250 frame_unwind_append_unwinder (gdbarch
, &xtensa_unwind
);
3251 dwarf2_append_unwinders (gdbarch
);
3253 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3255 xtensa_add_reggroups (gdbarch
);
3256 set_gdbarch_register_reggroup_p (gdbarch
, xtensa_register_reggroup_p
);
3258 set_gdbarch_iterate_over_regset_sections
3259 (gdbarch
, xtensa_iterate_over_regset_sections
);
3261 set_solib_svr4_fetch_link_map_offsets
3262 (gdbarch
, svr4_ilp32_fetch_link_map_offsets
);
3264 /* Hook in the ABI-specific overrides, if they have been registered. */
3265 gdbarch_init_osabi (info
, gdbarch
);
3271 xtensa_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3273 error (_("xtensa_dump_tdep(): not implemented"));
3277 _initialize_xtensa_tdep (void)
3279 gdbarch_register (bfd_arch_xtensa
, xtensa_gdbarch_init
, xtensa_dump_tdep
);
3280 xtensa_init_reggroups ();
3282 add_setshow_zuinteger_cmd ("xtensa",
3284 &xtensa_debug_level
,
3285 _("Set Xtensa debugging."),
3286 _("Show Xtensa debugging."), _("\
3287 When non-zero, Xtensa-specific debugging is enabled. \
3288 Can be 1, 2, 3, or 4 indicating the level of debugging."),
3291 &setdebuglist
, &showdebuglist
);