1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003, 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
32 #include "floatformat.h"
34 #include "reggroups.h"
37 #include "dummy-frame.h"
38 #include "elf/dwarf2.h"
39 #include "dwarf2-frame.h"
40 #include "dwarf2loc.h"
42 #include "frame-base.h"
43 #include "frame-unwind.h"
45 #include "arch-utils.h"
52 #include "gdb_assert.h"
54 #include "xtensa-tdep.h"
57 static int xtensa_debug_level
= 0;
59 #define DEBUGWARN(args...) \
60 if (xtensa_debug_level > 0) \
61 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
63 #define DEBUGINFO(args...) \
64 if (xtensa_debug_level > 1) \
65 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
67 #define DEBUGTRACE(args...) \
68 if (xtensa_debug_level > 2) \
69 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
71 #define DEBUGVERB(args...) \
72 if (xtensa_debug_level > 3) \
73 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
76 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
78 #define SP_ALIGNMENT 16
81 /* We use a6 through a11 for passing arguments to a function called by GDB. */
83 #define ARGS_FIRST_REG A6_REGNUM
84 #define ARGS_NUM_REGS 6
85 #define REGISTER_SIZE 4
88 /* Extract the call size from the return address or ps register. */
90 #define PS_CALLINC_SHIFT 16
91 #define PS_CALLINC_MASK 0x00030000
92 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
93 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
96 /* Convert a live Ax register number to the corresponding Areg number. */
98 #define AREG_NUMBER(r, wb) \
99 ((((r) - A0_REGNUM + (((wb) & WB_MASK)<<WB_SHIFT)) & AREGS_MASK) + AR_BASE)
102 /* Define prototypes. */
104 extern struct gdbarch_tdep
*xtensa_config_tdep (struct gdbarch_info
*);
105 extern int xtensa_config_byte_order (struct gdbarch_info
*);
108 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
109 indicates that the instruction is an ENTRY instruction. */
111 #define XTENSA_IS_ENTRY(op1) \
112 ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) ? ((op1) == 0x6c) : ((op1) == 0x36))
114 #define XTENSA_ENTRY_LENGTH 3
117 /* windowing_enabled() returns true, if windowing is enabled.
118 WOE must be set to 1; EXCM to 0.
119 Note: We assume that EXCM is always 0 for XEA1. */
122 windowing_enabled (CORE_ADDR ps
)
124 return ((ps
& (1 << 4)) == 0 && (ps
& (1 << 18)) != 0);
127 /* Return the window size of the previous call to the function from which we
130 This function is used to extract the return value after a called function
131 has returned to the callee. On Xtensa, the register that holds the return
132 value (from the perspective of the caller) depends on what call
133 instruction was used. For now, we are assuming that the call instruction
134 precedes the current address, so we simply analyze the call instruction.
135 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
136 method to call the inferior function. */
139 extract_call_winsize (CORE_ADDR pc
)
141 int winsize
= 4; /* Default: No call, e.g. dummy frame. */
145 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc
);
147 /* Read the previous instruction (should be a call[x]{4|8|12}. */
148 read_memory (pc
-3, buf
, 3);
149 insn
= extract_unsigned_integer (buf
, 3);
151 /* Decode call instruction:
153 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
154 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
156 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
157 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
160 (Return the default value (4) if we can't find a valid call insn. */
162 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
164 if (((insn
& 0xf) == 0x5) || ((insn
& 0xcf) == 0xc0))
165 winsize
= (insn
& 0x30) >> 2; /* 0, 4, 8, 12 */
169 if (((insn
>> 20) == 0x5) || (((insn
>> 16) & 0xf3) == 0x03))
170 winsize
= (insn
>> 16) & 0xc; /* 0, 4, 8, 12 */
176 /* REGISTER INFORMATION */
178 /* Returns the name of a register. */
181 xtensa_register_name (int regnum
)
183 /* Return the name stored in the register map. */
184 if (regnum
>= 0 && regnum
< gdbarch_num_regs (current_gdbarch
)
185 + gdbarch_num_pseudo_regs (current_gdbarch
))
186 return REGMAP
[regnum
].name
;
188 /* Invalid register number. */
189 internal_error (__FILE__
, __LINE__
, _("invalid register %d"), regnum
);
194 /* Return the type of a register. Create a new type, if necessary. */
196 static struct ctype_cache
198 struct ctype_cache
*next
;
200 struct type
*virtual_type
;
201 } *type_entries
= NULL
;
204 xtensa_register_type (struct gdbarch
*gdbarch
, int regnum
)
206 /* Return signed integer for ARx and Ax registers. */
207 if ((regnum
>= AR_BASE
&& regnum
< AR_BASE
+ NUM_AREGS
)
208 || (regnum
>= A0_BASE
&& regnum
< A0_BASE
+ 16))
209 return builtin_type_int
;
211 if (regnum
== PC_REGNUM
|| regnum
== A1_REGNUM
)
212 return lookup_pointer_type (builtin_type_void
);
214 /* Return the stored type for all other registers. */
215 else if (regnum
>= 0 && regnum
< gdbarch_num_regs (current_gdbarch
)
216 + gdbarch_num_pseudo_regs (current_gdbarch
))
218 xtensa_register_t
* reg
= ®MAP
[regnum
];
220 /* Set ctype for this register (only the first time we ask for it). */
224 struct ctype_cache
*tp
;
225 int size
= reg
->byte_size
;
227 /* We always use the memory representation, even if the register
232 reg
->ctype
= builtin_type_uint8
;
236 reg
->ctype
= builtin_type_uint16
;
240 reg
->ctype
= builtin_type_uint32
;
244 reg
->ctype
= builtin_type_uint64
;
248 reg
->ctype
= builtin_type_uint128
;
252 for (tp
= type_entries
; tp
!= NULL
; tp
= tp
->next
)
253 if (tp
->size
== size
)
258 char *name
= xmalloc (16);
259 tp
= xmalloc (sizeof (struct ctype_cache
));
260 tp
->next
= type_entries
;
264 sprintf (name
, "int%d", size
* 8);
265 tp
->virtual_type
= init_type (TYPE_CODE_INT
, size
,
266 TYPE_FLAG_UNSIGNED
, name
,
270 reg
->ctype
= tp
->virtual_type
;
276 /* Invalid register number. */
277 internal_error (__FILE__
, __LINE__
, _("invalid register number %d"), regnum
);
282 /* Returns the 'local' register number for stubs, dwarf2, etc.
283 The debugging information enumerates registers starting from 0 for A0
284 to n for An. So, we only have to add the base number for A0. */
287 xtensa_reg_to_regnum (int regnum
)
291 if (regnum
>= 0 && regnum
< 16)
292 return A0_BASE
+ regnum
;
295 i
< gdbarch_num_regs (current_gdbarch
)
296 + gdbarch_num_pseudo_regs (current_gdbarch
);
298 if (regnum
== REGMAP
[i
].target_number
)
301 /* Invalid register number. */
302 internal_error (__FILE__
, __LINE__
,
303 _("invalid dwarf/stabs register number %d"), regnum
);
308 /* Handle the special case of masked registers. */
310 /* Write the bits of a masked register to the various registers that
311 are combined into this register. Only the masked areas of these
312 registers are modified; the other fields are untouched.
313 (Note: The size of masked registers is always less or equal 32 bits.) */
316 xtensa_register_write_masked (xtensa_register_t
*reg
, unsigned char *buffer
)
318 unsigned int value
[(MAX_REGISTER_SIZE
+ 3) / 4];
320 const xtensa_mask_t
*mask
= reg
->mask
;
322 int shift
= 0; /* Shift for next mask (mod 32). */
323 int start
, size
; /* Start bit and size of current mask. */
325 unsigned int *ptr
= value
;
326 unsigned int regval
, m
, mem
= 0;
328 int bytesize
= reg
->byte_size
;
329 int bitsize
= bytesize
* 8;
332 DEBUGTRACE ("xtensa_register_write_masked ()\n");
334 /* Copy the masked register to host byte-order. */
335 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
336 for (i
= 0; i
< bytesize
; i
++)
339 mem
|= (buffer
[bytesize
- i
- 1] << 24);
344 for (i
= 0; i
< bytesize
; i
++)
347 mem
|= (buffer
[i
] << 24);
352 /* We might have to shift the final value:
353 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
354 bytesize & 3 == x -> shift (4-x) * 8. */
356 *ptr
= mem
>> (((0 - bytesize
) & 3) * 8);
360 /* Write the bits to the masked areas of the other registers. */
361 for (i
= 0; i
< mask
->count
; i
++)
363 start
= mask
->mask
[i
].bit_start
;
364 size
= mask
->mask
[i
].bit_size
;
365 regval
= mem
>> shift
;
367 if ((shift
+= size
) > bitsize
)
368 error (_("size of all masks is larger than the register"));
377 regval
|= mem
<< (size
- shift
);
380 /* Make sure we have a valid register. */
381 r
= mask
->mask
[i
].reg_num
;
382 if (r
>= 0 && size
> 0)
384 /* Don't overwrite the unmasked areas. */
385 m
= 0xffffffff >> (32 - size
) << start
;
387 regval
= (regval
& m
) | (read_register (r
) & ~m
);
388 write_register (r
, regval
);
394 /* Read the masked areas of the registers and assemble it into a single
398 xtensa_register_read_masked (xtensa_register_t
*reg
, unsigned char *buffer
)
400 unsigned int value
[(MAX_REGISTER_SIZE
+ 3) / 4];
402 const xtensa_mask_t
*mask
= reg
->mask
;
407 unsigned int *ptr
= value
;
408 unsigned int regval
, mem
= 0;
410 int bytesize
= reg
->byte_size
;
411 int bitsize
= bytesize
* 8;
414 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
415 reg
->name
== 0 ? "" : reg
->name
);
417 /* Assemble the register from the masked areas of other registers. */
418 for (i
= 0; i
< mask
->count
; i
++)
420 int r
= mask
->mask
[i
].reg_num
;
421 regval
= (r
>= 0) ? read_register (r
) : 0;
422 start
= mask
->mask
[i
].bit_start
;
423 size
= mask
->mask
[i
].bit_size
;
428 regval
&= (0xffffffff >> (32 - size
));
430 mem
|= regval
<< shift
;
432 if ((shift
+= size
) > bitsize
)
433 error (_("size of all masks is larger than the register"));
444 mem
= regval
>> (size
- shift
);
451 /* Copy value to target byte order. */
455 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
456 for (i
= 0; i
< bytesize
; i
++)
460 buffer
[bytesize
- i
- 1] = mem
& 0xff;
464 for (i
= 0; i
< bytesize
; i
++)
468 buffer
[i
] = mem
& 0xff;
474 /* Read pseudo registers. */
477 xtensa_pseudo_register_read (struct gdbarch
*gdbarch
,
478 struct regcache
*regcache
,
482 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
483 regnum
, xtensa_register_name (regnum
));
485 /* Check if it is FP (renumber it in this case -> A0...A15). */
486 if (regnum
== FP_ALIAS
)
487 error (_("trying to read FP"));
489 /* Read aliases a0..a15. */
490 if (regnum
>= A0_REGNUM
&& regnum
<= A15_REGNUM
)
492 gdb_byte
*buf
= (gdb_byte
*) alloca (MAX_REGISTER_SIZE
);
494 regcache_raw_read (regcache
, WB_REGNUM
, buf
);
495 regnum
= AREG_NUMBER (regnum
, extract_unsigned_integer (buf
, 4));
498 /* We can always read 'regular' registers. */
499 if (regnum
>= 0 && regnum
< gdbarch_num_regs (current_gdbarch
))
500 regcache_raw_read (regcache
, regnum
, buffer
);
502 /* Pseudo registers. */
504 && regnum
< gdbarch_num_regs (current_gdbarch
)
505 + gdbarch_num_pseudo_regs (current_gdbarch
))
507 xtensa_register_t
*reg
= ®MAP
[regnum
];
508 xtensa_register_type_t type
= reg
->type
;
509 int flags
= XTENSA_TARGET_FLAGS
;
511 /* Can we read Unknown or Unmapped registers? */
512 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
514 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
516 warning (_("cannot read register %s"),
517 xtensa_register_name (regnum
));
522 /* Some targets cannot read TIE register files. */
523 else if (type
== xtRegisterTypeTieRegfile
)
525 /* Use 'fetch' to get register? */
526 if (flags
& xtTargetFlagsUseFetchStore
)
528 warning (_("cannot read register"));
532 /* On some targets (esp. simulators), we can always read the reg. */
533 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
535 warning (_("cannot read register"));
540 /* We can always read mapped registers. */
541 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
543 xtensa_register_read_masked (reg
, (unsigned char *) buffer
);
547 /* Assume that we can read the register. */
548 regcache_raw_read (regcache
, regnum
, buffer
);
552 internal_error (__FILE__
, __LINE__
,
553 _("invalid register number %d"), regnum
);
557 /* Write pseudo registers. */
560 xtensa_pseudo_register_write (struct gdbarch
*gdbarch
,
561 struct regcache
*regcache
,
563 const gdb_byte
*buffer
)
565 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
566 regnum
, xtensa_register_name (regnum
));
568 /* Check if this is FP. */
569 if (regnum
== FP_ALIAS
)
570 error (_("trying to write FP"));
572 /* Renumber register, if aliase a0..a15. */
573 if (regnum
>= A0_REGNUM
&& regnum
<= A15_REGNUM
)
575 gdb_byte
*buf
= (gdb_byte
*) alloca (MAX_REGISTER_SIZE
);
578 regcache_raw_read (regcache
, WB_REGNUM
, buf
);
579 regnum
= AREG_NUMBER (regnum
, extract_unsigned_integer (buf
, 4));
582 /* We can always write 'core' registers.
583 Note: We might have converted Ax->ARy. */
584 if (regnum
>= 0 && regnum
< gdbarch_num_regs (current_gdbarch
))
585 regcache_raw_write (regcache
, regnum
, buffer
);
587 /* Pseudo registers. */
589 && regnum
< gdbarch_num_regs (current_gdbarch
)
590 + gdbarch_num_pseudo_regs (current_gdbarch
))
592 xtensa_register_t
*reg
= ®MAP
[regnum
];
593 xtensa_register_type_t type
= reg
->type
;
594 int flags
= XTENSA_TARGET_FLAGS
;
596 /* On most targets, we can't write registers of type "Unknown"
598 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
600 if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
602 warning (_("cannot write register %s"),
603 xtensa_register_name (regnum
));
608 /* Some targets cannot read TIE register files. */
609 else if (type
== xtRegisterTypeTieRegfile
)
611 /* Use 'store' to get register? */
612 if (flags
& xtTargetFlagsUseFetchStore
)
614 warning (_("cannot write register"));
618 /* On some targets (esp. simulators), we can always write
621 else if ((flags
& xtTargetFlagsNonVisibleRegs
) == 0)
623 warning (_("cannot write register"));
628 /* We can always write mapped registers. */
629 else if (type
== xtRegisterTypeMapped
|| type
== xtRegisterTypeTieState
)
631 xtensa_register_write_masked (reg
, (unsigned char *) buffer
);
635 /* Assume that we can write the register. */
636 regcache_raw_write (regcache
, regnum
, buffer
);
640 internal_error (__FILE__
, __LINE__
,
641 _("invalid register number %d"), regnum
);
645 static struct reggroup
*xtensa_ar_reggroup
;
646 static struct reggroup
*xtensa_user_reggroup
;
647 static struct reggroup
*xtensa_vectra_reggroup
;
650 xtensa_init_reggroups (void)
652 xtensa_ar_reggroup
= reggroup_new ("ar", USER_REGGROUP
);
653 xtensa_user_reggroup
= reggroup_new ("user", USER_REGGROUP
);
654 xtensa_vectra_reggroup
= reggroup_new ("vectra", USER_REGGROUP
);
659 xtensa_add_reggroups (struct gdbarch
*gdbarch
)
661 reggroup_add (gdbarch
, all_reggroup
);
662 reggroup_add (gdbarch
, save_reggroup
);
663 reggroup_add (gdbarch
, restore_reggroup
);
664 reggroup_add (gdbarch
, system_reggroup
);
665 reggroup_add (gdbarch
, vector_reggroup
); /* vectra */
666 reggroup_add (gdbarch
, general_reggroup
); /* core */
667 reggroup_add (gdbarch
, float_reggroup
); /* float */
669 reggroup_add (gdbarch
, xtensa_ar_reggroup
); /* ar */
670 reggroup_add (gdbarch
, xtensa_user_reggroup
); /* user */
671 reggroup_add (gdbarch
, xtensa_vectra_reggroup
); /* vectra */
675 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
676 | XTENSA_REGISTER_FLAGS_WRITABLE \
677 | XTENSA_REGISTER_FLAGS_VOLATILE)
679 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
680 | XTENSA_REGISTER_FLAGS_WRITABLE)
683 xtensa_register_reggroup_p (struct gdbarch
*gdbarch
,
685 struct reggroup
*group
)
687 xtensa_register_t
* reg
= ®MAP
[regnum
];
688 xtensa_register_type_t type
= reg
->type
;
689 xtensa_register_group_t rg
= reg
->group
;
691 /* First, skip registers that are not visible to this target
692 (unknown and unmapped registers when not using ISS). */
694 if (type
== xtRegisterTypeUnmapped
|| type
== xtRegisterTypeUnknown
)
696 if (group
== all_reggroup
)
698 if (group
== xtensa_ar_reggroup
)
699 return rg
& xtRegisterGroupAddrReg
;
700 if (group
== xtensa_user_reggroup
)
701 return rg
& xtRegisterGroupUser
;
702 if (group
== float_reggroup
)
703 return rg
& xtRegisterGroupFloat
;
704 if (group
== general_reggroup
)
705 return rg
& xtRegisterGroupGeneral
;
706 if (group
== float_reggroup
)
707 return rg
& xtRegisterGroupFloat
;
708 if (group
== system_reggroup
)
709 return rg
& xtRegisterGroupState
;
710 if (group
== vector_reggroup
|| group
== xtensa_vectra_reggroup
)
711 return rg
& xtRegisterGroupVectra
;
712 if (group
== save_reggroup
|| group
== restore_reggroup
)
713 return (regnum
< gdbarch_num_regs (current_gdbarch
)
714 && (reg
->flags
& SAVE_REST_FLAGS
) == SAVE_REST_VALID
);
720 /* CORE FILE SUPPORT */
722 /* Supply register REGNUM from the buffer specified by GREGS and LEN
723 in the general-purpose register set REGSET to register cache
724 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
727 xtensa_supply_gregset (const struct regset
*regset
,
733 const xtensa_elf_gregset_t
*regs
= gregs
;
736 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...) \n", regnum
);
738 if (regnum
== PC_REGNUM
|| regnum
== -1)
739 regcache_raw_supply (rc
, PC_REGNUM
, (char *) ®s
->pc
);
740 if (regnum
== PS_REGNUM
|| regnum
== -1)
741 regcache_raw_supply (rc
, PS_REGNUM
, (char *) ®s
->ps
);
742 if (regnum
== WB_REGNUM
|| regnum
== -1)
743 regcache_raw_supply (rc
, WB_REGNUM
, (char *) ®s
->windowbase
);
744 if (regnum
== WS_REGNUM
|| regnum
== -1)
745 regcache_raw_supply (rc
, WS_REGNUM
, (char *) ®s
->windowstart
);
746 if (regnum
== LBEG_REGNUM
|| regnum
== -1)
747 regcache_raw_supply (rc
, LBEG_REGNUM
, (char *) ®s
->lbeg
);
748 if (regnum
== LEND_REGNUM
|| regnum
== -1)
749 regcache_raw_supply (rc
, LEND_REGNUM
, (char *) ®s
->lend
);
750 if (regnum
== LCOUNT_REGNUM
|| regnum
== -1)
751 regcache_raw_supply (rc
, LCOUNT_REGNUM
, (char *) ®s
->lcount
);
752 if (regnum
== SAR_REGNUM
|| regnum
== -1)
753 regcache_raw_supply (rc
, SAR_REGNUM
, (char *) ®s
->sar
);
754 if (regnum
== EXCCAUSE_REGNUM
|| regnum
== -1)
755 regcache_raw_supply (rc
, EXCCAUSE_REGNUM
, (char *) ®s
->exccause
);
756 if (regnum
== EXCVADDR_REGNUM
|| regnum
== -1)
757 regcache_raw_supply (rc
, EXCVADDR_REGNUM
, (char *) ®s
->excvaddr
);
758 if (regnum
>= AR_BASE
&& regnum
< AR_BASE
+ NUM_AREGS
)
759 regcache_raw_supply (rc
, regnum
, (char *) ®s
->ar
[regnum
- AR_BASE
]);
760 else if (regnum
== -1)
762 for (i
= 0; i
< NUM_AREGS
; ++i
)
763 regcache_raw_supply (rc
, AR_BASE
+ i
, (char *) ®s
->ar
[i
]);
768 /* Xtensa register set. */
774 xtensa_supply_gregset
778 /* Return the appropriate register set for the core section identified
779 by SECT_NAME and SECT_SIZE. */
781 static const struct regset
*
782 xtensa_regset_from_core_section (struct gdbarch
*core_arch
,
783 const char *sect_name
,
786 DEBUGTRACE ("xtensa_regset_from_core_section "
787 "(..., sect_name==\"%s\", sect_size==%x) \n",
788 sect_name
, (int) sect_size
);
790 if (strcmp (sect_name
, ".reg") == 0
791 && sect_size
>= sizeof(xtensa_elf_gregset_t
))
792 return &xtensa_gregset
;
800 /* We currently don't support the call0-abi, so we have at max. 12 registers
801 saved on the stack. */
803 #define XTENSA_NUM_SAVED_AREGS 12
805 typedef struct xtensa_frame_cache
809 CORE_ADDR ra
; /* The raw return address; use to compute call_inc. */
811 int wb
; /* Base for this frame; -1 if not in regfile. */
812 int callsize
; /* Call size to next frame. */
814 CORE_ADDR aregs
[XTENSA_NUM_SAVED_AREGS
];
816 } xtensa_frame_cache_t
;
819 static struct xtensa_frame_cache
*
820 xtensa_alloc_frame_cache (void)
822 xtensa_frame_cache_t
*cache
;
825 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
827 cache
= FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t
);
834 cache
->callsize
= -1;
837 for (i
= 0; i
< XTENSA_NUM_SAVED_AREGS
; i
++)
838 cache
->aregs
[i
] = -1;
845 xtensa_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR address
)
847 return address
& ~15;
852 xtensa_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
856 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %p)\n", next_frame
);
858 frame_unwind_register (next_frame
, PC_REGNUM
, buf
);
860 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int)
861 extract_typed_address (buf
, builtin_type_void_func_ptr
));
863 return extract_typed_address (buf
, builtin_type_void_func_ptr
);
867 static struct frame_id
868 xtensa_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
873 /* next_frame->prev is a dummy frame. Return a frame ID of that frame. */
875 DEBUGTRACE ("xtensa_unwind_dummy_id ()\n");
877 pc
= frame_pc_unwind (next_frame
);
878 frame_unwind_register (next_frame
, A1_REGNUM
, buf
);
879 fp
= extract_unsigned_integer (buf
, 4);
881 /* Make dummy frame ID unique by adding a constant. */
882 return frame_id_build (fp
+SP_ALIGNMENT
, pc
);
886 static struct xtensa_frame_cache
*
887 xtensa_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
889 xtensa_frame_cache_t
*cache
;
891 CORE_ADDR ra
, wb
, ws
, pc
, sp
, ps
;
894 DEBUGTRACE ("xtensa_frame_cache (next_frame %p, *this_cache %p)\n",
895 next_frame
, this_cache
? *this_cache
: (void*)0xdeadbeef);
897 /* Already cached? */
901 /* Get pristine xtensa-frame. */
902 cache
= xtensa_alloc_frame_cache ();
905 /* Get windowbase, windowstart, ps, and pc. */
906 wb
= frame_unwind_register_unsigned (next_frame
, WB_REGNUM
);
907 ws
= frame_unwind_register_unsigned (next_frame
, WS_REGNUM
);
908 ps
= frame_unwind_register_unsigned (next_frame
, PS_REGNUM
);
909 pc
= frame_unwind_register_unsigned (next_frame
, PC_REGNUM
);
911 op1
= read_memory_integer (pc
, 1);
912 if (XTENSA_IS_ENTRY (op1
) || !windowing_enabled (read_register (PS_REGNUM
)))
914 int callinc
= CALLINC (frame_unwind_register_unsigned (next_frame
,
916 ra
= frame_unwind_register_unsigned (next_frame
,
917 A0_REGNUM
+ callinc
* 4);
919 DEBUGINFO("[xtensa_frame_cache] 'entry' at 0x%08x\n (callinc = %d)",
922 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
926 cache
->prev_sp
= read_register (A1_REGNUM
);
930 ra
= frame_unwind_register_unsigned (next_frame
, A0_REGNUM
);
931 cache
->callsize
= WINSIZE (ra
);
932 cache
->wb
= (wb
- (cache
->callsize
/ 4)) & ((NUM_AREGS
/ 4) - 1);
933 cache
->ws
= ws
& ~(1 << wb
);
936 cache
->pc
= ((frame_func_unwind (next_frame
, NORMAL_FRAME
) & 0xc0000000)
937 | (ra
& 0x3fffffff));
938 cache
->ps
= (ps
& ~PS_CALLINC_MASK
) | ((WINSIZE(ra
)/4) << PS_CALLINC_SHIFT
);
941 /* Note: We could also calculate the location on stack when we actually
942 access the register. However, this approach, saving the location
943 in the cache frame, is probably easier to support the call0 ABI. */
950 sp
= frame_unwind_register_unsigned (next_frame
, A1_REGNUM
) - 16;
952 for (i
= 0; i
< 4; i
++, sp
+= 4)
954 cache
->aregs
[i
] = sp
;
957 if (cache
->callsize
> 4)
959 /* Set A4...A7/A11. */
961 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4);
962 sp
= (CORE_ADDR
) read_memory_integer (sp
- 12, 4);
963 sp
-= cache
->callsize
* 4;
965 for ( /* i=4 */ ; i
< cache
->callsize
; i
++, sp
+= 4)
967 cache
->aregs
[i
] = sp
;
972 if (cache
->prev_sp
== 0)
976 /* Register window overflow already happened.
977 We can read caller's frame SP from the proper spill loction. */
979 read_memory_integer (cache
->aregs
[1],
980 register_size (current_gdbarch
,
985 /* Read caller's frame SP directly from the previous window. */
987 int regnum
= AREG_NUMBER (A1_REGNUM
, cache
->wb
);
989 cache
->prev_sp
= read_register (regnum
);
993 cache
->base
= frame_unwind_register_unsigned (next_frame
,A1_REGNUM
);
995 DEBUGINFO ("[xtensa_frame_cache] base 0x%08x, wb %d, "
996 "ws 0x%08x, callsize %d, pc 0x%08x, ps 0x%08x, prev_sp 0x%08x\n",
997 (unsigned int) cache
->base
, (unsigned int) cache
->wb
,
998 cache
->ws
, cache
->callsize
, (unsigned int) cache
->pc
,
999 (unsigned int) cache
->ps
, (unsigned int) cache
->prev_sp
);
1006 xtensa_frame_this_id (struct frame_info
*next_frame
,
1008 struct frame_id
*this_id
)
1010 struct xtensa_frame_cache
*cache
=
1011 xtensa_frame_cache (next_frame
, this_cache
);
1013 DEBUGTRACE ("xtensa_frame_this_id (next %p, *this %p)\n",
1014 next_frame
, *this_cache
);
1016 if (cache
->prev_sp
== 0)
1019 (*this_id
) = frame_id_build (cache
->prev_sp
, cache
->pc
);
1024 xtensa_frame_prev_register (struct frame_info
*next_frame
,
1028 enum lval_type
*lvalp
,
1033 struct xtensa_frame_cache
*cache
=
1034 xtensa_frame_cache (next_frame
, this_cache
);
1035 CORE_ADDR saved_reg
= 0;
1038 DEBUGTRACE ("xtensa_frame_prev_register (next %p, "
1039 "*this %p, regnum %d (%s), ...)\n",
1041 *this_cache
? *this_cache
: 0, regnum
,
1042 xtensa_register_name (regnum
));
1044 if (regnum
== WS_REGNUM
)
1047 saved_reg
= cache
->ws
;
1049 saved_reg
= 1 << cache
->wb
;
1051 else if (regnum
== WB_REGNUM
)
1052 saved_reg
= cache
->wb
;
1053 else if (regnum
== PC_REGNUM
)
1054 saved_reg
= cache
->pc
;
1055 else if (regnum
== PS_REGNUM
)
1056 saved_reg
= cache
->ps
;
1067 store_unsigned_integer (valuep
, 4, saved_reg
);
1072 /* Convert Ax register numbers to ARx register numbers. */
1073 if (regnum
>= A0_REGNUM
&& regnum
<= A15_REGNUM
)
1074 regnum
= AREG_NUMBER (regnum
, cache
->wb
);
1076 /* Check if ARx register has been saved to stack. */
1077 if (regnum
>= AR_BASE
&& regnum
<= (AR_BASE
+ NUM_AREGS
))
1079 int areg
= regnum
- AR_BASE
- (cache
->wb
* 4);
1082 && areg
< XTENSA_NUM_SAVED_AREGS
1083 && cache
->aregs
[areg
] != -1)
1086 *lvalp
= lval_memory
;
1087 *addrp
= cache
->aregs
[areg
];
1091 read_memory (*addrp
, valuep
,
1092 register_size (current_gdbarch
, regnum
));
1094 DEBUGINFO ("[xtensa_frame_prev_register] register on stack\n");
1099 /* Note: All other registers have been either saved to the dummy stack
1100 or are still alive in the processor. */
1103 *lvalp
= lval_register
;
1107 frame_unwind_register (next_frame
, (*realnump
), valuep
);
1111 static const struct frame_unwind
1112 xtensa_frame_unwind
=
1115 xtensa_frame_this_id
,
1116 xtensa_frame_prev_register
1119 static const struct frame_unwind
*
1120 xtensa_frame_sniffer (struct frame_info
*next_frame
)
1122 return &xtensa_frame_unwind
;
1126 xtensa_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
1128 struct xtensa_frame_cache
*cache
=
1129 xtensa_frame_cache (next_frame
, this_cache
);
1134 static const struct frame_base
1137 &xtensa_frame_unwind
,
1138 xtensa_frame_base_address
,
1139 xtensa_frame_base_address
,
1140 xtensa_frame_base_address
1145 xtensa_extract_return_value (struct type
*type
,
1146 struct regcache
*regcache
,
1149 bfd_byte
*valbuf
= dst
;
1150 int len
= TYPE_LENGTH (type
);
1155 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1157 gdb_assert(len
> 0);
1159 /* First, we have to find the caller window in the register file. */
1160 regcache_raw_read_unsigned (regcache
, PC_REGNUM
, &pc
);
1161 callsize
= extract_call_winsize (pc
);
1163 /* On Xtensa, we can return up to 4 words (or 2 when called by call12). */
1164 if (len
> (callsize
> 8 ? 8 : 16))
1165 internal_error (__FILE__
, __LINE__
,
1166 _("cannot extract return value of %d bytes long"), len
);
1168 /* Get the register offset of the return register (A2) in the caller
1170 regcache_raw_read_unsigned (regcache
, WB_REGNUM
, &wb
);
1171 areg
= AREG_NUMBER(A2_REGNUM
+ callsize
, wb
);
1173 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg
, len
);
1175 if (len
< 4 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1178 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1181 regcache_raw_read_part (regcache
, areg
, offset
, len
, valbuf
);
1183 regcache_raw_read (regcache
, areg
, valbuf
);
1189 xtensa_store_return_value (struct type
*type
,
1190 struct regcache
*regcache
,
1193 const bfd_byte
*valbuf
= dst
;
1197 int len
= TYPE_LENGTH (type
);
1200 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1202 regcache_raw_read_unsigned (regcache
, WB_REGNUM
, &wb
);
1203 regcache_raw_read_unsigned (regcache
, PC_REGNUM
, &pc
);
1204 callsize
= extract_call_winsize (pc
);
1206 if (len
> (callsize
> 8 ? 8 : 16))
1207 internal_error (__FILE__
, __LINE__
,
1208 _("unimplemented for this length: %d"),
1209 TYPE_LENGTH (type
));
1211 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1212 callsize
, (int) wb
);
1214 if (len
< 4 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1217 areg
= AREG_NUMBER (A2_REGNUM
+ callsize
, wb
);
1219 for (; len
> 0; len
-= 4, areg
++, valbuf
+= 4)
1222 regcache_raw_write_part (regcache
, areg
, offset
, len
, valbuf
);
1224 regcache_raw_write (regcache
, areg
, valbuf
);
1229 enum return_value_convention
1230 xtensa_return_value (struct gdbarch
*gdbarch
,
1231 struct type
*valtype
,
1232 struct regcache
*regcache
,
1234 const gdb_byte
*writebuf
)
1236 /* Note: Structures up to 16 bytes are returned in registers. */
1238 int struct_return
= ((TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
1239 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
1240 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
1241 && TYPE_LENGTH (valtype
) > 16);
1244 return RETURN_VALUE_STRUCT_CONVENTION
;
1246 DEBUGTRACE ("xtensa_return_value(...)\n");
1248 if (writebuf
!= NULL
)
1250 xtensa_store_return_value (valtype
, regcache
, writebuf
);
1253 if (readbuf
!= NULL
)
1255 gdb_assert (!struct_return
);
1256 xtensa_extract_return_value (valtype
, regcache
, readbuf
);
1258 return RETURN_VALUE_REGISTER_CONVENTION
;
1265 xtensa_push_dummy_call (struct gdbarch
*gdbarch
,
1266 struct value
*function
,
1267 struct regcache
*regcache
,
1270 struct value
**args
,
1273 CORE_ADDR struct_addr
)
1276 int size
, onstack_size
;
1277 gdb_byte
*buf
= (gdb_byte
*) alloca (16);
1279 struct argument_info
1281 const bfd_byte
*contents
;
1283 int onstack
; /* onstack == 0 => in reg */
1284 int align
; /* alignment */
1287 int offset
; /* stack offset if on stack */
1288 int regno
; /* regno if in register */
1292 struct argument_info
*arg_info
=
1293 (struct argument_info
*) alloca (nargs
* sizeof (struct argument_info
));
1297 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1299 if (xtensa_debug_level
> 3)
1302 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs
);
1303 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1304 "struct_addr=0x%x\n",
1305 (int) sp
, (int) struct_return
, (int) struct_addr
);
1307 for (i
= 0; i
< nargs
; i
++)
1309 struct value
*arg
= args
[i
];
1310 struct type
*arg_type
= check_typedef (value_type (arg
));
1311 fprintf_unfiltered (gdb_stdlog
, "%2d: %p %3d ",
1312 i
, arg
, TYPE_LENGTH (arg_type
));
1313 switch (TYPE_CODE (arg_type
))
1316 fprintf_unfiltered (gdb_stdlog
, "int");
1318 case TYPE_CODE_STRUCT
:
1319 fprintf_unfiltered (gdb_stdlog
, "struct");
1322 fprintf_unfiltered (gdb_stdlog
, "%3d", TYPE_CODE (arg_type
));
1325 fprintf_unfiltered (gdb_stdlog
, " %p\n",
1326 value_contents (arg
));
1330 /* First loop: collect information.
1331 Cast into type_long. (This shouldn't happen often for C because
1332 GDB already does this earlier.) It's possible that GDB could
1333 do it all the time but it's harmless to leave this code here. */
1340 size
= REGISTER_SIZE
;
1342 for (i
= 0; i
< nargs
; i
++)
1344 struct argument_info
*info
= &arg_info
[i
];
1345 struct value
*arg
= args
[i
];
1346 struct type
*arg_type
= check_typedef (value_type (arg
));
1348 switch (TYPE_CODE (arg_type
))
1351 case TYPE_CODE_BOOL
:
1352 case TYPE_CODE_CHAR
:
1353 case TYPE_CODE_RANGE
:
1354 case TYPE_CODE_ENUM
:
1356 /* Cast argument to long if necessary as the mask does it too. */
1357 if (TYPE_LENGTH (arg_type
) < TYPE_LENGTH (builtin_type_long
))
1359 arg_type
= builtin_type_long
;
1360 arg
= value_cast (arg_type
, arg
);
1362 info
->align
= TYPE_LENGTH (builtin_type_long
);
1367 /* Align doubles correctly. */
1368 if (TYPE_LENGTH (arg_type
) == TYPE_LENGTH (builtin_type_double
))
1369 info
->align
= TYPE_LENGTH (builtin_type_double
);
1371 info
->align
= TYPE_LENGTH (builtin_type_long
);
1374 case TYPE_CODE_STRUCT
:
1376 info
->align
= TYPE_LENGTH (builtin_type_long
);
1379 info
->length
= TYPE_LENGTH (arg_type
);
1380 info
->contents
= value_contents (arg
);
1382 /* Align size and onstack_size. */
1383 size
= (size
+ info
->align
- 1) & ~(info
->align
- 1);
1384 onstack_size
= (onstack_size
+ info
->align
- 1) & ~(info
->align
- 1);
1386 if (size
+ info
->length
> REGISTER_SIZE
* ARGS_NUM_REGS
)
1389 info
->u
.offset
= onstack_size
;
1390 onstack_size
+= info
->length
;
1395 info
->u
.regno
= ARGS_FIRST_REG
+ size
/ REGISTER_SIZE
;
1397 size
+= info
->length
;
1400 /* Adjust the stack pointer and align it. */
1401 sp
= align_down (sp
- onstack_size
, SP_ALIGNMENT
);
1403 /* Simulate MOVSP. */
1406 read_memory (osp
- 16, buf
, 16);
1407 write_memory (sp
- 16, buf
, 16);
1410 /* Second Loop: Load arguments. */
1414 store_unsigned_integer (buf
, REGISTER_SIZE
, struct_addr
);
1415 regcache_cooked_write (regcache
, ARGS_FIRST_REG
, buf
);
1418 for (i
= 0; i
< nargs
; i
++)
1420 struct argument_info
*info
= &arg_info
[i
];
1424 int n
= info
->length
;
1425 CORE_ADDR offset
= sp
+ info
->u
.offset
;
1427 /* Odd-sized structs are aligned to the lower side of a memory
1428 word in big-endian mode and require a shift. This only
1429 applies for structures smaller than one word. */
1431 if (n
< REGISTER_SIZE
&& TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1432 offset
+= (REGISTER_SIZE
- n
);
1434 write_memory (offset
, info
->contents
, info
->length
);
1439 int n
= info
->length
;
1440 const bfd_byte
*cp
= info
->contents
;
1441 int r
= info
->u
.regno
;
1443 /* Odd-sized structs are aligned to the lower side of registers in
1444 big-endian mode and require a shift. The odd-sized leftover will
1445 be at the end. Note that this is only true for structures smaller
1446 than REGISTER_SIZE; for larger odd-sized structures the excess
1447 will be left-aligned in the register on both endiannesses. */
1449 if (n
< REGISTER_SIZE
&& TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1451 ULONGEST v
= extract_unsigned_integer (cp
, REGISTER_SIZE
);
1452 v
= v
>> ((REGISTER_SIZE
- n
) * TARGET_CHAR_BIT
);
1454 store_unsigned_integer (buf
, REGISTER_SIZE
, v
);
1455 regcache_cooked_write (regcache
, r
, buf
);
1457 cp
+= REGISTER_SIZE
;
1464 /* ULONGEST v = extract_unsigned_integer (cp, REGISTER_SIZE);*/
1465 regcache_cooked_write (regcache
, r
, cp
);
1467 /* write_register (r, v); */
1468 cp
+= REGISTER_SIZE
;
1476 /* Set the return address of dummy frame to the dummy address.
1477 Note: The return address for the current function (in A0) is
1478 saved in the dummy frame, so we can savely overwrite A0 here. */
1480 ra
= (bp_addr
& 0x3fffffff) | 0x40000000;
1481 regcache_raw_read (regcache
, PS_REGNUM
, buf
);
1482 ps
= extract_unsigned_integer (buf
, 4) & ~0x00030000;
1483 regcache_cooked_write_unsigned (regcache
, A4_REGNUM
, ra
);
1484 regcache_cooked_write_unsigned (regcache
, PS_REGNUM
, ps
| 0x00010000);
1486 /* Set new stack pointer and return it. */
1487 regcache_cooked_write_unsigned (regcache
, A1_REGNUM
, sp
);
1488 /* Make dummy frame ID unique by adding a constant. */
1489 return sp
+ SP_ALIGNMENT
;
1493 /* Return a breakpoint for the current location of PC. We always use
1494 the density version if we have density instructions (regardless of the
1495 current instruction at PC), and use regular instructions otherwise. */
1497 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1498 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1499 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1500 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1502 const unsigned char *
1503 xtensa_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
1505 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
1506 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
1507 static unsigned char density_big_breakpoint
[] = DENSITY_BIG_BREAKPOINT
;
1508 static unsigned char density_little_breakpoint
[] = DENSITY_LITTLE_BREAKPOINT
;
1510 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr
);
1512 if (ISA_USE_DENSITY_INSTRUCTIONS
)
1514 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1516 *lenptr
= sizeof (density_big_breakpoint
);
1517 return density_big_breakpoint
;
1521 *lenptr
= sizeof (density_little_breakpoint
);
1522 return density_little_breakpoint
;
1527 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1529 *lenptr
= sizeof (big_breakpoint
);
1530 return big_breakpoint
;
1534 *lenptr
= sizeof (little_breakpoint
);
1535 return little_breakpoint
;
1541 /* Return the pc of the first real instruction. We assume that this
1542 machine uses register windows.
1544 If we have debug info ( line-number info, in particular ) we simply skip
1545 the code associated with the first function line effectively skipping
1546 the prologue code. It works even in cases like
1549 { int local_var = 1;
1553 because, for this source code, both Xtensa compilers will generate two
1554 separate entries ( with the same line number ) in dwarf line-number
1555 section to make sure there is a boundary between the prologue code and
1556 the rest of the function.
1558 If there is no debug info, we need to analyze the code. */
1561 xtensa_skip_prologue (CORE_ADDR start_pc
)
1563 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc
);
1565 if (ISA_USE_WINDOWED_REGISTERS
)
1568 struct symtab_and_line prologue_sal
;
1570 op1
= read_memory_integer (start_pc
, 1);
1571 if (!XTENSA_IS_ENTRY (op1
))
1574 prologue_sal
= find_pc_line (start_pc
, 0);
1575 if (prologue_sal
.line
!= 0)
1576 return prologue_sal
.end
;
1578 return start_pc
+ XTENSA_ENTRY_LENGTH
;
1582 internal_error (__FILE__
, __LINE__
,
1583 _("non-windowed configurations are not supported"));
1589 /* CONFIGURATION CHECK */
1591 /* Verify the current configuration. */
1594 xtensa_verify_config (struct gdbarch
*gdbarch
)
1596 struct ui_file
*log
;
1597 struct cleanup
*cleanups
;
1598 struct gdbarch_tdep
*tdep
;
1602 tdep
= gdbarch_tdep (gdbarch
);
1603 log
= mem_fileopen ();
1604 cleanups
= make_cleanup_ui_file_delete (log
);
1606 /* Verify that we got a reasonable number of AREGS. */
1607 if ((tdep
->num_aregs
& -tdep
->num_aregs
) != tdep
->num_aregs
)
1608 fprintf_unfiltered (log
, "\n\tnum_aregs: Number of AR registers (%d) "
1609 "is not a power of two!", tdep
->num_aregs
);
1611 /* Verify that certain registers exist. */
1612 if (tdep
->pc_regnum
== -1)
1613 fprintf_unfiltered (log
, "\n\tpc_regnum: No PC register");
1614 if (tdep
->ps_regnum
== -1)
1615 fprintf_unfiltered (log
, "\n\tps_regnum: No PS register");
1616 if (tdep
->wb_regnum
== -1)
1617 fprintf_unfiltered (log
, "\n\twb_regnum: No WB register");
1618 if (tdep
->ws_regnum
== -1)
1619 fprintf_unfiltered (log
, "\n\tws_regnum: No WS register");
1620 if (tdep
->ar_base
== -1)
1621 fprintf_unfiltered (log
, "\n\tar_base: No AR registers");
1622 if (tdep
->a0_base
== -1)
1623 fprintf_unfiltered (log
, "\n\ta0_base: No Ax registers");
1625 buf
= ui_file_xstrdup (log
, &dummy
);
1626 make_cleanup (xfree
, buf
);
1627 if (strlen (buf
) > 0)
1628 internal_error (__FILE__
, __LINE__
,
1629 _("the following are invalid: %s"), buf
);
1630 do_cleanups (cleanups
);
1634 /* Module "constructor" function. */
1636 static struct gdbarch
*
1637 xtensa_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1639 struct gdbarch_tdep
*tdep
;
1640 struct gdbarch
*gdbarch
;
1641 struct xtensa_abi_handler
*abi_handler
;
1643 DEBUGTRACE ("gdbarch_init()\n");
1645 /* We have to set the byte order before we call gdbarch_alloc. */
1646 info
.byte_order
= xtensa_config_byte_order (&info
);
1648 tdep
= xtensa_config_tdep (&info
);
1649 gdbarch
= gdbarch_alloc (&info
, tdep
);
1651 /* Verify our configuration. */
1652 xtensa_verify_config (gdbarch
);
1654 /* Pseudo-Register read/write */
1655 set_gdbarch_pseudo_register_read (gdbarch
, xtensa_pseudo_register_read
);
1656 set_gdbarch_pseudo_register_write (gdbarch
, xtensa_pseudo_register_write
);
1658 /* Set target information. */
1659 set_gdbarch_num_regs (gdbarch
, tdep
->num_regs
);
1660 set_gdbarch_num_pseudo_regs (gdbarch
, tdep
->num_pseudo_regs
);
1661 set_gdbarch_sp_regnum (gdbarch
, tdep
->a0_base
+ 1);
1662 set_gdbarch_pc_regnum (gdbarch
, tdep
->pc_regnum
);
1663 set_gdbarch_ps_regnum (gdbarch
, tdep
->ps_regnum
);
1665 /* Renumber registers for known formats (stab, dwarf, and dwarf2). */
1666 set_gdbarch_stab_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
1667 set_gdbarch_dwarf_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
1668 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, xtensa_reg_to_regnum
);
1670 /* We provide our own function to get register information. */
1671 set_gdbarch_register_name (gdbarch
, xtensa_register_name
);
1672 set_gdbarch_register_type (gdbarch
, xtensa_register_type
);
1674 /* To call functions from GDB using dummy frame */
1675 set_gdbarch_push_dummy_call (gdbarch
, xtensa_push_dummy_call
);
1677 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
1679 set_gdbarch_return_value (gdbarch
, xtensa_return_value
);
1681 /* Advance PC across any prologue instructions to reach "real" code. */
1682 set_gdbarch_skip_prologue (gdbarch
, xtensa_skip_prologue
);
1684 /* Stack grows downward. */
1685 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1687 /* Set breakpoints. */
1688 set_gdbarch_breakpoint_from_pc (gdbarch
, xtensa_breakpoint_from_pc
);
1690 /* After breakpoint instruction or illegal instruction, pc still
1691 points at break instruction, so don't decrement. */
1692 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
1694 /* We don't skip args. */
1695 set_gdbarch_frame_args_skip (gdbarch
, 0);
1697 set_gdbarch_unwind_pc (gdbarch
, xtensa_unwind_pc
);
1699 set_gdbarch_frame_align (gdbarch
, xtensa_frame_align
);
1701 set_gdbarch_unwind_dummy_id (gdbarch
, xtensa_unwind_dummy_id
);
1703 /* Frame handling. */
1704 frame_base_set_default (gdbarch
, &xtensa_frame_base
);
1705 frame_unwind_append_sniffer (gdbarch
, xtensa_frame_sniffer
);
1707 set_gdbarch_print_insn (gdbarch
, print_insn_xtensa
);
1709 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
1711 xtensa_add_reggroups (gdbarch
);
1712 set_gdbarch_register_reggroup_p (gdbarch
, xtensa_register_reggroup_p
);
1714 set_gdbarch_regset_from_core_section (gdbarch
,
1715 xtensa_regset_from_core_section
);
1721 /* Dump xtensa tdep structure. */
1724 xtensa_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
1726 error (_("xtensa_dump_tdep(): not implemented"));
1731 _initialize_xtensa_tdep (void)
1733 struct cmd_list_element
*c
;
1735 gdbarch_register (bfd_arch_xtensa
, xtensa_gdbarch_init
, xtensa_dump_tdep
);
1736 xtensa_init_reggroups ();
1738 add_setshow_zinteger_cmd ("xtensa",
1740 &xtensa_debug_level
, _("\
1741 Set Xtensa debugging."), _("\
1742 Show Xtensa debugging."), _("\
1743 When non-zero, Xtensa-specific debugging is enabled. \
1744 Can be 1, 2, 3, or 4 indicating the level of debugging."),
1747 &setdebuglist
, &showdebuglist
);