gdb/xtensa-tdep.h

   1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
   2
   3    Copyright (C) 2003, 2005, 2006, 2007, 2008, 2009
   4    Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21
  22 /* XTENSA_TDEP_VERSION can/should be changed along with XTENSA_CONFIG_VERSION
  23    whenever the "tdep" structure changes in an incompatible way.  */
  24
  25 #define XTENSA_TDEP_VERSION 0x60
  26
  27 /*  Xtensa register type.  */
  28
  29 typedef enum
  30 {
  31   xtRegisterTypeArRegfile = 1,  /* Register File ar0..arXX.  */
  32   xtRegisterTypeSpecialReg,     /* CPU states, such as PS, Booleans, (rsr).  */
  33   xtRegisterTypeUserReg,        /* User defined registers (rur).  */
  34   xtRegisterTypeTieRegfile,     /* User define register files.  */
  35   xtRegisterTypeTieState,       /* TIE States (mapped on user regs).  */
  36   xtRegisterTypeMapped,         /* Mapped on Special Registers.  */
  37   xtRegisterTypeUnmapped,       /* Special case of masked registers.  */
  38   xtRegisterTypeWindow,         /* Live window registers (a0..a15).  */
  39   xtRegisterTypeVirtual,        /* PC, FP.  */
  40   xtRegisterTypeUnknown
  41 } xtensa_register_type_t;
  42
  43
  44 /*  Xtensa register group.  */
  45
  46 #define XTENSA_MAX_COPROCESSOR  0x08  /* Number of Xtensa coprocessors.  */
  47
  48 typedef enum
  49 {
  50   xtRegisterGroupUnknown = 0,
  51   xtRegisterGroupRegFile        = 0x0001,    /* Register files without ARx.  */
  52   xtRegisterGroupAddrReg        = 0x0002,    /* ARx.  */
  53   xtRegisterGroupSpecialReg     = 0x0004,    /* SRxx.  */
  54   xtRegisterGroupUserReg        = 0x0008,    /* URxx.  */
  55   xtRegisterGroupState          = 0x0010,    /* States.  */
  56
  57   xtRegisterGroupGeneral        = 0x0100,    /* General registers, Ax, SR.  */
  58   xtRegisterGroupUser           = 0x0200,    /* User registers.  */
  59   xtRegisterGroupFloat          = 0x0400,    /* Floating Point.  */
  60   xtRegisterGroupVectra         = 0x0800,    /* Vectra.  */
  61   xtRegisterGroupSystem         = 0x1000,    /* System.  */
  62
  63   xtRegisterGroupNCP        = 0x00800000,    /* Non-CP non-base opt/custom.  */
  64   xtRegisterGroupCP0        = 0x01000000,    /* CP0.  */
  65   xtRegisterGroupCP1        = 0x02000000,    /* CP1.  */
  66   xtRegisterGroupCP2        = 0x04000000,    /* CP2.  */
  67   xtRegisterGroupCP3        = 0x08000000,    /* CP3.  */
  68   xtRegisterGroupCP4        = 0x10000000,    /* CP4.  */
  69   xtRegisterGroupCP5        = 0x20000000,    /* CP5.  */
  70   xtRegisterGroupCP6        = 0x40000000,    /* CP6.  */
  71   xtRegisterGroupCP7        = 0x80000000,    /* CP7.  */
  72
  73 } xtensa_register_group_t;
  74
  75
  76 /*  Xtensa target flags.  */
  77
  78 typedef enum
  79 {
  80   xtTargetFlagsNonVisibleRegs   = 0x0001,
  81   xtTargetFlagsUseFetchStore    = 0x0002,
  82 } xtensa_target_flags_t;
  83
  84
  85 /* Xtensa ELF core file register set representation ('.reg' section).
  86    Copied from target-side ELF header <xtensa/elf.h>.  */
  87
  88 typedef unsigned long xtensa_elf_greg_t;
  89
  90 typedef struct
  91 {
  92   xtensa_elf_greg_t pc;
  93   xtensa_elf_greg_t ps;
  94   xtensa_elf_greg_t lbeg;
  95   xtensa_elf_greg_t lend;
  96   xtensa_elf_greg_t lcount;
  97   xtensa_elf_greg_t sar;
  98   xtensa_elf_greg_t windowstart;
  99   xtensa_elf_greg_t windowbase;
 100   xtensa_elf_greg_t reserved[8+48];
 101   xtensa_elf_greg_t ar[64];
 102 } xtensa_elf_gregset_t;
 103
 104 #define XTENSA_ELF_NGREG (sizeof (xtensa_elf_gregset_t) \
 105                           / sizeof (xtensa_elf_greg_t))
 106
 107 /*  Mask.  */
 108
 109 typedef struct
 110 {
 111   int reg_num;
 112   int bit_start;
 113   int bit_size;
 114 } xtensa_reg_mask_t;
 115
 116 typedef struct
 117 {
 118   int count;
 119   xtensa_reg_mask_t *mask;
 120 } xtensa_mask_t;
 121
 122
 123 /*  Xtensa register representation.  */
 124
 125 typedef struct
 126 {
 127   char* name;                   /* Register name.  */
 128   int offset;                   /* Offset.  */
 129   xtensa_register_type_t type;  /* Register type.  */
 130   xtensa_register_group_t group;/* Register group.  */
 131   struct type* ctype;           /* C-type.  */
 132   int bit_size;                 /* The actual bit size in the target.  */
 133   int byte_size;                /* Actual space allocated in registers[].  */
 134   int align;                    /* Alignment for this register.  */
 135
 136   unsigned int target_number;   /* Register target number.  */
 137
 138   int flags;                    /* Flags.  */
 139   int coprocessor;              /* Coprocessor num, -1 for non-CP, else -2.  */
 140
 141   const xtensa_mask_t *mask;    /* Register is a compilation of other regs.  */
 142   const char *fetch;            /* Instruction sequence to fetch register.  */
 143   const char *store;            /* Instruction sequence to store register.  */
 144 } xtensa_register_t;
 145
 146 /*  For xtensa-config.c to expand to the structure above.  */
 147 #define XTREG(index,ofs,bsz,sz,al,tnum,flg,cp,ty,gr,name,fet,sto,mas,ct,x,y) \
 148         {#name, ofs, ty, ((gr)|((xtRegisterGroupNCP>>2)<<(cp+2))), \
 149          ct, bsz, sz, al, tnum, flg, cp, mas, fet, sto},
 150 #define XTREG_END {0, 0, 0, 0, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0},
 151
 152 #define XTENSA_REGISTER_FLAGS_PRIVILEGED        0x0001
 153 #define XTENSA_REGISTER_FLAGS_READABLE          0x0002
 154 #define XTENSA_REGISTER_FLAGS_WRITABLE          0x0004
 155 #define XTENSA_REGISTER_FLAGS_VOLATILE          0x0008
 156
 157 /*  Call-ABI for stack frame.  */
 158
 159 typedef enum
 160 {
 161   CallAbiDefault = 0,           /* Any 'callX' instructions; default stack.  */
 162   CallAbiCall0Only,             /* Only 'call0' instructions; flat stack.  */
 163 } call_abi_t;
 164
 165
 166 /*  Xtensa-specific target dependencies.  */
 167
 168 struct gdbarch_tdep
 169 {
 170   unsigned int target_flags;
 171
 172   /* Spill location for TIE register files under ocd.  */
 173
 174   unsigned int spill_location;
 175   unsigned int spill_size;
 176
 177   char *unused;                         /* Placeholder for compatibility.  */
 178   call_abi_t call_abi;                  /* Calling convention.  */
 179
 180   /* CPU configuration.  */
 181
 182   unsigned int debug_interrupt_level;
 183
 184   unsigned int icache_line_bytes;
 185   unsigned int dcache_line_bytes;
 186   unsigned int dcache_writeback;
 187
 188   unsigned int isa_use_windowed_registers;
 189   unsigned int isa_use_density_instructions;
 190   unsigned int isa_use_exceptions;
 191   unsigned int isa_use_ext_l32r;
 192   unsigned int isa_max_insn_size;       /* Maximum instruction length.  */
 193   unsigned int debug_num_ibreaks;       /* Number of IBREAKs.  */
 194   unsigned int debug_num_dbreaks;
 195
 196   /* Register map.  */
 197
 198   xtensa_register_t* regmap;
 199
 200   unsigned int num_regs;        /* Number of registers in register map.  */
 201   unsigned int num_nopriv_regs; /* Number of non-privileged registers.  */
 202   unsigned int num_pseudo_regs; /* Number of pseudo registers.  */
 203   unsigned int num_aregs;       /* Size of register file.  */
 204   unsigned int num_contexts;
 205
 206   int ar_base;                  /* Register number for AR0.  */
 207   int a0_base;                  /* Register number for A0 (pseudo).  */
 208   int wb_regnum;                /* Register number for WB.  */
 209   int ws_regnum;                /* Register number for WS.  */
 210   int pc_regnum;                /* Register number for PC.  */
 211   int ps_regnum;                /* Register number for PS.  */
 212   int lbeg_regnum;              /* Register numbers for count regs.  */
 213   int lend_regnum;
 214   int lcount_regnum;
 215   int sar_regnum;               /* Register number of SAR.  */
 216   int litbase_regnum;           /* Register number of LITBASE.  */
 217
 218   int interrupt_regnum;         /* Register number for interrupt.  */
 219   int interrupt2_regnum;        /* Register number for interrupt2.  */
 220   int cpenable_regnum;          /* Register number for cpenable.  */
 221   int debugcause_regnum;        /* Register number for debugcause.  */
 222   int exccause_regnum;          /* Register number for exccause.  */
 223   int excvaddr_regnum;          /* Register number for excvaddr.  */
 224
 225   int max_register_raw_size;
 226   int max_register_virtual_size;
 227   unsigned long *fp_layout;     /* Layout of custom/TIE regs in 'FP' area.  */
 228   unsigned int fp_layout_bytes; /* Size of layout information (in bytes).  */
 229   unsigned long *gregmap;
 230 };
 231
 232 /* Macro to instantiate a gdbarch_tdep structure.  */
 233
 234 #define XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spillsz)           \
 235         {                                                       \
 236           .target_flags = 0,                                    \
 237           .spill_location = -1,                                 \
 238           .spill_size = (spillsz),                              \
 239           .unused = 0,                                          \
 240           .call_abi = 0,                                        \
 241           .debug_interrupt_level = XCHAL_DEBUGLEVEL,            \
 242           .icache_line_bytes = XCHAL_ICACHE_LINESIZE,           \
 243           .dcache_line_bytes = XCHAL_DCACHE_LINESIZE,           \
 244           .dcache_writeback = XCHAL_DCACHE_IS_WRITEBACK,        \
 245           .isa_use_windowed_registers = (XSHAL_ABI != XTHAL_ABI_CALL0), \
 246           .isa_use_density_instructions = XCHAL_HAVE_DENSITY,   \
 247           .isa_use_exceptions = XCHAL_HAVE_EXCEPTIONS,          \
 248           .isa_use_ext_l32r = XSHAL_USE_ABSOLUTE_LITERALS,      \
 249           .isa_max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE,      \
 250           .debug_num_ibreaks = XCHAL_NUM_IBREAK,                \
 251           .debug_num_dbreaks = XCHAL_NUM_DBREAK,                \
 252           .regmap = rmap,                       \
 253           .num_regs = 0,                        \
 254           .num_nopriv_regs = 0,                 \
 255           .num_pseudo_regs = 0,                 \
 256           .num_aregs = XCHAL_NUM_AREGS,         \
 257           .num_contexts = XCHAL_NUM_CONTEXTS,   \
 258           .ar_base = -1,                        \
 259           .a0_base = -1,                        \
 260           .wb_regnum = -1,                      \
 261           .ws_regnum = -1,                      \
 262           .pc_regnum = -1,                      \
 263           .ps_regnum = -1,                      \
 264           .lbeg_regnum = -1,                    \
 265           .lend_regnum = -1,                    \
 266           .lcount_regnum = -1,                  \
 267           .sar_regnum = -1,                     \
 268           .litbase_regnum = -1,                 \
 269           .interrupt_regnum = -1,               \
 270           .interrupt2_regnum = -1,              \
 271           .cpenable_regnum = -1,                \
 272           .debugcause_regnum = -1,              \
 273           .exccause_regnum = -1,                \
 274           .excvaddr_regnum = -1,                \
 275           .max_register_raw_size = 0,           \
 276           .max_register_virtual_size = 0,       \
 277           .fp_layout = 0,                       \
 278           .fp_layout_bytes = 0,                 \
 279           .gregmap = 0,                         \
 280         }
 281 #define XTENSA_CONFIG_INSTANTIATE(rmap,spill_size)      \
 282         struct gdbarch_tdep xtensa_tdep = \
 283           XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spill_size);
 284
 285 #ifndef XCHAL_NUM_CONTEXTS
 286 #define XCHAL_NUM_CONTEXTS      0
 287 #endif
 288 #ifndef XCHAL_HAVE_EXCEPTIONS
 289 #define XCHAL_HAVE_EXCEPTIONS   1
 290 #endif
 291 #define WB_SHIFT          2
 292
 293 /* We assign fixed numbers to the registers of the "current" window
 294    (i.e., relative to WB).  The registers get remapped via the reg_map
 295    data structure to their corresponding register in the AR register
 296    file (see xtensa-tdep.c).  */
 297