gdbserver/linux-crisv32-low.cc

   1 /* GNU/Linux/CRIS specific low level interface, for the remote server for GDB.
   2    Copyright (C) 1995-2020 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #include "server.h"
  20 #include "linux-low.h"
  21 #include "nat/gdb_ptrace.h"
  22
  23 /* Linux target op definitions for the CRIS architecture.  */
  24
  25 class crisv32_target : public linux_process_target
  26 {
  27 public:
  28
  29   const regs_info *get_regs_info () override;
  30
  31   const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override;
  32
  33   bool supports_z_point_type (char z_type) override;
  34
  35 protected:
  36
  37   void low_arch_setup () override;
  38
  39   bool low_cannot_fetch_register (int regno) override;
  40
  41   bool low_cannot_store_register (int regno) override;
  42
  43   bool low_supports_breakpoints () override;
  44
  45   CORE_ADDR low_get_pc (regcache *regcache) override;
  46
  47   void low_set_pc (regcache *regcache, CORE_ADDR newpc) override;
  48
  49   bool low_breakpoint_at (CORE_ADDR pc) override;
  50
  51   int low_insert_point (raw_bkpt_type type, CORE_ADDR addr,
  52                         int size, raw_breakpoint *bp) override;
  53
  54   int low_remove_point (raw_bkpt_type type, CORE_ADDR addr,
  55                         int size, raw_breakpoint *bp) override;
  56 };
  57
  58 /* The singleton target ops object.  */
  59
  60 static crisv32_target the_crisv32_target;
  61
  62 bool
  63 crisv32_target::low_cannot_fetch_register (int regno)
  64 {
  65   gdb_assert_not_reached ("linux target op low_cannot_fetch_register "
  66                           "is not implemented by the target");
  67 }
  68
  69 bool
  70 crisv32_target::low_cannot_store_register (int regno)
  71 {
  72   gdb_assert_not_reached ("linux target op low_cannot_store_register "
  73                           "is not implemented by the target");
  74 }
  75
  76 bool
  77 crisv32_target::low_supports_breakpoints ()
  78 {
  79   return true;
  80 }
  81
  82 CORE_ADDR
  83 crisv32_target::low_get_pc (regcache *regcache)
  84 {
  85   return linux_get_pc_32bit (regcache);
  86 }
  87
  88 void
  89 crisv32_target::low_set_pc (regcache *regcache, CORE_ADDR pc)
  90 {
  91   linux_set_pc_32bit (regcache, pc);
  92 }
  93
  94 /* Defined in auto-generated file reg-crisv32.c.  */
  95 void init_registers_crisv32 (void);
  96 extern const struct target_desc *tdesc_crisv32;
  97
  98 /* CRISv32 */
  99 #define cris_num_regs 49
 100
 101 #ifndef PTRACE_GET_THREAD_AREA
 102 #define PTRACE_GET_THREAD_AREA 25
 103 #endif
 104
 105 /* Note: Ignoring USP (having the stack pointer in two locations causes trouble
 106    without any significant gain).  */
 107
 108 /* Locations need to match <include/asm/arch/ptrace.h>.  */
 109 static int cris_regmap[] = {
 110   1*4, 2*4, 3*4, 4*4,
 111   5*4, 6*4, 7*4, 8*4,
 112   9*4, 10*4, 11*4, 12*4,
 113   13*4, 14*4, 24*4, 15*4,
 114
 115   -1, -1, -1, 16*4,
 116   -1, 22*4, 23*4, 17*4,
 117   -1, -1, 21*4, 20*4,
 118   -1, 19*4, -1, 18*4,
 119
 120   25*4,
 121
 122   26*4, -1,   -1,   29*4,
 123   30*4, 31*4, 32*4, 33*4,
 124   34*4, 35*4, 36*4, 37*4,
 125   38*4, 39*4, 40*4, -1
 126
 127 };
 128
 129 static const unsigned short cris_breakpoint = 0xe938;
 130 #define cris_breakpoint_len 2
 131
 132 /* Implementation of target ops method "sw_breakpoint_from_kind".  */
 133
 134 const gdb_byte *
 135 crisv32_target::sw_breakpoint_from_kind (int kind, int *size)
 136 {
 137   *size = cris_breakpoint_len;
 138   return (const gdb_byte *) &cris_breakpoint;
 139 }
 140
 141 bool
 142 crisv32_target::low_breakpoint_at (CORE_ADDR where)
 143 {
 144   unsigned short insn;
 145
 146   read_memory (where, (unsigned char *) &insn, cris_breakpoint_len);
 147   if (insn == cris_breakpoint)
 148     return true;
 149
 150   /* If necessary, recognize more trap instructions here.  GDB only uses the
 151      one.  */
 152   return false;
 153 }
 154
 155 static void
 156 cris_write_data_breakpoint (struct regcache *regcache,
 157                             int bp, unsigned long start, unsigned long end)
 158 {
 159   switch (bp)
 160     {
 161     case 0:
 162       supply_register_by_name (regcache, "s3", &start);
 163       supply_register_by_name (regcache, "s4", &end);
 164       break;
 165     case 1:
 166       supply_register_by_name (regcache, "s5", &start);
 167       supply_register_by_name (regcache, "s6", &end);
 168       break;
 169     case 2:
 170       supply_register_by_name (regcache, "s7", &start);
 171       supply_register_by_name (regcache, "s8", &end);
 172       break;
 173     case 3:
 174       supply_register_by_name (regcache, "s9", &start);
 175       supply_register_by_name (regcache, "s10", &end);
 176       break;
 177     case 4:
 178       supply_register_by_name (regcache, "s11", &start);
 179       supply_register_by_name (regcache, "s12", &end);
 180       break;
 181     case 5:
 182       supply_register_by_name (regcache, "s13", &start);
 183       supply_register_by_name (regcache, "s14", &end);
 184       break;
 185     }
 186 }
 187
 188 bool
 189 crisv32_target::supports_z_point_type (char z_type)
 190 {
 191   switch (z_type)
 192     {
 193     case Z_PACKET_WRITE_WP:
 194     case Z_PACKET_READ_WP:
 195     case Z_PACKET_ACCESS_WP:
 196       return true;
 197     default:
 198       return false;
 199     }
 200 }
 201
 202 int
 203 crisv32_target::low_insert_point (raw_bkpt_type type, CORE_ADDR addr,
 204                                   int len, raw_breakpoint *bp)
 205 {
 206   int bp;
 207   unsigned long bp_ctrl;
 208   unsigned long start, end;
 209   unsigned long ccs;
 210   struct regcache *regcache;
 211
 212   regcache = get_thread_regcache (current_thread, 1);
 213
 214   /* Read watchpoints are set as access watchpoints, because of GDB's
 215      inability to deal with pure read watchpoints.  */
 216   if (type == raw_bkpt_type_read_wp)
 217     type = raw_bkpt_type_access_wp;
 218
 219   /* Get the configuration register.  */
 220   collect_register_by_name (regcache, "s0", &bp_ctrl);
 221
 222   /* The watchpoint allocation scheme is the simplest possible.
 223      For example, if a region is watched for read and
 224      a write watch is requested, a new watchpoint will
 225      be used.  Also, if a watch for a region that is already
 226      covered by one or more existing watchpoints, a new
 227      watchpoint will be used.  */
 228
 229   /* First, find a free data watchpoint.  */
 230   for (bp = 0; bp < 6; bp++)
 231     {
 232       /* Each data watchpoint's control registers occupy 2 bits
 233          (hence the 3), starting at bit 2 for D0 (hence the 2)
 234          with 4 bits between for each watchpoint (yes, the 4).  */
 235       if (!(bp_ctrl & (0x3 << (2 + (bp * 4)))))
 236         break;
 237     }
 238
 239   if (bp > 5)
 240     {
 241       /* We're out of watchpoints.  */
 242       return -1;
 243     }
 244
 245   /* Configure the control register first.  */
 246   if (type == raw_bkpt_type_read_wp || type == raw_bkpt_type_access_wp)
 247     {
 248       /* Trigger on read.  */
 249       bp_ctrl |= (1 << (2 + bp * 4));
 250     }
 251   if (type == raw_bkpt_type_write_wp || type == raw_bkpt_type_access_wp)
 252     {
 253       /* Trigger on write.  */
 254       bp_ctrl |= (2 << (2 + bp * 4));
 255     }
 256
 257   /* Setup the configuration register.  */
 258   supply_register_by_name (regcache, "s0", &bp_ctrl);
 259
 260   /* Setup the range.  */
 261   start = addr;
 262   end = addr + len - 1;
 263
 264   /* Configure the watchpoint register.  */
 265   cris_write_data_breakpoint (regcache, bp, start, end);
 266
 267   collect_register_by_name (regcache, "ccs", &ccs);
 268   /* Set the S1 flag to enable watchpoints.  */
 269   ccs |= (1 << 19);
 270   supply_register_by_name (regcache, "ccs", &ccs);
 271
 272   return 0;
 273 }
 274
 275 int
 276 crisv32_target::low_remove_point (raw_bkpt_type type, CORE_ADDR addr,
 277                                   int len, raw_breakpoint *bp)
 278 {
 279   int bp;
 280   unsigned long bp_ctrl;
 281   unsigned long start, end;
 282   struct regcache *regcache;
 283   unsigned long bp_d_regs[12];
 284
 285   regcache = get_thread_regcache (current_thread, 1);
 286
 287   /* Read watchpoints are set as access watchpoints, because of GDB's
 288      inability to deal with pure read watchpoints.  */
 289   if (type == raw_bkpt_type_read_wp)
 290     type = raw_bkpt_type_access_wp;
 291
 292   /* Get the configuration register.  */
 293   collect_register_by_name (regcache, "s0", &bp_ctrl);
 294
 295   /* Try to find a watchpoint that is configured for the
 296      specified range, then check that read/write also matches.  */
 297
 298   /* Ugly pointer arithmetic, since I cannot rely on a
 299      single switch (addr) as there may be several watchpoints with
 300      the same start address for example.  */
 301
 302   /* Get all range registers to simplify search.  */
 303   collect_register_by_name (regcache, "s3", &bp_d_regs[0]);
 304   collect_register_by_name (regcache, "s4", &bp_d_regs[1]);
 305   collect_register_by_name (regcache, "s5", &bp_d_regs[2]);
 306   collect_register_by_name (regcache, "s6", &bp_d_regs[3]);
 307   collect_register_by_name (regcache, "s7", &bp_d_regs[4]);
 308   collect_register_by_name (regcache, "s8", &bp_d_regs[5]);
 309   collect_register_by_name (regcache, "s9", &bp_d_regs[6]);
 310   collect_register_by_name (regcache, "s10", &bp_d_regs[7]);
 311   collect_register_by_name (regcache, "s11", &bp_d_regs[8]);
 312   collect_register_by_name (regcache, "s12", &bp_d_regs[9]);
 313   collect_register_by_name (regcache, "s13", &bp_d_regs[10]);
 314   collect_register_by_name (regcache, "s14", &bp_d_regs[11]);
 315
 316   for (bp = 0; bp < 6; bp++)
 317     {
 318       if (bp_d_regs[bp * 2] == addr
 319           && bp_d_regs[bp * 2 + 1] == (addr + len - 1)) {
 320         /* Matching range.  */
 321         int bitpos = 2 + bp * 4;
 322         int rw_bits;
 323
 324         /* Read/write bits for this BP.  */
 325         rw_bits = (bp_ctrl & (0x3 << bitpos)) >> bitpos;
 326
 327         if ((type == raw_bkpt_type_read_wp && rw_bits == 0x1)
 328             || (type == raw_bkpt_type_write_wp && rw_bits == 0x2)
 329             || (type == raw_bkpt_type_access_wp && rw_bits == 0x3))
 330           {
 331             /* Read/write matched.  */
 332             break;
 333           }
 334       }
 335     }
 336
 337   if (bp > 5)
 338     {
 339       /* No watchpoint matched.  */
 340       return -1;
 341     }
 342
 343   /* Found a matching watchpoint.  Now, deconfigure it by
 344      both disabling read/write in bp_ctrl and zeroing its
 345      start/end addresses.  */
 346   bp_ctrl &= ~(3 << (2 + (bp * 4)));
 347   /* Setup the configuration register.  */
 348   supply_register_by_name (regcache, "s0", &bp_ctrl);
 349
 350   start = end = 0;
 351   /* Configure the watchpoint register.  */
 352   cris_write_data_breakpoint (regcache, bp, start, end);
 353
 354   /* Note that we don't clear the S1 flag here.  It's done when continuing.  */
 355   return 0;
 356 }
 357
 358 static int
 359 cris_stopped_by_watchpoint (void)
 360 {
 361   unsigned long exs;
 362   struct regcache *regcache = get_thread_regcache (current_thread, 1);
 363
 364   collect_register_by_name (regcache, "exs", &exs);
 365
 366   return (((exs & 0xff00) >> 8) == 0xc);
 367 }
 368
 369 static CORE_ADDR
 370 cris_stopped_data_address (void)
 371 {
 372   unsigned long eda;
 373   struct regcache *regcache = get_thread_regcache (current_thread, 1);
 374
 375   collect_register_by_name (regcache, "eda", &eda);
 376
 377   /* FIXME: Possibly adjust to match watched range.  */
 378   return eda;
 379 }
 380
 381 ps_err_e
 382 ps_get_thread_area (struct ps_prochandle *ph,
 383                     lwpid_t lwpid, int idx, void **base)
 384 {
 385   if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
 386     return PS_ERR;
 387
 388   /* IDX is the bias from the thread pointer to the beginning of the
 389      thread descriptor.  It has to be subtracted due to implementation
 390      quirks in libthread_db.  */
 391   *base = (void *) ((char *) *base - idx);
 392   return PS_OK;
 393 }
 394
 395 static void
 396 cris_fill_gregset (struct regcache *regcache, void *buf)
 397 {
 398   int i;
 399
 400   for (i = 0; i < cris_num_regs; i++)
 401     {
 402       if (cris_regmap[i] != -1)
 403         collect_register (regcache, i, ((char *) buf) + cris_regmap[i]);
 404     }
 405 }
 406
 407 static void
 408 cris_store_gregset (struct regcache *regcache, const void *buf)
 409 {
 410   int i;
 411
 412   for (i = 0; i < cris_num_regs; i++)
 413     {
 414       if (cris_regmap[i] != -1)
 415         supply_register (regcache, i, ((char *) buf) + cris_regmap[i]);
 416     }
 417 }
 418
 419 void
 420 crisv32_target::low_arch_setup ()
 421 {
 422   current_process ()->tdesc = tdesc_crisv32;
 423 }
 424
 425 /* Support for hardware single step.  */
 426
 427 static int
 428 cris_supports_hardware_single_step (void)
 429 {
 430   return 1;
 431 }
 432
 433 static struct regset_info cris_regsets[] = {
 434   { PTRACE_GETREGS, PTRACE_SETREGS, 0, cris_num_regs * 4,
 435     GENERAL_REGS, cris_fill_gregset, cris_store_gregset },
 436   NULL_REGSET
 437 };
 438
 439
 440 static struct regsets_info cris_regsets_info =
 441   {
 442     cris_regsets, /* regsets */
 443     0, /* num_regsets */
 444     NULL, /* disabled_regsets */
 445   };
 446
 447 static struct usrregs_info cris_usrregs_info =
 448   {
 449     cris_num_regs,
 450     cris_regmap,
 451   };
 452
 453 static struct regs_info myregs_info =
 454   {
 455     NULL, /* regset_bitmap */
 456     &cris_usrregs_info,
 457     &cris_regsets_info
 458   };
 459
 460 const regs_info *
 461 crisv32_target::get_regs_info ()
 462 {
 463   return &myregs_info;
 464 }
 465
 466 struct linux_target_ops the_low_target = {
 467   cris_stopped_by_watchpoint,
 468   cris_stopped_data_address,
 469   NULL, /* collect_ptrace_register */
 470   NULL, /* supply_ptrace_register */
 471   NULL, /* siginfo_fixup */
 472   NULL, /* new_process */
 473   NULL, /* delete_process */
 474   NULL, /* new_thread */
 475   NULL, /* delete_thread */
 476   NULL, /* new_fork */
 477   NULL, /* prepare_to_resume */
 478   NULL, /* process_qsupported */
 479   NULL, /* supports_tracepoints */
 480   NULL, /* get_thread_area */
 481   NULL, /* install_fast_tracepoint_jump_pad */
 482   NULL, /* emit_ops */
 483   NULL, /* get_min_fast_tracepoint_insn_len */
 484   NULL, /* supports_range_stepping */
 485   cris_supports_hardware_single_step,
 486 };
 487
 488 /* The linux target ops object.  */
 489
 490 linux_process_target *the_linux_target = &the_crisv32_target;
 491
 492 void
 493 initialize_low_arch (void)
 494 {
 495   init_registers_crisv32 ();
 496
 497   initialize_regsets_info (&cris_regsets_info);
 498 }