gdbserver/linux-crisv32-low.cc

   1 /* GNU/Linux/CRIS specific low level interface, for the remote server for GDB.
   2    Copyright (C) 1995-2020 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #include "server.h"
  20 #include "linux-low.h"
  21 #include "nat/gdb_ptrace.h"
  22
  23 /* Linux target op definitions for the CRIS architecture.  */
  24
  25 class crisv32_target : public linux_process_target
  26 {
  27 public:
  28
  29   const regs_info *get_regs_info () override;
  30
  31   const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override;
  32
  33 protected:
  34
  35   void low_arch_setup () override;
  36
  37   bool low_cannot_fetch_register (int regno) override;
  38
  39   bool low_cannot_store_register (int regno) override;
  40
  41   bool low_supports_breakpoints () override;
  42
  43   CORE_ADDR low_get_pc (regcache *regcache) override;
  44
  45   void low_set_pc (regcache *regcache, CORE_ADDR newpc) override;
  46
  47   bool low_breakpoint_at (CORE_ADDR pc) override;
  48 };
  49
  50 /* The singleton target ops object.  */
  51
  52 static crisv32_target the_crisv32_target;
  53
  54 bool
  55 crisv32_target::low_cannot_fetch_register (int regno)
  56 {
  57   gdb_assert_not_reached ("linux target op low_cannot_fetch_register "
  58                           "is not implemented by the target");
  59 }
  60
  61 bool
  62 crisv32_target::low_cannot_store_register (int regno)
  63 {
  64   gdb_assert_not_reached ("linux target op low_cannot_store_register "
  65                           "is not implemented by the target");
  66 }
  67
  68 bool
  69 crisv32_target::low_supports_breakpoints ()
  70 {
  71   return true;
  72 }
  73
  74 CORE_ADDR
  75 crisv32_target::low_get_pc (regcache *regcache)
  76 {
  77   return linux_get_pc_32bit (regcache);
  78 }
  79
  80 void
  81 crisv32_target::low_set_pc (regcache *regcache, CORE_ADDR pc)
  82 {
  83   linux_set_pc_32bit (regcache, pc);
  84 }
  85
  86 /* Defined in auto-generated file reg-crisv32.c.  */
  87 void init_registers_crisv32 (void);
  88 extern const struct target_desc *tdesc_crisv32;
  89
  90 /* CRISv32 */
  91 #define cris_num_regs 49
  92
  93 #ifndef PTRACE_GET_THREAD_AREA
  94 #define PTRACE_GET_THREAD_AREA 25
  95 #endif
  96
  97 /* Note: Ignoring USP (having the stack pointer in two locations causes trouble
  98    without any significant gain).  */
  99
 100 /* Locations need to match <include/asm/arch/ptrace.h>.  */
 101 static int cris_regmap[] = {
 102   1*4, 2*4, 3*4, 4*4,
 103   5*4, 6*4, 7*4, 8*4,
 104   9*4, 10*4, 11*4, 12*4,
 105   13*4, 14*4, 24*4, 15*4,
 106
 107   -1, -1, -1, 16*4,
 108   -1, 22*4, 23*4, 17*4,
 109   -1, -1, 21*4, 20*4,
 110   -1, 19*4, -1, 18*4,
 111
 112   25*4,
 113
 114   26*4, -1,   -1,   29*4,
 115   30*4, 31*4, 32*4, 33*4,
 116   34*4, 35*4, 36*4, 37*4,
 117   38*4, 39*4, 40*4, -1
 118
 119 };
 120
 121 static const unsigned short cris_breakpoint = 0xe938;
 122 #define cris_breakpoint_len 2
 123
 124 /* Implementation of target ops method "sw_breakpoint_from_kind".  */
 125
 126 const gdb_byte *
 127 crisv32_target::sw_breakpoint_from_kind (int kind, int *size)
 128 {
 129   *size = cris_breakpoint_len;
 130   return (const gdb_byte *) &cris_breakpoint;
 131 }
 132
 133 bool
 134 crisv32_target::low_breakpoint_at (CORE_ADDR where)
 135 {
 136   unsigned short insn;
 137
 138   read_memory (where, (unsigned char *) &insn, cris_breakpoint_len);
 139   if (insn == cris_breakpoint)
 140     return true;
 141
 142   /* If necessary, recognize more trap instructions here.  GDB only uses the
 143      one.  */
 144   return false;
 145 }
 146
 147 static void
 148 cris_write_data_breakpoint (struct regcache *regcache,
 149                             int bp, unsigned long start, unsigned long end)
 150 {
 151   switch (bp)
 152     {
 153     case 0:
 154       supply_register_by_name (regcache, "s3", &start);
 155       supply_register_by_name (regcache, "s4", &end);
 156       break;
 157     case 1:
 158       supply_register_by_name (regcache, "s5", &start);
 159       supply_register_by_name (regcache, "s6", &end);
 160       break;
 161     case 2:
 162       supply_register_by_name (regcache, "s7", &start);
 163       supply_register_by_name (regcache, "s8", &end);
 164       break;
 165     case 3:
 166       supply_register_by_name (regcache, "s9", &start);
 167       supply_register_by_name (regcache, "s10", &end);
 168       break;
 169     case 4:
 170       supply_register_by_name (regcache, "s11", &start);
 171       supply_register_by_name (regcache, "s12", &end);
 172       break;
 173     case 5:
 174       supply_register_by_name (regcache, "s13", &start);
 175       supply_register_by_name (regcache, "s14", &end);
 176       break;
 177     }
 178 }
 179
 180 static int
 181 cris_supports_z_point_type (char z_type)
 182 {
 183   switch (z_type)
 184     {
 185     case Z_PACKET_WRITE_WP:
 186     case Z_PACKET_READ_WP:
 187     case Z_PACKET_ACCESS_WP:
 188       return 1;
 189     default:
 190       return 0;
 191     }
 192 }
 193
 194 static int
 195 cris_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
 196                    int len, struct raw_breakpoint *bp)
 197 {
 198   int bp;
 199   unsigned long bp_ctrl;
 200   unsigned long start, end;
 201   unsigned long ccs;
 202   struct regcache *regcache;
 203
 204   regcache = get_thread_regcache (current_thread, 1);
 205
 206   /* Read watchpoints are set as access watchpoints, because of GDB's
 207      inability to deal with pure read watchpoints.  */
 208   if (type == raw_bkpt_type_read_wp)
 209     type = raw_bkpt_type_access_wp;
 210
 211   /* Get the configuration register.  */
 212   collect_register_by_name (regcache, "s0", &bp_ctrl);
 213
 214   /* The watchpoint allocation scheme is the simplest possible.
 215      For example, if a region is watched for read and
 216      a write watch is requested, a new watchpoint will
 217      be used.  Also, if a watch for a region that is already
 218      covered by one or more existing watchpoints, a new
 219      watchpoint will be used.  */
 220
 221   /* First, find a free data watchpoint.  */
 222   for (bp = 0; bp < 6; bp++)
 223     {
 224       /* Each data watchpoint's control registers occupy 2 bits
 225          (hence the 3), starting at bit 2 for D0 (hence the 2)
 226          with 4 bits between for each watchpoint (yes, the 4).  */
 227       if (!(bp_ctrl & (0x3 << (2 + (bp * 4)))))
 228         break;
 229     }
 230
 231   if (bp > 5)
 232     {
 233       /* We're out of watchpoints.  */
 234       return -1;
 235     }
 236
 237   /* Configure the control register first.  */
 238   if (type == raw_bkpt_type_read_wp || type == raw_bkpt_type_access_wp)
 239     {
 240       /* Trigger on read.  */
 241       bp_ctrl |= (1 << (2 + bp * 4));
 242     }
 243   if (type == raw_bkpt_type_write_wp || type == raw_bkpt_type_access_wp)
 244     {
 245       /* Trigger on write.  */
 246       bp_ctrl |= (2 << (2 + bp * 4));
 247     }
 248
 249   /* Setup the configuration register.  */
 250   supply_register_by_name (regcache, "s0", &bp_ctrl);
 251
 252   /* Setup the range.  */
 253   start = addr;
 254   end = addr + len - 1;
 255
 256   /* Configure the watchpoint register.  */
 257   cris_write_data_breakpoint (regcache, bp, start, end);
 258
 259   collect_register_by_name (regcache, "ccs", &ccs);
 260   /* Set the S1 flag to enable watchpoints.  */
 261   ccs |= (1 << 19);
 262   supply_register_by_name (regcache, "ccs", &ccs);
 263
 264   return 0;
 265 }
 266
 267 static int
 268 cris_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, int len,
 269                    struct raw_breakpoint *bp)
 270 {
 271   int bp;
 272   unsigned long bp_ctrl;
 273   unsigned long start, end;
 274   struct regcache *regcache;
 275   unsigned long bp_d_regs[12];
 276
 277   regcache = get_thread_regcache (current_thread, 1);
 278
 279   /* Read watchpoints are set as access watchpoints, because of GDB's
 280      inability to deal with pure read watchpoints.  */
 281   if (type == raw_bkpt_type_read_wp)
 282     type = raw_bkpt_type_access_wp;
 283
 284   /* Get the configuration register.  */
 285   collect_register_by_name (regcache, "s0", &bp_ctrl);
 286
 287   /* Try to find a watchpoint that is configured for the
 288      specified range, then check that read/write also matches.  */
 289
 290   /* Ugly pointer arithmetic, since I cannot rely on a
 291      single switch (addr) as there may be several watchpoints with
 292      the same start address for example.  */
 293
 294   /* Get all range registers to simplify search.  */
 295   collect_register_by_name (regcache, "s3", &bp_d_regs[0]);
 296   collect_register_by_name (regcache, "s4", &bp_d_regs[1]);
 297   collect_register_by_name (regcache, "s5", &bp_d_regs[2]);
 298   collect_register_by_name (regcache, "s6", &bp_d_regs[3]);
 299   collect_register_by_name (regcache, "s7", &bp_d_regs[4]);
 300   collect_register_by_name (regcache, "s8", &bp_d_regs[5]);
 301   collect_register_by_name (regcache, "s9", &bp_d_regs[6]);
 302   collect_register_by_name (regcache, "s10", &bp_d_regs[7]);
 303   collect_register_by_name (regcache, "s11", &bp_d_regs[8]);
 304   collect_register_by_name (regcache, "s12", &bp_d_regs[9]);
 305   collect_register_by_name (regcache, "s13", &bp_d_regs[10]);
 306   collect_register_by_name (regcache, "s14", &bp_d_regs[11]);
 307
 308   for (bp = 0; bp < 6; bp++)
 309     {
 310       if (bp_d_regs[bp * 2] == addr
 311           && bp_d_regs[bp * 2 + 1] == (addr + len - 1)) {
 312         /* Matching range.  */
 313         int bitpos = 2 + bp * 4;
 314         int rw_bits;
 315
 316         /* Read/write bits for this BP.  */
 317         rw_bits = (bp_ctrl & (0x3 << bitpos)) >> bitpos;
 318
 319         if ((type == raw_bkpt_type_read_wp && rw_bits == 0x1)
 320             || (type == raw_bkpt_type_write_wp && rw_bits == 0x2)
 321             || (type == raw_bkpt_type_access_wp && rw_bits == 0x3))
 322           {
 323             /* Read/write matched.  */
 324             break;
 325           }
 326       }
 327     }
 328
 329   if (bp > 5)
 330     {
 331       /* No watchpoint matched.  */
 332       return -1;
 333     }
 334
 335   /* Found a matching watchpoint.  Now, deconfigure it by
 336      both disabling read/write in bp_ctrl and zeroing its
 337      start/end addresses.  */
 338   bp_ctrl &= ~(3 << (2 + (bp * 4)));
 339   /* Setup the configuration register.  */
 340   supply_register_by_name (regcache, "s0", &bp_ctrl);
 341
 342   start = end = 0;
 343   /* Configure the watchpoint register.  */
 344   cris_write_data_breakpoint (regcache, bp, start, end);
 345
 346   /* Note that we don't clear the S1 flag here.  It's done when continuing.  */
 347   return 0;
 348 }
 349
 350 static int
 351 cris_stopped_by_watchpoint (void)
 352 {
 353   unsigned long exs;
 354   struct regcache *regcache = get_thread_regcache (current_thread, 1);
 355
 356   collect_register_by_name (regcache, "exs", &exs);
 357
 358   return (((exs & 0xff00) >> 8) == 0xc);
 359 }
 360
 361 static CORE_ADDR
 362 cris_stopped_data_address (void)
 363 {
 364   unsigned long eda;
 365   struct regcache *regcache = get_thread_regcache (current_thread, 1);
 366
 367   collect_register_by_name (regcache, "eda", &eda);
 368
 369   /* FIXME: Possibly adjust to match watched range.  */
 370   return eda;
 371 }
 372
 373 ps_err_e
 374 ps_get_thread_area (struct ps_prochandle *ph,
 375                     lwpid_t lwpid, int idx, void **base)
 376 {
 377   if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
 378     return PS_ERR;
 379
 380   /* IDX is the bias from the thread pointer to the beginning of the
 381      thread descriptor.  It has to be subtracted due to implementation
 382      quirks in libthread_db.  */
 383   *base = (void *) ((char *) *base - idx);
 384   return PS_OK;
 385 }
 386
 387 static void
 388 cris_fill_gregset (struct regcache *regcache, void *buf)
 389 {
 390   int i;
 391
 392   for (i = 0; i < cris_num_regs; i++)
 393     {
 394       if (cris_regmap[i] != -1)
 395         collect_register (regcache, i, ((char *) buf) + cris_regmap[i]);
 396     }
 397 }
 398
 399 static void
 400 cris_store_gregset (struct regcache *regcache, const void *buf)
 401 {
 402   int i;
 403
 404   for (i = 0; i < cris_num_regs; i++)
 405     {
 406       if (cris_regmap[i] != -1)
 407         supply_register (regcache, i, ((char *) buf) + cris_regmap[i]);
 408     }
 409 }
 410
 411 void
 412 crisv32_target::low_arch_setup ()
 413 {
 414   current_process ()->tdesc = tdesc_crisv32;
 415 }
 416
 417 /* Support for hardware single step.  */
 418
 419 static int
 420 cris_supports_hardware_single_step (void)
 421 {
 422   return 1;
 423 }
 424
 425 static struct regset_info cris_regsets[] = {
 426   { PTRACE_GETREGS, PTRACE_SETREGS, 0, cris_num_regs * 4,
 427     GENERAL_REGS, cris_fill_gregset, cris_store_gregset },
 428   NULL_REGSET
 429 };
 430
 431
 432 static struct regsets_info cris_regsets_info =
 433   {
 434     cris_regsets, /* regsets */
 435     0, /* num_regsets */
 436     NULL, /* disabled_regsets */
 437   };
 438
 439 static struct usrregs_info cris_usrregs_info =
 440   {
 441     cris_num_regs,
 442     cris_regmap,
 443   };
 444
 445 static struct regs_info myregs_info =
 446   {
 447     NULL, /* regset_bitmap */
 448     &cris_usrregs_info,
 449     &cris_regsets_info
 450   };
 451
 452 const regs_info *
 453 crisv32_target::get_regs_info ()
 454 {
 455   return &myregs_info;
 456 }
 457
 458 struct linux_target_ops the_low_target = {
 459   cris_supports_z_point_type,
 460   cris_insert_point,
 461   cris_remove_point,
 462   cris_stopped_by_watchpoint,
 463   cris_stopped_data_address,
 464   NULL, /* collect_ptrace_register */
 465   NULL, /* supply_ptrace_register */
 466   NULL, /* siginfo_fixup */
 467   NULL, /* new_process */
 468   NULL, /* delete_process */
 469   NULL, /* new_thread */
 470   NULL, /* delete_thread */
 471   NULL, /* new_fork */
 472   NULL, /* prepare_to_resume */
 473   NULL, /* process_qsupported */
 474   NULL, /* supports_tracepoints */
 475   NULL, /* get_thread_area */
 476   NULL, /* install_fast_tracepoint_jump_pad */
 477   NULL, /* emit_ops */
 478   NULL, /* get_min_fast_tracepoint_insn_len */
 479   NULL, /* supports_range_stepping */
 480   cris_supports_hardware_single_step,
 481 };
 482
 483 /* The linux target ops object.  */
 484
 485 linux_process_target *the_linux_target = &the_crisv32_target;
 486
 487 void
 488 initialize_low_arch (void)
 489 {
 490   init_registers_crisv32 ();
 491
 492   initialize_regsets_info (&cris_regsets_info);
 493 }