1 /* GNU/Linux/CRIS specific low level interface, for the remote server for GDB.
2 Copyright (C) 1995-2020 Free Software Foundation, Inc.
4 This file is part of GDB.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 #include "linux-low.h"
21 #include "nat/gdb_ptrace.h"
23 /* Linux target op definitions for the CRIS architecture. */
25 class crisv32_target
: public linux_process_target
29 const regs_info
*get_regs_info () override
;
31 const gdb_byte
*sw_breakpoint_from_kind (int kind
, int *size
) override
;
35 void low_arch_setup () override
;
37 bool low_cannot_fetch_register (int regno
) override
;
39 bool low_cannot_store_register (int regno
) override
;
41 bool low_supports_breakpoints () override
;
43 CORE_ADDR
low_get_pc (regcache
*regcache
) override
;
45 void low_set_pc (regcache
*regcache
, CORE_ADDR newpc
) override
;
48 /* The singleton target ops object. */
50 static crisv32_target the_crisv32_target
;
53 crisv32_target::low_cannot_fetch_register (int regno
)
55 gdb_assert_not_reached ("linux target op low_cannot_fetch_register "
56 "is not implemented by the target");
60 crisv32_target::low_cannot_store_register (int regno
)
62 gdb_assert_not_reached ("linux target op low_cannot_store_register "
63 "is not implemented by the target");
67 crisv32_target::low_supports_breakpoints ()
73 crisv32_target::low_get_pc (regcache
*regcache
)
75 return linux_get_pc_32bit (regcache
);
79 crisv32_target::low_set_pc (regcache
*regcache
, CORE_ADDR pc
)
81 linux_set_pc_32bit (regcache
, pc
);
84 /* Defined in auto-generated file reg-crisv32.c. */
85 void init_registers_crisv32 (void);
86 extern const struct target_desc
*tdesc_crisv32
;
89 #define cris_num_regs 49
91 #ifndef PTRACE_GET_THREAD_AREA
92 #define PTRACE_GET_THREAD_AREA 25
95 /* Note: Ignoring USP (having the stack pointer in two locations causes trouble
96 without any significant gain). */
98 /* Locations need to match <include/asm/arch/ptrace.h>. */
99 static int cris_regmap
[] = {
102 9*4, 10*4, 11*4, 12*4,
103 13*4, 14*4, 24*4, 15*4,
106 -1, 22*4, 23*4, 17*4,
113 30*4, 31*4, 32*4, 33*4,
114 34*4, 35*4, 36*4, 37*4,
119 static const unsigned short cris_breakpoint
= 0xe938;
120 #define cris_breakpoint_len 2
122 /* Implementation of target ops method "sw_breakpoint_from_kind". */
125 crisv32_target::sw_breakpoint_from_kind (int kind
, int *size
)
127 *size
= cris_breakpoint_len
;
128 return (const gdb_byte
*) &cris_breakpoint
;
132 cris_breakpoint_at (CORE_ADDR where
)
136 the_target
->read_memory (where
, (unsigned char *) &insn
,
137 cris_breakpoint_len
);
138 if (insn
== cris_breakpoint
)
141 /* If necessary, recognize more trap instructions here. GDB only uses the
147 cris_write_data_breakpoint (struct regcache
*regcache
,
148 int bp
, unsigned long start
, unsigned long end
)
153 supply_register_by_name (regcache
, "s3", &start
);
154 supply_register_by_name (regcache
, "s4", &end
);
157 supply_register_by_name (regcache
, "s5", &start
);
158 supply_register_by_name (regcache
, "s6", &end
);
161 supply_register_by_name (regcache
, "s7", &start
);
162 supply_register_by_name (regcache
, "s8", &end
);
165 supply_register_by_name (regcache
, "s9", &start
);
166 supply_register_by_name (regcache
, "s10", &end
);
169 supply_register_by_name (regcache
, "s11", &start
);
170 supply_register_by_name (regcache
, "s12", &end
);
173 supply_register_by_name (regcache
, "s13", &start
);
174 supply_register_by_name (regcache
, "s14", &end
);
180 cris_supports_z_point_type (char z_type
)
184 case Z_PACKET_WRITE_WP
:
185 case Z_PACKET_READ_WP
:
186 case Z_PACKET_ACCESS_WP
:
194 cris_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
195 int len
, struct raw_breakpoint
*bp
)
198 unsigned long bp_ctrl
;
199 unsigned long start
, end
;
201 struct regcache
*regcache
;
203 regcache
= get_thread_regcache (current_thread
, 1);
205 /* Read watchpoints are set as access watchpoints, because of GDB's
206 inability to deal with pure read watchpoints. */
207 if (type
== raw_bkpt_type_read_wp
)
208 type
= raw_bkpt_type_access_wp
;
210 /* Get the configuration register. */
211 collect_register_by_name (regcache
, "s0", &bp_ctrl
);
213 /* The watchpoint allocation scheme is the simplest possible.
214 For example, if a region is watched for read and
215 a write watch is requested, a new watchpoint will
216 be used. Also, if a watch for a region that is already
217 covered by one or more existing watchpoints, a new
218 watchpoint will be used. */
220 /* First, find a free data watchpoint. */
221 for (bp
= 0; bp
< 6; bp
++)
223 /* Each data watchpoint's control registers occupy 2 bits
224 (hence the 3), starting at bit 2 for D0 (hence the 2)
225 with 4 bits between for each watchpoint (yes, the 4). */
226 if (!(bp_ctrl
& (0x3 << (2 + (bp
* 4)))))
232 /* We're out of watchpoints. */
236 /* Configure the control register first. */
237 if (type
== raw_bkpt_type_read_wp
|| type
== raw_bkpt_type_access_wp
)
239 /* Trigger on read. */
240 bp_ctrl
|= (1 << (2 + bp
* 4));
242 if (type
== raw_bkpt_type_write_wp
|| type
== raw_bkpt_type_access_wp
)
244 /* Trigger on write. */
245 bp_ctrl
|= (2 << (2 + bp
* 4));
248 /* Setup the configuration register. */
249 supply_register_by_name (regcache
, "s0", &bp_ctrl
);
251 /* Setup the range. */
253 end
= addr
+ len
- 1;
255 /* Configure the watchpoint register. */
256 cris_write_data_breakpoint (regcache
, bp
, start
, end
);
258 collect_register_by_name (regcache
, "ccs", &ccs
);
259 /* Set the S1 flag to enable watchpoints. */
261 supply_register_by_name (regcache
, "ccs", &ccs
);
267 cris_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
, int len
,
268 struct raw_breakpoint
*bp
)
271 unsigned long bp_ctrl
;
272 unsigned long start
, end
;
273 struct regcache
*regcache
;
274 unsigned long bp_d_regs
[12];
276 regcache
= get_thread_regcache (current_thread
, 1);
278 /* Read watchpoints are set as access watchpoints, because of GDB's
279 inability to deal with pure read watchpoints. */
280 if (type
== raw_bkpt_type_read_wp
)
281 type
= raw_bkpt_type_access_wp
;
283 /* Get the configuration register. */
284 collect_register_by_name (regcache
, "s0", &bp_ctrl
);
286 /* Try to find a watchpoint that is configured for the
287 specified range, then check that read/write also matches. */
289 /* Ugly pointer arithmetic, since I cannot rely on a
290 single switch (addr) as there may be several watchpoints with
291 the same start address for example. */
293 /* Get all range registers to simplify search. */
294 collect_register_by_name (regcache
, "s3", &bp_d_regs
[0]);
295 collect_register_by_name (regcache
, "s4", &bp_d_regs
[1]);
296 collect_register_by_name (regcache
, "s5", &bp_d_regs
[2]);
297 collect_register_by_name (regcache
, "s6", &bp_d_regs
[3]);
298 collect_register_by_name (regcache
, "s7", &bp_d_regs
[4]);
299 collect_register_by_name (regcache
, "s8", &bp_d_regs
[5]);
300 collect_register_by_name (regcache
, "s9", &bp_d_regs
[6]);
301 collect_register_by_name (regcache
, "s10", &bp_d_regs
[7]);
302 collect_register_by_name (regcache
, "s11", &bp_d_regs
[8]);
303 collect_register_by_name (regcache
, "s12", &bp_d_regs
[9]);
304 collect_register_by_name (regcache
, "s13", &bp_d_regs
[10]);
305 collect_register_by_name (regcache
, "s14", &bp_d_regs
[11]);
307 for (bp
= 0; bp
< 6; bp
++)
309 if (bp_d_regs
[bp
* 2] == addr
310 && bp_d_regs
[bp
* 2 + 1] == (addr
+ len
- 1)) {
311 /* Matching range. */
312 int bitpos
= 2 + bp
* 4;
315 /* Read/write bits for this BP. */
316 rw_bits
= (bp_ctrl
& (0x3 << bitpos
)) >> bitpos
;
318 if ((type
== raw_bkpt_type_read_wp
&& rw_bits
== 0x1)
319 || (type
== raw_bkpt_type_write_wp
&& rw_bits
== 0x2)
320 || (type
== raw_bkpt_type_access_wp
&& rw_bits
== 0x3))
322 /* Read/write matched. */
330 /* No watchpoint matched. */
334 /* Found a matching watchpoint. Now, deconfigure it by
335 both disabling read/write in bp_ctrl and zeroing its
336 start/end addresses. */
337 bp_ctrl
&= ~(3 << (2 + (bp
* 4)));
338 /* Setup the configuration register. */
339 supply_register_by_name (regcache
, "s0", &bp_ctrl
);
342 /* Configure the watchpoint register. */
343 cris_write_data_breakpoint (regcache
, bp
, start
, end
);
345 /* Note that we don't clear the S1 flag here. It's done when continuing. */
350 cris_stopped_by_watchpoint (void)
353 struct regcache
*regcache
= get_thread_regcache (current_thread
, 1);
355 collect_register_by_name (regcache
, "exs", &exs
);
357 return (((exs
& 0xff00) >> 8) == 0xc);
361 cris_stopped_data_address (void)
364 struct regcache
*regcache
= get_thread_regcache (current_thread
, 1);
366 collect_register_by_name (regcache
, "eda", &eda
);
368 /* FIXME: Possibly adjust to match watched range. */
373 ps_get_thread_area (struct ps_prochandle
*ph
,
374 lwpid_t lwpid
, int idx
, void **base
)
376 if (ptrace (PTRACE_GET_THREAD_AREA
, lwpid
, NULL
, base
) != 0)
379 /* IDX is the bias from the thread pointer to the beginning of the
380 thread descriptor. It has to be subtracted due to implementation
381 quirks in libthread_db. */
382 *base
= (void *) ((char *) *base
- idx
);
387 cris_fill_gregset (struct regcache
*regcache
, void *buf
)
391 for (i
= 0; i
< cris_num_regs
; i
++)
393 if (cris_regmap
[i
] != -1)
394 collect_register (regcache
, i
, ((char *) buf
) + cris_regmap
[i
]);
399 cris_store_gregset (struct regcache
*regcache
, const void *buf
)
403 for (i
= 0; i
< cris_num_regs
; i
++)
405 if (cris_regmap
[i
] != -1)
406 supply_register (regcache
, i
, ((char *) buf
) + cris_regmap
[i
]);
411 crisv32_target::low_arch_setup ()
413 current_process ()->tdesc
= tdesc_crisv32
;
416 /* Support for hardware single step. */
419 cris_supports_hardware_single_step (void)
424 static struct regset_info cris_regsets
[] = {
425 { PTRACE_GETREGS
, PTRACE_SETREGS
, 0, cris_num_regs
* 4,
426 GENERAL_REGS
, cris_fill_gregset
, cris_store_gregset
},
431 static struct regsets_info cris_regsets_info
=
433 cris_regsets
, /* regsets */
435 NULL
, /* disabled_regsets */
438 static struct usrregs_info cris_usrregs_info
=
444 static struct regs_info myregs_info
=
446 NULL
, /* regset_bitmap */
452 crisv32_target::get_regs_info ()
457 struct linux_target_ops the_low_target
= {
458 NULL
, /* get_next_pcs */
461 cris_supports_z_point_type
,
464 cris_stopped_by_watchpoint
,
465 cris_stopped_data_address
,
466 NULL
, /* collect_ptrace_register */
467 NULL
, /* supply_ptrace_register */
468 NULL
, /* siginfo_fixup */
469 NULL
, /* new_process */
470 NULL
, /* delete_process */
471 NULL
, /* new_thread */
472 NULL
, /* delete_thread */
474 NULL
, /* prepare_to_resume */
475 NULL
, /* process_qsupported */
476 NULL
, /* supports_tracepoints */
477 NULL
, /* get_thread_area */
478 NULL
, /* install_fast_tracepoint_jump_pad */
480 NULL
, /* get_min_fast_tracepoint_insn_len */
481 NULL
, /* supports_range_stepping */
482 cris_supports_hardware_single_step
,
485 /* The linux target ops object. */
487 linux_process_target
*the_linux_target
= &the_crisv32_target
;
490 initialize_low_arch (void)
492 init_registers_crisv32 ();
494 initialize_regsets_info (&cris_regsets_info
);