gdbserver/linux-mips-low.cc

   1 /* GNU/Linux/MIPS specific low level interface, for the remote server for GDB.
   2    Copyright (C) 1995-2020 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #include "server.h"
  20 #include "linux-low.h"
  21
  22 #include "nat/gdb_ptrace.h"
  23 #include <endian.h>
  24
  25 #include "nat/mips-linux-watch.h"
  26 #include "gdb_proc_service.h"
  27
  28 /* Linux target op definitions for the MIPS architecture.  */
  29
  30 class mips_target : public linux_process_target
  31 {
  32 public:
  33
  34   const regs_info *get_regs_info () override;
  35
  36   const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override;
  37
  38   bool supports_z_point_type (char z_type) override;
  39
  40 protected:
  41
  42   void low_arch_setup () override;
  43
  44   bool low_cannot_fetch_register (int regno) override;
  45
  46   bool low_cannot_store_register (int regno) override;
  47
  48   bool low_fetch_register (regcache *regcache, int regno) override;
  49
  50   bool low_supports_breakpoints () override;
  51
  52   CORE_ADDR low_get_pc (regcache *regcache) override;
  53
  54   void low_set_pc (regcache *regcache, CORE_ADDR newpc) override;
  55
  56   bool low_breakpoint_at (CORE_ADDR pc) override;
  57
  58   int low_insert_point (raw_bkpt_type type, CORE_ADDR addr,
  59                         int size, raw_breakpoint *bp) override;
  60
  61   int low_remove_point (raw_bkpt_type type, CORE_ADDR addr,
  62                         int size, raw_breakpoint *bp) override;
  63
  64   bool low_stopped_by_watchpoint () override;
  65
  66   CORE_ADDR low_stopped_data_address () override;
  67
  68   void low_collect_ptrace_register (regcache *regcache, int regno,
  69                                     char *buf) override;
  70
  71   void low_supply_ptrace_register (regcache *regcache, int regno,
  72                                    const char *buf) override;
  73 };
  74
  75 /* The singleton target ops object.  */
  76
  77 static mips_target the_mips_target;
  78
  79 /* Defined in auto-generated file mips-linux.c.  */
  80 void init_registers_mips_linux (void);
  81 extern const struct target_desc *tdesc_mips_linux;
  82
  83 /* Defined in auto-generated file mips-dsp-linux.c.  */
  84 void init_registers_mips_dsp_linux (void);
  85 extern const struct target_desc *tdesc_mips_dsp_linux;
  86
  87 /* Defined in auto-generated file mips64-linux.c.  */
  88 void init_registers_mips64_linux (void);
  89 extern const struct target_desc *tdesc_mips64_linux;
  90
  91 /* Defined in auto-generated file mips64-dsp-linux.c.  */
  92 void init_registers_mips64_dsp_linux (void);
  93 extern const struct target_desc *tdesc_mips64_dsp_linux;
  94
  95 #ifdef __mips64
  96 #define tdesc_mips_linux tdesc_mips64_linux
  97 #define tdesc_mips_dsp_linux tdesc_mips64_dsp_linux
  98 #endif
  99
 100 #ifndef PTRACE_GET_THREAD_AREA
 101 #define PTRACE_GET_THREAD_AREA 25
 102 #endif
 103
 104 #ifdef HAVE_SYS_REG_H
 105 #include <sys/reg.h>
 106 #endif
 107
 108 #define mips_num_regs 73
 109 #define mips_dsp_num_regs 80
 110
 111 #include <asm/ptrace.h>
 112
 113 #ifndef DSP_BASE
 114 #define DSP_BASE 71
 115 #define DSP_CONTROL 77
 116 #endif
 117
 118 union mips_register
 119 {
 120   unsigned char buf[8];
 121
 122   /* Deliberately signed, for proper sign extension.  */
 123   int reg32;
 124   long long reg64;
 125 };
 126
 127 /* Return the ptrace ``address'' of register REGNO. */
 128
 129 #define mips_base_regs                                                  \
 130   -1,  1,  2,  3,  4,  5,  6,  7,                                       \
 131   8,  9,  10, 11, 12, 13, 14, 15,                                       \
 132   16, 17, 18, 19, 20, 21, 22, 23,                                       \
 133   24, 25, 26, 27, 28, 29, 30, 31,                                       \
 134                                                                         \
 135   -1, MMLO, MMHI, BADVADDR, CAUSE, PC,                                  \
 136                                                                         \
 137   FPR_BASE,      FPR_BASE + 1,  FPR_BASE + 2,  FPR_BASE + 3,            \
 138   FPR_BASE + 4,  FPR_BASE + 5,  FPR_BASE + 6,  FPR_BASE + 7,            \
 139   FPR_BASE + 8,  FPR_BASE + 9,  FPR_BASE + 10, FPR_BASE + 11,           \
 140   FPR_BASE + 12, FPR_BASE + 13, FPR_BASE + 14, FPR_BASE + 15,           \
 141   FPR_BASE + 16, FPR_BASE + 17, FPR_BASE + 18, FPR_BASE + 19,           \
 142   FPR_BASE + 20, FPR_BASE + 21, FPR_BASE + 22, FPR_BASE + 23,           \
 143   FPR_BASE + 24, FPR_BASE + 25, FPR_BASE + 26, FPR_BASE + 27,           \
 144   FPR_BASE + 28, FPR_BASE + 29, FPR_BASE + 30, FPR_BASE + 31,           \
 145   FPC_CSR, FPC_EIR
 146
 147 #define mips_dsp_regs                                                   \
 148   DSP_BASE,      DSP_BASE + 1,  DSP_BASE + 2,  DSP_BASE + 3,            \
 149   DSP_BASE + 4,  DSP_BASE + 5,                                          \
 150   DSP_CONTROL
 151
 152 static int mips_regmap[mips_num_regs] = {
 153   mips_base_regs,
 154   0
 155 };
 156
 157 static int mips_dsp_regmap[mips_dsp_num_regs] = {
 158   mips_base_regs,
 159   mips_dsp_regs,
 160   0
 161 };
 162
 163 /* DSP registers are not in any regset and can only be accessed
 164    individually.  */
 165
 166 static unsigned char mips_dsp_regset_bitmap[(mips_dsp_num_regs + 7) / 8] = {
 167   0xfe, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0x80
 168 };
 169
 170 static int have_dsp = -1;
 171
 172 /* Try peeking at an arbitrarily chosen DSP register and pick the available
 173    user register set accordingly.  */
 174
 175 static const struct target_desc *
 176 mips_read_description (void)
 177 {
 178   if (have_dsp < 0)
 179     {
 180       int pid = lwpid_of (current_thread);
 181
 182       errno = 0;
 183       ptrace (PTRACE_PEEKUSER, pid, DSP_CONTROL, 0);
 184       switch (errno)
 185         {
 186         case 0:
 187           have_dsp = 1;
 188           break;
 189         case EIO:
 190           have_dsp = 0;
 191           break;
 192         default:
 193           perror_with_name ("ptrace");
 194           break;
 195         }
 196     }
 197
 198   return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux;
 199 }
 200
 201 void
 202 mips_target::low_arch_setup ()
 203 {
 204   current_process ()->tdesc = mips_read_description ();
 205 }
 206
 207 /* Per-process arch-specific data we want to keep.  */
 208
 209 struct arch_process_info
 210 {
 211   /* -1 if the kernel and/or CPU do not support watch registers.
 212       1 if watch_readback is valid and we can read style, num_valid
 213         and the masks.
 214       0 if we need to read the watch_readback.  */
 215
 216   int watch_readback_valid;
 217
 218   /* Cached watch register read values.  */
 219
 220   struct pt_watch_regs watch_readback;
 221
 222   /* Current watchpoint requests for this process.  */
 223
 224   struct mips_watchpoint *current_watches;
 225
 226   /* The current set of watch register values for writing the
 227      registers.  */
 228
 229   struct pt_watch_regs watch_mirror;
 230 };
 231
 232 /* Per-thread arch-specific data we want to keep.  */
 233
 234 struct arch_lwp_info
 235 {
 236   /* Non-zero if our copy differs from what's recorded in the thread.  */
 237   int watch_registers_changed;
 238 };
 239
 240 /* From mips-linux-nat.c.  */
 241
 242 /* Pseudo registers can not be read.  ptrace does not provide a way to
 243    read (or set) PS_REGNUM, and there's no point in reading or setting
 244    ZERO_REGNUM, it's always 0.  We also can not set BADVADDR, CAUSE,
 245    or FCRIR via ptrace().  */
 246
 247 bool
 248 mips_target::low_cannot_fetch_register (int regno)
 249 {
 250   const struct target_desc *tdesc;
 251
 252   if (get_regs_info ()->usrregs->regmap[regno] == -1)
 253     return true;
 254
 255   tdesc = current_process ()->tdesc;
 256
 257   /* On n32 we can't access 64-bit registers via PTRACE_PEEKUSR.  */
 258   if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE))
 259     return true;
 260
 261   if (find_regno (tdesc, "r0") == regno)
 262     return true;
 263
 264   return false;
 265 }
 266
 267 bool
 268 mips_target::low_cannot_store_register (int regno)
 269 {
 270   const struct target_desc *tdesc;
 271
 272   if (get_regs_info ()->usrregs->regmap[regno] == -1)
 273     return true;
 274
 275   tdesc = current_process ()->tdesc;
 276
 277   /* On n32 we can't access 64-bit registers via PTRACE_POKEUSR.  */
 278   if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE))
 279     return true;
 280
 281   if (find_regno (tdesc, "r0") == regno)
 282     return true;
 283
 284   if (find_regno (tdesc, "cause") == regno)
 285     return true;
 286
 287   if (find_regno (tdesc, "badvaddr") == regno)
 288     return true;
 289
 290   if (find_regno (tdesc, "fir") == regno)
 291     return true;
 292
 293   return false;
 294 }
 295
 296 bool
 297 mips_target::low_fetch_register (regcache *regcache, int regno)
 298 {
 299   const struct target_desc *tdesc = current_process ()->tdesc;
 300
 301   if (find_regno (tdesc, "r0") == regno)
 302     {
 303       supply_register_zeroed (regcache, regno);
 304       return true;
 305     }
 306
 307   return false;
 308 }
 309
 310 bool
 311 mips_target::low_supports_breakpoints ()
 312 {
 313   return true;
 314 }
 315
 316 CORE_ADDR
 317 mips_target::low_get_pc (regcache *regcache)
 318 {
 319   union mips_register pc;
 320   collect_register_by_name (regcache, "pc", pc.buf);
 321   return register_size (regcache->tdesc, 0) == 4 ? pc.reg32 : pc.reg64;
 322 }
 323
 324 void
 325 mips_target::low_set_pc (regcache *regcache, CORE_ADDR pc)
 326 {
 327   union mips_register newpc;
 328   if (register_size (regcache->tdesc, 0) == 4)
 329     newpc.reg32 = pc;
 330   else
 331     newpc.reg64 = pc;
 332
 333   supply_register_by_name (regcache, "pc", newpc.buf);
 334 }
 335
 336 /* Correct in either endianness.  */
 337 static const unsigned int mips_breakpoint = 0x0005000d;
 338 #define mips_breakpoint_len 4
 339
 340 /* Implementation of target ops method "sw_breakpoint_from_kind".  */
 341
 342 const gdb_byte *
 343 mips_target::sw_breakpoint_from_kind (int kind, int *size)
 344 {
 345   *size = mips_breakpoint_len;
 346   return (const gdb_byte *) &mips_breakpoint;
 347 }
 348
 349 bool
 350 mips_target::low_breakpoint_at (CORE_ADDR where)
 351 {
 352   unsigned int insn;
 353
 354   read_memory (where, (unsigned char *) &insn, 4);
 355   if (insn == mips_breakpoint)
 356     return true;
 357
 358   /* If necessary, recognize more trap instructions here.  GDB only uses the
 359      one.  */
 360   return false;
 361 }
 362
 363 /* Mark the watch registers of lwp, represented by ENTRY, as changed.  */
 364
 365 static void
 366 update_watch_registers_callback (thread_info *thread)
 367 {
 368   struct lwp_info *lwp = get_thread_lwp (thread);
 369
 370   /* The actual update is done later just before resuming the lwp,
 371      we just mark that the registers need updating.  */
 372   lwp->arch_private->watch_registers_changed = 1;
 373
 374   /* If the lwp isn't stopped, force it to momentarily pause, so
 375      we can update its watch registers.  */
 376   if (!lwp->stopped)
 377     linux_stop_lwp (lwp);
 378 }
 379
 380 /* This is the implementation of linux_target_ops method
 381    new_process.  */
 382
 383 static struct arch_process_info *
 384 mips_linux_new_process (void)
 385 {
 386   struct arch_process_info *info = XCNEW (struct arch_process_info);
 387
 388   return info;
 389 }
 390
 391 /* This is the implementation of linux_target_ops method
 392    delete_process.  */
 393
 394 static void
 395 mips_linux_delete_process (struct arch_process_info *info)
 396 {
 397   xfree (info);
 398 }
 399
 400 /* This is the implementation of linux_target_ops method new_thread.
 401    Mark the watch registers as changed, so the threads' copies will
 402    be updated.  */
 403
 404 static void
 405 mips_linux_new_thread (struct lwp_info *lwp)
 406 {
 407   struct arch_lwp_info *info = XCNEW (struct arch_lwp_info);
 408
 409   info->watch_registers_changed = 1;
 410
 411   lwp->arch_private = info;
 412 }
 413
 414 /* Function to call when a thread is being deleted.  */
 415
 416 static void
 417 mips_linux_delete_thread (struct arch_lwp_info *arch_lwp)
 418 {
 419   xfree (arch_lwp);
 420 }
 421
 422 /* Create a new mips_watchpoint and add it to the list.  */
 423
 424 static void
 425 mips_add_watchpoint (struct arch_process_info *priv, CORE_ADDR addr, int len,
 426                      enum target_hw_bp_type watch_type)
 427 {
 428   struct mips_watchpoint *new_watch;
 429   struct mips_watchpoint **pw;
 430
 431   new_watch = XNEW (struct mips_watchpoint);
 432   new_watch->addr = addr;
 433   new_watch->len = len;
 434   new_watch->type = watch_type;
 435   new_watch->next = NULL;
 436
 437   pw = &priv->current_watches;
 438   while (*pw != NULL)
 439     pw = &(*pw)->next;
 440   *pw = new_watch;
 441 }
 442
 443 /* Hook to call when a new fork is attached.  */
 444
 445 static void
 446 mips_linux_new_fork (struct process_info *parent,
 447                         struct process_info *child)
 448 {
 449   struct arch_process_info *parent_private;
 450   struct arch_process_info *child_private;
 451   struct mips_watchpoint *wp;
 452
 453   /* These are allocated by linux_add_process.  */
 454   gdb_assert (parent->priv != NULL
 455               && parent->priv->arch_private != NULL);
 456   gdb_assert (child->priv != NULL
 457               && child->priv->arch_private != NULL);
 458
 459   /* Linux kernel before 2.6.33 commit
 460      72f674d203cd230426437cdcf7dd6f681dad8b0d
 461      will inherit hardware debug registers from parent
 462      on fork/vfork/clone.  Newer Linux kernels create such tasks with
 463      zeroed debug registers.
 464
 465      GDB core assumes the child inherits the watchpoints/hw
 466      breakpoints of the parent, and will remove them all from the
 467      forked off process.  Copy the debug registers mirrors into the
 468      new process so that all breakpoints and watchpoints can be
 469      removed together.  The debug registers mirror will become zeroed
 470      in the end before detaching the forked off process, thus making
 471      this compatible with older Linux kernels too.  */
 472
 473   parent_private = parent->priv->arch_private;
 474   child_private = child->priv->arch_private;
 475
 476   child_private->watch_readback_valid = parent_private->watch_readback_valid;
 477   child_private->watch_readback = parent_private->watch_readback;
 478
 479   for (wp = parent_private->current_watches; wp != NULL; wp = wp->next)
 480     mips_add_watchpoint (child_private, wp->addr, wp->len, wp->type);
 481
 482   child_private->watch_mirror = parent_private->watch_mirror;
 483 }
 484 /* This is the implementation of linux_target_ops method
 485    prepare_to_resume.  If the watch regs have changed, update the
 486    thread's copies.  */
 487
 488 static void
 489 mips_linux_prepare_to_resume (struct lwp_info *lwp)
 490 {
 491   ptid_t ptid = ptid_of (get_lwp_thread (lwp));
 492   struct process_info *proc = find_process_pid (ptid.pid ());
 493   struct arch_process_info *priv = proc->priv->arch_private;
 494
 495   if (lwp->arch_private->watch_registers_changed)
 496     {
 497       /* Only update the watch registers if we have set or unset a
 498          watchpoint already.  */
 499       if (mips_linux_watch_get_num_valid (&priv->watch_mirror) > 0)
 500         {
 501           /* Write the mirrored watch register values.  */
 502           int tid = ptid.lwp ();
 503
 504           if (-1 == ptrace (PTRACE_SET_WATCH_REGS, tid,
 505                             &priv->watch_mirror, NULL))
 506             perror_with_name ("Couldn't write watch register");
 507         }
 508
 509       lwp->arch_private->watch_registers_changed = 0;
 510     }
 511 }
 512
 513 bool
 514 mips_target::supports_z_point_type (char z_type)
 515 {
 516   switch (z_type)
 517     {
 518     case Z_PACKET_WRITE_WP:
 519     case Z_PACKET_READ_WP:
 520     case Z_PACKET_ACCESS_WP:
 521       return true;
 522     default:
 523       return false;
 524     }
 525 }
 526
 527 /* This is the implementation of linux target ops method
 528    low_insert_point.  */
 529
 530 int
 531 mips_target::low_insert_point (raw_bkpt_type type, CORE_ADDR addr,
 532                                int len, raw_breakpoint *bp)
 533 {
 534   struct process_info *proc = current_process ();
 535   struct arch_process_info *priv = proc->priv->arch_private;
 536   struct pt_watch_regs regs;
 537   long lwpid;
 538   enum target_hw_bp_type watch_type;
 539   uint32_t irw;
 540
 541   lwpid = lwpid_of (current_thread);
 542   if (!mips_linux_read_watch_registers (lwpid,
 543                                         &priv->watch_readback,
 544                                         &priv->watch_readback_valid,
 545                                         0))
 546     return -1;
 547
 548   if (len <= 0)
 549     return -1;
 550
 551   regs = priv->watch_readback;
 552   /* Add the current watches.  */
 553   mips_linux_watch_populate_regs (priv->current_watches, &regs);
 554
 555   /* Now try to add the new watch.  */
 556   watch_type = raw_bkpt_type_to_target_hw_bp_type (type);
 557   irw = mips_linux_watch_type_to_irw (watch_type);
 558   if (!mips_linux_watch_try_one_watch (&regs, addr, len, irw))
 559     return -1;
 560
 561   /* It fit.  Stick it on the end of the list.  */
 562   mips_add_watchpoint (priv, addr, len, watch_type);
 563
 564   priv->watch_mirror = regs;
 565
 566   /* Only update the threads of this process.  */
 567   for_each_thread (proc->pid, update_watch_registers_callback);
 568
 569   return 0;
 570 }
 571
 572 /* This is the implementation of linux target ops method
 573    low_remove_point.  */
 574
 575 int
 576 mips_target::low_remove_point (raw_bkpt_type type, CORE_ADDR addr,
 577                                int len, raw_breakpoint *bp)
 578 {
 579   struct process_info *proc = current_process ();
 580   struct arch_process_info *priv = proc->priv->arch_private;
 581
 582   int deleted_one;
 583   enum target_hw_bp_type watch_type;
 584
 585   struct mips_watchpoint **pw;
 586   struct mips_watchpoint *w;
 587
 588   /* Search for a known watch that matches.  Then unlink and free it.  */
 589   watch_type = raw_bkpt_type_to_target_hw_bp_type (type);
 590   deleted_one = 0;
 591   pw = &priv->current_watches;
 592   while ((w = *pw))
 593     {
 594       if (w->addr == addr && w->len == len && w->type == watch_type)
 595         {
 596           *pw = w->next;
 597           free (w);
 598           deleted_one = 1;
 599           break;
 600         }
 601       pw = &(w->next);
 602     }
 603
 604   if (!deleted_one)
 605     return -1;  /* We don't know about it, fail doing nothing.  */
 606
 607   /* At this point watch_readback is known to be valid because we
 608      could not have added the watch without reading it.  */
 609   gdb_assert (priv->watch_readback_valid == 1);
 610
 611   priv->watch_mirror = priv->watch_readback;
 612   mips_linux_watch_populate_regs (priv->current_watches,
 613                                   &priv->watch_mirror);
 614
 615   /* Only update the threads of this process.  */
 616   for_each_thread (proc->pid, update_watch_registers_callback);
 617
 618   return 0;
 619 }
 620
 621 /* This is the implementation of linux target ops method
 622    low_stopped_by_watchpoint.  The watchhi R and W bits indicate
 623    the watch register triggered. */
 624
 625 bool
 626 mips_target::low_stopped_by_watchpoint ()
 627 {
 628   struct process_info *proc = current_process ();
 629   struct arch_process_info *priv = proc->priv->arch_private;
 630   int n;
 631   int num_valid;
 632   long lwpid = lwpid_of (current_thread);
 633
 634   if (!mips_linux_read_watch_registers (lwpid,
 635                                         &priv->watch_readback,
 636                                         &priv->watch_readback_valid,
 637                                         1))
 638     return 0;
 639
 640   num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback);
 641
 642   for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
 643     if (mips_linux_watch_get_watchhi (&priv->watch_readback, n)
 644         & (R_MASK | W_MASK))
 645       return true;
 646
 647   return false;
 648 }
 649
 650 /* This is the implementation of linux target ops method
 651    low_stopped_data_address.  */
 652
 653 CORE_ADDR
 654 mips_target::low_stopped_data_address ()
 655 {
 656   struct process_info *proc = current_process ();
 657   struct arch_process_info *priv = proc->priv->arch_private;
 658   int n;
 659   int num_valid;
 660   long lwpid = lwpid_of (current_thread);
 661
 662   /* On MIPS we don't know the low order 3 bits of the data address.
 663      GDB does not support remote targets that can't report the
 664      watchpoint address.  So, make our best guess; return the starting
 665      address of a watchpoint request which overlaps the one that
 666      triggered.  */
 667
 668   if (!mips_linux_read_watch_registers (lwpid,
 669                                         &priv->watch_readback,
 670                                         &priv->watch_readback_valid,
 671                                         0))
 672     return 0;
 673
 674   num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback);
 675
 676   for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
 677     if (mips_linux_watch_get_watchhi (&priv->watch_readback, n)
 678         & (R_MASK | W_MASK))
 679       {
 680         CORE_ADDR t_low, t_hi;
 681         int t_irw;
 682         struct mips_watchpoint *watch;
 683
 684         t_low = mips_linux_watch_get_watchlo (&priv->watch_readback, n);
 685         t_irw = t_low & IRW_MASK;
 686         t_hi = (mips_linux_watch_get_watchhi (&priv->watch_readback, n)
 687                 | IRW_MASK);
 688         t_low &= ~(CORE_ADDR)t_hi;
 689
 690         for (watch = priv->current_watches;
 691              watch != NULL;
 692              watch = watch->next)
 693           {
 694             CORE_ADDR addr = watch->addr;
 695             CORE_ADDR last_byte = addr + watch->len - 1;
 696
 697             if ((t_irw & mips_linux_watch_type_to_irw (watch->type)) == 0)
 698               {
 699                 /* Different type.  */
 700                 continue;
 701               }
 702             /* Check for overlap of even a single byte.  */
 703             if (last_byte >= t_low && addr <= t_low + t_hi)
 704               return addr;
 705           }
 706       }
 707
 708   /* Shouldn't happen.  */
 709   return 0;
 710 }
 711
 712 /* Fetch the thread-local storage pointer for libthread_db.  */
 713
 714 ps_err_e
 715 ps_get_thread_area (struct ps_prochandle *ph,
 716                     lwpid_t lwpid, int idx, void **base)
 717 {
 718   if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
 719     return PS_ERR;
 720
 721   /* IDX is the bias from the thread pointer to the beginning of the
 722      thread descriptor.  It has to be subtracted due to implementation
 723      quirks in libthread_db.  */
 724   *base = (void *) ((char *)*base - idx);
 725
 726   return PS_OK;
 727 }
 728
 729 static void
 730 mips_collect_register (struct regcache *regcache,
 731                        int use_64bit, int regno, union mips_register *reg)
 732 {
 733   union mips_register tmp_reg;
 734
 735   if (use_64bit)
 736     {
 737       collect_register (regcache, regno, &tmp_reg.reg64);
 738       *reg = tmp_reg;
 739     }
 740   else
 741     {
 742       collect_register (regcache, regno, &tmp_reg.reg32);
 743       reg->reg64 = tmp_reg.reg32;
 744     }
 745 }
 746
 747 static void
 748 mips_supply_register (struct regcache *regcache,
 749                       int use_64bit, int regno, const union mips_register *reg)
 750 {
 751   int offset = 0;
 752
 753   /* For big-endian 32-bit targets, ignore the high four bytes of each
 754      eight-byte slot.  */
 755   if (__BYTE_ORDER == __BIG_ENDIAN && !use_64bit)
 756     offset = 4;
 757
 758   supply_register (regcache, regno, reg->buf + offset);
 759 }
 760
 761 #ifdef HAVE_PTRACE_GETREGS
 762
 763 static void
 764 mips_collect_register_32bit (struct regcache *regcache,
 765                              int use_64bit, int regno, unsigned char *buf)
 766 {
 767   union mips_register tmp_reg;
 768   int reg32;
 769
 770   mips_collect_register (regcache, use_64bit, regno, &tmp_reg);
 771   reg32 = tmp_reg.reg64;
 772   memcpy (buf, &reg32, 4);
 773 }
 774
 775 static void
 776 mips_supply_register_32bit (struct regcache *regcache,
 777                             int use_64bit, int regno, const unsigned char *buf)
 778 {
 779   union mips_register tmp_reg;
 780   int reg32;
 781
 782   memcpy (&reg32, buf, 4);
 783   tmp_reg.reg64 = reg32;
 784   mips_supply_register (regcache, use_64bit, regno, &tmp_reg);
 785 }
 786
 787 static void
 788 mips_fill_gregset (struct regcache *regcache, void *buf)
 789 {
 790   union mips_register *regset = (union mips_register *) buf;
 791   int i, use_64bit;
 792   const struct target_desc *tdesc = regcache->tdesc;
 793
 794   use_64bit = (register_size (tdesc, 0) == 8);
 795
 796   for (i = 1; i < 32; i++)
 797     mips_collect_register (regcache, use_64bit, i, regset + i);
 798
 799   mips_collect_register (regcache, use_64bit,
 800                          find_regno (tdesc, "lo"), regset + 32);
 801   mips_collect_register (regcache, use_64bit,
 802                          find_regno (tdesc, "hi"), regset + 33);
 803   mips_collect_register (regcache, use_64bit,
 804                          find_regno (tdesc, "pc"), regset + 34);
 805   mips_collect_register (regcache, use_64bit,
 806                          find_regno (tdesc, "badvaddr"), regset + 35);
 807   mips_collect_register (regcache, use_64bit,
 808                          find_regno (tdesc, "status"), regset + 36);
 809   mips_collect_register (regcache, use_64bit,
 810                          find_regno (tdesc, "cause"), regset + 37);
 811
 812   mips_collect_register (regcache, use_64bit,
 813                          find_regno (tdesc, "restart"), regset + 0);
 814 }
 815
 816 static void
 817 mips_store_gregset (struct regcache *regcache, const void *buf)
 818 {
 819   const union mips_register *regset = (const union mips_register *) buf;
 820   int i, use_64bit;
 821
 822   use_64bit = (register_size (regcache->tdesc, 0) == 8);
 823
 824   supply_register_by_name_zeroed (regcache, "r0");
 825
 826   for (i = 1; i < 32; i++)
 827     mips_supply_register (regcache, use_64bit, i, regset + i);
 828
 829   mips_supply_register (regcache, use_64bit,
 830                         find_regno (regcache->tdesc, "lo"), regset + 32);
 831   mips_supply_register (regcache, use_64bit,
 832                         find_regno (regcache->tdesc, "hi"), regset + 33);
 833   mips_supply_register (regcache, use_64bit,
 834                         find_regno (regcache->tdesc, "pc"), regset + 34);
 835   mips_supply_register (regcache, use_64bit,
 836                         find_regno (regcache->tdesc, "badvaddr"), regset + 35);
 837   mips_supply_register (regcache, use_64bit,
 838                         find_regno (regcache->tdesc, "status"), regset + 36);
 839   mips_supply_register (regcache, use_64bit,
 840                         find_regno (regcache->tdesc, "cause"), regset + 37);
 841
 842   mips_supply_register (regcache, use_64bit,
 843                         find_regno (regcache->tdesc, "restart"), regset + 0);
 844 }
 845
 846 static void
 847 mips_fill_fpregset (struct regcache *regcache, void *buf)
 848 {
 849   union mips_register *regset = (union mips_register *) buf;
 850   int i, use_64bit, first_fp, big_endian;
 851
 852   use_64bit = (register_size (regcache->tdesc, 0) == 8);
 853   first_fp = find_regno (regcache->tdesc, "f0");
 854   big_endian = (__BYTE_ORDER == __BIG_ENDIAN);
 855
 856   /* See GDB for a discussion of this peculiar layout.  */
 857   for (i = 0; i < 32; i++)
 858     if (use_64bit)
 859       collect_register (regcache, first_fp + i, regset[i].buf);
 860     else
 861       collect_register (regcache, first_fp + i,
 862                         regset[i & ~1].buf + 4 * (big_endian != (i & 1)));
 863
 864   mips_collect_register_32bit (regcache, use_64bit,
 865                                find_regno (regcache->tdesc, "fcsr"), regset[32].buf);
 866   mips_collect_register_32bit (regcache, use_64bit,
 867                                find_regno (regcache->tdesc, "fir"),
 868                                regset[32].buf + 4);
 869 }
 870
 871 static void
 872 mips_store_fpregset (struct regcache *regcache, const void *buf)
 873 {
 874   const union mips_register *regset = (const union mips_register *) buf;
 875   int i, use_64bit, first_fp, big_endian;
 876
 877   use_64bit = (register_size (regcache->tdesc, 0) == 8);
 878   first_fp = find_regno (regcache->tdesc, "f0");
 879   big_endian = (__BYTE_ORDER == __BIG_ENDIAN);
 880
 881   /* See GDB for a discussion of this peculiar layout.  */
 882   for (i = 0; i < 32; i++)
 883     if (use_64bit)
 884       supply_register (regcache, first_fp + i, regset[i].buf);
 885     else
 886       supply_register (regcache, first_fp + i,
 887                        regset[i & ~1].buf + 4 * (big_endian != (i & 1)));
 888
 889   mips_supply_register_32bit (regcache, use_64bit,
 890                               find_regno (regcache->tdesc, "fcsr"),
 891                               regset[32].buf);
 892   mips_supply_register_32bit (regcache, use_64bit,
 893                               find_regno (regcache->tdesc, "fir"),
 894                               regset[32].buf + 4);
 895 }
 896 #endif /* HAVE_PTRACE_GETREGS */
 897
 898 /* Take care of 32-bit registers with 64-bit ptrace, POKEUSER side.  */
 899
 900 void
 901 mips_target::low_collect_ptrace_register (regcache *regcache, int regno,
 902                                           char *buf)
 903 {
 904   int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8;
 905
 906   if (use_64bit && register_size (regcache->tdesc, regno) == 4)
 907     {
 908       union mips_register reg;
 909
 910       mips_collect_register (regcache, 0, regno, &reg);
 911       memcpy (buf, &reg, sizeof (reg));
 912     }
 913   else
 914     collect_register (regcache, regno, buf);
 915 }
 916
 917 /* Take care of 32-bit registers with 64-bit ptrace, PEEKUSER side.  */
 918
 919 void
 920 mips_target::low_supply_ptrace_register (regcache *regcache, int regno,
 921                                          const char *buf)
 922 {
 923   int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8;
 924
 925   if (use_64bit && register_size (regcache->tdesc, regno) == 4)
 926     {
 927       union mips_register reg;
 928
 929       memcpy (&reg, buf, sizeof (reg));
 930       mips_supply_register (regcache, 0, regno, &reg);
 931     }
 932   else
 933     supply_register (regcache, regno, buf);
 934 }
 935
 936 static struct regset_info mips_regsets[] = {
 937 #ifdef HAVE_PTRACE_GETREGS
 938   { PTRACE_GETREGS, PTRACE_SETREGS, 0, 38 * 8, GENERAL_REGS,
 939     mips_fill_gregset, mips_store_gregset },
 940   { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, 33 * 8, FP_REGS,
 941     mips_fill_fpregset, mips_store_fpregset },
 942 #endif /* HAVE_PTRACE_GETREGS */
 943   NULL_REGSET
 944 };
 945
 946 static struct regsets_info mips_regsets_info =
 947   {
 948     mips_regsets, /* regsets */
 949     0, /* num_regsets */
 950     NULL, /* disabled_regsets */
 951   };
 952
 953 static struct usrregs_info mips_dsp_usrregs_info =
 954   {
 955     mips_dsp_num_regs,
 956     mips_dsp_regmap,
 957   };
 958
 959 static struct usrregs_info mips_usrregs_info =
 960   {
 961     mips_num_regs,
 962     mips_regmap,
 963   };
 964
 965 static struct regs_info dsp_regs_info =
 966   {
 967     mips_dsp_regset_bitmap,
 968     &mips_dsp_usrregs_info,
 969     &mips_regsets_info
 970   };
 971
 972 static struct regs_info myregs_info =
 973   {
 974     NULL, /* regset_bitmap */
 975     &mips_usrregs_info,
 976     &mips_regsets_info
 977   };
 978
 979 const regs_info *
 980 mips_target::get_regs_info ()
 981 {
 982   if (have_dsp)
 983     return &dsp_regs_info;
 984   else
 985     return &myregs_info;
 986 }
 987
 988 struct linux_target_ops the_low_target = {
 989   mips_linux_new_process,
 990   mips_linux_delete_process,
 991   mips_linux_new_thread,
 992   mips_linux_delete_thread,
 993   mips_linux_new_fork,
 994   mips_linux_prepare_to_resume
 995 };
 996
 997 /* The linux target ops object.  */
 998
 999 linux_process_target *the_linux_target = &the_mips_target;
1000
1001 void
1002 initialize_low_arch (void)
1003 {
1004   /* Initialize the Linux target descriptions.  */
1005   init_registers_mips_linux ();
1006   init_registers_mips_dsp_linux ();
1007   init_registers_mips64_linux ();
1008   init_registers_mips64_dsp_linux ();
1009
1010   initialize_regsets_info (&mips_regsets_info);
1011 }