1 /* GNU/Linux/PowerPC specific low level interface, for the remote server for
3 Copyright (C) 1995-2020 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "linux-low.h"
23 #include "elf/common.h"
26 #include <asm/ptrace.h>
28 #include "arch/ppc-linux-common.h"
29 #include "arch/ppc-linux-tdesc.h"
30 #include "nat/ppc-linux.h"
31 #include "nat/linux-ptrace.h"
32 #include "linux-ppc-tdesc-init.h"
34 #include "tracepoint.h"
36 #define PPC_FIELD(value, from, len) \
37 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
38 #define PPC_SEXT(v, bs) \
39 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
40 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
41 - ((CORE_ADDR) 1 << ((bs) - 1)))
42 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
43 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
44 #define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
45 #define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
47 /* Linux target op definitions for the PowerPC architecture. */
49 class ppc_target
: public linux_process_target
53 const regs_info
*get_regs_info () override
;
55 const gdb_byte
*sw_breakpoint_from_kind (int kind
, int *size
) override
;
57 bool supports_z_point_type (char z_type
) override
;
61 void low_arch_setup () override
;
63 bool low_cannot_fetch_register (int regno
) override
;
65 bool low_cannot_store_register (int regno
) override
;
67 bool low_supports_breakpoints () override
;
69 CORE_ADDR
low_get_pc (regcache
*regcache
) override
;
71 void low_set_pc (regcache
*regcache
, CORE_ADDR newpc
) override
;
73 bool low_breakpoint_at (CORE_ADDR pc
) override
;
75 int low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
76 int size
, raw_breakpoint
*bp
) override
;
78 int low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
79 int size
, raw_breakpoint
*bp
) override
;
82 /* The singleton target ops object. */
84 static ppc_target the_ppc_target
;
86 /* Holds the AT_HWCAP auxv entry. */
88 static unsigned long ppc_hwcap
;
90 /* Holds the AT_HWCAP2 auxv entry. */
92 static unsigned long ppc_hwcap2
;
95 #define ppc_num_regs 73
98 /* We use a constant for FPSCR instead of PT_FPSCR, because
99 many shipped PPC64 kernels had the wrong value in ptrace.h. */
100 static int ppc_regmap
[] =
101 {PT_R0
* 8, PT_R1
* 8, PT_R2
* 8, PT_R3
* 8,
102 PT_R4
* 8, PT_R5
* 8, PT_R6
* 8, PT_R7
* 8,
103 PT_R8
* 8, PT_R9
* 8, PT_R10
* 8, PT_R11
* 8,
104 PT_R12
* 8, PT_R13
* 8, PT_R14
* 8, PT_R15
* 8,
105 PT_R16
* 8, PT_R17
* 8, PT_R18
* 8, PT_R19
* 8,
106 PT_R20
* 8, PT_R21
* 8, PT_R22
* 8, PT_R23
* 8,
107 PT_R24
* 8, PT_R25
* 8, PT_R26
* 8, PT_R27
* 8,
108 PT_R28
* 8, PT_R29
* 8, PT_R30
* 8, PT_R31
* 8,
109 PT_FPR0
*8, PT_FPR0
*8 + 8, PT_FPR0
*8+16, PT_FPR0
*8+24,
110 PT_FPR0
*8+32, PT_FPR0
*8+40, PT_FPR0
*8+48, PT_FPR0
*8+56,
111 PT_FPR0
*8+64, PT_FPR0
*8+72, PT_FPR0
*8+80, PT_FPR0
*8+88,
112 PT_FPR0
*8+96, PT_FPR0
*8+104, PT_FPR0
*8+112, PT_FPR0
*8+120,
113 PT_FPR0
*8+128, PT_FPR0
*8+136, PT_FPR0
*8+144, PT_FPR0
*8+152,
114 PT_FPR0
*8+160, PT_FPR0
*8+168, PT_FPR0
*8+176, PT_FPR0
*8+184,
115 PT_FPR0
*8+192, PT_FPR0
*8+200, PT_FPR0
*8+208, PT_FPR0
*8+216,
116 PT_FPR0
*8+224, PT_FPR0
*8+232, PT_FPR0
*8+240, PT_FPR0
*8+248,
117 PT_NIP
* 8, PT_MSR
* 8, PT_CCR
* 8, PT_LNK
* 8,
118 PT_CTR
* 8, PT_XER
* 8, PT_FPR0
*8 + 256,
119 PT_ORIG_R3
* 8, PT_TRAP
* 8 };
121 /* Currently, don't check/send MQ. */
122 static int ppc_regmap
[] =
123 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
124 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
125 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
126 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
127 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
128 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
129 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
130 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
131 PT_FPR0
*4, PT_FPR0
*4 + 8, PT_FPR0
*4+16, PT_FPR0
*4+24,
132 PT_FPR0
*4+32, PT_FPR0
*4+40, PT_FPR0
*4+48, PT_FPR0
*4+56,
133 PT_FPR0
*4+64, PT_FPR0
*4+72, PT_FPR0
*4+80, PT_FPR0
*4+88,
134 PT_FPR0
*4+96, PT_FPR0
*4+104, PT_FPR0
*4+112, PT_FPR0
*4+120,
135 PT_FPR0
*4+128, PT_FPR0
*4+136, PT_FPR0
*4+144, PT_FPR0
*4+152,
136 PT_FPR0
*4+160, PT_FPR0
*4+168, PT_FPR0
*4+176, PT_FPR0
*4+184,
137 PT_FPR0
*4+192, PT_FPR0
*4+200, PT_FPR0
*4+208, PT_FPR0
*4+216,
138 PT_FPR0
*4+224, PT_FPR0
*4+232, PT_FPR0
*4+240, PT_FPR0
*4+248,
139 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
140 PT_CTR
* 4, PT_XER
* 4, PT_FPSCR
* 4,
141 PT_ORIG_R3
* 4, PT_TRAP
* 4
144 static int ppc_regmap_e500
[] =
145 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
146 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
147 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
148 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
149 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
150 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
151 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
152 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
161 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
162 PT_CTR
* 4, PT_XER
* 4, -1,
163 PT_ORIG_R3
* 4, PT_TRAP
* 4
167 /* Check whether the kernel provides a register set with number
168 REGSET_ID of size REGSETSIZE for process/thread TID. */
171 ppc_check_regset (int tid
, int regset_id
, int regsetsize
)
173 void *buf
= alloca (regsetsize
);
177 iov
.iov_len
= regsetsize
;
179 if (ptrace (PTRACE_GETREGSET
, tid
, regset_id
, &iov
) >= 0
186 ppc_target::low_cannot_store_register (int regno
)
188 const struct target_desc
*tdesc
= current_process ()->tdesc
;
190 #ifndef __powerpc64__
191 /* Some kernels do not allow us to store fpscr. */
192 if (!(ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
193 && regno
== find_regno (tdesc
, "fpscr"))
197 /* Some kernels do not allow us to store orig_r3 or trap. */
198 if (regno
== find_regno (tdesc
, "orig_r3")
199 || regno
== find_regno (tdesc
, "trap"))
206 ppc_target::low_cannot_fetch_register (int regno
)
212 ppc_collect_ptrace_register (struct regcache
*regcache
, int regno
, char *buf
)
214 memset (buf
, 0, sizeof (long));
216 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
218 /* Little-endian values always sit at the left end of the buffer. */
219 collect_register (regcache
, regno
, buf
);
221 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
223 /* Big-endian values sit at the right end of the buffer. In case of
224 registers whose sizes are smaller than sizeof (long), we must use a
225 padding to access them correctly. */
226 int size
= register_size (regcache
->tdesc
, regno
);
228 if (size
< sizeof (long))
229 collect_register (regcache
, regno
, buf
+ sizeof (long) - size
);
231 collect_register (regcache
, regno
, buf
);
234 perror_with_name ("Unexpected byte order");
238 ppc_supply_ptrace_register (struct regcache
*regcache
,
239 int regno
, const char *buf
)
241 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
243 /* Little-endian values always sit at the left end of the buffer. */
244 supply_register (regcache
, regno
, buf
);
246 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
248 /* Big-endian values sit at the right end of the buffer. In case of
249 registers whose sizes are smaller than sizeof (long), we must use a
250 padding to access them correctly. */
251 int size
= register_size (regcache
->tdesc
, regno
);
253 if (size
< sizeof (long))
254 supply_register (regcache
, regno
, buf
+ sizeof (long) - size
);
256 supply_register (regcache
, regno
, buf
);
259 perror_with_name ("Unexpected byte order");
263 ppc_target::low_supports_breakpoints ()
269 ppc_target::low_get_pc (regcache
*regcache
)
271 if (register_size (regcache
->tdesc
, 0) == 4)
274 collect_register_by_name (regcache
, "pc", &pc
);
275 return (CORE_ADDR
) pc
;
280 collect_register_by_name (regcache
, "pc", &pc
);
281 return (CORE_ADDR
) pc
;
286 ppc_target::low_set_pc (regcache
*regcache
, CORE_ADDR pc
)
288 if (register_size (regcache
->tdesc
, 0) == 4)
290 unsigned int newpc
= pc
;
291 supply_register_by_name (regcache
, "pc", &newpc
);
295 unsigned long newpc
= pc
;
296 supply_register_by_name (regcache
, "pc", &newpc
);
300 #ifndef __powerpc64__
301 static int ppc_regmap_adjusted
;
305 /* Correct in either endianness.
306 This instruction is "twge r2, r2", which GDB uses as a software
308 static const unsigned int ppc_breakpoint
= 0x7d821008;
309 #define ppc_breakpoint_len 4
311 /* Implementation of target ops method "sw_breakpoint_from_kind". */
314 ppc_target::sw_breakpoint_from_kind (int kind
, int *size
)
316 *size
= ppc_breakpoint_len
;
317 return (const gdb_byte
*) &ppc_breakpoint
;
321 ppc_target::low_breakpoint_at (CORE_ADDR where
)
325 read_memory (where
, (unsigned char *) &insn
, 4);
326 if (insn
== ppc_breakpoint
)
328 /* If necessary, recognize more trap instructions here. GDB only uses
334 /* Implement supports_z_point_type target-ops.
335 Returns true if type Z_TYPE breakpoint is supported.
337 Handling software breakpoint at server side, so tracepoints
338 and breakpoints can be inserted at the same location. */
341 ppc_target::supports_z_point_type (char z_type
)
348 case Z_PACKET_WRITE_WP
:
349 case Z_PACKET_ACCESS_WP
:
355 /* Implement the low_insert_point linux target op.
356 Returns 0 on success, -1 on failure and 1 on unsupported. */
359 ppc_target::low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
360 int size
, raw_breakpoint
*bp
)
364 case raw_bkpt_type_sw
:
365 return insert_memory_breakpoint (bp
);
367 case raw_bkpt_type_hw
:
368 case raw_bkpt_type_write_wp
:
369 case raw_bkpt_type_access_wp
:
376 /* Implement the low_remove_point linux target op.
377 Returns 0 on success, -1 on failure and 1 on unsupported. */
380 ppc_target::low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
381 int size
, raw_breakpoint
*bp
)
385 case raw_bkpt_type_sw
:
386 return remove_memory_breakpoint (bp
);
388 case raw_bkpt_type_hw
:
389 case raw_bkpt_type_write_wp
:
390 case raw_bkpt_type_access_wp
:
397 /* Provide only a fill function for the general register set. ps_lgetregs
398 will use this for NPTL support. */
400 static void ppc_fill_gregset (struct regcache
*regcache
, void *buf
)
404 for (i
= 0; i
< 32; i
++)
405 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
407 for (i
= 64; i
< 70; i
++)
408 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
410 for (i
= 71; i
< 73; i
++)
411 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
414 /* Program Priority Register regset fill function. */
417 ppc_fill_pprregset (struct regcache
*regcache
, void *buf
)
419 char *ppr
= (char *) buf
;
421 collect_register_by_name (regcache
, "ppr", ppr
);
424 /* Program Priority Register regset store function. */
427 ppc_store_pprregset (struct regcache
*regcache
, const void *buf
)
429 const char *ppr
= (const char *) buf
;
431 supply_register_by_name (regcache
, "ppr", ppr
);
434 /* Data Stream Control Register regset fill function. */
437 ppc_fill_dscrregset (struct regcache
*regcache
, void *buf
)
439 char *dscr
= (char *) buf
;
441 collect_register_by_name (regcache
, "dscr", dscr
);
444 /* Data Stream Control Register regset store function. */
447 ppc_store_dscrregset (struct regcache
*regcache
, const void *buf
)
449 const char *dscr
= (const char *) buf
;
451 supply_register_by_name (regcache
, "dscr", dscr
);
454 /* Target Address Register regset fill function. */
457 ppc_fill_tarregset (struct regcache
*regcache
, void *buf
)
459 char *tar
= (char *) buf
;
461 collect_register_by_name (regcache
, "tar", tar
);
464 /* Target Address Register regset store function. */
467 ppc_store_tarregset (struct regcache
*regcache
, const void *buf
)
469 const char *tar
= (const char *) buf
;
471 supply_register_by_name (regcache
, "tar", tar
);
474 /* Event-Based Branching regset store function. Unless the inferior
475 has a perf event open, ptrace can return in error when reading and
476 writing to the regset, with ENODATA. For reading, the registers
477 will correctly show as unavailable. For writing, gdbserver
478 currently only caches any register writes from P and G packets and
479 the stub always tries to write all the regsets when resuming the
480 inferior, which would result in frequent warnings. For this
481 reason, we don't define a fill function. This also means that the
482 client-side regcache will be dirty if the user tries to write to
483 the EBB registers. G packets that the client sends to write to
484 unrelated registers will also include data for EBB registers, even
485 if they are unavailable. */
488 ppc_store_ebbregset (struct regcache
*regcache
, const void *buf
)
490 const char *regset
= (const char *) buf
;
492 /* The order in the kernel regset is: EBBRR, EBBHR, BESCR. In the
493 .dat file is BESCR, EBBHR, EBBRR. */
494 supply_register_by_name (regcache
, "ebbrr", ®set
[0]);
495 supply_register_by_name (regcache
, "ebbhr", ®set
[8]);
496 supply_register_by_name (regcache
, "bescr", ®set
[16]);
499 /* Performance Monitoring Unit regset fill function. */
502 ppc_fill_pmuregset (struct regcache
*regcache
, void *buf
)
504 char *regset
= (char *) buf
;
506 /* The order in the kernel regset is SIAR, SDAR, SIER, MMCR2, MMCR0.
507 In the .dat file is MMCR0, MMCR2, SIAR, SDAR, SIER. */
508 collect_register_by_name (regcache
, "siar", ®set
[0]);
509 collect_register_by_name (regcache
, "sdar", ®set
[8]);
510 collect_register_by_name (regcache
, "sier", ®set
[16]);
511 collect_register_by_name (regcache
, "mmcr2", ®set
[24]);
512 collect_register_by_name (regcache
, "mmcr0", ®set
[32]);
515 /* Performance Monitoring Unit regset store function. */
518 ppc_store_pmuregset (struct regcache
*regcache
, const void *buf
)
520 const char *regset
= (const char *) buf
;
522 supply_register_by_name (regcache
, "siar", ®set
[0]);
523 supply_register_by_name (regcache
, "sdar", ®set
[8]);
524 supply_register_by_name (regcache
, "sier", ®set
[16]);
525 supply_register_by_name (regcache
, "mmcr2", ®set
[24]);
526 supply_register_by_name (regcache
, "mmcr0", ®set
[32]);
529 /* Hardware Transactional Memory special-purpose register regset fill
533 ppc_fill_tm_sprregset (struct regcache
*regcache
, void *buf
)
536 char *regset
= (char *) buf
;
538 base
= find_regno (regcache
->tdesc
, "tfhar");
539 for (i
= 0; i
< 3; i
++)
540 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
543 /* Hardware Transactional Memory special-purpose register regset store
547 ppc_store_tm_sprregset (struct regcache
*regcache
, const void *buf
)
550 const char *regset
= (const char *) buf
;
552 base
= find_regno (regcache
->tdesc
, "tfhar");
553 for (i
= 0; i
< 3; i
++)
554 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
557 /* For the same reasons as the EBB regset, none of the HTM
558 checkpointed regsets have a fill function. These registers are
559 only available if the inferior is in a transaction. */
561 /* Hardware Transactional Memory checkpointed general-purpose regset
565 ppc_store_tm_cgprregset (struct regcache
*regcache
, const void *buf
)
567 int i
, base
, size
, endian_offset
;
568 const char *regset
= (const char *) buf
;
570 base
= find_regno (regcache
->tdesc
, "cr0");
571 size
= register_size (regcache
->tdesc
, base
);
573 gdb_assert (size
== 4 || size
== 8);
575 for (i
= 0; i
< 32; i
++)
576 supply_register (regcache
, base
+ i
, ®set
[i
* size
]);
580 if ((size
== 8) && (__BYTE_ORDER
== __BIG_ENDIAN
))
583 supply_register_by_name (regcache
, "ccr",
584 ®set
[PT_CCR
* size
+ endian_offset
]);
586 supply_register_by_name (regcache
, "cxer",
587 ®set
[PT_XER
* size
+ endian_offset
]);
589 supply_register_by_name (regcache
, "clr", ®set
[PT_LNK
* size
]);
590 supply_register_by_name (regcache
, "cctr", ®set
[PT_CTR
* size
]);
593 /* Hardware Transactional Memory checkpointed floating-point regset
597 ppc_store_tm_cfprregset (struct regcache
*regcache
, const void *buf
)
600 const char *regset
= (const char *) buf
;
602 base
= find_regno (regcache
->tdesc
, "cf0");
604 for (i
= 0; i
< 32; i
++)
605 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
607 supply_register_by_name (regcache
, "cfpscr", ®set
[32 * 8]);
610 /* Hardware Transactional Memory checkpointed vector regset store
614 ppc_store_tm_cvrregset (struct regcache
*regcache
, const void *buf
)
617 const char *regset
= (const char *) buf
;
620 base
= find_regno (regcache
->tdesc
, "cvr0");
622 for (i
= 0; i
< 32; i
++)
623 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
625 if (__BYTE_ORDER
== __BIG_ENDIAN
)
628 supply_register_by_name (regcache
, "cvscr",
629 ®set
[32 * 16 + vscr_offset
]);
631 supply_register_by_name (regcache
, "cvrsave", ®set
[33 * 16]);
634 /* Hardware Transactional Memory checkpointed vector-scalar regset
638 ppc_store_tm_cvsxregset (struct regcache
*regcache
, const void *buf
)
641 const char *regset
= (const char *) buf
;
643 base
= find_regno (regcache
->tdesc
, "cvs0h");
644 for (i
= 0; i
< 32; i
++)
645 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
648 /* Hardware Transactional Memory checkpointed Program Priority
649 Register regset store function. */
652 ppc_store_tm_cpprregset (struct regcache
*regcache
, const void *buf
)
654 const char *cppr
= (const char *) buf
;
656 supply_register_by_name (regcache
, "cppr", cppr
);
659 /* Hardware Transactional Memory checkpointed Data Stream Control
660 Register regset store function. */
663 ppc_store_tm_cdscrregset (struct regcache
*regcache
, const void *buf
)
665 const char *cdscr
= (const char *) buf
;
667 supply_register_by_name (regcache
, "cdscr", cdscr
);
670 /* Hardware Transactional Memory checkpointed Target Address Register
671 regset store function. */
674 ppc_store_tm_ctarregset (struct regcache
*regcache
, const void *buf
)
676 const char *ctar
= (const char *) buf
;
678 supply_register_by_name (regcache
, "ctar", ctar
);
682 ppc_fill_vsxregset (struct regcache
*regcache
, void *buf
)
685 char *regset
= (char *) buf
;
687 base
= find_regno (regcache
->tdesc
, "vs0h");
688 for (i
= 0; i
< 32; i
++)
689 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
693 ppc_store_vsxregset (struct regcache
*regcache
, const void *buf
)
696 const char *regset
= (const char *) buf
;
698 base
= find_regno (regcache
->tdesc
, "vs0h");
699 for (i
= 0; i
< 32; i
++)
700 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
704 ppc_fill_vrregset (struct regcache
*regcache
, void *buf
)
707 char *regset
= (char *) buf
;
710 base
= find_regno (regcache
->tdesc
, "vr0");
711 for (i
= 0; i
< 32; i
++)
712 collect_register (regcache
, base
+ i
, ®set
[i
* 16]);
714 if (__BYTE_ORDER
== __BIG_ENDIAN
)
717 collect_register_by_name (regcache
, "vscr",
718 ®set
[32 * 16 + vscr_offset
]);
720 collect_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
724 ppc_store_vrregset (struct regcache
*regcache
, const void *buf
)
727 const char *regset
= (const char *) buf
;
730 base
= find_regno (regcache
->tdesc
, "vr0");
731 for (i
= 0; i
< 32; i
++)
732 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
734 if (__BYTE_ORDER
== __BIG_ENDIAN
)
737 supply_register_by_name (regcache
, "vscr",
738 ®set
[32 * 16 + vscr_offset
]);
739 supply_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
742 struct gdb_evrregset_t
744 unsigned long evr
[32];
745 unsigned long long acc
;
746 unsigned long spefscr
;
750 ppc_fill_evrregset (struct regcache
*regcache
, void *buf
)
753 struct gdb_evrregset_t
*regset
= (struct gdb_evrregset_t
*) buf
;
755 ev0
= find_regno (regcache
->tdesc
, "ev0h");
756 for (i
= 0; i
< 32; i
++)
757 collect_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
759 collect_register_by_name (regcache
, "acc", ®set
->acc
);
760 collect_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
764 ppc_store_evrregset (struct regcache
*regcache
, const void *buf
)
767 const struct gdb_evrregset_t
*regset
= (const struct gdb_evrregset_t
*) buf
;
769 ev0
= find_regno (regcache
->tdesc
, "ev0h");
770 for (i
= 0; i
< 32; i
++)
771 supply_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
773 supply_register_by_name (regcache
, "acc", ®set
->acc
);
774 supply_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
777 /* Support for hardware single step. */
780 ppc_supports_hardware_single_step (void)
785 static struct regset_info ppc_regsets
[] = {
786 /* List the extra register sets before GENERAL_REGS. That way we will
787 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
788 general registers. Some kernels support these, but not the newer
789 PPC_PTRACE_GETREGS. */
790 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CTAR
, 0, EXTENDED_REGS
,
791 NULL
, ppc_store_tm_ctarregset
},
792 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CDSCR
, 0, EXTENDED_REGS
,
793 NULL
, ppc_store_tm_cdscrregset
},
794 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CPPR
, 0, EXTENDED_REGS
,
795 NULL
, ppc_store_tm_cpprregset
},
796 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CVSX
, 0, EXTENDED_REGS
,
797 NULL
, ppc_store_tm_cvsxregset
},
798 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CVMX
, 0, EXTENDED_REGS
,
799 NULL
, ppc_store_tm_cvrregset
},
800 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CFPR
, 0, EXTENDED_REGS
,
801 NULL
, ppc_store_tm_cfprregset
},
802 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CGPR
, 0, EXTENDED_REGS
,
803 NULL
, ppc_store_tm_cgprregset
},
804 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_SPR
, 0, EXTENDED_REGS
,
805 ppc_fill_tm_sprregset
, ppc_store_tm_sprregset
},
806 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_EBB
, 0, EXTENDED_REGS
,
807 NULL
, ppc_store_ebbregset
},
808 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PMU
, 0, EXTENDED_REGS
,
809 ppc_fill_pmuregset
, ppc_store_pmuregset
},
810 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TAR
, 0, EXTENDED_REGS
,
811 ppc_fill_tarregset
, ppc_store_tarregset
},
812 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PPR
, 0, EXTENDED_REGS
,
813 ppc_fill_pprregset
, ppc_store_pprregset
},
814 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_DSCR
, 0, EXTENDED_REGS
,
815 ppc_fill_dscrregset
, ppc_store_dscrregset
},
816 { PTRACE_GETVSXREGS
, PTRACE_SETVSXREGS
, 0, 0, EXTENDED_REGS
,
817 ppc_fill_vsxregset
, ppc_store_vsxregset
},
818 { PTRACE_GETVRREGS
, PTRACE_SETVRREGS
, 0, 0, EXTENDED_REGS
,
819 ppc_fill_vrregset
, ppc_store_vrregset
},
820 { PTRACE_GETEVRREGS
, PTRACE_SETEVRREGS
, 0, 0, EXTENDED_REGS
,
821 ppc_fill_evrregset
, ppc_store_evrregset
},
822 { 0, 0, 0, 0, GENERAL_REGS
, ppc_fill_gregset
, NULL
},
826 static struct usrregs_info ppc_usrregs_info
=
832 static struct regsets_info ppc_regsets_info
=
834 ppc_regsets
, /* regsets */
836 NULL
, /* disabled_regsets */
839 static struct regs_info myregs_info
=
841 NULL
, /* regset_bitmap */
847 ppc_target::get_regs_info ()
853 ppc_target::low_arch_setup ()
855 const struct target_desc
*tdesc
;
856 struct regset_info
*regset
;
857 struct ppc_linux_features features
= ppc_linux_no_features
;
859 int tid
= lwpid_of (current_thread
);
861 features
.wordsize
= ppc_linux_target_wordsize (tid
);
863 if (features
.wordsize
== 4)
864 tdesc
= tdesc_powerpc_32l
;
866 tdesc
= tdesc_powerpc_64l
;
868 current_process ()->tdesc
= tdesc
;
870 /* The value of current_process ()->tdesc needs to be set for this
872 ppc_hwcap
= linux_get_hwcap (features
.wordsize
);
873 ppc_hwcap2
= linux_get_hwcap2 (features
.wordsize
);
875 features
.isa205
= ppc_linux_has_isa205 (ppc_hwcap
);
877 if (ppc_hwcap
& PPC_FEATURE_HAS_VSX
)
880 if (ppc_hwcap
& PPC_FEATURE_HAS_ALTIVEC
)
881 features
.altivec
= true;
883 if ((ppc_hwcap2
& PPC_FEATURE2_DSCR
)
884 && ppc_check_regset (tid
, NT_PPC_DSCR
, PPC_LINUX_SIZEOF_DSCRREGSET
)
885 && ppc_check_regset (tid
, NT_PPC_PPR
, PPC_LINUX_SIZEOF_PPRREGSET
))
887 features
.ppr_dscr
= true;
888 if ((ppc_hwcap2
& PPC_FEATURE2_ARCH_2_07
)
889 && (ppc_hwcap2
& PPC_FEATURE2_TAR
)
890 && (ppc_hwcap2
& PPC_FEATURE2_EBB
)
891 && ppc_check_regset (tid
, NT_PPC_TAR
,
892 PPC_LINUX_SIZEOF_TARREGSET
)
893 && ppc_check_regset (tid
, NT_PPC_EBB
,
894 PPC_LINUX_SIZEOF_EBBREGSET
)
895 && ppc_check_regset (tid
, NT_PPC_PMU
,
896 PPC_LINUX_SIZEOF_PMUREGSET
))
898 features
.isa207
= true;
899 if ((ppc_hwcap2
& PPC_FEATURE2_HTM
)
900 && ppc_check_regset (tid
, NT_PPC_TM_SPR
,
901 PPC_LINUX_SIZEOF_TM_SPRREGSET
))
906 tdesc
= ppc_linux_match_description (features
);
908 /* On 32-bit machines, check for SPE registers.
909 Set the low target's regmap field as appropriately. */
910 #ifndef __powerpc64__
911 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
912 tdesc
= tdesc_powerpc_e500l
;
914 if (!ppc_regmap_adjusted
)
916 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
917 ppc_usrregs_info
.regmap
= ppc_regmap_e500
;
919 /* If the FPSCR is 64-bit wide, we need to fetch the whole
920 64-bit slot and not just its second word. The PT_FPSCR
921 supplied in a 32-bit GDB compilation doesn't reflect
923 if (register_size (tdesc
, 70) == 8)
924 ppc_regmap
[70] = (48 + 2*32) * sizeof (long);
926 ppc_regmap_adjusted
= 1;
930 current_process ()->tdesc
= tdesc
;
932 for (regset
= ppc_regsets
; regset
->size
>= 0; regset
++)
933 switch (regset
->get_request
)
935 case PTRACE_GETVRREGS
:
936 regset
->size
= features
.altivec
? PPC_LINUX_SIZEOF_VRREGSET
: 0;
938 case PTRACE_GETVSXREGS
:
939 regset
->size
= features
.vsx
? PPC_LINUX_SIZEOF_VSXREGSET
: 0;
941 case PTRACE_GETEVRREGS
:
942 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
943 regset
->size
= 32 * 4 + 8 + 4;
947 case PTRACE_GETREGSET
:
948 switch (regset
->nt_type
)
951 regset
->size
= (features
.ppr_dscr
?
952 PPC_LINUX_SIZEOF_PPRREGSET
: 0);
955 regset
->size
= (features
.ppr_dscr
?
956 PPC_LINUX_SIZEOF_DSCRREGSET
: 0);
959 regset
->size
= (features
.isa207
?
960 PPC_LINUX_SIZEOF_TARREGSET
: 0);
963 regset
->size
= (features
.isa207
?
964 PPC_LINUX_SIZEOF_EBBREGSET
: 0);
967 regset
->size
= (features
.isa207
?
968 PPC_LINUX_SIZEOF_PMUREGSET
: 0);
971 regset
->size
= (features
.htm
?
972 PPC_LINUX_SIZEOF_TM_SPRREGSET
: 0);
975 if (features
.wordsize
== 4)
976 regset
->size
= (features
.htm
?
977 PPC32_LINUX_SIZEOF_CGPRREGSET
: 0);
979 regset
->size
= (features
.htm
?
980 PPC64_LINUX_SIZEOF_CGPRREGSET
: 0);
983 regset
->size
= (features
.htm
?
984 PPC_LINUX_SIZEOF_CFPRREGSET
: 0);
987 regset
->size
= (features
.htm
?
988 PPC_LINUX_SIZEOF_CVMXREGSET
: 0);
991 regset
->size
= (features
.htm
?
992 PPC_LINUX_SIZEOF_CVSXREGSET
: 0);
995 regset
->size
= (features
.htm
?
996 PPC_LINUX_SIZEOF_CPPRREGSET
: 0);
998 case NT_PPC_TM_CDSCR
:
999 regset
->size
= (features
.htm
?
1000 PPC_LINUX_SIZEOF_CDSCRREGSET
: 0);
1002 case NT_PPC_TM_CTAR
:
1003 regset
->size
= (features
.htm
?
1004 PPC_LINUX_SIZEOF_CTARREGSET
: 0);
1015 /* Implementation of linux_target_ops method "supports_tracepoints". */
1018 ppc_supports_tracepoints (void)
1023 /* Get the thread area address. This is used to recognize which
1024 thread is which when tracing with the in-process agent library. We
1025 don't read anything from the address, and treat it as opaque; it's
1026 the address itself that we assume is unique per-thread. */
1029 ppc_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
1031 struct lwp_info
*lwp
= find_lwp_pid (ptid_t (lwpid
));
1032 struct thread_info
*thr
= get_lwp_thread (lwp
);
1033 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
1036 #ifdef __powerpc64__
1037 if (register_size (regcache
->tdesc
, 0) == 8)
1038 collect_register_by_name (regcache
, "r13", &tp
);
1041 collect_register_by_name (regcache
, "r2", &tp
);
1048 #ifdef __powerpc64__
1050 /* Older glibc doesn't provide this. */
1052 #ifndef EF_PPC64_ABI
1053 #define EF_PPC64_ABI 3
1056 /* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
1060 is_elfv2_inferior (void)
1062 /* To be used as fallback if we're unable to determine the right result -
1063 assume inferior uses the same ABI as gdbserver. */
1065 const int def_res
= 1;
1067 const int def_res
= 0;
1072 const struct target_desc
*tdesc
= current_process ()->tdesc
;
1073 int wordsize
= register_size (tdesc
, 0);
1075 if (!linux_get_auxv (wordsize
, AT_PHDR
, &phdr
))
1078 /* Assume ELF header is at the beginning of the page where program headers
1079 are located. If it doesn't look like one, bail. */
1081 read_inferior_memory (phdr
& ~0xfff, (unsigned char *) &ehdr
, sizeof ehdr
);
1082 if (memcmp(ehdr
.e_ident
, ELFMAG
, SELFMAG
))
1085 return (ehdr
.e_flags
& EF_PPC64_ABI
) == 2;
1090 /* Generate a ds-form instruction in BUF and return the number of bytes written
1093 | OPCD | RST | RA | DS |XO| */
1095 __attribute__((unused
)) /* Maybe unused due to conditional compilation. */
1097 gen_ds_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int ds
, int xo
)
1101 gdb_assert ((opcd
& ~0x3f) == 0);
1102 gdb_assert ((rst
& ~0x1f) == 0);
1103 gdb_assert ((ra
& ~0x1f) == 0);
1104 gdb_assert ((xo
& ~0x3) == 0);
1106 insn
= (rst
<< 21) | (ra
<< 16) | (ds
& 0xfffc) | (xo
& 0x3);
1107 *buf
= (opcd
<< 26) | insn
;
1111 /* Followings are frequently used ds-form instructions. */
1113 #define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
1114 #define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
1115 #define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
1116 #define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
1118 /* Generate a d-form instruction in BUF.
1121 | OPCD | RST | RA | D | */
1124 gen_d_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int si
)
1128 gdb_assert ((opcd
& ~0x3f) == 0);
1129 gdb_assert ((rst
& ~0x1f) == 0);
1130 gdb_assert ((ra
& ~0x1f) == 0);
1132 insn
= (rst
<< 21) | (ra
<< 16) | (si
& 0xffff);
1133 *buf
= (opcd
<< 26) | insn
;
1137 /* Followings are frequently used d-form instructions. */
1139 #define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
1140 #define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
1141 #define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
1142 #define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
1143 #define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
1144 #define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
1145 #define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
1146 #define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
1147 #define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
1149 /* Generate a xfx-form instruction in BUF and return the number of bytes
1153 | OPCD | RST | RI | XO |/| */
1156 gen_xfx_form (uint32_t *buf
, int opcd
, int rst
, int ri
, int xo
)
1159 unsigned int n
= ((ri
& 0x1f) << 5) | ((ri
>> 5) & 0x1f);
1161 gdb_assert ((opcd
& ~0x3f) == 0);
1162 gdb_assert ((rst
& ~0x1f) == 0);
1163 gdb_assert ((xo
& ~0x3ff) == 0);
1165 insn
= (rst
<< 21) | (n
<< 11) | (xo
<< 1);
1166 *buf
= (opcd
<< 26) | insn
;
1170 /* Followings are frequently used xfx-form instructions. */
1172 #define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
1173 #define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
1174 #define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
1175 #define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
1176 #define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
1178 #define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
1181 /* Generate a x-form instruction in BUF and return the number of bytes written.
1184 | OPCD | RST | RA | RB | XO |RC| */
1187 gen_x_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int rb
, int xo
, int rc
)
1191 gdb_assert ((opcd
& ~0x3f) == 0);
1192 gdb_assert ((rst
& ~0x1f) == 0);
1193 gdb_assert ((ra
& ~0x1f) == 0);
1194 gdb_assert ((rb
& ~0x1f) == 0);
1195 gdb_assert ((xo
& ~0x3ff) == 0);
1196 gdb_assert ((rc
& ~1) == 0);
1198 insn
= (rst
<< 21) | (ra
<< 16) | (rb
<< 11) | (xo
<< 1) | rc
;
1199 *buf
= (opcd
<< 26) | insn
;
1203 /* Followings are frequently used x-form instructions. */
1205 #define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
1206 #define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
1207 #define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
1208 #define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
1209 /* Assume bf = cr7. */
1210 #define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
1213 /* Generate a md-form instruction in BUF and return the number of bytes written.
1215 0 6 11 16 21 27 30 31 32
1216 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
1219 gen_md_form (uint32_t *buf
, int opcd
, int rs
, int ra
, int sh
, int mb
,
1223 unsigned int n
= ((mb
& 0x1f) << 1) | ((mb
>> 5) & 0x1);
1224 unsigned int sh0_4
= sh
& 0x1f;
1225 unsigned int sh5
= (sh
>> 5) & 1;
1227 gdb_assert ((opcd
& ~0x3f) == 0);
1228 gdb_assert ((rs
& ~0x1f) == 0);
1229 gdb_assert ((ra
& ~0x1f) == 0);
1230 gdb_assert ((sh
& ~0x3f) == 0);
1231 gdb_assert ((mb
& ~0x3f) == 0);
1232 gdb_assert ((xo
& ~0x7) == 0);
1233 gdb_assert ((rc
& ~0x1) == 0);
1235 insn
= (rs
<< 21) | (ra
<< 16) | (sh0_4
<< 11) | (n
<< 5)
1236 | (sh5
<< 1) | (xo
<< 2) | (rc
& 1);
1237 *buf
= (opcd
<< 26) | insn
;
1241 /* The following are frequently used md-form instructions. */
1243 #define GEN_RLDICL(buf, ra, rs ,sh, mb) \
1244 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
1245 #define GEN_RLDICR(buf, ra, rs ,sh, mb) \
1246 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
1248 /* Generate a i-form instruction in BUF and return the number of bytes written.
1251 | OPCD | LI |AA|LK| */
1254 gen_i_form (uint32_t *buf
, int opcd
, int li
, int aa
, int lk
)
1258 gdb_assert ((opcd
& ~0x3f) == 0);
1260 insn
= (li
& 0x3fffffc) | (aa
& 1) | (lk
& 1);
1261 *buf
= (opcd
<< 26) | insn
;
1265 /* The following are frequently used i-form instructions. */
1267 #define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
1268 #define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
1270 /* Generate a b-form instruction in BUF and return the number of bytes written.
1273 | OPCD | BO | BI | BD |AA|LK| */
1276 gen_b_form (uint32_t *buf
, int opcd
, int bo
, int bi
, int bd
,
1281 gdb_assert ((opcd
& ~0x3f) == 0);
1282 gdb_assert ((bo
& ~0x1f) == 0);
1283 gdb_assert ((bi
& ~0x1f) == 0);
1285 insn
= (bo
<< 21) | (bi
<< 16) | (bd
& 0xfffc) | (aa
& 1) | (lk
& 1);
1286 *buf
= (opcd
<< 26) | insn
;
1290 /* The following are frequently used b-form instructions. */
1291 /* Assume bi = cr7. */
1292 #define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
1294 /* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
1295 respectively. They are primary used for save/restore GPRs in jump-pad,
1296 not used for bytecode compiling. */
1298 #ifdef __powerpc64__
1299 #define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
1300 GEN_LD (buf, rt, ra, si) : \
1301 GEN_LWZ (buf, rt, ra, si))
1302 #define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
1303 GEN_STD (buf, rt, ra, si) : \
1304 GEN_STW (buf, rt, ra, si))
1306 #define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
1307 #define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
1310 /* Generate a sequence of instructions to load IMM in the register REG.
1311 Write the instructions in BUF and return the number of bytes written. */
1314 gen_limm (uint32_t *buf
, int reg
, uint64_t imm
, int is_64
)
1318 if ((imm
+ 32768) < 65536)
1320 /* li reg, imm[15:0] */
1321 p
+= GEN_LI (p
, reg
, imm
);
1323 else if ((imm
>> 32) == 0)
1325 /* lis reg, imm[31:16]
1326 ori reg, reg, imm[15:0]
1327 rldicl reg, reg, 0, 32 */
1328 p
+= GEN_LIS (p
, reg
, (imm
>> 16) & 0xffff);
1329 if ((imm
& 0xffff) != 0)
1330 p
+= GEN_ORI (p
, reg
, reg
, imm
& 0xffff);
1331 /* Clear upper 32-bit if sign-bit is set. */
1332 if (imm
& (1u << 31) && is_64
)
1333 p
+= GEN_RLDICL (p
, reg
, reg
, 0, 32);
1338 /* lis reg, <imm[63:48]>
1339 ori reg, reg, <imm[48:32]>
1340 rldicr reg, reg, 32, 31
1341 oris reg, reg, <imm[31:16]>
1342 ori reg, reg, <imm[15:0]> */
1343 p
+= GEN_LIS (p
, reg
, ((imm
>> 48) & 0xffff));
1344 if (((imm
>> 32) & 0xffff) != 0)
1345 p
+= GEN_ORI (p
, reg
, reg
, ((imm
>> 32) & 0xffff));
1346 p
+= GEN_RLDICR (p
, reg
, reg
, 32, 31);
1347 if (((imm
>> 16) & 0xffff) != 0)
1348 p
+= GEN_ORIS (p
, reg
, reg
, ((imm
>> 16) & 0xffff));
1349 if ((imm
& 0xffff) != 0)
1350 p
+= GEN_ORI (p
, reg
, reg
, (imm
& 0xffff));
1356 /* Generate a sequence for atomically exchange at location LOCK.
1357 This code sequence clobbers r6, r7, r8. LOCK is the location for
1358 the atomic-xchg, OLD_VALUE is expected old value stored in the
1359 location, and R_NEW is a register for the new value. */
1362 gen_atomic_xchg (uint32_t *buf
, CORE_ADDR lock
, int old_value
, int r_new
,
1365 const int r_lock
= 6;
1366 const int r_old
= 7;
1367 const int r_tmp
= 8;
1371 1: lwarx TMP, 0, LOCK
1377 p
+= gen_limm (p
, r_lock
, lock
, is_64
);
1378 p
+= gen_limm (p
, r_old
, old_value
, is_64
);
1380 p
+= GEN_LWARX (p
, r_tmp
, 0, r_lock
);
1381 p
+= GEN_CMPW (p
, r_tmp
, r_old
);
1382 p
+= GEN_BNE (p
, -8);
1383 p
+= GEN_STWCX (p
, r_new
, 0, r_lock
);
1384 p
+= GEN_BNE (p
, -16);
1389 /* Generate a sequence of instructions for calling a function
1390 at address of FN. Return the number of bytes are written in BUF. */
1393 gen_call (uint32_t *buf
, CORE_ADDR fn
, int is_64
, int is_opd
)
1397 /* Must be called by r12 for caller to calculate TOC address. */
1398 p
+= gen_limm (p
, 12, fn
, is_64
);
1401 p
+= GEN_LOAD (p
, 11, 12, 16, is_64
);
1402 p
+= GEN_LOAD (p
, 2, 12, 8, is_64
);
1403 p
+= GEN_LOAD (p
, 12, 12, 0, is_64
);
1405 p
+= GEN_MTSPR (p
, 12, 9); /* mtctr r12 */
1406 *p
++ = 0x4e800421; /* bctrl */
1411 /* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1412 of instruction. This function is used to adjust pc-relative instructions
1416 ppc_relocate_instruction (CORE_ADDR
*to
, CORE_ADDR oldloc
)
1421 read_inferior_memory (oldloc
, (unsigned char *) &insn
, 4);
1422 op6
= PPC_OP6 (insn
);
1424 if (op6
== 18 && (insn
& 2) == 0)
1426 /* branch && AA = 0 */
1427 rel
= PPC_LI (insn
);
1428 newrel
= (oldloc
- *to
) + rel
;
1430 /* Out of range. Cannot relocate instruction. */
1431 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1434 insn
= (insn
& ~0x3fffffc) | (newrel
& 0x3fffffc);
1436 else if (op6
== 16 && (insn
& 2) == 0)
1438 /* conditional branch && AA = 0 */
1440 /* If the new relocation is too big for even a 26-bit unconditional
1441 branch, there is nothing we can do. Just abort.
1443 Otherwise, if it can be fit in 16-bit conditional branch, just
1444 copy the instruction and relocate the address.
1446 If the it's big for conditional-branch (16-bit), try to invert the
1447 condition and jump with 26-bit branch. For example,
1458 After this transform, we are actually jump from *TO+4 instead of *TO,
1459 so check the relocation again because it will be 1-insn farther then
1460 before if *TO is after OLDLOC.
1463 For BDNZT (or so) is transformed from
1475 See also "BO field encodings". */
1477 rel
= PPC_BD (insn
);
1478 newrel
= (oldloc
- *to
) + rel
;
1480 if (newrel
< (1 << 15) && newrel
>= -(1 << 15))
1481 insn
= (insn
& ~0xfffc) | (newrel
& 0xfffc);
1482 else if ((PPC_BO (insn
) & 0x14) == 0x4 || (PPC_BO (insn
) & 0x14) == 0x10)
1486 /* Out of range. Cannot relocate instruction. */
1487 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1490 if ((PPC_BO (insn
) & 0x14) == 0x4)
1492 else if ((PPC_BO (insn
) & 0x14) == 0x10)
1495 /* Jump over the unconditional branch. */
1496 insn
= (insn
& ~0xfffc) | 0x8;
1497 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1500 /* Build a unconditional branch and copy LK bit. */
1501 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1502 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1507 else if ((PPC_BO (insn
) & 0x14) == 0)
1509 uint32_t bdnz_insn
= (16 << 26) | (0x10 << 21) | 12;
1510 uint32_t bf_insn
= (16 << 26) | (0x4 << 21) | 8;
1514 /* Out of range. Cannot relocate instruction. */
1515 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1518 /* Copy BI field. */
1519 bf_insn
|= (insn
& 0x1f0000);
1521 /* Invert condition. */
1522 bdnz_insn
|= (insn
^ (1 << 22)) & (1 << 22);
1523 bf_insn
|= (insn
^ (1 << 24)) & (1 << 24);
1525 target_write_memory (*to
, (unsigned char *) &bdnz_insn
, 4);
1527 target_write_memory (*to
, (unsigned char *) &bf_insn
, 4);
1530 /* Build a unconditional branch and copy LK bit. */
1531 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1532 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1537 else /* (BO & 0x14) == 0x14, branch always. */
1539 /* Out of range. Cannot relocate instruction. */
1540 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1543 /* Build a unconditional branch and copy LK bit. */
1544 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1545 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1552 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1556 /* Implement install_fast_tracepoint_jump_pad of target_ops.
1557 See target.h for details. */
1560 ppc_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1561 CORE_ADDR collector
,
1564 CORE_ADDR
*jump_entry
,
1565 CORE_ADDR
*trampoline
,
1566 ULONGEST
*trampoline_size
,
1567 unsigned char *jjump_pad_insn
,
1568 ULONGEST
*jjump_pad_insn_size
,
1569 CORE_ADDR
*adjusted_insn_addr
,
1570 CORE_ADDR
*adjusted_insn_addr_end
,
1576 CORE_ADDR buildaddr
= *jump_entry
;
1577 const CORE_ADDR entryaddr
= *jump_entry
;
1578 int rsz
, min_frame
, frame_size
, tp_reg
;
1579 #ifdef __powerpc64__
1580 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
1581 int is_64
= register_size (regcache
->tdesc
, 0) == 8;
1582 int is_opd
= is_64
&& !is_elfv2_inferior ();
1584 int is_64
= 0, is_opd
= 0;
1587 #ifdef __powerpc64__
1590 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1593 frame_size
= (40 * rsz
) + min_frame
;
1601 frame_size
= (40 * rsz
) + min_frame
;
1603 #ifdef __powerpc64__
1607 /* Stack frame layout for this jump pad,
1609 High thread_area (r13/r2) |
1610 tpoint - collecting_t obj
1620 R0 - collected registers
1626 The code flow of this jump pad,
1631 4. Call gdb_collector
1632 5. Restore GPR and SPR
1634 7. Build a jump for back to the program
1635 8. Copy/relocate original instruction
1636 9. Build a jump for replacing original instruction. */
1638 /* Adjust stack pointer. */
1640 p
+= GEN_STDU (p
, 1, 1, -frame_size
); /* stdu r1,-frame_size(r1) */
1642 p
+= GEN_STWU (p
, 1, 1, -frame_size
); /* stwu r1,-frame_size(r1) */
1644 /* Store GPRs. Save R1 later, because it had just been modified, but
1645 we want the original value. */
1646 for (j
= 2; j
< 32; j
++)
1647 p
+= GEN_STORE (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1648 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1649 /* Set r0 to the original value of r1 before adjusting stack frame,
1650 and then save it. */
1651 p
+= GEN_ADDI (p
, 0, 1, frame_size
);
1652 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 1 * rsz
, is_64
);
1654 /* Save CR, XER, LR, and CTR. */
1655 p
+= GEN_MFCR (p
, 3); /* mfcr r3 */
1656 p
+= GEN_MFSPR (p
, 4, 1); /* mfxer r4 */
1657 p
+= GEN_MFSPR (p
, 5, 8); /* mflr r5 */
1658 p
+= GEN_MFSPR (p
, 6, 9); /* mfctr r6 */
1659 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
);/* std r3, 32(r1) */
1660 p
+= GEN_STORE (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
);/* std r4, 33(r1) */
1661 p
+= GEN_STORE (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
);/* std r5, 34(r1) */
1662 p
+= GEN_STORE (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
);/* std r6, 35(r1) */
1664 /* Save PC<tpaddr> */
1665 p
+= gen_limm (p
, 3, tpaddr
, is_64
);
1666 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 36 * rsz
, is_64
);
1669 /* Setup arguments to collector. */
1670 /* Set r4 to collected registers. */
1671 p
+= GEN_ADDI (p
, 4, 1, min_frame
);
1672 /* Set r3 to TPOINT. */
1673 p
+= gen_limm (p
, 3, tpoint
, is_64
);
1675 /* Prepare collecting_t object for lock. */
1676 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 37 * rsz
, is_64
);
1677 p
+= GEN_STORE (p
, tp_reg
, 1, min_frame
+ 38 * rsz
, is_64
);
1678 /* Set R5 to collecting object. */
1679 p
+= GEN_ADDI (p
, 5, 1, 37 * rsz
);
1681 p
+= GEN_LWSYNC (p
);
1682 p
+= gen_atomic_xchg (p
, lockaddr
, 0, 5, is_64
);
1683 p
+= GEN_LWSYNC (p
);
1685 /* Call to collector. */
1686 p
+= gen_call (p
, collector
, is_64
, is_opd
);
1688 /* Simply write 0 to release the lock. */
1689 p
+= gen_limm (p
, 3, lockaddr
, is_64
);
1690 p
+= gen_limm (p
, 4, 0, is_64
);
1691 p
+= GEN_LWSYNC (p
);
1692 p
+= GEN_STORE (p
, 4, 3, 0, is_64
);
1694 /* Restore stack and registers. */
1695 p
+= GEN_LOAD (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
); /* ld r3, 32(r1) */
1696 p
+= GEN_LOAD (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
); /* ld r4, 33(r1) */
1697 p
+= GEN_LOAD (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
); /* ld r5, 34(r1) */
1698 p
+= GEN_LOAD (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
); /* ld r6, 35(r1) */
1699 p
+= GEN_MTCR (p
, 3); /* mtcr r3 */
1700 p
+= GEN_MTSPR (p
, 4, 1); /* mtxer r4 */
1701 p
+= GEN_MTSPR (p
, 5, 8); /* mtlr r5 */
1702 p
+= GEN_MTSPR (p
, 6, 9); /* mtctr r6 */
1705 for (j
= 2; j
< 32; j
++)
1706 p
+= GEN_LOAD (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1707 p
+= GEN_LOAD (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1709 p
+= GEN_ADDI (p
, 1, 1, frame_size
);
1711 /* Flush instructions to inferior memory. */
1712 target_write_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1714 /* Now, insert the original instruction to execute in the jump pad. */
1715 *adjusted_insn_addr
= buildaddr
+ (p
- buf
) * 4;
1716 *adjusted_insn_addr_end
= *adjusted_insn_addr
;
1717 ppc_relocate_instruction (adjusted_insn_addr_end
, tpaddr
);
1719 /* Verify the relocation size. If should be 4 for normal copy,
1720 8 or 12 for some conditional branch. */
1721 if ((*adjusted_insn_addr_end
- *adjusted_insn_addr
== 0)
1722 || (*adjusted_insn_addr_end
- *adjusted_insn_addr
> 12))
1724 sprintf (err
, "E.Unexpected instruction length = %d"
1725 "when relocate instruction.",
1726 (int) (*adjusted_insn_addr_end
- *adjusted_insn_addr
));
1730 buildaddr
= *adjusted_insn_addr_end
;
1732 /* Finally, write a jump back to the program. */
1733 offset
= (tpaddr
+ 4) - buildaddr
;
1734 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1736 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1737 "(offset 0x%x > 26-bit).", offset
);
1741 p
+= GEN_B (p
, offset
);
1742 target_write_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1743 *jump_entry
= buildaddr
+ (p
- buf
) * 4;
1745 /* The jump pad is now built. Wire in a jump to our jump pad. This
1746 is always done last (by our caller actually), so that we can
1747 install fast tracepoints with threads running. This relies on
1748 the agent's atomic write support. */
1749 offset
= entryaddr
- tpaddr
;
1750 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1752 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1753 "(offset 0x%x > 26-bit).", offset
);
1757 GEN_B ((uint32_t *) jjump_pad_insn
, offset
);
1758 *jjump_pad_insn_size
= 4;
1763 /* Returns the minimum instruction length for installing a tracepoint. */
1766 ppc_get_min_fast_tracepoint_insn_len (void)
1771 /* Emits a given buffer into the target at current_insn_ptr. Length
1772 is in units of 32-bit words. */
1775 emit_insns (uint32_t *buf
, int n
)
1777 n
= n
* sizeof (uint32_t);
1778 target_write_memory (current_insn_ptr
, (unsigned char *) buf
, n
);
1779 current_insn_ptr
+= n
;
1782 #define __EMIT_ASM(NAME, INSNS) \
1785 extern uint32_t start_bcax_ ## NAME []; \
1786 extern uint32_t end_bcax_ ## NAME []; \
1787 emit_insns (start_bcax_ ## NAME, \
1788 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1789 __asm__ (".section .text.__ppcbcax\n\t" \
1790 "start_bcax_" #NAME ":\n\t" \
1792 "end_bcax_" #NAME ":\n\t" \
1796 #define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1797 #define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1801 Bytecode execution stack frame - 32-bit
1803 | LR save area (SP + 4)
1804 SP' -> +- Back chain (SP + 0)
1805 | Save r31 for access saved arguments
1806 | Save r30 for bytecode stack pointer
1807 | Save r4 for incoming argument *value
1808 | Save r3 for incoming argument regs
1809 r30 -> +- Bytecode execution stack
1811 | 64-byte (8 doublewords) at initial.
1812 | Expand stack as needed.
1815 | Some padding for minimum stack frame and 16-byte alignment.
1817 SP +- Back-chain (SP')
1823 r30 is the stack-pointer for bytecode machine.
1824 It should point to next-empty, so we can use LDU for pop.
1825 r3 is used for cache of the high part of TOP value.
1826 It was the first argument, pointer to regs.
1827 r4 is used for cache of the low part of TOP value.
1828 It was the second argument, pointer to the result.
1829 We should set *result = TOP after leaving this function.
1832 * To restore stack at epilogue
1834 * To check stack is big enough for bytecode execution.
1836 * To return execution result.
1841 /* Regardless of endian, register 3 is always high part, 4 is low part.
1842 These defines are used when the register pair is stored/loaded.
1843 Likewise, to simplify code, have a similiar define for 5:6. */
1845 #if __BYTE_ORDER == __LITTLE_ENDIAN
1846 #define TOP_FIRST "4"
1847 #define TOP_SECOND "3"
1848 #define TMP_FIRST "6"
1849 #define TMP_SECOND "5"
1851 #define TOP_FIRST "3"
1852 #define TOP_SECOND "4"
1853 #define TMP_FIRST "5"
1854 #define TMP_SECOND "6"
1857 /* Emit prologue in inferior memory. See above comments. */
1860 ppc_emit_prologue (void)
1862 EMIT_ASM (/* Save return address. */
1865 /* Adjust SP. 96 is the initial frame size. */
1867 /* Save r30 and incoming arguments. */
1868 "stw 31, 96-4(1) \n"
1869 "stw 30, 96-8(1) \n"
1870 "stw 4, 96-12(1) \n"
1871 "stw 3, 96-16(1) \n"
1872 /* Point r31 to original r1 for access arguments. */
1874 /* Set r30 to pointing stack-top. */
1876 /* Initial r3/TOP to 0. */
1881 /* Emit epilogue in inferior memory. See above comments. */
1884 ppc_emit_epilogue (void)
1886 EMIT_ASM (/* *result = TOP */
1888 "stw " TOP_FIRST
", 0(5) \n"
1889 "stw " TOP_SECOND
", 4(5) \n"
1890 /* Restore registers. */
1897 /* Return 0 for no-error. */
1903 /* TOP = stack[--sp] + TOP */
1908 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1909 "lwz " TMP_SECOND
", 4(30)\n"
1914 /* TOP = stack[--sp] - TOP */
1919 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1920 "lwz " TMP_SECOND
", 4(30) \n"
1922 "subfe 3, 3, 5 \n");
1925 /* TOP = stack[--sp] * TOP */
1930 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1931 "lwz " TMP_SECOND
", 4(30) \n"
1940 /* TOP = stack[--sp] << TOP */
1945 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1946 "lwz " TMP_SECOND
", 4(30) \n"
1947 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1948 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1949 "slw 5, 5, 4\n" /* Shift high part left */
1950 "slw 4, 6, 4\n" /* Shift low part left */
1951 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
1952 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
1954 "or 3, 7, 3\n"); /* Assemble high part */
1957 /* Top = stack[--sp] >> TOP
1958 (Arithmetic shift right) */
1961 ppc_emit_rsh_signed (void)
1963 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1964 "lwz " TMP_SECOND
", 4(30) \n"
1965 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1966 "sraw 3, 5, 4\n" /* Shift high part right */
1968 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
1969 "sraw 4, 5, 7\n" /* Shift high to low */
1972 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
1973 "srw 4, 6, 4\n" /* Shift low part right */
1974 "slw 5, 5, 7\n" /* Shift high to low */
1975 "or 4, 4, 5\n" /* Assemble low part */
1979 /* Top = stack[--sp] >> TOP
1980 (Logical shift right) */
1983 ppc_emit_rsh_unsigned (void)
1985 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1986 "lwz " TMP_SECOND
", 4(30) \n"
1987 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1988 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1989 "srw 6, 6, 4\n" /* Shift low part right */
1990 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
1991 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
1993 "srw 3, 5, 4\n" /* Shift high part right */
1994 "or 4, 6, 7\n"); /* Assemble low part */
1997 /* Emit code for signed-extension specified by ARG. */
2000 ppc_emit_ext (int arg
)
2005 EMIT_ASM ("extsb 4, 4\n"
2009 EMIT_ASM ("extsh 4, 4\n"
2013 EMIT_ASM ("srawi 3, 4, 31");
2020 /* Emit code for zero-extension specified by ARG. */
2023 ppc_emit_zero_ext (int arg
)
2028 EMIT_ASM ("clrlwi 4,4,24\n"
2032 EMIT_ASM ("clrlwi 4,4,16\n"
2036 EMIT_ASM ("li 3, 0");
2044 i.e., TOP = (TOP == 0) ? 1 : 0; */
2047 ppc_emit_log_not (void)
2049 EMIT_ASM ("or 4, 3, 4 \n"
2055 /* TOP = stack[--sp] & TOP */
2058 ppc_emit_bit_and (void)
2060 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2061 "lwz " TMP_SECOND
", 4(30) \n"
2066 /* TOP = stack[--sp] | TOP */
2069 ppc_emit_bit_or (void)
2071 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2072 "lwz " TMP_SECOND
", 4(30) \n"
2077 /* TOP = stack[--sp] ^ TOP */
2080 ppc_emit_bit_xor (void)
2082 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2083 "lwz " TMP_SECOND
", 4(30) \n"
2089 i.e., TOP = ~(TOP | TOP) */
2092 ppc_emit_bit_not (void)
2094 EMIT_ASM ("nor 3, 3, 3 \n"
2098 /* TOP = stack[--sp] == TOP */
2101 ppc_emit_equal (void)
2103 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2104 "lwz " TMP_SECOND
", 4(30) \n"
2113 /* TOP = stack[--sp] < TOP
2114 (Signed comparison) */
2117 ppc_emit_less_signed (void)
2119 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2120 "lwz " TMP_SECOND
", 4(30) \n"
2123 /* CR6 bit 0 = low less and high equal */
2124 "crand 6*4+0, 6*4+0, 7*4+2\n"
2125 /* CR7 bit 0 = (low less and high equal) or high less */
2126 "cror 7*4+0, 7*4+0, 6*4+0\n"
2128 "rlwinm 4, 4, 29, 31, 31 \n"
2132 /* TOP = stack[--sp] < TOP
2133 (Unsigned comparison) */
2136 ppc_emit_less_unsigned (void)
2138 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2139 "lwz " TMP_SECOND
", 4(30) \n"
2142 /* CR6 bit 0 = low less and high equal */
2143 "crand 6*4+0, 6*4+0, 7*4+2\n"
2144 /* CR7 bit 0 = (low less and high equal) or high less */
2145 "cror 7*4+0, 7*4+0, 6*4+0\n"
2147 "rlwinm 4, 4, 29, 31, 31 \n"
2151 /* Access the memory address in TOP in size of SIZE.
2152 Zero-extend the read value. */
2155 ppc_emit_ref (int size
)
2160 EMIT_ASM ("lbz 4, 0(4)\n"
2164 EMIT_ASM ("lhz 4, 0(4)\n"
2168 EMIT_ASM ("lwz 4, 0(4)\n"
2172 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2173 EMIT_ASM ("lwz 3, 4(4)\n"
2176 EMIT_ASM ("lwz 3, 0(4)\n"
2185 ppc_emit_const (LONGEST num
)
2190 p
+= gen_limm (p
, 3, num
>> 32 & 0xffffffff, 0);
2191 p
+= gen_limm (p
, 4, num
& 0xffffffff, 0);
2193 emit_insns (buf
, p
- buf
);
2194 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2197 /* Set TOP to the value of register REG by calling get_raw_reg function
2198 with two argument, collected buffer and register number. */
2201 ppc_emit_reg (int reg
)
2206 /* fctx->regs is passed in r3 and then saved in -16(31). */
2207 p
+= GEN_LWZ (p
, 3, 31, -16);
2208 p
+= GEN_LI (p
, 4, reg
); /* li r4, reg */
2209 p
+= gen_call (p
, get_raw_reg_func_addr (), 0, 0);
2211 emit_insns (buf
, p
- buf
);
2212 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2214 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2216 EMIT_ASM ("mr 5, 4\n"
2222 /* TOP = stack[--sp] */
2227 EMIT_ASM ("lwzu " TOP_FIRST
", 8(30) \n"
2228 "lwz " TOP_SECOND
", 4(30) \n");
2231 /* stack[sp++] = TOP
2233 Because we may use up bytecode stack, expand 8 doublewords more
2237 ppc_emit_stack_flush (void)
2239 /* Make sure bytecode stack is big enough before push.
2240 Otherwise, expand 64-byte more. */
2242 EMIT_ASM (" stw " TOP_FIRST
", 0(30) \n"
2243 " stw " TOP_SECOND
", 4(30)\n"
2244 " addi 5, 30, -(8 + 8) \n"
2247 " stwu 31, -64(1) \n"
2248 "1:addi 30, 30, -8 \n");
2251 /* Swap TOP and stack[sp-1] */
2254 ppc_emit_swap (void)
2256 EMIT_ASM ("lwz " TMP_FIRST
", 8(30) \n"
2257 "lwz " TMP_SECOND
", 12(30) \n"
2258 "stw " TOP_FIRST
", 8(30) \n"
2259 "stw " TOP_SECOND
", 12(30) \n"
2264 /* Discard N elements in the stack. Also used for ppc64. */
2267 ppc_emit_stack_adjust (int n
)
2279 p
+= GEN_ADDI (p
, 30, 30, n
);
2281 emit_insns (buf
, p
- buf
);
2282 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2285 /* Call function FN. */
2288 ppc_emit_call (CORE_ADDR fn
)
2293 p
+= gen_call (p
, fn
, 0, 0);
2295 emit_insns (buf
, p
- buf
);
2296 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2299 /* FN's prototype is `LONGEST(*fn)(int)'.
2304 ppc_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2309 /* Setup argument. arg1 is a 16-bit value. */
2310 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2311 p
+= gen_call (p
, fn
, 0, 0);
2313 emit_insns (buf
, p
- buf
);
2314 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2316 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2318 EMIT_ASM ("mr 5, 4\n"
2324 /* FN's prototype is `void(*fn)(int,LONGEST)'.
2327 TOP should be preserved/restored before/after the call. */
2330 ppc_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2335 /* Save TOP. 0(30) is next-empty. */
2336 p
+= GEN_STW (p
, 3, 30, 0);
2337 p
+= GEN_STW (p
, 4, 30, 4);
2339 /* Setup argument. arg1 is a 16-bit value. */
2340 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2342 p
+= GEN_MR (p
, 5, 4);
2343 p
+= GEN_MR (p
, 6, 3);
2347 p
+= GEN_MR (p
, 5, 3);
2348 p
+= GEN_MR (p
, 6, 4);
2350 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2351 p
+= gen_call (p
, fn
, 0, 0);
2354 p
+= GEN_LWZ (p
, 3, 30, 0);
2355 p
+= GEN_LWZ (p
, 4, 30, 4);
2357 emit_insns (buf
, p
- buf
);
2358 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2361 /* Note in the following goto ops:
2363 When emitting goto, the target address is later relocated by
2364 write_goto_address. OFFSET_P is the offset of the branch instruction
2365 in the code sequence, and SIZE_P is how to relocate the instruction,
2366 recognized by ppc_write_goto_address. In current implementation,
2367 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2370 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2373 ppc_emit_if_goto (int *offset_p
, int *size_p
)
2375 EMIT_ASM ("or. 3, 3, 4 \n"
2376 "lwzu " TOP_FIRST
", 8(30) \n"
2377 "lwz " TOP_SECOND
", 4(30) \n"
2386 /* Unconditional goto. Also used for ppc64. */
2389 ppc_emit_goto (int *offset_p
, int *size_p
)
2391 EMIT_ASM ("1:b 1b");
2399 /* Goto if stack[--sp] == TOP */
2402 ppc_emit_eq_goto (int *offset_p
, int *size_p
)
2404 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2405 "lwz " TMP_SECOND
", 4(30) \n"
2409 "lwzu " TOP_FIRST
", 8(30) \n"
2410 "lwz " TOP_SECOND
", 4(30) \n"
2419 /* Goto if stack[--sp] != TOP */
2422 ppc_emit_ne_goto (int *offset_p
, int *size_p
)
2424 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2425 "lwz " TMP_SECOND
", 4(30) \n"
2429 "lwzu " TOP_FIRST
", 8(30) \n"
2430 "lwz " TOP_SECOND
", 4(30) \n"
2439 /* Goto if stack[--sp] < TOP */
2442 ppc_emit_lt_goto (int *offset_p
, int *size_p
)
2444 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2445 "lwz " TMP_SECOND
", 4(30) \n"
2448 /* CR6 bit 0 = low less and high equal */
2449 "crand 6*4+0, 6*4+0, 7*4+2\n"
2450 /* CR7 bit 0 = (low less and high equal) or high less */
2451 "cror 7*4+0, 7*4+0, 6*4+0\n"
2452 "lwzu " TOP_FIRST
", 8(30) \n"
2453 "lwz " TOP_SECOND
", 4(30)\n"
2462 /* Goto if stack[--sp] <= TOP */
2465 ppc_emit_le_goto (int *offset_p
, int *size_p
)
2467 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2468 "lwz " TMP_SECOND
", 4(30) \n"
2471 /* CR6 bit 0 = low less/equal and high equal */
2472 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2473 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2474 "cror 7*4+0, 7*4+0, 6*4+0\n"
2475 "lwzu " TOP_FIRST
", 8(30) \n"
2476 "lwz " TOP_SECOND
", 4(30)\n"
2485 /* Goto if stack[--sp] > TOP */
2488 ppc_emit_gt_goto (int *offset_p
, int *size_p
)
2490 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2491 "lwz " TMP_SECOND
", 4(30) \n"
2494 /* CR6 bit 0 = low greater and high equal */
2495 "crand 6*4+0, 6*4+1, 7*4+2\n"
2496 /* CR7 bit 0 = (low greater and high equal) or high greater */
2497 "cror 7*4+0, 7*4+1, 6*4+0\n"
2498 "lwzu " TOP_FIRST
", 8(30) \n"
2499 "lwz " TOP_SECOND
", 4(30)\n"
2508 /* Goto if stack[--sp] >= TOP */
2511 ppc_emit_ge_goto (int *offset_p
, int *size_p
)
2513 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2514 "lwz " TMP_SECOND
", 4(30) \n"
2517 /* CR6 bit 0 = low ge and high equal */
2518 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2519 /* CR7 bit 0 = (low ge and high equal) or high greater */
2520 "cror 7*4+0, 7*4+1, 6*4+0\n"
2521 "lwzu " TOP_FIRST
", 8(30)\n"
2522 "lwz " TOP_SECOND
", 4(30)\n"
2531 /* Relocate previous emitted branch instruction. FROM is the address
2532 of the branch instruction, TO is the goto target address, and SIZE
2533 if the value we set by *SIZE_P before. Currently, it is either
2534 24 or 14 of branch and conditional-branch instruction.
2535 Also used for ppc64. */
2538 ppc_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2540 long rel
= to
- from
;
2544 read_inferior_memory (from
, (unsigned char *) &insn
, 4);
2545 opcd
= (insn
>> 26) & 0x3f;
2551 || (rel
>= (1 << 15) || rel
< -(1 << 15)))
2553 insn
= (insn
& ~0xfffc) | (rel
& 0xfffc);
2557 || (rel
>= (1 << 25) || rel
< -(1 << 25)))
2559 insn
= (insn
& ~0x3fffffc) | (rel
& 0x3fffffc);
2566 target_write_memory (from
, (unsigned char *) &insn
, 4);
2569 /* Table of emit ops for 32-bit. */
2571 static struct emit_ops ppc_emit_ops_impl
=
2579 ppc_emit_rsh_signed
,
2580 ppc_emit_rsh_unsigned
,
2588 ppc_emit_less_signed
,
2589 ppc_emit_less_unsigned
,
2593 ppc_write_goto_address
,
2598 ppc_emit_stack_flush
,
2601 ppc_emit_stack_adjust
,
2602 ppc_emit_int_call_1
,
2603 ppc_emit_void_call_2
,
2612 #ifdef __powerpc64__
2616 Bytecode execution stack frame - 64-bit
2618 | LR save area (SP + 16)
2619 | CR save area (SP + 8)
2620 SP' -> +- Back chain (SP + 0)
2621 | Save r31 for access saved arguments
2622 | Save r30 for bytecode stack pointer
2623 | Save r4 for incoming argument *value
2624 | Save r3 for incoming argument regs
2625 r30 -> +- Bytecode execution stack
2627 | 64-byte (8 doublewords) at initial.
2628 | Expand stack as needed.
2631 | Some padding for minimum stack frame.
2633 SP +- Back-chain (SP')
2636 = 112 + (4 * 8) + 64
2639 r30 is the stack-pointer for bytecode machine.
2640 It should point to next-empty, so we can use LDU for pop.
2641 r3 is used for cache of TOP value.
2642 It was the first argument, pointer to regs.
2643 r4 is the second argument, pointer to the result.
2644 We should set *result = TOP after leaving this function.
2647 * To restore stack at epilogue
2649 * To check stack is big enough for bytecode execution.
2650 => r30 - 8 > SP + 112
2651 * To return execution result.
2656 /* Emit prologue in inferior memory. See above comments. */
2659 ppc64v1_emit_prologue (void)
2661 /* On ELFv1, function pointers really point to function descriptor,
2662 so emit one here. We don't care about contents of words 1 and 2,
2663 so let them just overlap out code. */
2664 uint64_t opd
= current_insn_ptr
+ 8;
2667 /* Mind the strict aliasing rules. */
2668 memcpy (buf
, &opd
, sizeof buf
);
2670 EMIT_ASM (/* Save return address. */
2673 /* Save r30 and incoming arguments. */
2678 /* Point r31 to current r1 for access arguments. */
2680 /* Adjust SP. 208 is the initial frame size. */
2681 "stdu 1, -208(1) \n"
2682 /* Set r30 to pointing stack-top. */
2683 "addi 30, 1, 168 \n"
2684 /* Initial r3/TOP to 0. */
2688 /* Emit prologue in inferior memory. See above comments. */
2691 ppc64v2_emit_prologue (void)
2693 EMIT_ASM (/* Save return address. */
2696 /* Save r30 and incoming arguments. */
2701 /* Point r31 to current r1 for access arguments. */
2703 /* Adjust SP. 208 is the initial frame size. */
2704 "stdu 1, -208(1) \n"
2705 /* Set r30 to pointing stack-top. */
2706 "addi 30, 1, 168 \n"
2707 /* Initial r3/TOP to 0. */
2711 /* Emit epilogue in inferior memory. See above comments. */
2714 ppc64_emit_epilogue (void)
2716 EMIT_ASM (/* Restore SP. */
2721 /* Restore registers. */
2726 /* Return 0 for no-error. */
2732 /* TOP = stack[--sp] + TOP */
2735 ppc64_emit_add (void)
2737 EMIT_ASM ("ldu 4, 8(30) \n"
2741 /* TOP = stack[--sp] - TOP */
2744 ppc64_emit_sub (void)
2746 EMIT_ASM ("ldu 4, 8(30) \n"
2750 /* TOP = stack[--sp] * TOP */
2753 ppc64_emit_mul (void)
2755 EMIT_ASM ("ldu 4, 8(30) \n"
2756 "mulld 3, 4, 3 \n");
2759 /* TOP = stack[--sp] << TOP */
2762 ppc64_emit_lsh (void)
2764 EMIT_ASM ("ldu 4, 8(30) \n"
2768 /* Top = stack[--sp] >> TOP
2769 (Arithmetic shift right) */
2772 ppc64_emit_rsh_signed (void)
2774 EMIT_ASM ("ldu 4, 8(30) \n"
2778 /* Top = stack[--sp] >> TOP
2779 (Logical shift right) */
2782 ppc64_emit_rsh_unsigned (void)
2784 EMIT_ASM ("ldu 4, 8(30) \n"
2788 /* Emit code for signed-extension specified by ARG. */
2791 ppc64_emit_ext (int arg
)
2796 EMIT_ASM ("extsb 3, 3");
2799 EMIT_ASM ("extsh 3, 3");
2802 EMIT_ASM ("extsw 3, 3");
2809 /* Emit code for zero-extension specified by ARG. */
2812 ppc64_emit_zero_ext (int arg
)
2817 EMIT_ASM ("rldicl 3,3,0,56");
2820 EMIT_ASM ("rldicl 3,3,0,48");
2823 EMIT_ASM ("rldicl 3,3,0,32");
2831 i.e., TOP = (TOP == 0) ? 1 : 0; */
2834 ppc64_emit_log_not (void)
2836 EMIT_ASM ("cntlzd 3, 3 \n"
2840 /* TOP = stack[--sp] & TOP */
2843 ppc64_emit_bit_and (void)
2845 EMIT_ASM ("ldu 4, 8(30) \n"
2849 /* TOP = stack[--sp] | TOP */
2852 ppc64_emit_bit_or (void)
2854 EMIT_ASM ("ldu 4, 8(30) \n"
2858 /* TOP = stack[--sp] ^ TOP */
2861 ppc64_emit_bit_xor (void)
2863 EMIT_ASM ("ldu 4, 8(30) \n"
2868 i.e., TOP = ~(TOP | TOP) */
2871 ppc64_emit_bit_not (void)
2873 EMIT_ASM ("nor 3, 3, 3 \n");
2876 /* TOP = stack[--sp] == TOP */
2879 ppc64_emit_equal (void)
2881 EMIT_ASM ("ldu 4, 8(30) \n"
2887 /* TOP = stack[--sp] < TOP
2888 (Signed comparison) */
2891 ppc64_emit_less_signed (void)
2893 EMIT_ASM ("ldu 4, 8(30) \n"
2896 "rlwinm 3, 3, 29, 31, 31 \n");
2899 /* TOP = stack[--sp] < TOP
2900 (Unsigned comparison) */
2903 ppc64_emit_less_unsigned (void)
2905 EMIT_ASM ("ldu 4, 8(30) \n"
2908 "rlwinm 3, 3, 29, 31, 31 \n");
2911 /* Access the memory address in TOP in size of SIZE.
2912 Zero-extend the read value. */
2915 ppc64_emit_ref (int size
)
2920 EMIT_ASM ("lbz 3, 0(3)");
2923 EMIT_ASM ("lhz 3, 0(3)");
2926 EMIT_ASM ("lwz 3, 0(3)");
2929 EMIT_ASM ("ld 3, 0(3)");
2937 ppc64_emit_const (LONGEST num
)
2942 p
+= gen_limm (p
, 3, num
, 1);
2944 emit_insns (buf
, p
- buf
);
2945 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2948 /* Set TOP to the value of register REG by calling get_raw_reg function
2949 with two argument, collected buffer and register number. */
2952 ppc64v1_emit_reg (int reg
)
2957 /* fctx->regs is passed in r3 and then saved in 176(1). */
2958 p
+= GEN_LD (p
, 3, 31, -32);
2959 p
+= GEN_LI (p
, 4, reg
);
2960 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2961 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 1);
2962 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2964 emit_insns (buf
, p
- buf
);
2965 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2968 /* Likewise, for ELFv2. */
2971 ppc64v2_emit_reg (int reg
)
2976 /* fctx->regs is passed in r3 and then saved in 176(1). */
2977 p
+= GEN_LD (p
, 3, 31, -32);
2978 p
+= GEN_LI (p
, 4, reg
);
2979 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
2980 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 0);
2981 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
2983 emit_insns (buf
, p
- buf
);
2984 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2987 /* TOP = stack[--sp] */
2990 ppc64_emit_pop (void)
2992 EMIT_ASM ("ldu 3, 8(30)");
2995 /* stack[sp++] = TOP
2997 Because we may use up bytecode stack, expand 8 doublewords more
3001 ppc64_emit_stack_flush (void)
3003 /* Make sure bytecode stack is big enough before push.
3004 Otherwise, expand 64-byte more. */
3006 EMIT_ASM (" std 3, 0(30) \n"
3007 " addi 4, 30, -(112 + 8) \n"
3010 " stdu 31, -64(1) \n"
3011 "1:addi 30, 30, -8 \n");
3014 /* Swap TOP and stack[sp-1] */
3017 ppc64_emit_swap (void)
3019 EMIT_ASM ("ld 4, 8(30) \n"
3024 /* Call function FN - ELFv1. */
3027 ppc64v1_emit_call (CORE_ADDR fn
)
3032 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3033 p
+= gen_call (p
, fn
, 1, 1);
3034 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3036 emit_insns (buf
, p
- buf
);
3037 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3040 /* Call function FN - ELFv2. */
3043 ppc64v2_emit_call (CORE_ADDR fn
)
3048 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3049 p
+= gen_call (p
, fn
, 1, 0);
3050 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3052 emit_insns (buf
, p
- buf
);
3053 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3056 /* FN's prototype is `LONGEST(*fn)(int)'.
3061 ppc64v1_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
3066 /* Setup argument. arg1 is a 16-bit value. */
3067 p
+= gen_limm (p
, 3, arg1
, 1);
3068 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3069 p
+= gen_call (p
, fn
, 1, 1);
3070 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3072 emit_insns (buf
, p
- buf
);
3073 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3076 /* Likewise for ELFv2. */
3079 ppc64v2_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
3084 /* Setup argument. arg1 is a 16-bit value. */
3085 p
+= gen_limm (p
, 3, arg1
, 1);
3086 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3087 p
+= gen_call (p
, fn
, 1, 0);
3088 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3090 emit_insns (buf
, p
- buf
);
3091 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3094 /* FN's prototype is `void(*fn)(int,LONGEST)'.
3097 TOP should be preserved/restored before/after the call. */
3100 ppc64v1_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3105 /* Save TOP. 0(30) is next-empty. */
3106 p
+= GEN_STD (p
, 3, 30, 0);
3108 /* Setup argument. arg1 is a 16-bit value. */
3109 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
3110 p
+= gen_limm (p
, 3, arg1
, 1);
3111 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3112 p
+= gen_call (p
, fn
, 1, 1);
3113 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3116 p
+= GEN_LD (p
, 3, 30, 0);
3118 emit_insns (buf
, p
- buf
);
3119 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3122 /* Likewise for ELFv2. */
3125 ppc64v2_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3130 /* Save TOP. 0(30) is next-empty. */
3131 p
+= GEN_STD (p
, 3, 30, 0);
3133 /* Setup argument. arg1 is a 16-bit value. */
3134 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
3135 p
+= gen_limm (p
, 3, arg1
, 1);
3136 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3137 p
+= gen_call (p
, fn
, 1, 0);
3138 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3141 p
+= GEN_LD (p
, 3, 30, 0);
3143 emit_insns (buf
, p
- buf
);
3144 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3147 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
3150 ppc64_emit_if_goto (int *offset_p
, int *size_p
)
3152 EMIT_ASM ("cmpdi 7, 3, 0 \n"
3162 /* Goto if stack[--sp] == TOP */
3165 ppc64_emit_eq_goto (int *offset_p
, int *size_p
)
3167 EMIT_ASM ("ldu 4, 8(30) \n"
3178 /* Goto if stack[--sp] != TOP */
3181 ppc64_emit_ne_goto (int *offset_p
, int *size_p
)
3183 EMIT_ASM ("ldu 4, 8(30) \n"
3194 /* Goto if stack[--sp] < TOP */
3197 ppc64_emit_lt_goto (int *offset_p
, int *size_p
)
3199 EMIT_ASM ("ldu 4, 8(30) \n"
3210 /* Goto if stack[--sp] <= TOP */
3213 ppc64_emit_le_goto (int *offset_p
, int *size_p
)
3215 EMIT_ASM ("ldu 4, 8(30) \n"
3226 /* Goto if stack[--sp] > TOP */
3229 ppc64_emit_gt_goto (int *offset_p
, int *size_p
)
3231 EMIT_ASM ("ldu 4, 8(30) \n"
3242 /* Goto if stack[--sp] >= TOP */
3245 ppc64_emit_ge_goto (int *offset_p
, int *size_p
)
3247 EMIT_ASM ("ldu 4, 8(30) \n"
3258 /* Table of emit ops for 64-bit ELFv1. */
3260 static struct emit_ops ppc64v1_emit_ops_impl
=
3262 ppc64v1_emit_prologue
,
3263 ppc64_emit_epilogue
,
3268 ppc64_emit_rsh_signed
,
3269 ppc64_emit_rsh_unsigned
,
3277 ppc64_emit_less_signed
,
3278 ppc64_emit_less_unsigned
,
3282 ppc_write_goto_address
,
3287 ppc64_emit_stack_flush
,
3288 ppc64_emit_zero_ext
,
3290 ppc_emit_stack_adjust
,
3291 ppc64v1_emit_int_call_1
,
3292 ppc64v1_emit_void_call_2
,
3301 /* Table of emit ops for 64-bit ELFv2. */
3303 static struct emit_ops ppc64v2_emit_ops_impl
=
3305 ppc64v2_emit_prologue
,
3306 ppc64_emit_epilogue
,
3311 ppc64_emit_rsh_signed
,
3312 ppc64_emit_rsh_unsigned
,
3320 ppc64_emit_less_signed
,
3321 ppc64_emit_less_unsigned
,
3325 ppc_write_goto_address
,
3330 ppc64_emit_stack_flush
,
3331 ppc64_emit_zero_ext
,
3333 ppc_emit_stack_adjust
,
3334 ppc64v2_emit_int_call_1
,
3335 ppc64v2_emit_void_call_2
,
3346 /* Implementation of linux_target_ops method "emit_ops". */
3348 static struct emit_ops
*
3351 #ifdef __powerpc64__
3352 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3354 if (register_size (regcache
->tdesc
, 0) == 8)
3356 if (is_elfv2_inferior ())
3357 return &ppc64v2_emit_ops_impl
;
3359 return &ppc64v1_emit_ops_impl
;
3362 return &ppc_emit_ops_impl
;
3365 /* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3368 ppc_get_ipa_tdesc_idx (void)
3370 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3371 const struct target_desc
*tdesc
= regcache
->tdesc
;
3373 #ifdef __powerpc64__
3374 if (tdesc
== tdesc_powerpc_64l
)
3375 return PPC_TDESC_BASE
;
3376 if (tdesc
== tdesc_powerpc_altivec64l
)
3377 return PPC_TDESC_ALTIVEC
;
3378 if (tdesc
== tdesc_powerpc_vsx64l
)
3379 return PPC_TDESC_VSX
;
3380 if (tdesc
== tdesc_powerpc_isa205_64l
)
3381 return PPC_TDESC_ISA205
;
3382 if (tdesc
== tdesc_powerpc_isa205_altivec64l
)
3383 return PPC_TDESC_ISA205_ALTIVEC
;
3384 if (tdesc
== tdesc_powerpc_isa205_vsx64l
)
3385 return PPC_TDESC_ISA205_VSX
;
3386 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx64l
)
3387 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3388 if (tdesc
== tdesc_powerpc_isa207_vsx64l
)
3389 return PPC_TDESC_ISA207_VSX
;
3390 if (tdesc
== tdesc_powerpc_isa207_htm_vsx64l
)
3391 return PPC_TDESC_ISA207_HTM_VSX
;
3394 if (tdesc
== tdesc_powerpc_32l
)
3395 return PPC_TDESC_BASE
;
3396 if (tdesc
== tdesc_powerpc_altivec32l
)
3397 return PPC_TDESC_ALTIVEC
;
3398 if (tdesc
== tdesc_powerpc_vsx32l
)
3399 return PPC_TDESC_VSX
;
3400 if (tdesc
== tdesc_powerpc_isa205_32l
)
3401 return PPC_TDESC_ISA205
;
3402 if (tdesc
== tdesc_powerpc_isa205_altivec32l
)
3403 return PPC_TDESC_ISA205_ALTIVEC
;
3404 if (tdesc
== tdesc_powerpc_isa205_vsx32l
)
3405 return PPC_TDESC_ISA205_VSX
;
3406 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx32l
)
3407 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3408 if (tdesc
== tdesc_powerpc_isa207_vsx32l
)
3409 return PPC_TDESC_ISA207_VSX
;
3410 if (tdesc
== tdesc_powerpc_isa207_htm_vsx32l
)
3411 return PPC_TDESC_ISA207_HTM_VSX
;
3412 if (tdesc
== tdesc_powerpc_e500l
)
3413 return PPC_TDESC_E500
;
3418 struct linux_target_ops the_low_target
= {
3419 ppc_collect_ptrace_register
,
3420 ppc_supply_ptrace_register
,
3421 NULL
, /* siginfo_fixup */
3422 NULL
, /* new_process */
3423 NULL
, /* delete_process */
3424 NULL
, /* new_thread */
3425 NULL
, /* delete_thread */
3426 NULL
, /* new_fork */
3427 NULL
, /* prepare_to_resume */
3428 NULL
, /* process_qsupported */
3429 ppc_supports_tracepoints
,
3430 ppc_get_thread_area
,
3431 ppc_install_fast_tracepoint_jump_pad
,
3433 ppc_get_min_fast_tracepoint_insn_len
,
3434 NULL
, /* supports_range_stepping */
3435 ppc_supports_hardware_single_step
,
3436 NULL
, /* get_syscall_trapinfo */
3437 ppc_get_ipa_tdesc_idx
,
3440 /* The linux target ops object. */
3442 linux_process_target
*the_linux_target
= &the_ppc_target
;
3445 initialize_low_arch (void)
3447 /* Initialize the Linux target descriptions. */
3449 init_registers_powerpc_32l ();
3450 init_registers_powerpc_altivec32l ();
3451 init_registers_powerpc_vsx32l ();
3452 init_registers_powerpc_isa205_32l ();
3453 init_registers_powerpc_isa205_altivec32l ();
3454 init_registers_powerpc_isa205_vsx32l ();
3455 init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
3456 init_registers_powerpc_isa207_vsx32l ();
3457 init_registers_powerpc_isa207_htm_vsx32l ();
3458 init_registers_powerpc_e500l ();
3460 init_registers_powerpc_64l ();
3461 init_registers_powerpc_altivec64l ();
3462 init_registers_powerpc_vsx64l ();
3463 init_registers_powerpc_isa205_64l ();
3464 init_registers_powerpc_isa205_altivec64l ();
3465 init_registers_powerpc_isa205_vsx64l ();
3466 init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
3467 init_registers_powerpc_isa207_vsx64l ();
3468 init_registers_powerpc_isa207_htm_vsx64l ();
3471 initialize_regsets_info (&ppc_regsets_info
);