1 /* GNU/Linux/PowerPC specific low level interface, for the remote server for
3 Copyright (C) 1995-2020 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "linux-low.h"
23 #include "elf/common.h"
26 #include <asm/ptrace.h>
28 #include "arch/ppc-linux-common.h"
29 #include "arch/ppc-linux-tdesc.h"
30 #include "nat/ppc-linux.h"
31 #include "nat/linux-ptrace.h"
32 #include "linux-ppc-tdesc-init.h"
34 #include "tracepoint.h"
36 #define PPC_FIELD(value, from, len) \
37 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
38 #define PPC_SEXT(v, bs) \
39 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
40 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
41 - ((CORE_ADDR) 1 << ((bs) - 1)))
42 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
43 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
44 #define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
45 #define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
47 /* Holds the AT_HWCAP auxv entry. */
49 static unsigned long ppc_hwcap
;
51 /* Holds the AT_HWCAP2 auxv entry. */
53 static unsigned long ppc_hwcap2
;
56 #define ppc_num_regs 73
59 /* We use a constant for FPSCR instead of PT_FPSCR, because
60 many shipped PPC64 kernels had the wrong value in ptrace.h. */
61 static int ppc_regmap
[] =
62 {PT_R0
* 8, PT_R1
* 8, PT_R2
* 8, PT_R3
* 8,
63 PT_R4
* 8, PT_R5
* 8, PT_R6
* 8, PT_R7
* 8,
64 PT_R8
* 8, PT_R9
* 8, PT_R10
* 8, PT_R11
* 8,
65 PT_R12
* 8, PT_R13
* 8, PT_R14
* 8, PT_R15
* 8,
66 PT_R16
* 8, PT_R17
* 8, PT_R18
* 8, PT_R19
* 8,
67 PT_R20
* 8, PT_R21
* 8, PT_R22
* 8, PT_R23
* 8,
68 PT_R24
* 8, PT_R25
* 8, PT_R26
* 8, PT_R27
* 8,
69 PT_R28
* 8, PT_R29
* 8, PT_R30
* 8, PT_R31
* 8,
70 PT_FPR0
*8, PT_FPR0
*8 + 8, PT_FPR0
*8+16, PT_FPR0
*8+24,
71 PT_FPR0
*8+32, PT_FPR0
*8+40, PT_FPR0
*8+48, PT_FPR0
*8+56,
72 PT_FPR0
*8+64, PT_FPR0
*8+72, PT_FPR0
*8+80, PT_FPR0
*8+88,
73 PT_FPR0
*8+96, PT_FPR0
*8+104, PT_FPR0
*8+112, PT_FPR0
*8+120,
74 PT_FPR0
*8+128, PT_FPR0
*8+136, PT_FPR0
*8+144, PT_FPR0
*8+152,
75 PT_FPR0
*8+160, PT_FPR0
*8+168, PT_FPR0
*8+176, PT_FPR0
*8+184,
76 PT_FPR0
*8+192, PT_FPR0
*8+200, PT_FPR0
*8+208, PT_FPR0
*8+216,
77 PT_FPR0
*8+224, PT_FPR0
*8+232, PT_FPR0
*8+240, PT_FPR0
*8+248,
78 PT_NIP
* 8, PT_MSR
* 8, PT_CCR
* 8, PT_LNK
* 8,
79 PT_CTR
* 8, PT_XER
* 8, PT_FPR0
*8 + 256,
80 PT_ORIG_R3
* 8, PT_TRAP
* 8 };
82 /* Currently, don't check/send MQ. */
83 static int ppc_regmap
[] =
84 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
85 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
86 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
87 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
88 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
89 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
90 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
91 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
92 PT_FPR0
*4, PT_FPR0
*4 + 8, PT_FPR0
*4+16, PT_FPR0
*4+24,
93 PT_FPR0
*4+32, PT_FPR0
*4+40, PT_FPR0
*4+48, PT_FPR0
*4+56,
94 PT_FPR0
*4+64, PT_FPR0
*4+72, PT_FPR0
*4+80, PT_FPR0
*4+88,
95 PT_FPR0
*4+96, PT_FPR0
*4+104, PT_FPR0
*4+112, PT_FPR0
*4+120,
96 PT_FPR0
*4+128, PT_FPR0
*4+136, PT_FPR0
*4+144, PT_FPR0
*4+152,
97 PT_FPR0
*4+160, PT_FPR0
*4+168, PT_FPR0
*4+176, PT_FPR0
*4+184,
98 PT_FPR0
*4+192, PT_FPR0
*4+200, PT_FPR0
*4+208, PT_FPR0
*4+216,
99 PT_FPR0
*4+224, PT_FPR0
*4+232, PT_FPR0
*4+240, PT_FPR0
*4+248,
100 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
101 PT_CTR
* 4, PT_XER
* 4, PT_FPSCR
* 4,
102 PT_ORIG_R3
* 4, PT_TRAP
* 4
105 static int ppc_regmap_e500
[] =
106 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
107 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
108 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
109 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
110 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
111 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
112 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
113 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
122 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
123 PT_CTR
* 4, PT_XER
* 4, -1,
124 PT_ORIG_R3
* 4, PT_TRAP
* 4
128 /* Check whether the kernel provides a register set with number
129 REGSET_ID of size REGSETSIZE for process/thread TID. */
132 ppc_check_regset (int tid
, int regset_id
, int regsetsize
)
134 void *buf
= alloca (regsetsize
);
138 iov
.iov_len
= regsetsize
;
140 if (ptrace (PTRACE_GETREGSET
, tid
, regset_id
, &iov
) >= 0
147 ppc_cannot_store_register (int regno
)
149 const struct target_desc
*tdesc
= current_process ()->tdesc
;
151 #ifndef __powerpc64__
152 /* Some kernels do not allow us to store fpscr. */
153 if (!(ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
154 && regno
== find_regno (tdesc
, "fpscr"))
158 /* Some kernels do not allow us to store orig_r3 or trap. */
159 if (regno
== find_regno (tdesc
, "orig_r3")
160 || regno
== find_regno (tdesc
, "trap"))
167 ppc_cannot_fetch_register (int regno
)
173 ppc_collect_ptrace_register (struct regcache
*regcache
, int regno
, char *buf
)
175 memset (buf
, 0, sizeof (long));
177 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
179 /* Little-endian values always sit at the left end of the buffer. */
180 collect_register (regcache
, regno
, buf
);
182 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
184 /* Big-endian values sit at the right end of the buffer. In case of
185 registers whose sizes are smaller than sizeof (long), we must use a
186 padding to access them correctly. */
187 int size
= register_size (regcache
->tdesc
, regno
);
189 if (size
< sizeof (long))
190 collect_register (regcache
, regno
, buf
+ sizeof (long) - size
);
192 collect_register (regcache
, regno
, buf
);
195 perror_with_name ("Unexpected byte order");
199 ppc_supply_ptrace_register (struct regcache
*regcache
,
200 int regno
, const char *buf
)
202 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
204 /* Little-endian values always sit at the left end of the buffer. */
205 supply_register (regcache
, regno
, buf
);
207 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
209 /* Big-endian values sit at the right end of the buffer. In case of
210 registers whose sizes are smaller than sizeof (long), we must use a
211 padding to access them correctly. */
212 int size
= register_size (regcache
->tdesc
, regno
);
214 if (size
< sizeof (long))
215 supply_register (regcache
, regno
, buf
+ sizeof (long) - size
);
217 supply_register (regcache
, regno
, buf
);
220 perror_with_name ("Unexpected byte order");
224 ppc_get_pc (struct regcache
*regcache
)
226 if (register_size (regcache
->tdesc
, 0) == 4)
229 collect_register_by_name (regcache
, "pc", &pc
);
230 return (CORE_ADDR
) pc
;
235 collect_register_by_name (regcache
, "pc", &pc
);
236 return (CORE_ADDR
) pc
;
241 ppc_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
243 if (register_size (regcache
->tdesc
, 0) == 4)
245 unsigned int newpc
= pc
;
246 supply_register_by_name (regcache
, "pc", &newpc
);
250 unsigned long newpc
= pc
;
251 supply_register_by_name (regcache
, "pc", &newpc
);
255 #ifndef __powerpc64__
256 static int ppc_regmap_adjusted
;
260 /* Correct in either endianness.
261 This instruction is "twge r2, r2", which GDB uses as a software
263 static const unsigned int ppc_breakpoint
= 0x7d821008;
264 #define ppc_breakpoint_len 4
266 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
268 static const gdb_byte
*
269 ppc_sw_breakpoint_from_kind (int kind
, int *size
)
271 *size
= ppc_breakpoint_len
;
272 return (const gdb_byte
*) &ppc_breakpoint
;
276 ppc_breakpoint_at (CORE_ADDR where
)
280 the_target
->read_memory (where
, (unsigned char *) &insn
, 4);
281 if (insn
== ppc_breakpoint
)
283 /* If necessary, recognize more trap instructions here. GDB only uses
289 /* Implement supports_z_point_type target-ops.
290 Returns true if type Z_TYPE breakpoint is supported.
292 Handling software breakpoint at server side, so tracepoints
293 and breakpoints can be inserted at the same location. */
296 ppc_supports_z_point_type (char z_type
)
303 case Z_PACKET_WRITE_WP
:
304 case Z_PACKET_ACCESS_WP
:
310 /* Implement insert_point target-ops.
311 Returns 0 on success, -1 on failure and 1 on unsupported. */
314 ppc_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
315 int size
, struct raw_breakpoint
*bp
)
319 case raw_bkpt_type_sw
:
320 return insert_memory_breakpoint (bp
);
322 case raw_bkpt_type_hw
:
323 case raw_bkpt_type_write_wp
:
324 case raw_bkpt_type_access_wp
:
331 /* Implement remove_point target-ops.
332 Returns 0 on success, -1 on failure and 1 on unsupported. */
335 ppc_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
336 int size
, struct raw_breakpoint
*bp
)
340 case raw_bkpt_type_sw
:
341 return remove_memory_breakpoint (bp
);
343 case raw_bkpt_type_hw
:
344 case raw_bkpt_type_write_wp
:
345 case raw_bkpt_type_access_wp
:
352 /* Provide only a fill function for the general register set. ps_lgetregs
353 will use this for NPTL support. */
355 static void ppc_fill_gregset (struct regcache
*regcache
, void *buf
)
359 for (i
= 0; i
< 32; i
++)
360 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
362 for (i
= 64; i
< 70; i
++)
363 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
365 for (i
= 71; i
< 73; i
++)
366 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
369 /* Program Priority Register regset fill function. */
372 ppc_fill_pprregset (struct regcache
*regcache
, void *buf
)
374 char *ppr
= (char *) buf
;
376 collect_register_by_name (regcache
, "ppr", ppr
);
379 /* Program Priority Register regset store function. */
382 ppc_store_pprregset (struct regcache
*regcache
, const void *buf
)
384 const char *ppr
= (const char *) buf
;
386 supply_register_by_name (regcache
, "ppr", ppr
);
389 /* Data Stream Control Register regset fill function. */
392 ppc_fill_dscrregset (struct regcache
*regcache
, void *buf
)
394 char *dscr
= (char *) buf
;
396 collect_register_by_name (regcache
, "dscr", dscr
);
399 /* Data Stream Control Register regset store function. */
402 ppc_store_dscrregset (struct regcache
*regcache
, const void *buf
)
404 const char *dscr
= (const char *) buf
;
406 supply_register_by_name (regcache
, "dscr", dscr
);
409 /* Target Address Register regset fill function. */
412 ppc_fill_tarregset (struct regcache
*regcache
, void *buf
)
414 char *tar
= (char *) buf
;
416 collect_register_by_name (regcache
, "tar", tar
);
419 /* Target Address Register regset store function. */
422 ppc_store_tarregset (struct regcache
*regcache
, const void *buf
)
424 const char *tar
= (const char *) buf
;
426 supply_register_by_name (regcache
, "tar", tar
);
429 /* Event-Based Branching regset store function. Unless the inferior
430 has a perf event open, ptrace can return in error when reading and
431 writing to the regset, with ENODATA. For reading, the registers
432 will correctly show as unavailable. For writing, gdbserver
433 currently only caches any register writes from P and G packets and
434 the stub always tries to write all the regsets when resuming the
435 inferior, which would result in frequent warnings. For this
436 reason, we don't define a fill function. This also means that the
437 client-side regcache will be dirty if the user tries to write to
438 the EBB registers. G packets that the client sends to write to
439 unrelated registers will also include data for EBB registers, even
440 if they are unavailable. */
443 ppc_store_ebbregset (struct regcache
*regcache
, const void *buf
)
445 const char *regset
= (const char *) buf
;
447 /* The order in the kernel regset is: EBBRR, EBBHR, BESCR. In the
448 .dat file is BESCR, EBBHR, EBBRR. */
449 supply_register_by_name (regcache
, "ebbrr", ®set
[0]);
450 supply_register_by_name (regcache
, "ebbhr", ®set
[8]);
451 supply_register_by_name (regcache
, "bescr", ®set
[16]);
454 /* Performance Monitoring Unit regset fill function. */
457 ppc_fill_pmuregset (struct regcache
*regcache
, void *buf
)
459 char *regset
= (char *) buf
;
461 /* The order in the kernel regset is SIAR, SDAR, SIER, MMCR2, MMCR0.
462 In the .dat file is MMCR0, MMCR2, SIAR, SDAR, SIER. */
463 collect_register_by_name (regcache
, "siar", ®set
[0]);
464 collect_register_by_name (regcache
, "sdar", ®set
[8]);
465 collect_register_by_name (regcache
, "sier", ®set
[16]);
466 collect_register_by_name (regcache
, "mmcr2", ®set
[24]);
467 collect_register_by_name (regcache
, "mmcr0", ®set
[32]);
470 /* Performance Monitoring Unit regset store function. */
473 ppc_store_pmuregset (struct regcache
*regcache
, const void *buf
)
475 const char *regset
= (const char *) buf
;
477 supply_register_by_name (regcache
, "siar", ®set
[0]);
478 supply_register_by_name (regcache
, "sdar", ®set
[8]);
479 supply_register_by_name (regcache
, "sier", ®set
[16]);
480 supply_register_by_name (regcache
, "mmcr2", ®set
[24]);
481 supply_register_by_name (regcache
, "mmcr0", ®set
[32]);
484 /* Hardware Transactional Memory special-purpose register regset fill
488 ppc_fill_tm_sprregset (struct regcache
*regcache
, void *buf
)
491 char *regset
= (char *) buf
;
493 base
= find_regno (regcache
->tdesc
, "tfhar");
494 for (i
= 0; i
< 3; i
++)
495 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
498 /* Hardware Transactional Memory special-purpose register regset store
502 ppc_store_tm_sprregset (struct regcache
*regcache
, const void *buf
)
505 const char *regset
= (const char *) buf
;
507 base
= find_regno (regcache
->tdesc
, "tfhar");
508 for (i
= 0; i
< 3; i
++)
509 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
512 /* For the same reasons as the EBB regset, none of the HTM
513 checkpointed regsets have a fill function. These registers are
514 only available if the inferior is in a transaction. */
516 /* Hardware Transactional Memory checkpointed general-purpose regset
520 ppc_store_tm_cgprregset (struct regcache
*regcache
, const void *buf
)
522 int i
, base
, size
, endian_offset
;
523 const char *regset
= (const char *) buf
;
525 base
= find_regno (regcache
->tdesc
, "cr0");
526 size
= register_size (regcache
->tdesc
, base
);
528 gdb_assert (size
== 4 || size
== 8);
530 for (i
= 0; i
< 32; i
++)
531 supply_register (regcache
, base
+ i
, ®set
[i
* size
]);
535 if ((size
== 8) && (__BYTE_ORDER
== __BIG_ENDIAN
))
538 supply_register_by_name (regcache
, "ccr",
539 ®set
[PT_CCR
* size
+ endian_offset
]);
541 supply_register_by_name (regcache
, "cxer",
542 ®set
[PT_XER
* size
+ endian_offset
]);
544 supply_register_by_name (regcache
, "clr", ®set
[PT_LNK
* size
]);
545 supply_register_by_name (regcache
, "cctr", ®set
[PT_CTR
* size
]);
548 /* Hardware Transactional Memory checkpointed floating-point regset
552 ppc_store_tm_cfprregset (struct regcache
*regcache
, const void *buf
)
555 const char *regset
= (const char *) buf
;
557 base
= find_regno (regcache
->tdesc
, "cf0");
559 for (i
= 0; i
< 32; i
++)
560 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
562 supply_register_by_name (regcache
, "cfpscr", ®set
[32 * 8]);
565 /* Hardware Transactional Memory checkpointed vector regset store
569 ppc_store_tm_cvrregset (struct regcache
*regcache
, const void *buf
)
572 const char *regset
= (const char *) buf
;
575 base
= find_regno (regcache
->tdesc
, "cvr0");
577 for (i
= 0; i
< 32; i
++)
578 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
580 if (__BYTE_ORDER
== __BIG_ENDIAN
)
583 supply_register_by_name (regcache
, "cvscr",
584 ®set
[32 * 16 + vscr_offset
]);
586 supply_register_by_name (regcache
, "cvrsave", ®set
[33 * 16]);
589 /* Hardware Transactional Memory checkpointed vector-scalar regset
593 ppc_store_tm_cvsxregset (struct regcache
*regcache
, const void *buf
)
596 const char *regset
= (const char *) buf
;
598 base
= find_regno (regcache
->tdesc
, "cvs0h");
599 for (i
= 0; i
< 32; i
++)
600 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
603 /* Hardware Transactional Memory checkpointed Program Priority
604 Register regset store function. */
607 ppc_store_tm_cpprregset (struct regcache
*regcache
, const void *buf
)
609 const char *cppr
= (const char *) buf
;
611 supply_register_by_name (regcache
, "cppr", cppr
);
614 /* Hardware Transactional Memory checkpointed Data Stream Control
615 Register regset store function. */
618 ppc_store_tm_cdscrregset (struct regcache
*regcache
, const void *buf
)
620 const char *cdscr
= (const char *) buf
;
622 supply_register_by_name (regcache
, "cdscr", cdscr
);
625 /* Hardware Transactional Memory checkpointed Target Address Register
626 regset store function. */
629 ppc_store_tm_ctarregset (struct regcache
*regcache
, const void *buf
)
631 const char *ctar
= (const char *) buf
;
633 supply_register_by_name (regcache
, "ctar", ctar
);
637 ppc_fill_vsxregset (struct regcache
*regcache
, void *buf
)
640 char *regset
= (char *) buf
;
642 base
= find_regno (regcache
->tdesc
, "vs0h");
643 for (i
= 0; i
< 32; i
++)
644 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
648 ppc_store_vsxregset (struct regcache
*regcache
, const void *buf
)
651 const char *regset
= (const char *) buf
;
653 base
= find_regno (regcache
->tdesc
, "vs0h");
654 for (i
= 0; i
< 32; i
++)
655 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
659 ppc_fill_vrregset (struct regcache
*regcache
, void *buf
)
662 char *regset
= (char *) buf
;
665 base
= find_regno (regcache
->tdesc
, "vr0");
666 for (i
= 0; i
< 32; i
++)
667 collect_register (regcache
, base
+ i
, ®set
[i
* 16]);
669 if (__BYTE_ORDER
== __BIG_ENDIAN
)
672 collect_register_by_name (regcache
, "vscr",
673 ®set
[32 * 16 + vscr_offset
]);
675 collect_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
679 ppc_store_vrregset (struct regcache
*regcache
, const void *buf
)
682 const char *regset
= (const char *) buf
;
685 base
= find_regno (regcache
->tdesc
, "vr0");
686 for (i
= 0; i
< 32; i
++)
687 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
689 if (__BYTE_ORDER
== __BIG_ENDIAN
)
692 supply_register_by_name (regcache
, "vscr",
693 ®set
[32 * 16 + vscr_offset
]);
694 supply_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
697 struct gdb_evrregset_t
699 unsigned long evr
[32];
700 unsigned long long acc
;
701 unsigned long spefscr
;
705 ppc_fill_evrregset (struct regcache
*regcache
, void *buf
)
708 struct gdb_evrregset_t
*regset
= (struct gdb_evrregset_t
*) buf
;
710 ev0
= find_regno (regcache
->tdesc
, "ev0h");
711 for (i
= 0; i
< 32; i
++)
712 collect_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
714 collect_register_by_name (regcache
, "acc", ®set
->acc
);
715 collect_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
719 ppc_store_evrregset (struct regcache
*regcache
, const void *buf
)
722 const struct gdb_evrregset_t
*regset
= (const struct gdb_evrregset_t
*) buf
;
724 ev0
= find_regno (regcache
->tdesc
, "ev0h");
725 for (i
= 0; i
< 32; i
++)
726 supply_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
728 supply_register_by_name (regcache
, "acc", ®set
->acc
);
729 supply_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
732 /* Support for hardware single step. */
735 ppc_supports_hardware_single_step (void)
740 static struct regset_info ppc_regsets
[] = {
741 /* List the extra register sets before GENERAL_REGS. That way we will
742 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
743 general registers. Some kernels support these, but not the newer
744 PPC_PTRACE_GETREGS. */
745 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CTAR
, 0, EXTENDED_REGS
,
746 NULL
, ppc_store_tm_ctarregset
},
747 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CDSCR
, 0, EXTENDED_REGS
,
748 NULL
, ppc_store_tm_cdscrregset
},
749 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CPPR
, 0, EXTENDED_REGS
,
750 NULL
, ppc_store_tm_cpprregset
},
751 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CVSX
, 0, EXTENDED_REGS
,
752 NULL
, ppc_store_tm_cvsxregset
},
753 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CVMX
, 0, EXTENDED_REGS
,
754 NULL
, ppc_store_tm_cvrregset
},
755 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CFPR
, 0, EXTENDED_REGS
,
756 NULL
, ppc_store_tm_cfprregset
},
757 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CGPR
, 0, EXTENDED_REGS
,
758 NULL
, ppc_store_tm_cgprregset
},
759 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_SPR
, 0, EXTENDED_REGS
,
760 ppc_fill_tm_sprregset
, ppc_store_tm_sprregset
},
761 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_EBB
, 0, EXTENDED_REGS
,
762 NULL
, ppc_store_ebbregset
},
763 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PMU
, 0, EXTENDED_REGS
,
764 ppc_fill_pmuregset
, ppc_store_pmuregset
},
765 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TAR
, 0, EXTENDED_REGS
,
766 ppc_fill_tarregset
, ppc_store_tarregset
},
767 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PPR
, 0, EXTENDED_REGS
,
768 ppc_fill_pprregset
, ppc_store_pprregset
},
769 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_DSCR
, 0, EXTENDED_REGS
,
770 ppc_fill_dscrregset
, ppc_store_dscrregset
},
771 { PTRACE_GETVSXREGS
, PTRACE_SETVSXREGS
, 0, 0, EXTENDED_REGS
,
772 ppc_fill_vsxregset
, ppc_store_vsxregset
},
773 { PTRACE_GETVRREGS
, PTRACE_SETVRREGS
, 0, 0, EXTENDED_REGS
,
774 ppc_fill_vrregset
, ppc_store_vrregset
},
775 { PTRACE_GETEVRREGS
, PTRACE_SETEVRREGS
, 0, 0, EXTENDED_REGS
,
776 ppc_fill_evrregset
, ppc_store_evrregset
},
777 { 0, 0, 0, 0, GENERAL_REGS
, ppc_fill_gregset
, NULL
},
781 static struct usrregs_info ppc_usrregs_info
=
787 static struct regsets_info ppc_regsets_info
=
789 ppc_regsets
, /* regsets */
791 NULL
, /* disabled_regsets */
794 static struct regs_info regs_info
=
796 NULL
, /* regset_bitmap */
801 static const struct regs_info
*
808 ppc_arch_setup (void)
810 const struct target_desc
*tdesc
;
811 struct regset_info
*regset
;
812 struct ppc_linux_features features
= ppc_linux_no_features
;
814 int tid
= lwpid_of (current_thread
);
816 features
.wordsize
= ppc_linux_target_wordsize (tid
);
818 if (features
.wordsize
== 4)
819 tdesc
= tdesc_powerpc_32l
;
821 tdesc
= tdesc_powerpc_64l
;
823 current_process ()->tdesc
= tdesc
;
825 /* The value of current_process ()->tdesc needs to be set for this
827 ppc_hwcap
= linux_get_hwcap (features
.wordsize
);
828 ppc_hwcap2
= linux_get_hwcap2 (features
.wordsize
);
830 features
.isa205
= ppc_linux_has_isa205 (ppc_hwcap
);
832 if (ppc_hwcap
& PPC_FEATURE_HAS_VSX
)
835 if (ppc_hwcap
& PPC_FEATURE_HAS_ALTIVEC
)
836 features
.altivec
= true;
838 if ((ppc_hwcap2
& PPC_FEATURE2_DSCR
)
839 && ppc_check_regset (tid
, NT_PPC_DSCR
, PPC_LINUX_SIZEOF_DSCRREGSET
)
840 && ppc_check_regset (tid
, NT_PPC_PPR
, PPC_LINUX_SIZEOF_PPRREGSET
))
842 features
.ppr_dscr
= true;
843 if ((ppc_hwcap2
& PPC_FEATURE2_ARCH_2_07
)
844 && (ppc_hwcap2
& PPC_FEATURE2_TAR
)
845 && (ppc_hwcap2
& PPC_FEATURE2_EBB
)
846 && ppc_check_regset (tid
, NT_PPC_TAR
,
847 PPC_LINUX_SIZEOF_TARREGSET
)
848 && ppc_check_regset (tid
, NT_PPC_EBB
,
849 PPC_LINUX_SIZEOF_EBBREGSET
)
850 && ppc_check_regset (tid
, NT_PPC_PMU
,
851 PPC_LINUX_SIZEOF_PMUREGSET
))
853 features
.isa207
= true;
854 if ((ppc_hwcap2
& PPC_FEATURE2_HTM
)
855 && ppc_check_regset (tid
, NT_PPC_TM_SPR
,
856 PPC_LINUX_SIZEOF_TM_SPRREGSET
))
861 tdesc
= ppc_linux_match_description (features
);
863 /* On 32-bit machines, check for SPE registers.
864 Set the low target's regmap field as appropriately. */
865 #ifndef __powerpc64__
866 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
867 tdesc
= tdesc_powerpc_e500l
;
869 if (!ppc_regmap_adjusted
)
871 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
872 ppc_usrregs_info
.regmap
= ppc_regmap_e500
;
874 /* If the FPSCR is 64-bit wide, we need to fetch the whole
875 64-bit slot and not just its second word. The PT_FPSCR
876 supplied in a 32-bit GDB compilation doesn't reflect
878 if (register_size (tdesc
, 70) == 8)
879 ppc_regmap
[70] = (48 + 2*32) * sizeof (long);
881 ppc_regmap_adjusted
= 1;
885 current_process ()->tdesc
= tdesc
;
887 for (regset
= ppc_regsets
; regset
->size
>= 0; regset
++)
888 switch (regset
->get_request
)
890 case PTRACE_GETVRREGS
:
891 regset
->size
= features
.altivec
? PPC_LINUX_SIZEOF_VRREGSET
: 0;
893 case PTRACE_GETVSXREGS
:
894 regset
->size
= features
.vsx
? PPC_LINUX_SIZEOF_VSXREGSET
: 0;
896 case PTRACE_GETEVRREGS
:
897 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
898 regset
->size
= 32 * 4 + 8 + 4;
902 case PTRACE_GETREGSET
:
903 switch (regset
->nt_type
)
906 regset
->size
= (features
.ppr_dscr
?
907 PPC_LINUX_SIZEOF_PPRREGSET
: 0);
910 regset
->size
= (features
.ppr_dscr
?
911 PPC_LINUX_SIZEOF_DSCRREGSET
: 0);
914 regset
->size
= (features
.isa207
?
915 PPC_LINUX_SIZEOF_TARREGSET
: 0);
918 regset
->size
= (features
.isa207
?
919 PPC_LINUX_SIZEOF_EBBREGSET
: 0);
922 regset
->size
= (features
.isa207
?
923 PPC_LINUX_SIZEOF_PMUREGSET
: 0);
926 regset
->size
= (features
.htm
?
927 PPC_LINUX_SIZEOF_TM_SPRREGSET
: 0);
930 if (features
.wordsize
== 4)
931 regset
->size
= (features
.htm
?
932 PPC32_LINUX_SIZEOF_CGPRREGSET
: 0);
934 regset
->size
= (features
.htm
?
935 PPC64_LINUX_SIZEOF_CGPRREGSET
: 0);
938 regset
->size
= (features
.htm
?
939 PPC_LINUX_SIZEOF_CFPRREGSET
: 0);
942 regset
->size
= (features
.htm
?
943 PPC_LINUX_SIZEOF_CVMXREGSET
: 0);
946 regset
->size
= (features
.htm
?
947 PPC_LINUX_SIZEOF_CVSXREGSET
: 0);
950 regset
->size
= (features
.htm
?
951 PPC_LINUX_SIZEOF_CPPRREGSET
: 0);
953 case NT_PPC_TM_CDSCR
:
954 regset
->size
= (features
.htm
?
955 PPC_LINUX_SIZEOF_CDSCRREGSET
: 0);
958 regset
->size
= (features
.htm
?
959 PPC_LINUX_SIZEOF_CTARREGSET
: 0);
970 /* Implementation of linux_target_ops method "supports_tracepoints". */
973 ppc_supports_tracepoints (void)
978 /* Get the thread area address. This is used to recognize which
979 thread is which when tracing with the in-process agent library. We
980 don't read anything from the address, and treat it as opaque; it's
981 the address itself that we assume is unique per-thread. */
984 ppc_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
986 struct lwp_info
*lwp
= find_lwp_pid (ptid_t (lwpid
));
987 struct thread_info
*thr
= get_lwp_thread (lwp
);
988 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
992 if (register_size (regcache
->tdesc
, 0) == 8)
993 collect_register_by_name (regcache
, "r13", &tp
);
996 collect_register_by_name (regcache
, "r2", &tp
);
1003 #ifdef __powerpc64__
1005 /* Older glibc doesn't provide this. */
1007 #ifndef EF_PPC64_ABI
1008 #define EF_PPC64_ABI 3
1011 /* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
1015 is_elfv2_inferior (void)
1017 /* To be used as fallback if we're unable to determine the right result -
1018 assume inferior uses the same ABI as gdbserver. */
1020 const int def_res
= 1;
1022 const int def_res
= 0;
1027 const struct target_desc
*tdesc
= current_process ()->tdesc
;
1028 int wordsize
= register_size (tdesc
, 0);
1030 if (!linux_get_auxv (wordsize
, AT_PHDR
, &phdr
))
1033 /* Assume ELF header is at the beginning of the page where program headers
1034 are located. If it doesn't look like one, bail. */
1036 read_inferior_memory (phdr
& ~0xfff, (unsigned char *) &ehdr
, sizeof ehdr
);
1037 if (memcmp(ehdr
.e_ident
, ELFMAG
, SELFMAG
))
1040 return (ehdr
.e_flags
& EF_PPC64_ABI
) == 2;
1045 /* Generate a ds-form instruction in BUF and return the number of bytes written
1048 | OPCD | RST | RA | DS |XO| */
1050 __attribute__((unused
)) /* Maybe unused due to conditional compilation. */
1052 gen_ds_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int ds
, int xo
)
1056 gdb_assert ((opcd
& ~0x3f) == 0);
1057 gdb_assert ((rst
& ~0x1f) == 0);
1058 gdb_assert ((ra
& ~0x1f) == 0);
1059 gdb_assert ((xo
& ~0x3) == 0);
1061 insn
= (rst
<< 21) | (ra
<< 16) | (ds
& 0xfffc) | (xo
& 0x3);
1062 *buf
= (opcd
<< 26) | insn
;
1066 /* Followings are frequently used ds-form instructions. */
1068 #define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
1069 #define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
1070 #define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
1071 #define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
1073 /* Generate a d-form instruction in BUF.
1076 | OPCD | RST | RA | D | */
1079 gen_d_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int si
)
1083 gdb_assert ((opcd
& ~0x3f) == 0);
1084 gdb_assert ((rst
& ~0x1f) == 0);
1085 gdb_assert ((ra
& ~0x1f) == 0);
1087 insn
= (rst
<< 21) | (ra
<< 16) | (si
& 0xffff);
1088 *buf
= (opcd
<< 26) | insn
;
1092 /* Followings are frequently used d-form instructions. */
1094 #define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
1095 #define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
1096 #define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
1097 #define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
1098 #define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
1099 #define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
1100 #define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
1101 #define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
1102 #define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
1104 /* Generate a xfx-form instruction in BUF and return the number of bytes
1108 | OPCD | RST | RI | XO |/| */
1111 gen_xfx_form (uint32_t *buf
, int opcd
, int rst
, int ri
, int xo
)
1114 unsigned int n
= ((ri
& 0x1f) << 5) | ((ri
>> 5) & 0x1f);
1116 gdb_assert ((opcd
& ~0x3f) == 0);
1117 gdb_assert ((rst
& ~0x1f) == 0);
1118 gdb_assert ((xo
& ~0x3ff) == 0);
1120 insn
= (rst
<< 21) | (n
<< 11) | (xo
<< 1);
1121 *buf
= (opcd
<< 26) | insn
;
1125 /* Followings are frequently used xfx-form instructions. */
1127 #define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
1128 #define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
1129 #define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
1130 #define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
1131 #define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
1133 #define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
1136 /* Generate a x-form instruction in BUF and return the number of bytes written.
1139 | OPCD | RST | RA | RB | XO |RC| */
1142 gen_x_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int rb
, int xo
, int rc
)
1146 gdb_assert ((opcd
& ~0x3f) == 0);
1147 gdb_assert ((rst
& ~0x1f) == 0);
1148 gdb_assert ((ra
& ~0x1f) == 0);
1149 gdb_assert ((rb
& ~0x1f) == 0);
1150 gdb_assert ((xo
& ~0x3ff) == 0);
1151 gdb_assert ((rc
& ~1) == 0);
1153 insn
= (rst
<< 21) | (ra
<< 16) | (rb
<< 11) | (xo
<< 1) | rc
;
1154 *buf
= (opcd
<< 26) | insn
;
1158 /* Followings are frequently used x-form instructions. */
1160 #define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
1161 #define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
1162 #define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
1163 #define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
1164 /* Assume bf = cr7. */
1165 #define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
1168 /* Generate a md-form instruction in BUF and return the number of bytes written.
1170 0 6 11 16 21 27 30 31 32
1171 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
1174 gen_md_form (uint32_t *buf
, int opcd
, int rs
, int ra
, int sh
, int mb
,
1178 unsigned int n
= ((mb
& 0x1f) << 1) | ((mb
>> 5) & 0x1);
1179 unsigned int sh0_4
= sh
& 0x1f;
1180 unsigned int sh5
= (sh
>> 5) & 1;
1182 gdb_assert ((opcd
& ~0x3f) == 0);
1183 gdb_assert ((rs
& ~0x1f) == 0);
1184 gdb_assert ((ra
& ~0x1f) == 0);
1185 gdb_assert ((sh
& ~0x3f) == 0);
1186 gdb_assert ((mb
& ~0x3f) == 0);
1187 gdb_assert ((xo
& ~0x7) == 0);
1188 gdb_assert ((rc
& ~0x1) == 0);
1190 insn
= (rs
<< 21) | (ra
<< 16) | (sh0_4
<< 11) | (n
<< 5)
1191 | (sh5
<< 1) | (xo
<< 2) | (rc
& 1);
1192 *buf
= (opcd
<< 26) | insn
;
1196 /* The following are frequently used md-form instructions. */
1198 #define GEN_RLDICL(buf, ra, rs ,sh, mb) \
1199 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
1200 #define GEN_RLDICR(buf, ra, rs ,sh, mb) \
1201 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
1203 /* Generate a i-form instruction in BUF and return the number of bytes written.
1206 | OPCD | LI |AA|LK| */
1209 gen_i_form (uint32_t *buf
, int opcd
, int li
, int aa
, int lk
)
1213 gdb_assert ((opcd
& ~0x3f) == 0);
1215 insn
= (li
& 0x3fffffc) | (aa
& 1) | (lk
& 1);
1216 *buf
= (opcd
<< 26) | insn
;
1220 /* The following are frequently used i-form instructions. */
1222 #define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
1223 #define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
1225 /* Generate a b-form instruction in BUF and return the number of bytes written.
1228 | OPCD | BO | BI | BD |AA|LK| */
1231 gen_b_form (uint32_t *buf
, int opcd
, int bo
, int bi
, int bd
,
1236 gdb_assert ((opcd
& ~0x3f) == 0);
1237 gdb_assert ((bo
& ~0x1f) == 0);
1238 gdb_assert ((bi
& ~0x1f) == 0);
1240 insn
= (bo
<< 21) | (bi
<< 16) | (bd
& 0xfffc) | (aa
& 1) | (lk
& 1);
1241 *buf
= (opcd
<< 26) | insn
;
1245 /* The following are frequently used b-form instructions. */
1246 /* Assume bi = cr7. */
1247 #define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
1249 /* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
1250 respectively. They are primary used for save/restore GPRs in jump-pad,
1251 not used for bytecode compiling. */
1253 #ifdef __powerpc64__
1254 #define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
1255 GEN_LD (buf, rt, ra, si) : \
1256 GEN_LWZ (buf, rt, ra, si))
1257 #define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
1258 GEN_STD (buf, rt, ra, si) : \
1259 GEN_STW (buf, rt, ra, si))
1261 #define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
1262 #define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
1265 /* Generate a sequence of instructions to load IMM in the register REG.
1266 Write the instructions in BUF and return the number of bytes written. */
1269 gen_limm (uint32_t *buf
, int reg
, uint64_t imm
, int is_64
)
1273 if ((imm
+ 32768) < 65536)
1275 /* li reg, imm[15:0] */
1276 p
+= GEN_LI (p
, reg
, imm
);
1278 else if ((imm
>> 32) == 0)
1280 /* lis reg, imm[31:16]
1281 ori reg, reg, imm[15:0]
1282 rldicl reg, reg, 0, 32 */
1283 p
+= GEN_LIS (p
, reg
, (imm
>> 16) & 0xffff);
1284 if ((imm
& 0xffff) != 0)
1285 p
+= GEN_ORI (p
, reg
, reg
, imm
& 0xffff);
1286 /* Clear upper 32-bit if sign-bit is set. */
1287 if (imm
& (1u << 31) && is_64
)
1288 p
+= GEN_RLDICL (p
, reg
, reg
, 0, 32);
1293 /* lis reg, <imm[63:48]>
1294 ori reg, reg, <imm[48:32]>
1295 rldicr reg, reg, 32, 31
1296 oris reg, reg, <imm[31:16]>
1297 ori reg, reg, <imm[15:0]> */
1298 p
+= GEN_LIS (p
, reg
, ((imm
>> 48) & 0xffff));
1299 if (((imm
>> 32) & 0xffff) != 0)
1300 p
+= GEN_ORI (p
, reg
, reg
, ((imm
>> 32) & 0xffff));
1301 p
+= GEN_RLDICR (p
, reg
, reg
, 32, 31);
1302 if (((imm
>> 16) & 0xffff) != 0)
1303 p
+= GEN_ORIS (p
, reg
, reg
, ((imm
>> 16) & 0xffff));
1304 if ((imm
& 0xffff) != 0)
1305 p
+= GEN_ORI (p
, reg
, reg
, (imm
& 0xffff));
1311 /* Generate a sequence for atomically exchange at location LOCK.
1312 This code sequence clobbers r6, r7, r8. LOCK is the location for
1313 the atomic-xchg, OLD_VALUE is expected old value stored in the
1314 location, and R_NEW is a register for the new value. */
1317 gen_atomic_xchg (uint32_t *buf
, CORE_ADDR lock
, int old_value
, int r_new
,
1320 const int r_lock
= 6;
1321 const int r_old
= 7;
1322 const int r_tmp
= 8;
1326 1: lwarx TMP, 0, LOCK
1332 p
+= gen_limm (p
, r_lock
, lock
, is_64
);
1333 p
+= gen_limm (p
, r_old
, old_value
, is_64
);
1335 p
+= GEN_LWARX (p
, r_tmp
, 0, r_lock
);
1336 p
+= GEN_CMPW (p
, r_tmp
, r_old
);
1337 p
+= GEN_BNE (p
, -8);
1338 p
+= GEN_STWCX (p
, r_new
, 0, r_lock
);
1339 p
+= GEN_BNE (p
, -16);
1344 /* Generate a sequence of instructions for calling a function
1345 at address of FN. Return the number of bytes are written in BUF. */
1348 gen_call (uint32_t *buf
, CORE_ADDR fn
, int is_64
, int is_opd
)
1352 /* Must be called by r12 for caller to calculate TOC address. */
1353 p
+= gen_limm (p
, 12, fn
, is_64
);
1356 p
+= GEN_LOAD (p
, 11, 12, 16, is_64
);
1357 p
+= GEN_LOAD (p
, 2, 12, 8, is_64
);
1358 p
+= GEN_LOAD (p
, 12, 12, 0, is_64
);
1360 p
+= GEN_MTSPR (p
, 12, 9); /* mtctr r12 */
1361 *p
++ = 0x4e800421; /* bctrl */
1366 /* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1367 of instruction. This function is used to adjust pc-relative instructions
1371 ppc_relocate_instruction (CORE_ADDR
*to
, CORE_ADDR oldloc
)
1376 read_inferior_memory (oldloc
, (unsigned char *) &insn
, 4);
1377 op6
= PPC_OP6 (insn
);
1379 if (op6
== 18 && (insn
& 2) == 0)
1381 /* branch && AA = 0 */
1382 rel
= PPC_LI (insn
);
1383 newrel
= (oldloc
- *to
) + rel
;
1385 /* Out of range. Cannot relocate instruction. */
1386 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1389 insn
= (insn
& ~0x3fffffc) | (newrel
& 0x3fffffc);
1391 else if (op6
== 16 && (insn
& 2) == 0)
1393 /* conditional branch && AA = 0 */
1395 /* If the new relocation is too big for even a 26-bit unconditional
1396 branch, there is nothing we can do. Just abort.
1398 Otherwise, if it can be fit in 16-bit conditional branch, just
1399 copy the instruction and relocate the address.
1401 If the it's big for conditional-branch (16-bit), try to invert the
1402 condition and jump with 26-bit branch. For example,
1413 After this transform, we are actually jump from *TO+4 instead of *TO,
1414 so check the relocation again because it will be 1-insn farther then
1415 before if *TO is after OLDLOC.
1418 For BDNZT (or so) is transformed from
1430 See also "BO field encodings". */
1432 rel
= PPC_BD (insn
);
1433 newrel
= (oldloc
- *to
) + rel
;
1435 if (newrel
< (1 << 15) && newrel
>= -(1 << 15))
1436 insn
= (insn
& ~0xfffc) | (newrel
& 0xfffc);
1437 else if ((PPC_BO (insn
) & 0x14) == 0x4 || (PPC_BO (insn
) & 0x14) == 0x10)
1441 /* Out of range. Cannot relocate instruction. */
1442 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1445 if ((PPC_BO (insn
) & 0x14) == 0x4)
1447 else if ((PPC_BO (insn
) & 0x14) == 0x10)
1450 /* Jump over the unconditional branch. */
1451 insn
= (insn
& ~0xfffc) | 0x8;
1452 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1455 /* Build a unconditional branch and copy LK bit. */
1456 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1457 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1462 else if ((PPC_BO (insn
) & 0x14) == 0)
1464 uint32_t bdnz_insn
= (16 << 26) | (0x10 << 21) | 12;
1465 uint32_t bf_insn
= (16 << 26) | (0x4 << 21) | 8;
1469 /* Out of range. Cannot relocate instruction. */
1470 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1473 /* Copy BI field. */
1474 bf_insn
|= (insn
& 0x1f0000);
1476 /* Invert condition. */
1477 bdnz_insn
|= (insn
^ (1 << 22)) & (1 << 22);
1478 bf_insn
|= (insn
^ (1 << 24)) & (1 << 24);
1480 target_write_memory (*to
, (unsigned char *) &bdnz_insn
, 4);
1482 target_write_memory (*to
, (unsigned char *) &bf_insn
, 4);
1485 /* Build a unconditional branch and copy LK bit. */
1486 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1487 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1492 else /* (BO & 0x14) == 0x14, branch always. */
1494 /* Out of range. Cannot relocate instruction. */
1495 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1498 /* Build a unconditional branch and copy LK bit. */
1499 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1500 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1507 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1511 /* Implement install_fast_tracepoint_jump_pad of target_ops.
1512 See target.h for details. */
1515 ppc_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1516 CORE_ADDR collector
,
1519 CORE_ADDR
*jump_entry
,
1520 CORE_ADDR
*trampoline
,
1521 ULONGEST
*trampoline_size
,
1522 unsigned char *jjump_pad_insn
,
1523 ULONGEST
*jjump_pad_insn_size
,
1524 CORE_ADDR
*adjusted_insn_addr
,
1525 CORE_ADDR
*adjusted_insn_addr_end
,
1531 CORE_ADDR buildaddr
= *jump_entry
;
1532 const CORE_ADDR entryaddr
= *jump_entry
;
1533 int rsz
, min_frame
, frame_size
, tp_reg
;
1534 #ifdef __powerpc64__
1535 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
1536 int is_64
= register_size (regcache
->tdesc
, 0) == 8;
1537 int is_opd
= is_64
&& !is_elfv2_inferior ();
1539 int is_64
= 0, is_opd
= 0;
1542 #ifdef __powerpc64__
1545 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1548 frame_size
= (40 * rsz
) + min_frame
;
1556 frame_size
= (40 * rsz
) + min_frame
;
1558 #ifdef __powerpc64__
1562 /* Stack frame layout for this jump pad,
1564 High thread_area (r13/r2) |
1565 tpoint - collecting_t obj
1575 R0 - collected registers
1581 The code flow of this jump pad,
1586 4. Call gdb_collector
1587 5. Restore GPR and SPR
1589 7. Build a jump for back to the program
1590 8. Copy/relocate original instruction
1591 9. Build a jump for replacing original instruction. */
1593 /* Adjust stack pointer. */
1595 p
+= GEN_STDU (p
, 1, 1, -frame_size
); /* stdu r1,-frame_size(r1) */
1597 p
+= GEN_STWU (p
, 1, 1, -frame_size
); /* stwu r1,-frame_size(r1) */
1599 /* Store GPRs. Save R1 later, because it had just been modified, but
1600 we want the original value. */
1601 for (j
= 2; j
< 32; j
++)
1602 p
+= GEN_STORE (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1603 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1604 /* Set r0 to the original value of r1 before adjusting stack frame,
1605 and then save it. */
1606 p
+= GEN_ADDI (p
, 0, 1, frame_size
);
1607 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 1 * rsz
, is_64
);
1609 /* Save CR, XER, LR, and CTR. */
1610 p
+= GEN_MFCR (p
, 3); /* mfcr r3 */
1611 p
+= GEN_MFSPR (p
, 4, 1); /* mfxer r4 */
1612 p
+= GEN_MFSPR (p
, 5, 8); /* mflr r5 */
1613 p
+= GEN_MFSPR (p
, 6, 9); /* mfctr r6 */
1614 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
);/* std r3, 32(r1) */
1615 p
+= GEN_STORE (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
);/* std r4, 33(r1) */
1616 p
+= GEN_STORE (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
);/* std r5, 34(r1) */
1617 p
+= GEN_STORE (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
);/* std r6, 35(r1) */
1619 /* Save PC<tpaddr> */
1620 p
+= gen_limm (p
, 3, tpaddr
, is_64
);
1621 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 36 * rsz
, is_64
);
1624 /* Setup arguments to collector. */
1625 /* Set r4 to collected registers. */
1626 p
+= GEN_ADDI (p
, 4, 1, min_frame
);
1627 /* Set r3 to TPOINT. */
1628 p
+= gen_limm (p
, 3, tpoint
, is_64
);
1630 /* Prepare collecting_t object for lock. */
1631 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 37 * rsz
, is_64
);
1632 p
+= GEN_STORE (p
, tp_reg
, 1, min_frame
+ 38 * rsz
, is_64
);
1633 /* Set R5 to collecting object. */
1634 p
+= GEN_ADDI (p
, 5, 1, 37 * rsz
);
1636 p
+= GEN_LWSYNC (p
);
1637 p
+= gen_atomic_xchg (p
, lockaddr
, 0, 5, is_64
);
1638 p
+= GEN_LWSYNC (p
);
1640 /* Call to collector. */
1641 p
+= gen_call (p
, collector
, is_64
, is_opd
);
1643 /* Simply write 0 to release the lock. */
1644 p
+= gen_limm (p
, 3, lockaddr
, is_64
);
1645 p
+= gen_limm (p
, 4, 0, is_64
);
1646 p
+= GEN_LWSYNC (p
);
1647 p
+= GEN_STORE (p
, 4, 3, 0, is_64
);
1649 /* Restore stack and registers. */
1650 p
+= GEN_LOAD (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
); /* ld r3, 32(r1) */
1651 p
+= GEN_LOAD (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
); /* ld r4, 33(r1) */
1652 p
+= GEN_LOAD (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
); /* ld r5, 34(r1) */
1653 p
+= GEN_LOAD (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
); /* ld r6, 35(r1) */
1654 p
+= GEN_MTCR (p
, 3); /* mtcr r3 */
1655 p
+= GEN_MTSPR (p
, 4, 1); /* mtxer r4 */
1656 p
+= GEN_MTSPR (p
, 5, 8); /* mtlr r5 */
1657 p
+= GEN_MTSPR (p
, 6, 9); /* mtctr r6 */
1660 for (j
= 2; j
< 32; j
++)
1661 p
+= GEN_LOAD (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1662 p
+= GEN_LOAD (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1664 p
+= GEN_ADDI (p
, 1, 1, frame_size
);
1666 /* Flush instructions to inferior memory. */
1667 target_write_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1669 /* Now, insert the original instruction to execute in the jump pad. */
1670 *adjusted_insn_addr
= buildaddr
+ (p
- buf
) * 4;
1671 *adjusted_insn_addr_end
= *adjusted_insn_addr
;
1672 ppc_relocate_instruction (adjusted_insn_addr_end
, tpaddr
);
1674 /* Verify the relocation size. If should be 4 for normal copy,
1675 8 or 12 for some conditional branch. */
1676 if ((*adjusted_insn_addr_end
- *adjusted_insn_addr
== 0)
1677 || (*adjusted_insn_addr_end
- *adjusted_insn_addr
> 12))
1679 sprintf (err
, "E.Unexpected instruction length = %d"
1680 "when relocate instruction.",
1681 (int) (*adjusted_insn_addr_end
- *adjusted_insn_addr
));
1685 buildaddr
= *adjusted_insn_addr_end
;
1687 /* Finally, write a jump back to the program. */
1688 offset
= (tpaddr
+ 4) - buildaddr
;
1689 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1691 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1692 "(offset 0x%x > 26-bit).", offset
);
1696 p
+= GEN_B (p
, offset
);
1697 target_write_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1698 *jump_entry
= buildaddr
+ (p
- buf
) * 4;
1700 /* The jump pad is now built. Wire in a jump to our jump pad. This
1701 is always done last (by our caller actually), so that we can
1702 install fast tracepoints with threads running. This relies on
1703 the agent's atomic write support. */
1704 offset
= entryaddr
- tpaddr
;
1705 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1707 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1708 "(offset 0x%x > 26-bit).", offset
);
1712 GEN_B ((uint32_t *) jjump_pad_insn
, offset
);
1713 *jjump_pad_insn_size
= 4;
1718 /* Returns the minimum instruction length for installing a tracepoint. */
1721 ppc_get_min_fast_tracepoint_insn_len (void)
1726 /* Emits a given buffer into the target at current_insn_ptr. Length
1727 is in units of 32-bit words. */
1730 emit_insns (uint32_t *buf
, int n
)
1732 n
= n
* sizeof (uint32_t);
1733 target_write_memory (current_insn_ptr
, (unsigned char *) buf
, n
);
1734 current_insn_ptr
+= n
;
1737 #define __EMIT_ASM(NAME, INSNS) \
1740 extern uint32_t start_bcax_ ## NAME []; \
1741 extern uint32_t end_bcax_ ## NAME []; \
1742 emit_insns (start_bcax_ ## NAME, \
1743 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1744 __asm__ (".section .text.__ppcbcax\n\t" \
1745 "start_bcax_" #NAME ":\n\t" \
1747 "end_bcax_" #NAME ":\n\t" \
1751 #define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1752 #define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1756 Bytecode execution stack frame - 32-bit
1758 | LR save area (SP + 4)
1759 SP' -> +- Back chain (SP + 0)
1760 | Save r31 for access saved arguments
1761 | Save r30 for bytecode stack pointer
1762 | Save r4 for incoming argument *value
1763 | Save r3 for incoming argument regs
1764 r30 -> +- Bytecode execution stack
1766 | 64-byte (8 doublewords) at initial.
1767 | Expand stack as needed.
1770 | Some padding for minimum stack frame and 16-byte alignment.
1772 SP +- Back-chain (SP')
1778 r30 is the stack-pointer for bytecode machine.
1779 It should point to next-empty, so we can use LDU for pop.
1780 r3 is used for cache of the high part of TOP value.
1781 It was the first argument, pointer to regs.
1782 r4 is used for cache of the low part of TOP value.
1783 It was the second argument, pointer to the result.
1784 We should set *result = TOP after leaving this function.
1787 * To restore stack at epilogue
1789 * To check stack is big enough for bytecode execution.
1791 * To return execution result.
1796 /* Regardless of endian, register 3 is always high part, 4 is low part.
1797 These defines are used when the register pair is stored/loaded.
1798 Likewise, to simplify code, have a similiar define for 5:6. */
1800 #if __BYTE_ORDER == __LITTLE_ENDIAN
1801 #define TOP_FIRST "4"
1802 #define TOP_SECOND "3"
1803 #define TMP_FIRST "6"
1804 #define TMP_SECOND "5"
1806 #define TOP_FIRST "3"
1807 #define TOP_SECOND "4"
1808 #define TMP_FIRST "5"
1809 #define TMP_SECOND "6"
1812 /* Emit prologue in inferior memory. See above comments. */
1815 ppc_emit_prologue (void)
1817 EMIT_ASM (/* Save return address. */
1820 /* Adjust SP. 96 is the initial frame size. */
1822 /* Save r30 and incoming arguments. */
1823 "stw 31, 96-4(1) \n"
1824 "stw 30, 96-8(1) \n"
1825 "stw 4, 96-12(1) \n"
1826 "stw 3, 96-16(1) \n"
1827 /* Point r31 to original r1 for access arguments. */
1829 /* Set r30 to pointing stack-top. */
1831 /* Initial r3/TOP to 0. */
1836 /* Emit epilogue in inferior memory. See above comments. */
1839 ppc_emit_epilogue (void)
1841 EMIT_ASM (/* *result = TOP */
1843 "stw " TOP_FIRST
", 0(5) \n"
1844 "stw " TOP_SECOND
", 4(5) \n"
1845 /* Restore registers. */
1852 /* Return 0 for no-error. */
1858 /* TOP = stack[--sp] + TOP */
1863 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1864 "lwz " TMP_SECOND
", 4(30)\n"
1869 /* TOP = stack[--sp] - TOP */
1874 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1875 "lwz " TMP_SECOND
", 4(30) \n"
1877 "subfe 3, 3, 5 \n");
1880 /* TOP = stack[--sp] * TOP */
1885 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1886 "lwz " TMP_SECOND
", 4(30) \n"
1895 /* TOP = stack[--sp] << TOP */
1900 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1901 "lwz " TMP_SECOND
", 4(30) \n"
1902 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1903 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1904 "slw 5, 5, 4\n" /* Shift high part left */
1905 "slw 4, 6, 4\n" /* Shift low part left */
1906 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
1907 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
1909 "or 3, 7, 3\n"); /* Assemble high part */
1912 /* Top = stack[--sp] >> TOP
1913 (Arithmetic shift right) */
1916 ppc_emit_rsh_signed (void)
1918 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1919 "lwz " TMP_SECOND
", 4(30) \n"
1920 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1921 "sraw 3, 5, 4\n" /* Shift high part right */
1923 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
1924 "sraw 4, 5, 7\n" /* Shift high to low */
1927 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
1928 "srw 4, 6, 4\n" /* Shift low part right */
1929 "slw 5, 5, 7\n" /* Shift high to low */
1930 "or 4, 4, 5\n" /* Assemble low part */
1934 /* Top = stack[--sp] >> TOP
1935 (Logical shift right) */
1938 ppc_emit_rsh_unsigned (void)
1940 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1941 "lwz " TMP_SECOND
", 4(30) \n"
1942 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1943 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1944 "srw 6, 6, 4\n" /* Shift low part right */
1945 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
1946 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
1948 "srw 3, 5, 4\n" /* Shift high part right */
1949 "or 4, 6, 7\n"); /* Assemble low part */
1952 /* Emit code for signed-extension specified by ARG. */
1955 ppc_emit_ext (int arg
)
1960 EMIT_ASM ("extsb 4, 4\n"
1964 EMIT_ASM ("extsh 4, 4\n"
1968 EMIT_ASM ("srawi 3, 4, 31");
1975 /* Emit code for zero-extension specified by ARG. */
1978 ppc_emit_zero_ext (int arg
)
1983 EMIT_ASM ("clrlwi 4,4,24\n"
1987 EMIT_ASM ("clrlwi 4,4,16\n"
1991 EMIT_ASM ("li 3, 0");
1999 i.e., TOP = (TOP == 0) ? 1 : 0; */
2002 ppc_emit_log_not (void)
2004 EMIT_ASM ("or 4, 3, 4 \n"
2010 /* TOP = stack[--sp] & TOP */
2013 ppc_emit_bit_and (void)
2015 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2016 "lwz " TMP_SECOND
", 4(30) \n"
2021 /* TOP = stack[--sp] | TOP */
2024 ppc_emit_bit_or (void)
2026 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2027 "lwz " TMP_SECOND
", 4(30) \n"
2032 /* TOP = stack[--sp] ^ TOP */
2035 ppc_emit_bit_xor (void)
2037 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2038 "lwz " TMP_SECOND
", 4(30) \n"
2044 i.e., TOP = ~(TOP | TOP) */
2047 ppc_emit_bit_not (void)
2049 EMIT_ASM ("nor 3, 3, 3 \n"
2053 /* TOP = stack[--sp] == TOP */
2056 ppc_emit_equal (void)
2058 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2059 "lwz " TMP_SECOND
", 4(30) \n"
2068 /* TOP = stack[--sp] < TOP
2069 (Signed comparison) */
2072 ppc_emit_less_signed (void)
2074 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2075 "lwz " TMP_SECOND
", 4(30) \n"
2078 /* CR6 bit 0 = low less and high equal */
2079 "crand 6*4+0, 6*4+0, 7*4+2\n"
2080 /* CR7 bit 0 = (low less and high equal) or high less */
2081 "cror 7*4+0, 7*4+0, 6*4+0\n"
2083 "rlwinm 4, 4, 29, 31, 31 \n"
2087 /* TOP = stack[--sp] < TOP
2088 (Unsigned comparison) */
2091 ppc_emit_less_unsigned (void)
2093 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2094 "lwz " TMP_SECOND
", 4(30) \n"
2097 /* CR6 bit 0 = low less and high equal */
2098 "crand 6*4+0, 6*4+0, 7*4+2\n"
2099 /* CR7 bit 0 = (low less and high equal) or high less */
2100 "cror 7*4+0, 7*4+0, 6*4+0\n"
2102 "rlwinm 4, 4, 29, 31, 31 \n"
2106 /* Access the memory address in TOP in size of SIZE.
2107 Zero-extend the read value. */
2110 ppc_emit_ref (int size
)
2115 EMIT_ASM ("lbz 4, 0(4)\n"
2119 EMIT_ASM ("lhz 4, 0(4)\n"
2123 EMIT_ASM ("lwz 4, 0(4)\n"
2127 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2128 EMIT_ASM ("lwz 3, 4(4)\n"
2131 EMIT_ASM ("lwz 3, 0(4)\n"
2140 ppc_emit_const (LONGEST num
)
2145 p
+= gen_limm (p
, 3, num
>> 32 & 0xffffffff, 0);
2146 p
+= gen_limm (p
, 4, num
& 0xffffffff, 0);
2148 emit_insns (buf
, p
- buf
);
2149 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2152 /* Set TOP to the value of register REG by calling get_raw_reg function
2153 with two argument, collected buffer and register number. */
2156 ppc_emit_reg (int reg
)
2161 /* fctx->regs is passed in r3 and then saved in -16(31). */
2162 p
+= GEN_LWZ (p
, 3, 31, -16);
2163 p
+= GEN_LI (p
, 4, reg
); /* li r4, reg */
2164 p
+= gen_call (p
, get_raw_reg_func_addr (), 0, 0);
2166 emit_insns (buf
, p
- buf
);
2167 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2169 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2171 EMIT_ASM ("mr 5, 4\n"
2177 /* TOP = stack[--sp] */
2182 EMIT_ASM ("lwzu " TOP_FIRST
", 8(30) \n"
2183 "lwz " TOP_SECOND
", 4(30) \n");
2186 /* stack[sp++] = TOP
2188 Because we may use up bytecode stack, expand 8 doublewords more
2192 ppc_emit_stack_flush (void)
2194 /* Make sure bytecode stack is big enough before push.
2195 Otherwise, expand 64-byte more. */
2197 EMIT_ASM (" stw " TOP_FIRST
", 0(30) \n"
2198 " stw " TOP_SECOND
", 4(30)\n"
2199 " addi 5, 30, -(8 + 8) \n"
2202 " stwu 31, -64(1) \n"
2203 "1:addi 30, 30, -8 \n");
2206 /* Swap TOP and stack[sp-1] */
2209 ppc_emit_swap (void)
2211 EMIT_ASM ("lwz " TMP_FIRST
", 8(30) \n"
2212 "lwz " TMP_SECOND
", 12(30) \n"
2213 "stw " TOP_FIRST
", 8(30) \n"
2214 "stw " TOP_SECOND
", 12(30) \n"
2219 /* Discard N elements in the stack. Also used for ppc64. */
2222 ppc_emit_stack_adjust (int n
)
2234 p
+= GEN_ADDI (p
, 30, 30, n
);
2236 emit_insns (buf
, p
- buf
);
2237 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2240 /* Call function FN. */
2243 ppc_emit_call (CORE_ADDR fn
)
2248 p
+= gen_call (p
, fn
, 0, 0);
2250 emit_insns (buf
, p
- buf
);
2251 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2254 /* FN's prototype is `LONGEST(*fn)(int)'.
2259 ppc_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2264 /* Setup argument. arg1 is a 16-bit value. */
2265 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2266 p
+= gen_call (p
, fn
, 0, 0);
2268 emit_insns (buf
, p
- buf
);
2269 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2271 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2273 EMIT_ASM ("mr 5, 4\n"
2279 /* FN's prototype is `void(*fn)(int,LONGEST)'.
2282 TOP should be preserved/restored before/after the call. */
2285 ppc_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2290 /* Save TOP. 0(30) is next-empty. */
2291 p
+= GEN_STW (p
, 3, 30, 0);
2292 p
+= GEN_STW (p
, 4, 30, 4);
2294 /* Setup argument. arg1 is a 16-bit value. */
2295 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2297 p
+= GEN_MR (p
, 5, 4);
2298 p
+= GEN_MR (p
, 6, 3);
2302 p
+= GEN_MR (p
, 5, 3);
2303 p
+= GEN_MR (p
, 6, 4);
2305 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2306 p
+= gen_call (p
, fn
, 0, 0);
2309 p
+= GEN_LWZ (p
, 3, 30, 0);
2310 p
+= GEN_LWZ (p
, 4, 30, 4);
2312 emit_insns (buf
, p
- buf
);
2313 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2316 /* Note in the following goto ops:
2318 When emitting goto, the target address is later relocated by
2319 write_goto_address. OFFSET_P is the offset of the branch instruction
2320 in the code sequence, and SIZE_P is how to relocate the instruction,
2321 recognized by ppc_write_goto_address. In current implementation,
2322 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2325 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2328 ppc_emit_if_goto (int *offset_p
, int *size_p
)
2330 EMIT_ASM ("or. 3, 3, 4 \n"
2331 "lwzu " TOP_FIRST
", 8(30) \n"
2332 "lwz " TOP_SECOND
", 4(30) \n"
2341 /* Unconditional goto. Also used for ppc64. */
2344 ppc_emit_goto (int *offset_p
, int *size_p
)
2346 EMIT_ASM ("1:b 1b");
2354 /* Goto if stack[--sp] == TOP */
2357 ppc_emit_eq_goto (int *offset_p
, int *size_p
)
2359 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2360 "lwz " TMP_SECOND
", 4(30) \n"
2364 "lwzu " TOP_FIRST
", 8(30) \n"
2365 "lwz " TOP_SECOND
", 4(30) \n"
2374 /* Goto if stack[--sp] != TOP */
2377 ppc_emit_ne_goto (int *offset_p
, int *size_p
)
2379 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2380 "lwz " TMP_SECOND
", 4(30) \n"
2384 "lwzu " TOP_FIRST
", 8(30) \n"
2385 "lwz " TOP_SECOND
", 4(30) \n"
2394 /* Goto if stack[--sp] < TOP */
2397 ppc_emit_lt_goto (int *offset_p
, int *size_p
)
2399 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2400 "lwz " TMP_SECOND
", 4(30) \n"
2403 /* CR6 bit 0 = low less and high equal */
2404 "crand 6*4+0, 6*4+0, 7*4+2\n"
2405 /* CR7 bit 0 = (low less and high equal) or high less */
2406 "cror 7*4+0, 7*4+0, 6*4+0\n"
2407 "lwzu " TOP_FIRST
", 8(30) \n"
2408 "lwz " TOP_SECOND
", 4(30)\n"
2417 /* Goto if stack[--sp] <= TOP */
2420 ppc_emit_le_goto (int *offset_p
, int *size_p
)
2422 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2423 "lwz " TMP_SECOND
", 4(30) \n"
2426 /* CR6 bit 0 = low less/equal and high equal */
2427 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2428 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2429 "cror 7*4+0, 7*4+0, 6*4+0\n"
2430 "lwzu " TOP_FIRST
", 8(30) \n"
2431 "lwz " TOP_SECOND
", 4(30)\n"
2440 /* Goto if stack[--sp] > TOP */
2443 ppc_emit_gt_goto (int *offset_p
, int *size_p
)
2445 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2446 "lwz " TMP_SECOND
", 4(30) \n"
2449 /* CR6 bit 0 = low greater and high equal */
2450 "crand 6*4+0, 6*4+1, 7*4+2\n"
2451 /* CR7 bit 0 = (low greater and high equal) or high greater */
2452 "cror 7*4+0, 7*4+1, 6*4+0\n"
2453 "lwzu " TOP_FIRST
", 8(30) \n"
2454 "lwz " TOP_SECOND
", 4(30)\n"
2463 /* Goto if stack[--sp] >= TOP */
2466 ppc_emit_ge_goto (int *offset_p
, int *size_p
)
2468 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2469 "lwz " TMP_SECOND
", 4(30) \n"
2472 /* CR6 bit 0 = low ge and high equal */
2473 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2474 /* CR7 bit 0 = (low ge and high equal) or high greater */
2475 "cror 7*4+0, 7*4+1, 6*4+0\n"
2476 "lwzu " TOP_FIRST
", 8(30)\n"
2477 "lwz " TOP_SECOND
", 4(30)\n"
2486 /* Relocate previous emitted branch instruction. FROM is the address
2487 of the branch instruction, TO is the goto target address, and SIZE
2488 if the value we set by *SIZE_P before. Currently, it is either
2489 24 or 14 of branch and conditional-branch instruction.
2490 Also used for ppc64. */
2493 ppc_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2495 long rel
= to
- from
;
2499 read_inferior_memory (from
, (unsigned char *) &insn
, 4);
2500 opcd
= (insn
>> 26) & 0x3f;
2506 || (rel
>= (1 << 15) || rel
< -(1 << 15)))
2508 insn
= (insn
& ~0xfffc) | (rel
& 0xfffc);
2512 || (rel
>= (1 << 25) || rel
< -(1 << 25)))
2514 insn
= (insn
& ~0x3fffffc) | (rel
& 0x3fffffc);
2521 target_write_memory (from
, (unsigned char *) &insn
, 4);
2524 /* Table of emit ops for 32-bit. */
2526 static struct emit_ops ppc_emit_ops_impl
=
2534 ppc_emit_rsh_signed
,
2535 ppc_emit_rsh_unsigned
,
2543 ppc_emit_less_signed
,
2544 ppc_emit_less_unsigned
,
2548 ppc_write_goto_address
,
2553 ppc_emit_stack_flush
,
2556 ppc_emit_stack_adjust
,
2557 ppc_emit_int_call_1
,
2558 ppc_emit_void_call_2
,
2567 #ifdef __powerpc64__
2571 Bytecode execution stack frame - 64-bit
2573 | LR save area (SP + 16)
2574 | CR save area (SP + 8)
2575 SP' -> +- Back chain (SP + 0)
2576 | Save r31 for access saved arguments
2577 | Save r30 for bytecode stack pointer
2578 | Save r4 for incoming argument *value
2579 | Save r3 for incoming argument regs
2580 r30 -> +- Bytecode execution stack
2582 | 64-byte (8 doublewords) at initial.
2583 | Expand stack as needed.
2586 | Some padding for minimum stack frame.
2588 SP +- Back-chain (SP')
2591 = 112 + (4 * 8) + 64
2594 r30 is the stack-pointer for bytecode machine.
2595 It should point to next-empty, so we can use LDU for pop.
2596 r3 is used for cache of TOP value.
2597 It was the first argument, pointer to regs.
2598 r4 is the second argument, pointer to the result.
2599 We should set *result = TOP after leaving this function.
2602 * To restore stack at epilogue
2604 * To check stack is big enough for bytecode execution.
2605 => r30 - 8 > SP + 112
2606 * To return execution result.
2611 /* Emit prologue in inferior memory. See above comments. */
2614 ppc64v1_emit_prologue (void)
2616 /* On ELFv1, function pointers really point to function descriptor,
2617 so emit one here. We don't care about contents of words 1 and 2,
2618 so let them just overlap out code. */
2619 uint64_t opd
= current_insn_ptr
+ 8;
2622 /* Mind the strict aliasing rules. */
2623 memcpy (buf
, &opd
, sizeof buf
);
2625 EMIT_ASM (/* Save return address. */
2628 /* Save r30 and incoming arguments. */
2633 /* Point r31 to current r1 for access arguments. */
2635 /* Adjust SP. 208 is the initial frame size. */
2636 "stdu 1, -208(1) \n"
2637 /* Set r30 to pointing stack-top. */
2638 "addi 30, 1, 168 \n"
2639 /* Initial r3/TOP to 0. */
2643 /* Emit prologue in inferior memory. See above comments. */
2646 ppc64v2_emit_prologue (void)
2648 EMIT_ASM (/* Save return address. */
2651 /* Save r30 and incoming arguments. */
2656 /* Point r31 to current r1 for access arguments. */
2658 /* Adjust SP. 208 is the initial frame size. */
2659 "stdu 1, -208(1) \n"
2660 /* Set r30 to pointing stack-top. */
2661 "addi 30, 1, 168 \n"
2662 /* Initial r3/TOP to 0. */
2666 /* Emit epilogue in inferior memory. See above comments. */
2669 ppc64_emit_epilogue (void)
2671 EMIT_ASM (/* Restore SP. */
2676 /* Restore registers. */
2681 /* Return 0 for no-error. */
2687 /* TOP = stack[--sp] + TOP */
2690 ppc64_emit_add (void)
2692 EMIT_ASM ("ldu 4, 8(30) \n"
2696 /* TOP = stack[--sp] - TOP */
2699 ppc64_emit_sub (void)
2701 EMIT_ASM ("ldu 4, 8(30) \n"
2705 /* TOP = stack[--sp] * TOP */
2708 ppc64_emit_mul (void)
2710 EMIT_ASM ("ldu 4, 8(30) \n"
2711 "mulld 3, 4, 3 \n");
2714 /* TOP = stack[--sp] << TOP */
2717 ppc64_emit_lsh (void)
2719 EMIT_ASM ("ldu 4, 8(30) \n"
2723 /* Top = stack[--sp] >> TOP
2724 (Arithmetic shift right) */
2727 ppc64_emit_rsh_signed (void)
2729 EMIT_ASM ("ldu 4, 8(30) \n"
2733 /* Top = stack[--sp] >> TOP
2734 (Logical shift right) */
2737 ppc64_emit_rsh_unsigned (void)
2739 EMIT_ASM ("ldu 4, 8(30) \n"
2743 /* Emit code for signed-extension specified by ARG. */
2746 ppc64_emit_ext (int arg
)
2751 EMIT_ASM ("extsb 3, 3");
2754 EMIT_ASM ("extsh 3, 3");
2757 EMIT_ASM ("extsw 3, 3");
2764 /* Emit code for zero-extension specified by ARG. */
2767 ppc64_emit_zero_ext (int arg
)
2772 EMIT_ASM ("rldicl 3,3,0,56");
2775 EMIT_ASM ("rldicl 3,3,0,48");
2778 EMIT_ASM ("rldicl 3,3,0,32");
2786 i.e., TOP = (TOP == 0) ? 1 : 0; */
2789 ppc64_emit_log_not (void)
2791 EMIT_ASM ("cntlzd 3, 3 \n"
2795 /* TOP = stack[--sp] & TOP */
2798 ppc64_emit_bit_and (void)
2800 EMIT_ASM ("ldu 4, 8(30) \n"
2804 /* TOP = stack[--sp] | TOP */
2807 ppc64_emit_bit_or (void)
2809 EMIT_ASM ("ldu 4, 8(30) \n"
2813 /* TOP = stack[--sp] ^ TOP */
2816 ppc64_emit_bit_xor (void)
2818 EMIT_ASM ("ldu 4, 8(30) \n"
2823 i.e., TOP = ~(TOP | TOP) */
2826 ppc64_emit_bit_not (void)
2828 EMIT_ASM ("nor 3, 3, 3 \n");
2831 /* TOP = stack[--sp] == TOP */
2834 ppc64_emit_equal (void)
2836 EMIT_ASM ("ldu 4, 8(30) \n"
2842 /* TOP = stack[--sp] < TOP
2843 (Signed comparison) */
2846 ppc64_emit_less_signed (void)
2848 EMIT_ASM ("ldu 4, 8(30) \n"
2851 "rlwinm 3, 3, 29, 31, 31 \n");
2854 /* TOP = stack[--sp] < TOP
2855 (Unsigned comparison) */
2858 ppc64_emit_less_unsigned (void)
2860 EMIT_ASM ("ldu 4, 8(30) \n"
2863 "rlwinm 3, 3, 29, 31, 31 \n");
2866 /* Access the memory address in TOP in size of SIZE.
2867 Zero-extend the read value. */
2870 ppc64_emit_ref (int size
)
2875 EMIT_ASM ("lbz 3, 0(3)");
2878 EMIT_ASM ("lhz 3, 0(3)");
2881 EMIT_ASM ("lwz 3, 0(3)");
2884 EMIT_ASM ("ld 3, 0(3)");
2892 ppc64_emit_const (LONGEST num
)
2897 p
+= gen_limm (p
, 3, num
, 1);
2899 emit_insns (buf
, p
- buf
);
2900 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2903 /* Set TOP to the value of register REG by calling get_raw_reg function
2904 with two argument, collected buffer and register number. */
2907 ppc64v1_emit_reg (int reg
)
2912 /* fctx->regs is passed in r3 and then saved in 176(1). */
2913 p
+= GEN_LD (p
, 3, 31, -32);
2914 p
+= GEN_LI (p
, 4, reg
);
2915 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2916 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 1);
2917 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2919 emit_insns (buf
, p
- buf
);
2920 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2923 /* Likewise, for ELFv2. */
2926 ppc64v2_emit_reg (int reg
)
2931 /* fctx->regs is passed in r3 and then saved in 176(1). */
2932 p
+= GEN_LD (p
, 3, 31, -32);
2933 p
+= GEN_LI (p
, 4, reg
);
2934 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
2935 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 0);
2936 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
2938 emit_insns (buf
, p
- buf
);
2939 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2942 /* TOP = stack[--sp] */
2945 ppc64_emit_pop (void)
2947 EMIT_ASM ("ldu 3, 8(30)");
2950 /* stack[sp++] = TOP
2952 Because we may use up bytecode stack, expand 8 doublewords more
2956 ppc64_emit_stack_flush (void)
2958 /* Make sure bytecode stack is big enough before push.
2959 Otherwise, expand 64-byte more. */
2961 EMIT_ASM (" std 3, 0(30) \n"
2962 " addi 4, 30, -(112 + 8) \n"
2965 " stdu 31, -64(1) \n"
2966 "1:addi 30, 30, -8 \n");
2969 /* Swap TOP and stack[sp-1] */
2972 ppc64_emit_swap (void)
2974 EMIT_ASM ("ld 4, 8(30) \n"
2979 /* Call function FN - ELFv1. */
2982 ppc64v1_emit_call (CORE_ADDR fn
)
2987 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2988 p
+= gen_call (p
, fn
, 1, 1);
2989 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2991 emit_insns (buf
, p
- buf
);
2992 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2995 /* Call function FN - ELFv2. */
2998 ppc64v2_emit_call (CORE_ADDR fn
)
3003 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3004 p
+= gen_call (p
, fn
, 1, 0);
3005 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3007 emit_insns (buf
, p
- buf
);
3008 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3011 /* FN's prototype is `LONGEST(*fn)(int)'.
3016 ppc64v1_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
3021 /* Setup argument. arg1 is a 16-bit value. */
3022 p
+= gen_limm (p
, 3, arg1
, 1);
3023 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3024 p
+= gen_call (p
, fn
, 1, 1);
3025 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3027 emit_insns (buf
, p
- buf
);
3028 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3031 /* Likewise for ELFv2. */
3034 ppc64v2_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
3039 /* Setup argument. arg1 is a 16-bit value. */
3040 p
+= gen_limm (p
, 3, arg1
, 1);
3041 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3042 p
+= gen_call (p
, fn
, 1, 0);
3043 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3045 emit_insns (buf
, p
- buf
);
3046 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3049 /* FN's prototype is `void(*fn)(int,LONGEST)'.
3052 TOP should be preserved/restored before/after the call. */
3055 ppc64v1_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3060 /* Save TOP. 0(30) is next-empty. */
3061 p
+= GEN_STD (p
, 3, 30, 0);
3063 /* Setup argument. arg1 is a 16-bit value. */
3064 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
3065 p
+= gen_limm (p
, 3, arg1
, 1);
3066 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3067 p
+= gen_call (p
, fn
, 1, 1);
3068 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3071 p
+= GEN_LD (p
, 3, 30, 0);
3073 emit_insns (buf
, p
- buf
);
3074 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3077 /* Likewise for ELFv2. */
3080 ppc64v2_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3085 /* Save TOP. 0(30) is next-empty. */
3086 p
+= GEN_STD (p
, 3, 30, 0);
3088 /* Setup argument. arg1 is a 16-bit value. */
3089 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
3090 p
+= gen_limm (p
, 3, arg1
, 1);
3091 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3092 p
+= gen_call (p
, fn
, 1, 0);
3093 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3096 p
+= GEN_LD (p
, 3, 30, 0);
3098 emit_insns (buf
, p
- buf
);
3099 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3102 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
3105 ppc64_emit_if_goto (int *offset_p
, int *size_p
)
3107 EMIT_ASM ("cmpdi 7, 3, 0 \n"
3117 /* Goto if stack[--sp] == TOP */
3120 ppc64_emit_eq_goto (int *offset_p
, int *size_p
)
3122 EMIT_ASM ("ldu 4, 8(30) \n"
3133 /* Goto if stack[--sp] != TOP */
3136 ppc64_emit_ne_goto (int *offset_p
, int *size_p
)
3138 EMIT_ASM ("ldu 4, 8(30) \n"
3149 /* Goto if stack[--sp] < TOP */
3152 ppc64_emit_lt_goto (int *offset_p
, int *size_p
)
3154 EMIT_ASM ("ldu 4, 8(30) \n"
3165 /* Goto if stack[--sp] <= TOP */
3168 ppc64_emit_le_goto (int *offset_p
, int *size_p
)
3170 EMIT_ASM ("ldu 4, 8(30) \n"
3181 /* Goto if stack[--sp] > TOP */
3184 ppc64_emit_gt_goto (int *offset_p
, int *size_p
)
3186 EMIT_ASM ("ldu 4, 8(30) \n"
3197 /* Goto if stack[--sp] >= TOP */
3200 ppc64_emit_ge_goto (int *offset_p
, int *size_p
)
3202 EMIT_ASM ("ldu 4, 8(30) \n"
3213 /* Table of emit ops for 64-bit ELFv1. */
3215 static struct emit_ops ppc64v1_emit_ops_impl
=
3217 ppc64v1_emit_prologue
,
3218 ppc64_emit_epilogue
,
3223 ppc64_emit_rsh_signed
,
3224 ppc64_emit_rsh_unsigned
,
3232 ppc64_emit_less_signed
,
3233 ppc64_emit_less_unsigned
,
3237 ppc_write_goto_address
,
3242 ppc64_emit_stack_flush
,
3243 ppc64_emit_zero_ext
,
3245 ppc_emit_stack_adjust
,
3246 ppc64v1_emit_int_call_1
,
3247 ppc64v1_emit_void_call_2
,
3256 /* Table of emit ops for 64-bit ELFv2. */
3258 static struct emit_ops ppc64v2_emit_ops_impl
=
3260 ppc64v2_emit_prologue
,
3261 ppc64_emit_epilogue
,
3266 ppc64_emit_rsh_signed
,
3267 ppc64_emit_rsh_unsigned
,
3275 ppc64_emit_less_signed
,
3276 ppc64_emit_less_unsigned
,
3280 ppc_write_goto_address
,
3285 ppc64_emit_stack_flush
,
3286 ppc64_emit_zero_ext
,
3288 ppc_emit_stack_adjust
,
3289 ppc64v2_emit_int_call_1
,
3290 ppc64v2_emit_void_call_2
,
3301 /* Implementation of linux_target_ops method "emit_ops". */
3303 static struct emit_ops
*
3306 #ifdef __powerpc64__
3307 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3309 if (register_size (regcache
->tdesc
, 0) == 8)
3311 if (is_elfv2_inferior ())
3312 return &ppc64v2_emit_ops_impl
;
3314 return &ppc64v1_emit_ops_impl
;
3317 return &ppc_emit_ops_impl
;
3320 /* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3323 ppc_get_ipa_tdesc_idx (void)
3325 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3326 const struct target_desc
*tdesc
= regcache
->tdesc
;
3328 #ifdef __powerpc64__
3329 if (tdesc
== tdesc_powerpc_64l
)
3330 return PPC_TDESC_BASE
;
3331 if (tdesc
== tdesc_powerpc_altivec64l
)
3332 return PPC_TDESC_ALTIVEC
;
3333 if (tdesc
== tdesc_powerpc_vsx64l
)
3334 return PPC_TDESC_VSX
;
3335 if (tdesc
== tdesc_powerpc_isa205_64l
)
3336 return PPC_TDESC_ISA205
;
3337 if (tdesc
== tdesc_powerpc_isa205_altivec64l
)
3338 return PPC_TDESC_ISA205_ALTIVEC
;
3339 if (tdesc
== tdesc_powerpc_isa205_vsx64l
)
3340 return PPC_TDESC_ISA205_VSX
;
3341 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx64l
)
3342 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3343 if (tdesc
== tdesc_powerpc_isa207_vsx64l
)
3344 return PPC_TDESC_ISA207_VSX
;
3345 if (tdesc
== tdesc_powerpc_isa207_htm_vsx64l
)
3346 return PPC_TDESC_ISA207_HTM_VSX
;
3349 if (tdesc
== tdesc_powerpc_32l
)
3350 return PPC_TDESC_BASE
;
3351 if (tdesc
== tdesc_powerpc_altivec32l
)
3352 return PPC_TDESC_ALTIVEC
;
3353 if (tdesc
== tdesc_powerpc_vsx32l
)
3354 return PPC_TDESC_VSX
;
3355 if (tdesc
== tdesc_powerpc_isa205_32l
)
3356 return PPC_TDESC_ISA205
;
3357 if (tdesc
== tdesc_powerpc_isa205_altivec32l
)
3358 return PPC_TDESC_ISA205_ALTIVEC
;
3359 if (tdesc
== tdesc_powerpc_isa205_vsx32l
)
3360 return PPC_TDESC_ISA205_VSX
;
3361 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx32l
)
3362 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3363 if (tdesc
== tdesc_powerpc_isa207_vsx32l
)
3364 return PPC_TDESC_ISA207_VSX
;
3365 if (tdesc
== tdesc_powerpc_isa207_htm_vsx32l
)
3366 return PPC_TDESC_ISA207_HTM_VSX
;
3367 if (tdesc
== tdesc_powerpc_e500l
)
3368 return PPC_TDESC_E500
;
3373 struct linux_target_ops the_low_target
= {
3376 ppc_cannot_fetch_register
,
3377 ppc_cannot_store_register
,
3378 NULL
, /* fetch_register */
3381 NULL
, /* breakpoint_kind_from_pc */
3382 ppc_sw_breakpoint_from_kind
,
3386 ppc_supports_z_point_type
,
3391 ppc_collect_ptrace_register
,
3392 ppc_supply_ptrace_register
,
3393 NULL
, /* siginfo_fixup */
3394 NULL
, /* new_process */
3395 NULL
, /* delete_process */
3396 NULL
, /* new_thread */
3397 NULL
, /* delete_thread */
3398 NULL
, /* new_fork */
3399 NULL
, /* prepare_to_resume */
3400 NULL
, /* process_qsupported */
3401 ppc_supports_tracepoints
,
3402 ppc_get_thread_area
,
3403 ppc_install_fast_tracepoint_jump_pad
,
3405 ppc_get_min_fast_tracepoint_insn_len
,
3406 NULL
, /* supports_range_stepping */
3407 NULL
, /* breakpoint_kind_from_current_state */
3408 ppc_supports_hardware_single_step
,
3409 NULL
, /* get_syscall_trapinfo */
3410 ppc_get_ipa_tdesc_idx
,
3414 initialize_low_arch (void)
3416 /* Initialize the Linux target descriptions. */
3418 init_registers_powerpc_32l ();
3419 init_registers_powerpc_altivec32l ();
3420 init_registers_powerpc_vsx32l ();
3421 init_registers_powerpc_isa205_32l ();
3422 init_registers_powerpc_isa205_altivec32l ();
3423 init_registers_powerpc_isa205_vsx32l ();
3424 init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
3425 init_registers_powerpc_isa207_vsx32l ();
3426 init_registers_powerpc_isa207_htm_vsx32l ();
3427 init_registers_powerpc_e500l ();
3429 init_registers_powerpc_64l ();
3430 init_registers_powerpc_altivec64l ();
3431 init_registers_powerpc_vsx64l ();
3432 init_registers_powerpc_isa205_64l ();
3433 init_registers_powerpc_isa205_altivec64l ();
3434 init_registers_powerpc_isa205_vsx64l ();
3435 init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
3436 init_registers_powerpc_isa207_vsx64l ();
3437 init_registers_powerpc_isa207_htm_vsx64l ();
3440 initialize_regsets_info (&ppc_regsets_info
);