1 /* GNU/Linux/PowerPC specific low level interface, for the remote server for
3 Copyright (C) 1995-2020 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "linux-low.h"
23 #include "elf/common.h"
26 #include <asm/ptrace.h>
28 #include "arch/ppc-linux-common.h"
29 #include "arch/ppc-linux-tdesc.h"
30 #include "nat/ppc-linux.h"
31 #include "nat/linux-ptrace.h"
32 #include "linux-ppc-tdesc-init.h"
34 #include "tracepoint.h"
36 #define PPC_FIELD(value, from, len) \
37 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
38 #define PPC_SEXT(v, bs) \
39 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
40 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
41 - ((CORE_ADDR) 1 << ((bs) - 1)))
42 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
43 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
44 #define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
45 #define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
47 /* Linux target op definitions for the PowerPC architecture. */
49 class ppc_target
: public linux_process_target
53 const regs_info
*get_regs_info () override
;
55 const gdb_byte
*sw_breakpoint_from_kind (int kind
, int *size
) override
;
57 bool supports_z_point_type (char z_type
) override
;
60 void low_collect_ptrace_register (regcache
*regcache
, int regno
,
63 void low_supply_ptrace_register (regcache
*regcache
, int regno
,
64 const char *buf
) override
;
66 bool supports_tracepoints () override
;
70 void low_arch_setup () override
;
72 bool low_cannot_fetch_register (int regno
) override
;
74 bool low_cannot_store_register (int regno
) override
;
76 bool low_supports_breakpoints () override
;
78 CORE_ADDR
low_get_pc (regcache
*regcache
) override
;
80 void low_set_pc (regcache
*regcache
, CORE_ADDR newpc
) override
;
82 bool low_breakpoint_at (CORE_ADDR pc
) override
;
84 int low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
85 int size
, raw_breakpoint
*bp
) override
;
87 int low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
88 int size
, raw_breakpoint
*bp
) override
;
91 /* The singleton target ops object. */
93 static ppc_target the_ppc_target
;
95 /* Holds the AT_HWCAP auxv entry. */
97 static unsigned long ppc_hwcap
;
99 /* Holds the AT_HWCAP2 auxv entry. */
101 static unsigned long ppc_hwcap2
;
104 #define ppc_num_regs 73
107 /* We use a constant for FPSCR instead of PT_FPSCR, because
108 many shipped PPC64 kernels had the wrong value in ptrace.h. */
109 static int ppc_regmap
[] =
110 {PT_R0
* 8, PT_R1
* 8, PT_R2
* 8, PT_R3
* 8,
111 PT_R4
* 8, PT_R5
* 8, PT_R6
* 8, PT_R7
* 8,
112 PT_R8
* 8, PT_R9
* 8, PT_R10
* 8, PT_R11
* 8,
113 PT_R12
* 8, PT_R13
* 8, PT_R14
* 8, PT_R15
* 8,
114 PT_R16
* 8, PT_R17
* 8, PT_R18
* 8, PT_R19
* 8,
115 PT_R20
* 8, PT_R21
* 8, PT_R22
* 8, PT_R23
* 8,
116 PT_R24
* 8, PT_R25
* 8, PT_R26
* 8, PT_R27
* 8,
117 PT_R28
* 8, PT_R29
* 8, PT_R30
* 8, PT_R31
* 8,
118 PT_FPR0
*8, PT_FPR0
*8 + 8, PT_FPR0
*8+16, PT_FPR0
*8+24,
119 PT_FPR0
*8+32, PT_FPR0
*8+40, PT_FPR0
*8+48, PT_FPR0
*8+56,
120 PT_FPR0
*8+64, PT_FPR0
*8+72, PT_FPR0
*8+80, PT_FPR0
*8+88,
121 PT_FPR0
*8+96, PT_FPR0
*8+104, PT_FPR0
*8+112, PT_FPR0
*8+120,
122 PT_FPR0
*8+128, PT_FPR0
*8+136, PT_FPR0
*8+144, PT_FPR0
*8+152,
123 PT_FPR0
*8+160, PT_FPR0
*8+168, PT_FPR0
*8+176, PT_FPR0
*8+184,
124 PT_FPR0
*8+192, PT_FPR0
*8+200, PT_FPR0
*8+208, PT_FPR0
*8+216,
125 PT_FPR0
*8+224, PT_FPR0
*8+232, PT_FPR0
*8+240, PT_FPR0
*8+248,
126 PT_NIP
* 8, PT_MSR
* 8, PT_CCR
* 8, PT_LNK
* 8,
127 PT_CTR
* 8, PT_XER
* 8, PT_FPR0
*8 + 256,
128 PT_ORIG_R3
* 8, PT_TRAP
* 8 };
130 /* Currently, don't check/send MQ. */
131 static int ppc_regmap
[] =
132 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
133 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
134 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
135 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
136 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
137 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
138 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
139 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
140 PT_FPR0
*4, PT_FPR0
*4 + 8, PT_FPR0
*4+16, PT_FPR0
*4+24,
141 PT_FPR0
*4+32, PT_FPR0
*4+40, PT_FPR0
*4+48, PT_FPR0
*4+56,
142 PT_FPR0
*4+64, PT_FPR0
*4+72, PT_FPR0
*4+80, PT_FPR0
*4+88,
143 PT_FPR0
*4+96, PT_FPR0
*4+104, PT_FPR0
*4+112, PT_FPR0
*4+120,
144 PT_FPR0
*4+128, PT_FPR0
*4+136, PT_FPR0
*4+144, PT_FPR0
*4+152,
145 PT_FPR0
*4+160, PT_FPR0
*4+168, PT_FPR0
*4+176, PT_FPR0
*4+184,
146 PT_FPR0
*4+192, PT_FPR0
*4+200, PT_FPR0
*4+208, PT_FPR0
*4+216,
147 PT_FPR0
*4+224, PT_FPR0
*4+232, PT_FPR0
*4+240, PT_FPR0
*4+248,
148 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
149 PT_CTR
* 4, PT_XER
* 4, PT_FPSCR
* 4,
150 PT_ORIG_R3
* 4, PT_TRAP
* 4
153 static int ppc_regmap_e500
[] =
154 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
155 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
156 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
157 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
158 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
159 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
160 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
161 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
170 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
171 PT_CTR
* 4, PT_XER
* 4, -1,
172 PT_ORIG_R3
* 4, PT_TRAP
* 4
176 /* Check whether the kernel provides a register set with number
177 REGSET_ID of size REGSETSIZE for process/thread TID. */
180 ppc_check_regset (int tid
, int regset_id
, int regsetsize
)
182 void *buf
= alloca (regsetsize
);
186 iov
.iov_len
= regsetsize
;
188 if (ptrace (PTRACE_GETREGSET
, tid
, regset_id
, &iov
) >= 0
195 ppc_target::low_cannot_store_register (int regno
)
197 const struct target_desc
*tdesc
= current_process ()->tdesc
;
199 #ifndef __powerpc64__
200 /* Some kernels do not allow us to store fpscr. */
201 if (!(ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
202 && regno
== find_regno (tdesc
, "fpscr"))
206 /* Some kernels do not allow us to store orig_r3 or trap. */
207 if (regno
== find_regno (tdesc
, "orig_r3")
208 || regno
== find_regno (tdesc
, "trap"))
215 ppc_target::low_cannot_fetch_register (int regno
)
221 ppc_target::low_collect_ptrace_register (regcache
*regcache
, int regno
,
224 memset (buf
, 0, sizeof (long));
226 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
228 /* Little-endian values always sit at the left end of the buffer. */
229 collect_register (regcache
, regno
, buf
);
231 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
233 /* Big-endian values sit at the right end of the buffer. In case of
234 registers whose sizes are smaller than sizeof (long), we must use a
235 padding to access them correctly. */
236 int size
= register_size (regcache
->tdesc
, regno
);
238 if (size
< sizeof (long))
239 collect_register (regcache
, regno
, buf
+ sizeof (long) - size
);
241 collect_register (regcache
, regno
, buf
);
244 perror_with_name ("Unexpected byte order");
248 ppc_target::low_supply_ptrace_register (regcache
*regcache
, int regno
,
251 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
253 /* Little-endian values always sit at the left end of the buffer. */
254 supply_register (regcache
, regno
, buf
);
256 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
258 /* Big-endian values sit at the right end of the buffer. In case of
259 registers whose sizes are smaller than sizeof (long), we must use a
260 padding to access them correctly. */
261 int size
= register_size (regcache
->tdesc
, regno
);
263 if (size
< sizeof (long))
264 supply_register (regcache
, regno
, buf
+ sizeof (long) - size
);
266 supply_register (regcache
, regno
, buf
);
269 perror_with_name ("Unexpected byte order");
273 ppc_target::low_supports_breakpoints ()
279 ppc_target::low_get_pc (regcache
*regcache
)
281 if (register_size (regcache
->tdesc
, 0) == 4)
284 collect_register_by_name (regcache
, "pc", &pc
);
285 return (CORE_ADDR
) pc
;
290 collect_register_by_name (regcache
, "pc", &pc
);
291 return (CORE_ADDR
) pc
;
296 ppc_target::low_set_pc (regcache
*regcache
, CORE_ADDR pc
)
298 if (register_size (regcache
->tdesc
, 0) == 4)
300 unsigned int newpc
= pc
;
301 supply_register_by_name (regcache
, "pc", &newpc
);
305 unsigned long newpc
= pc
;
306 supply_register_by_name (regcache
, "pc", &newpc
);
310 #ifndef __powerpc64__
311 static int ppc_regmap_adjusted
;
315 /* Correct in either endianness.
316 This instruction is "twge r2, r2", which GDB uses as a software
318 static const unsigned int ppc_breakpoint
= 0x7d821008;
319 #define ppc_breakpoint_len 4
321 /* Implementation of target ops method "sw_breakpoint_from_kind". */
324 ppc_target::sw_breakpoint_from_kind (int kind
, int *size
)
326 *size
= ppc_breakpoint_len
;
327 return (const gdb_byte
*) &ppc_breakpoint
;
331 ppc_target::low_breakpoint_at (CORE_ADDR where
)
335 read_memory (where
, (unsigned char *) &insn
, 4);
336 if (insn
== ppc_breakpoint
)
338 /* If necessary, recognize more trap instructions here. GDB only uses
344 /* Implement supports_z_point_type target-ops.
345 Returns true if type Z_TYPE breakpoint is supported.
347 Handling software breakpoint at server side, so tracepoints
348 and breakpoints can be inserted at the same location. */
351 ppc_target::supports_z_point_type (char z_type
)
358 case Z_PACKET_WRITE_WP
:
359 case Z_PACKET_ACCESS_WP
:
365 /* Implement the low_insert_point linux target op.
366 Returns 0 on success, -1 on failure and 1 on unsupported. */
369 ppc_target::low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
370 int size
, raw_breakpoint
*bp
)
374 case raw_bkpt_type_sw
:
375 return insert_memory_breakpoint (bp
);
377 case raw_bkpt_type_hw
:
378 case raw_bkpt_type_write_wp
:
379 case raw_bkpt_type_access_wp
:
386 /* Implement the low_remove_point linux target op.
387 Returns 0 on success, -1 on failure and 1 on unsupported. */
390 ppc_target::low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
391 int size
, raw_breakpoint
*bp
)
395 case raw_bkpt_type_sw
:
396 return remove_memory_breakpoint (bp
);
398 case raw_bkpt_type_hw
:
399 case raw_bkpt_type_write_wp
:
400 case raw_bkpt_type_access_wp
:
407 /* Provide only a fill function for the general register set. ps_lgetregs
408 will use this for NPTL support. */
410 static void ppc_fill_gregset (struct regcache
*regcache
, void *buf
)
414 ppc_target
*my_ppc_target
= (ppc_target
*) the_linux_target
;
416 for (i
= 0; i
< 32; i
++)
417 my_ppc_target
->low_collect_ptrace_register (regcache
, i
,
418 (char *) buf
+ ppc_regmap
[i
]);
420 for (i
= 64; i
< 70; i
++)
421 my_ppc_target
->low_collect_ptrace_register (regcache
, i
,
422 (char *) buf
+ ppc_regmap
[i
]);
424 for (i
= 71; i
< 73; i
++)
425 my_ppc_target
->low_collect_ptrace_register (regcache
, i
,
426 (char *) buf
+ ppc_regmap
[i
]);
429 /* Program Priority Register regset fill function. */
432 ppc_fill_pprregset (struct regcache
*regcache
, void *buf
)
434 char *ppr
= (char *) buf
;
436 collect_register_by_name (regcache
, "ppr", ppr
);
439 /* Program Priority Register regset store function. */
442 ppc_store_pprregset (struct regcache
*regcache
, const void *buf
)
444 const char *ppr
= (const char *) buf
;
446 supply_register_by_name (regcache
, "ppr", ppr
);
449 /* Data Stream Control Register regset fill function. */
452 ppc_fill_dscrregset (struct regcache
*regcache
, void *buf
)
454 char *dscr
= (char *) buf
;
456 collect_register_by_name (regcache
, "dscr", dscr
);
459 /* Data Stream Control Register regset store function. */
462 ppc_store_dscrregset (struct regcache
*regcache
, const void *buf
)
464 const char *dscr
= (const char *) buf
;
466 supply_register_by_name (regcache
, "dscr", dscr
);
469 /* Target Address Register regset fill function. */
472 ppc_fill_tarregset (struct regcache
*regcache
, void *buf
)
474 char *tar
= (char *) buf
;
476 collect_register_by_name (regcache
, "tar", tar
);
479 /* Target Address Register regset store function. */
482 ppc_store_tarregset (struct regcache
*regcache
, const void *buf
)
484 const char *tar
= (const char *) buf
;
486 supply_register_by_name (regcache
, "tar", tar
);
489 /* Event-Based Branching regset store function. Unless the inferior
490 has a perf event open, ptrace can return in error when reading and
491 writing to the regset, with ENODATA. For reading, the registers
492 will correctly show as unavailable. For writing, gdbserver
493 currently only caches any register writes from P and G packets and
494 the stub always tries to write all the regsets when resuming the
495 inferior, which would result in frequent warnings. For this
496 reason, we don't define a fill function. This also means that the
497 client-side regcache will be dirty if the user tries to write to
498 the EBB registers. G packets that the client sends to write to
499 unrelated registers will also include data for EBB registers, even
500 if they are unavailable. */
503 ppc_store_ebbregset (struct regcache
*regcache
, const void *buf
)
505 const char *regset
= (const char *) buf
;
507 /* The order in the kernel regset is: EBBRR, EBBHR, BESCR. In the
508 .dat file is BESCR, EBBHR, EBBRR. */
509 supply_register_by_name (regcache
, "ebbrr", ®set
[0]);
510 supply_register_by_name (regcache
, "ebbhr", ®set
[8]);
511 supply_register_by_name (regcache
, "bescr", ®set
[16]);
514 /* Performance Monitoring Unit regset fill function. */
517 ppc_fill_pmuregset (struct regcache
*regcache
, void *buf
)
519 char *regset
= (char *) buf
;
521 /* The order in the kernel regset is SIAR, SDAR, SIER, MMCR2, MMCR0.
522 In the .dat file is MMCR0, MMCR2, SIAR, SDAR, SIER. */
523 collect_register_by_name (regcache
, "siar", ®set
[0]);
524 collect_register_by_name (regcache
, "sdar", ®set
[8]);
525 collect_register_by_name (regcache
, "sier", ®set
[16]);
526 collect_register_by_name (regcache
, "mmcr2", ®set
[24]);
527 collect_register_by_name (regcache
, "mmcr0", ®set
[32]);
530 /* Performance Monitoring Unit regset store function. */
533 ppc_store_pmuregset (struct regcache
*regcache
, const void *buf
)
535 const char *regset
= (const char *) buf
;
537 supply_register_by_name (regcache
, "siar", ®set
[0]);
538 supply_register_by_name (regcache
, "sdar", ®set
[8]);
539 supply_register_by_name (regcache
, "sier", ®set
[16]);
540 supply_register_by_name (regcache
, "mmcr2", ®set
[24]);
541 supply_register_by_name (regcache
, "mmcr0", ®set
[32]);
544 /* Hardware Transactional Memory special-purpose register regset fill
548 ppc_fill_tm_sprregset (struct regcache
*regcache
, void *buf
)
551 char *regset
= (char *) buf
;
553 base
= find_regno (regcache
->tdesc
, "tfhar");
554 for (i
= 0; i
< 3; i
++)
555 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
558 /* Hardware Transactional Memory special-purpose register regset store
562 ppc_store_tm_sprregset (struct regcache
*regcache
, const void *buf
)
565 const char *regset
= (const char *) buf
;
567 base
= find_regno (regcache
->tdesc
, "tfhar");
568 for (i
= 0; i
< 3; i
++)
569 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
572 /* For the same reasons as the EBB regset, none of the HTM
573 checkpointed regsets have a fill function. These registers are
574 only available if the inferior is in a transaction. */
576 /* Hardware Transactional Memory checkpointed general-purpose regset
580 ppc_store_tm_cgprregset (struct regcache
*regcache
, const void *buf
)
582 int i
, base
, size
, endian_offset
;
583 const char *regset
= (const char *) buf
;
585 base
= find_regno (regcache
->tdesc
, "cr0");
586 size
= register_size (regcache
->tdesc
, base
);
588 gdb_assert (size
== 4 || size
== 8);
590 for (i
= 0; i
< 32; i
++)
591 supply_register (regcache
, base
+ i
, ®set
[i
* size
]);
595 if ((size
== 8) && (__BYTE_ORDER
== __BIG_ENDIAN
))
598 supply_register_by_name (regcache
, "ccr",
599 ®set
[PT_CCR
* size
+ endian_offset
]);
601 supply_register_by_name (regcache
, "cxer",
602 ®set
[PT_XER
* size
+ endian_offset
]);
604 supply_register_by_name (regcache
, "clr", ®set
[PT_LNK
* size
]);
605 supply_register_by_name (regcache
, "cctr", ®set
[PT_CTR
* size
]);
608 /* Hardware Transactional Memory checkpointed floating-point regset
612 ppc_store_tm_cfprregset (struct regcache
*regcache
, const void *buf
)
615 const char *regset
= (const char *) buf
;
617 base
= find_regno (regcache
->tdesc
, "cf0");
619 for (i
= 0; i
< 32; i
++)
620 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
622 supply_register_by_name (regcache
, "cfpscr", ®set
[32 * 8]);
625 /* Hardware Transactional Memory checkpointed vector regset store
629 ppc_store_tm_cvrregset (struct regcache
*regcache
, const void *buf
)
632 const char *regset
= (const char *) buf
;
635 base
= find_regno (regcache
->tdesc
, "cvr0");
637 for (i
= 0; i
< 32; i
++)
638 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
640 if (__BYTE_ORDER
== __BIG_ENDIAN
)
643 supply_register_by_name (regcache
, "cvscr",
644 ®set
[32 * 16 + vscr_offset
]);
646 supply_register_by_name (regcache
, "cvrsave", ®set
[33 * 16]);
649 /* Hardware Transactional Memory checkpointed vector-scalar regset
653 ppc_store_tm_cvsxregset (struct regcache
*regcache
, const void *buf
)
656 const char *regset
= (const char *) buf
;
658 base
= find_regno (regcache
->tdesc
, "cvs0h");
659 for (i
= 0; i
< 32; i
++)
660 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
663 /* Hardware Transactional Memory checkpointed Program Priority
664 Register regset store function. */
667 ppc_store_tm_cpprregset (struct regcache
*regcache
, const void *buf
)
669 const char *cppr
= (const char *) buf
;
671 supply_register_by_name (regcache
, "cppr", cppr
);
674 /* Hardware Transactional Memory checkpointed Data Stream Control
675 Register regset store function. */
678 ppc_store_tm_cdscrregset (struct regcache
*regcache
, const void *buf
)
680 const char *cdscr
= (const char *) buf
;
682 supply_register_by_name (regcache
, "cdscr", cdscr
);
685 /* Hardware Transactional Memory checkpointed Target Address Register
686 regset store function. */
689 ppc_store_tm_ctarregset (struct regcache
*regcache
, const void *buf
)
691 const char *ctar
= (const char *) buf
;
693 supply_register_by_name (regcache
, "ctar", ctar
);
697 ppc_fill_vsxregset (struct regcache
*regcache
, void *buf
)
700 char *regset
= (char *) buf
;
702 base
= find_regno (regcache
->tdesc
, "vs0h");
703 for (i
= 0; i
< 32; i
++)
704 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
708 ppc_store_vsxregset (struct regcache
*regcache
, const void *buf
)
711 const char *regset
= (const char *) buf
;
713 base
= find_regno (regcache
->tdesc
, "vs0h");
714 for (i
= 0; i
< 32; i
++)
715 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
719 ppc_fill_vrregset (struct regcache
*regcache
, void *buf
)
722 char *regset
= (char *) buf
;
725 base
= find_regno (regcache
->tdesc
, "vr0");
726 for (i
= 0; i
< 32; i
++)
727 collect_register (regcache
, base
+ i
, ®set
[i
* 16]);
729 if (__BYTE_ORDER
== __BIG_ENDIAN
)
732 collect_register_by_name (regcache
, "vscr",
733 ®set
[32 * 16 + vscr_offset
]);
735 collect_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
739 ppc_store_vrregset (struct regcache
*regcache
, const void *buf
)
742 const char *regset
= (const char *) buf
;
745 base
= find_regno (regcache
->tdesc
, "vr0");
746 for (i
= 0; i
< 32; i
++)
747 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
749 if (__BYTE_ORDER
== __BIG_ENDIAN
)
752 supply_register_by_name (regcache
, "vscr",
753 ®set
[32 * 16 + vscr_offset
]);
754 supply_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
757 struct gdb_evrregset_t
759 unsigned long evr
[32];
760 unsigned long long acc
;
761 unsigned long spefscr
;
765 ppc_fill_evrregset (struct regcache
*regcache
, void *buf
)
768 struct gdb_evrregset_t
*regset
= (struct gdb_evrregset_t
*) buf
;
770 ev0
= find_regno (regcache
->tdesc
, "ev0h");
771 for (i
= 0; i
< 32; i
++)
772 collect_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
774 collect_register_by_name (regcache
, "acc", ®set
->acc
);
775 collect_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
779 ppc_store_evrregset (struct regcache
*regcache
, const void *buf
)
782 const struct gdb_evrregset_t
*regset
= (const struct gdb_evrregset_t
*) buf
;
784 ev0
= find_regno (regcache
->tdesc
, "ev0h");
785 for (i
= 0; i
< 32; i
++)
786 supply_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
788 supply_register_by_name (regcache
, "acc", ®set
->acc
);
789 supply_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
792 /* Support for hardware single step. */
795 ppc_supports_hardware_single_step (void)
800 static struct regset_info ppc_regsets
[] = {
801 /* List the extra register sets before GENERAL_REGS. That way we will
802 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
803 general registers. Some kernels support these, but not the newer
804 PPC_PTRACE_GETREGS. */
805 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CTAR
, 0, EXTENDED_REGS
,
806 NULL
, ppc_store_tm_ctarregset
},
807 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CDSCR
, 0, EXTENDED_REGS
,
808 NULL
, ppc_store_tm_cdscrregset
},
809 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CPPR
, 0, EXTENDED_REGS
,
810 NULL
, ppc_store_tm_cpprregset
},
811 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CVSX
, 0, EXTENDED_REGS
,
812 NULL
, ppc_store_tm_cvsxregset
},
813 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CVMX
, 0, EXTENDED_REGS
,
814 NULL
, ppc_store_tm_cvrregset
},
815 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CFPR
, 0, EXTENDED_REGS
,
816 NULL
, ppc_store_tm_cfprregset
},
817 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CGPR
, 0, EXTENDED_REGS
,
818 NULL
, ppc_store_tm_cgprregset
},
819 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_SPR
, 0, EXTENDED_REGS
,
820 ppc_fill_tm_sprregset
, ppc_store_tm_sprregset
},
821 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_EBB
, 0, EXTENDED_REGS
,
822 NULL
, ppc_store_ebbregset
},
823 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PMU
, 0, EXTENDED_REGS
,
824 ppc_fill_pmuregset
, ppc_store_pmuregset
},
825 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TAR
, 0, EXTENDED_REGS
,
826 ppc_fill_tarregset
, ppc_store_tarregset
},
827 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PPR
, 0, EXTENDED_REGS
,
828 ppc_fill_pprregset
, ppc_store_pprregset
},
829 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_DSCR
, 0, EXTENDED_REGS
,
830 ppc_fill_dscrregset
, ppc_store_dscrregset
},
831 { PTRACE_GETVSXREGS
, PTRACE_SETVSXREGS
, 0, 0, EXTENDED_REGS
,
832 ppc_fill_vsxregset
, ppc_store_vsxregset
},
833 { PTRACE_GETVRREGS
, PTRACE_SETVRREGS
, 0, 0, EXTENDED_REGS
,
834 ppc_fill_vrregset
, ppc_store_vrregset
},
835 { PTRACE_GETEVRREGS
, PTRACE_SETEVRREGS
, 0, 0, EXTENDED_REGS
,
836 ppc_fill_evrregset
, ppc_store_evrregset
},
837 { 0, 0, 0, 0, GENERAL_REGS
, ppc_fill_gregset
, NULL
},
841 static struct usrregs_info ppc_usrregs_info
=
847 static struct regsets_info ppc_regsets_info
=
849 ppc_regsets
, /* regsets */
851 NULL
, /* disabled_regsets */
854 static struct regs_info myregs_info
=
856 NULL
, /* regset_bitmap */
862 ppc_target::get_regs_info ()
868 ppc_target::low_arch_setup ()
870 const struct target_desc
*tdesc
;
871 struct regset_info
*regset
;
872 struct ppc_linux_features features
= ppc_linux_no_features
;
874 int tid
= lwpid_of (current_thread
);
876 features
.wordsize
= ppc_linux_target_wordsize (tid
);
878 if (features
.wordsize
== 4)
879 tdesc
= tdesc_powerpc_32l
;
881 tdesc
= tdesc_powerpc_64l
;
883 current_process ()->tdesc
= tdesc
;
885 /* The value of current_process ()->tdesc needs to be set for this
887 ppc_hwcap
= linux_get_hwcap (features
.wordsize
);
888 ppc_hwcap2
= linux_get_hwcap2 (features
.wordsize
);
890 features
.isa205
= ppc_linux_has_isa205 (ppc_hwcap
);
892 if (ppc_hwcap
& PPC_FEATURE_HAS_VSX
)
895 if (ppc_hwcap
& PPC_FEATURE_HAS_ALTIVEC
)
896 features
.altivec
= true;
898 if ((ppc_hwcap2
& PPC_FEATURE2_DSCR
)
899 && ppc_check_regset (tid
, NT_PPC_DSCR
, PPC_LINUX_SIZEOF_DSCRREGSET
)
900 && ppc_check_regset (tid
, NT_PPC_PPR
, PPC_LINUX_SIZEOF_PPRREGSET
))
902 features
.ppr_dscr
= true;
903 if ((ppc_hwcap2
& PPC_FEATURE2_ARCH_2_07
)
904 && (ppc_hwcap2
& PPC_FEATURE2_TAR
)
905 && (ppc_hwcap2
& PPC_FEATURE2_EBB
)
906 && ppc_check_regset (tid
, NT_PPC_TAR
,
907 PPC_LINUX_SIZEOF_TARREGSET
)
908 && ppc_check_regset (tid
, NT_PPC_EBB
,
909 PPC_LINUX_SIZEOF_EBBREGSET
)
910 && ppc_check_regset (tid
, NT_PPC_PMU
,
911 PPC_LINUX_SIZEOF_PMUREGSET
))
913 features
.isa207
= true;
914 if ((ppc_hwcap2
& PPC_FEATURE2_HTM
)
915 && ppc_check_regset (tid
, NT_PPC_TM_SPR
,
916 PPC_LINUX_SIZEOF_TM_SPRREGSET
))
921 tdesc
= ppc_linux_match_description (features
);
923 /* On 32-bit machines, check for SPE registers.
924 Set the low target's regmap field as appropriately. */
925 #ifndef __powerpc64__
926 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
927 tdesc
= tdesc_powerpc_e500l
;
929 if (!ppc_regmap_adjusted
)
931 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
932 ppc_usrregs_info
.regmap
= ppc_regmap_e500
;
934 /* If the FPSCR is 64-bit wide, we need to fetch the whole
935 64-bit slot and not just its second word. The PT_FPSCR
936 supplied in a 32-bit GDB compilation doesn't reflect
938 if (register_size (tdesc
, 70) == 8)
939 ppc_regmap
[70] = (48 + 2*32) * sizeof (long);
941 ppc_regmap_adjusted
= 1;
945 current_process ()->tdesc
= tdesc
;
947 for (regset
= ppc_regsets
; regset
->size
>= 0; regset
++)
948 switch (regset
->get_request
)
950 case PTRACE_GETVRREGS
:
951 regset
->size
= features
.altivec
? PPC_LINUX_SIZEOF_VRREGSET
: 0;
953 case PTRACE_GETVSXREGS
:
954 regset
->size
= features
.vsx
? PPC_LINUX_SIZEOF_VSXREGSET
: 0;
956 case PTRACE_GETEVRREGS
:
957 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
958 regset
->size
= 32 * 4 + 8 + 4;
962 case PTRACE_GETREGSET
:
963 switch (regset
->nt_type
)
966 regset
->size
= (features
.ppr_dscr
?
967 PPC_LINUX_SIZEOF_PPRREGSET
: 0);
970 regset
->size
= (features
.ppr_dscr
?
971 PPC_LINUX_SIZEOF_DSCRREGSET
: 0);
974 regset
->size
= (features
.isa207
?
975 PPC_LINUX_SIZEOF_TARREGSET
: 0);
978 regset
->size
= (features
.isa207
?
979 PPC_LINUX_SIZEOF_EBBREGSET
: 0);
982 regset
->size
= (features
.isa207
?
983 PPC_LINUX_SIZEOF_PMUREGSET
: 0);
986 regset
->size
= (features
.htm
?
987 PPC_LINUX_SIZEOF_TM_SPRREGSET
: 0);
990 if (features
.wordsize
== 4)
991 regset
->size
= (features
.htm
?
992 PPC32_LINUX_SIZEOF_CGPRREGSET
: 0);
994 regset
->size
= (features
.htm
?
995 PPC64_LINUX_SIZEOF_CGPRREGSET
: 0);
998 regset
->size
= (features
.htm
?
999 PPC_LINUX_SIZEOF_CFPRREGSET
: 0);
1001 case NT_PPC_TM_CVMX
:
1002 regset
->size
= (features
.htm
?
1003 PPC_LINUX_SIZEOF_CVMXREGSET
: 0);
1005 case NT_PPC_TM_CVSX
:
1006 regset
->size
= (features
.htm
?
1007 PPC_LINUX_SIZEOF_CVSXREGSET
: 0);
1009 case NT_PPC_TM_CPPR
:
1010 regset
->size
= (features
.htm
?
1011 PPC_LINUX_SIZEOF_CPPRREGSET
: 0);
1013 case NT_PPC_TM_CDSCR
:
1014 regset
->size
= (features
.htm
?
1015 PPC_LINUX_SIZEOF_CDSCRREGSET
: 0);
1017 case NT_PPC_TM_CTAR
:
1018 regset
->size
= (features
.htm
?
1019 PPC_LINUX_SIZEOF_CTARREGSET
: 0);
1030 /* Implementation of target ops method "supports_tracepoints". */
1033 ppc_target::supports_tracepoints ()
1038 /* Get the thread area address. This is used to recognize which
1039 thread is which when tracing with the in-process agent library. We
1040 don't read anything from the address, and treat it as opaque; it's
1041 the address itself that we assume is unique per-thread. */
1044 ppc_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
1046 struct lwp_info
*lwp
= find_lwp_pid (ptid_t (lwpid
));
1047 struct thread_info
*thr
= get_lwp_thread (lwp
);
1048 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
1051 #ifdef __powerpc64__
1052 if (register_size (regcache
->tdesc
, 0) == 8)
1053 collect_register_by_name (regcache
, "r13", &tp
);
1056 collect_register_by_name (regcache
, "r2", &tp
);
1063 #ifdef __powerpc64__
1065 /* Older glibc doesn't provide this. */
1067 #ifndef EF_PPC64_ABI
1068 #define EF_PPC64_ABI 3
1071 /* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
1075 is_elfv2_inferior (void)
1077 /* To be used as fallback if we're unable to determine the right result -
1078 assume inferior uses the same ABI as gdbserver. */
1080 const int def_res
= 1;
1082 const int def_res
= 0;
1087 const struct target_desc
*tdesc
= current_process ()->tdesc
;
1088 int wordsize
= register_size (tdesc
, 0);
1090 if (!linux_get_auxv (wordsize
, AT_PHDR
, &phdr
))
1093 /* Assume ELF header is at the beginning of the page where program headers
1094 are located. If it doesn't look like one, bail. */
1096 read_inferior_memory (phdr
& ~0xfff, (unsigned char *) &ehdr
, sizeof ehdr
);
1097 if (memcmp(ehdr
.e_ident
, ELFMAG
, SELFMAG
))
1100 return (ehdr
.e_flags
& EF_PPC64_ABI
) == 2;
1105 /* Generate a ds-form instruction in BUF and return the number of bytes written
1108 | OPCD | RST | RA | DS |XO| */
1110 __attribute__((unused
)) /* Maybe unused due to conditional compilation. */
1112 gen_ds_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int ds
, int xo
)
1116 gdb_assert ((opcd
& ~0x3f) == 0);
1117 gdb_assert ((rst
& ~0x1f) == 0);
1118 gdb_assert ((ra
& ~0x1f) == 0);
1119 gdb_assert ((xo
& ~0x3) == 0);
1121 insn
= (rst
<< 21) | (ra
<< 16) | (ds
& 0xfffc) | (xo
& 0x3);
1122 *buf
= (opcd
<< 26) | insn
;
1126 /* Followings are frequently used ds-form instructions. */
1128 #define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
1129 #define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
1130 #define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
1131 #define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
1133 /* Generate a d-form instruction in BUF.
1136 | OPCD | RST | RA | D | */
1139 gen_d_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int si
)
1143 gdb_assert ((opcd
& ~0x3f) == 0);
1144 gdb_assert ((rst
& ~0x1f) == 0);
1145 gdb_assert ((ra
& ~0x1f) == 0);
1147 insn
= (rst
<< 21) | (ra
<< 16) | (si
& 0xffff);
1148 *buf
= (opcd
<< 26) | insn
;
1152 /* Followings are frequently used d-form instructions. */
1154 #define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
1155 #define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
1156 #define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
1157 #define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
1158 #define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
1159 #define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
1160 #define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
1161 #define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
1162 #define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
1164 /* Generate a xfx-form instruction in BUF and return the number of bytes
1168 | OPCD | RST | RI | XO |/| */
1171 gen_xfx_form (uint32_t *buf
, int opcd
, int rst
, int ri
, int xo
)
1174 unsigned int n
= ((ri
& 0x1f) << 5) | ((ri
>> 5) & 0x1f);
1176 gdb_assert ((opcd
& ~0x3f) == 0);
1177 gdb_assert ((rst
& ~0x1f) == 0);
1178 gdb_assert ((xo
& ~0x3ff) == 0);
1180 insn
= (rst
<< 21) | (n
<< 11) | (xo
<< 1);
1181 *buf
= (opcd
<< 26) | insn
;
1185 /* Followings are frequently used xfx-form instructions. */
1187 #define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
1188 #define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
1189 #define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
1190 #define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
1191 #define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
1193 #define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
1196 /* Generate a x-form instruction in BUF and return the number of bytes written.
1199 | OPCD | RST | RA | RB | XO |RC| */
1202 gen_x_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int rb
, int xo
, int rc
)
1206 gdb_assert ((opcd
& ~0x3f) == 0);
1207 gdb_assert ((rst
& ~0x1f) == 0);
1208 gdb_assert ((ra
& ~0x1f) == 0);
1209 gdb_assert ((rb
& ~0x1f) == 0);
1210 gdb_assert ((xo
& ~0x3ff) == 0);
1211 gdb_assert ((rc
& ~1) == 0);
1213 insn
= (rst
<< 21) | (ra
<< 16) | (rb
<< 11) | (xo
<< 1) | rc
;
1214 *buf
= (opcd
<< 26) | insn
;
1218 /* Followings are frequently used x-form instructions. */
1220 #define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
1221 #define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
1222 #define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
1223 #define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
1224 /* Assume bf = cr7. */
1225 #define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
1228 /* Generate a md-form instruction in BUF and return the number of bytes written.
1230 0 6 11 16 21 27 30 31 32
1231 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
1234 gen_md_form (uint32_t *buf
, int opcd
, int rs
, int ra
, int sh
, int mb
,
1238 unsigned int n
= ((mb
& 0x1f) << 1) | ((mb
>> 5) & 0x1);
1239 unsigned int sh0_4
= sh
& 0x1f;
1240 unsigned int sh5
= (sh
>> 5) & 1;
1242 gdb_assert ((opcd
& ~0x3f) == 0);
1243 gdb_assert ((rs
& ~0x1f) == 0);
1244 gdb_assert ((ra
& ~0x1f) == 0);
1245 gdb_assert ((sh
& ~0x3f) == 0);
1246 gdb_assert ((mb
& ~0x3f) == 0);
1247 gdb_assert ((xo
& ~0x7) == 0);
1248 gdb_assert ((rc
& ~0x1) == 0);
1250 insn
= (rs
<< 21) | (ra
<< 16) | (sh0_4
<< 11) | (n
<< 5)
1251 | (sh5
<< 1) | (xo
<< 2) | (rc
& 1);
1252 *buf
= (opcd
<< 26) | insn
;
1256 /* The following are frequently used md-form instructions. */
1258 #define GEN_RLDICL(buf, ra, rs ,sh, mb) \
1259 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
1260 #define GEN_RLDICR(buf, ra, rs ,sh, mb) \
1261 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
1263 /* Generate a i-form instruction in BUF and return the number of bytes written.
1266 | OPCD | LI |AA|LK| */
1269 gen_i_form (uint32_t *buf
, int opcd
, int li
, int aa
, int lk
)
1273 gdb_assert ((opcd
& ~0x3f) == 0);
1275 insn
= (li
& 0x3fffffc) | (aa
& 1) | (lk
& 1);
1276 *buf
= (opcd
<< 26) | insn
;
1280 /* The following are frequently used i-form instructions. */
1282 #define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
1283 #define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
1285 /* Generate a b-form instruction in BUF and return the number of bytes written.
1288 | OPCD | BO | BI | BD |AA|LK| */
1291 gen_b_form (uint32_t *buf
, int opcd
, int bo
, int bi
, int bd
,
1296 gdb_assert ((opcd
& ~0x3f) == 0);
1297 gdb_assert ((bo
& ~0x1f) == 0);
1298 gdb_assert ((bi
& ~0x1f) == 0);
1300 insn
= (bo
<< 21) | (bi
<< 16) | (bd
& 0xfffc) | (aa
& 1) | (lk
& 1);
1301 *buf
= (opcd
<< 26) | insn
;
1305 /* The following are frequently used b-form instructions. */
1306 /* Assume bi = cr7. */
1307 #define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
1309 /* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
1310 respectively. They are primary used for save/restore GPRs in jump-pad,
1311 not used for bytecode compiling. */
1313 #ifdef __powerpc64__
1314 #define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
1315 GEN_LD (buf, rt, ra, si) : \
1316 GEN_LWZ (buf, rt, ra, si))
1317 #define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
1318 GEN_STD (buf, rt, ra, si) : \
1319 GEN_STW (buf, rt, ra, si))
1321 #define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
1322 #define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
1325 /* Generate a sequence of instructions to load IMM in the register REG.
1326 Write the instructions in BUF and return the number of bytes written. */
1329 gen_limm (uint32_t *buf
, int reg
, uint64_t imm
, int is_64
)
1333 if ((imm
+ 32768) < 65536)
1335 /* li reg, imm[15:0] */
1336 p
+= GEN_LI (p
, reg
, imm
);
1338 else if ((imm
>> 32) == 0)
1340 /* lis reg, imm[31:16]
1341 ori reg, reg, imm[15:0]
1342 rldicl reg, reg, 0, 32 */
1343 p
+= GEN_LIS (p
, reg
, (imm
>> 16) & 0xffff);
1344 if ((imm
& 0xffff) != 0)
1345 p
+= GEN_ORI (p
, reg
, reg
, imm
& 0xffff);
1346 /* Clear upper 32-bit if sign-bit is set. */
1347 if (imm
& (1u << 31) && is_64
)
1348 p
+= GEN_RLDICL (p
, reg
, reg
, 0, 32);
1353 /* lis reg, <imm[63:48]>
1354 ori reg, reg, <imm[48:32]>
1355 rldicr reg, reg, 32, 31
1356 oris reg, reg, <imm[31:16]>
1357 ori reg, reg, <imm[15:0]> */
1358 p
+= GEN_LIS (p
, reg
, ((imm
>> 48) & 0xffff));
1359 if (((imm
>> 32) & 0xffff) != 0)
1360 p
+= GEN_ORI (p
, reg
, reg
, ((imm
>> 32) & 0xffff));
1361 p
+= GEN_RLDICR (p
, reg
, reg
, 32, 31);
1362 if (((imm
>> 16) & 0xffff) != 0)
1363 p
+= GEN_ORIS (p
, reg
, reg
, ((imm
>> 16) & 0xffff));
1364 if ((imm
& 0xffff) != 0)
1365 p
+= GEN_ORI (p
, reg
, reg
, (imm
& 0xffff));
1371 /* Generate a sequence for atomically exchange at location LOCK.
1372 This code sequence clobbers r6, r7, r8. LOCK is the location for
1373 the atomic-xchg, OLD_VALUE is expected old value stored in the
1374 location, and R_NEW is a register for the new value. */
1377 gen_atomic_xchg (uint32_t *buf
, CORE_ADDR lock
, int old_value
, int r_new
,
1380 const int r_lock
= 6;
1381 const int r_old
= 7;
1382 const int r_tmp
= 8;
1386 1: lwarx TMP, 0, LOCK
1392 p
+= gen_limm (p
, r_lock
, lock
, is_64
);
1393 p
+= gen_limm (p
, r_old
, old_value
, is_64
);
1395 p
+= GEN_LWARX (p
, r_tmp
, 0, r_lock
);
1396 p
+= GEN_CMPW (p
, r_tmp
, r_old
);
1397 p
+= GEN_BNE (p
, -8);
1398 p
+= GEN_STWCX (p
, r_new
, 0, r_lock
);
1399 p
+= GEN_BNE (p
, -16);
1404 /* Generate a sequence of instructions for calling a function
1405 at address of FN. Return the number of bytes are written in BUF. */
1408 gen_call (uint32_t *buf
, CORE_ADDR fn
, int is_64
, int is_opd
)
1412 /* Must be called by r12 for caller to calculate TOC address. */
1413 p
+= gen_limm (p
, 12, fn
, is_64
);
1416 p
+= GEN_LOAD (p
, 11, 12, 16, is_64
);
1417 p
+= GEN_LOAD (p
, 2, 12, 8, is_64
);
1418 p
+= GEN_LOAD (p
, 12, 12, 0, is_64
);
1420 p
+= GEN_MTSPR (p
, 12, 9); /* mtctr r12 */
1421 *p
++ = 0x4e800421; /* bctrl */
1426 /* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1427 of instruction. This function is used to adjust pc-relative instructions
1431 ppc_relocate_instruction (CORE_ADDR
*to
, CORE_ADDR oldloc
)
1436 read_inferior_memory (oldloc
, (unsigned char *) &insn
, 4);
1437 op6
= PPC_OP6 (insn
);
1439 if (op6
== 18 && (insn
& 2) == 0)
1441 /* branch && AA = 0 */
1442 rel
= PPC_LI (insn
);
1443 newrel
= (oldloc
- *to
) + rel
;
1445 /* Out of range. Cannot relocate instruction. */
1446 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1449 insn
= (insn
& ~0x3fffffc) | (newrel
& 0x3fffffc);
1451 else if (op6
== 16 && (insn
& 2) == 0)
1453 /* conditional branch && AA = 0 */
1455 /* If the new relocation is too big for even a 26-bit unconditional
1456 branch, there is nothing we can do. Just abort.
1458 Otherwise, if it can be fit in 16-bit conditional branch, just
1459 copy the instruction and relocate the address.
1461 If the it's big for conditional-branch (16-bit), try to invert the
1462 condition and jump with 26-bit branch. For example,
1473 After this transform, we are actually jump from *TO+4 instead of *TO,
1474 so check the relocation again because it will be 1-insn farther then
1475 before if *TO is after OLDLOC.
1478 For BDNZT (or so) is transformed from
1490 See also "BO field encodings". */
1492 rel
= PPC_BD (insn
);
1493 newrel
= (oldloc
- *to
) + rel
;
1495 if (newrel
< (1 << 15) && newrel
>= -(1 << 15))
1496 insn
= (insn
& ~0xfffc) | (newrel
& 0xfffc);
1497 else if ((PPC_BO (insn
) & 0x14) == 0x4 || (PPC_BO (insn
) & 0x14) == 0x10)
1501 /* Out of range. Cannot relocate instruction. */
1502 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1505 if ((PPC_BO (insn
) & 0x14) == 0x4)
1507 else if ((PPC_BO (insn
) & 0x14) == 0x10)
1510 /* Jump over the unconditional branch. */
1511 insn
= (insn
& ~0xfffc) | 0x8;
1512 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1515 /* Build a unconditional branch and copy LK bit. */
1516 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1517 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1522 else if ((PPC_BO (insn
) & 0x14) == 0)
1524 uint32_t bdnz_insn
= (16 << 26) | (0x10 << 21) | 12;
1525 uint32_t bf_insn
= (16 << 26) | (0x4 << 21) | 8;
1529 /* Out of range. Cannot relocate instruction. */
1530 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1533 /* Copy BI field. */
1534 bf_insn
|= (insn
& 0x1f0000);
1536 /* Invert condition. */
1537 bdnz_insn
|= (insn
^ (1 << 22)) & (1 << 22);
1538 bf_insn
|= (insn
^ (1 << 24)) & (1 << 24);
1540 target_write_memory (*to
, (unsigned char *) &bdnz_insn
, 4);
1542 target_write_memory (*to
, (unsigned char *) &bf_insn
, 4);
1545 /* Build a unconditional branch and copy LK bit. */
1546 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1547 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1552 else /* (BO & 0x14) == 0x14, branch always. */
1554 /* Out of range. Cannot relocate instruction. */
1555 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1558 /* Build a unconditional branch and copy LK bit. */
1559 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1560 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1567 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1571 /* Implement install_fast_tracepoint_jump_pad of target_ops.
1572 See target.h for details. */
1575 ppc_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1576 CORE_ADDR collector
,
1579 CORE_ADDR
*jump_entry
,
1580 CORE_ADDR
*trampoline
,
1581 ULONGEST
*trampoline_size
,
1582 unsigned char *jjump_pad_insn
,
1583 ULONGEST
*jjump_pad_insn_size
,
1584 CORE_ADDR
*adjusted_insn_addr
,
1585 CORE_ADDR
*adjusted_insn_addr_end
,
1591 CORE_ADDR buildaddr
= *jump_entry
;
1592 const CORE_ADDR entryaddr
= *jump_entry
;
1593 int rsz
, min_frame
, frame_size
, tp_reg
;
1594 #ifdef __powerpc64__
1595 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
1596 int is_64
= register_size (regcache
->tdesc
, 0) == 8;
1597 int is_opd
= is_64
&& !is_elfv2_inferior ();
1599 int is_64
= 0, is_opd
= 0;
1602 #ifdef __powerpc64__
1605 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1608 frame_size
= (40 * rsz
) + min_frame
;
1616 frame_size
= (40 * rsz
) + min_frame
;
1618 #ifdef __powerpc64__
1622 /* Stack frame layout for this jump pad,
1624 High thread_area (r13/r2) |
1625 tpoint - collecting_t obj
1635 R0 - collected registers
1641 The code flow of this jump pad,
1646 4. Call gdb_collector
1647 5. Restore GPR and SPR
1649 7. Build a jump for back to the program
1650 8. Copy/relocate original instruction
1651 9. Build a jump for replacing original instruction. */
1653 /* Adjust stack pointer. */
1655 p
+= GEN_STDU (p
, 1, 1, -frame_size
); /* stdu r1,-frame_size(r1) */
1657 p
+= GEN_STWU (p
, 1, 1, -frame_size
); /* stwu r1,-frame_size(r1) */
1659 /* Store GPRs. Save R1 later, because it had just been modified, but
1660 we want the original value. */
1661 for (j
= 2; j
< 32; j
++)
1662 p
+= GEN_STORE (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1663 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1664 /* Set r0 to the original value of r1 before adjusting stack frame,
1665 and then save it. */
1666 p
+= GEN_ADDI (p
, 0, 1, frame_size
);
1667 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 1 * rsz
, is_64
);
1669 /* Save CR, XER, LR, and CTR. */
1670 p
+= GEN_MFCR (p
, 3); /* mfcr r3 */
1671 p
+= GEN_MFSPR (p
, 4, 1); /* mfxer r4 */
1672 p
+= GEN_MFSPR (p
, 5, 8); /* mflr r5 */
1673 p
+= GEN_MFSPR (p
, 6, 9); /* mfctr r6 */
1674 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
);/* std r3, 32(r1) */
1675 p
+= GEN_STORE (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
);/* std r4, 33(r1) */
1676 p
+= GEN_STORE (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
);/* std r5, 34(r1) */
1677 p
+= GEN_STORE (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
);/* std r6, 35(r1) */
1679 /* Save PC<tpaddr> */
1680 p
+= gen_limm (p
, 3, tpaddr
, is_64
);
1681 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 36 * rsz
, is_64
);
1684 /* Setup arguments to collector. */
1685 /* Set r4 to collected registers. */
1686 p
+= GEN_ADDI (p
, 4, 1, min_frame
);
1687 /* Set r3 to TPOINT. */
1688 p
+= gen_limm (p
, 3, tpoint
, is_64
);
1690 /* Prepare collecting_t object for lock. */
1691 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 37 * rsz
, is_64
);
1692 p
+= GEN_STORE (p
, tp_reg
, 1, min_frame
+ 38 * rsz
, is_64
);
1693 /* Set R5 to collecting object. */
1694 p
+= GEN_ADDI (p
, 5, 1, 37 * rsz
);
1696 p
+= GEN_LWSYNC (p
);
1697 p
+= gen_atomic_xchg (p
, lockaddr
, 0, 5, is_64
);
1698 p
+= GEN_LWSYNC (p
);
1700 /* Call to collector. */
1701 p
+= gen_call (p
, collector
, is_64
, is_opd
);
1703 /* Simply write 0 to release the lock. */
1704 p
+= gen_limm (p
, 3, lockaddr
, is_64
);
1705 p
+= gen_limm (p
, 4, 0, is_64
);
1706 p
+= GEN_LWSYNC (p
);
1707 p
+= GEN_STORE (p
, 4, 3, 0, is_64
);
1709 /* Restore stack and registers. */
1710 p
+= GEN_LOAD (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
); /* ld r3, 32(r1) */
1711 p
+= GEN_LOAD (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
); /* ld r4, 33(r1) */
1712 p
+= GEN_LOAD (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
); /* ld r5, 34(r1) */
1713 p
+= GEN_LOAD (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
); /* ld r6, 35(r1) */
1714 p
+= GEN_MTCR (p
, 3); /* mtcr r3 */
1715 p
+= GEN_MTSPR (p
, 4, 1); /* mtxer r4 */
1716 p
+= GEN_MTSPR (p
, 5, 8); /* mtlr r5 */
1717 p
+= GEN_MTSPR (p
, 6, 9); /* mtctr r6 */
1720 for (j
= 2; j
< 32; j
++)
1721 p
+= GEN_LOAD (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1722 p
+= GEN_LOAD (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1724 p
+= GEN_ADDI (p
, 1, 1, frame_size
);
1726 /* Flush instructions to inferior memory. */
1727 target_write_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1729 /* Now, insert the original instruction to execute in the jump pad. */
1730 *adjusted_insn_addr
= buildaddr
+ (p
- buf
) * 4;
1731 *adjusted_insn_addr_end
= *adjusted_insn_addr
;
1732 ppc_relocate_instruction (adjusted_insn_addr_end
, tpaddr
);
1734 /* Verify the relocation size. If should be 4 for normal copy,
1735 8 or 12 for some conditional branch. */
1736 if ((*adjusted_insn_addr_end
- *adjusted_insn_addr
== 0)
1737 || (*adjusted_insn_addr_end
- *adjusted_insn_addr
> 12))
1739 sprintf (err
, "E.Unexpected instruction length = %d"
1740 "when relocate instruction.",
1741 (int) (*adjusted_insn_addr_end
- *adjusted_insn_addr
));
1745 buildaddr
= *adjusted_insn_addr_end
;
1747 /* Finally, write a jump back to the program. */
1748 offset
= (tpaddr
+ 4) - buildaddr
;
1749 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1751 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1752 "(offset 0x%x > 26-bit).", offset
);
1756 p
+= GEN_B (p
, offset
);
1757 target_write_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1758 *jump_entry
= buildaddr
+ (p
- buf
) * 4;
1760 /* The jump pad is now built. Wire in a jump to our jump pad. This
1761 is always done last (by our caller actually), so that we can
1762 install fast tracepoints with threads running. This relies on
1763 the agent's atomic write support. */
1764 offset
= entryaddr
- tpaddr
;
1765 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1767 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1768 "(offset 0x%x > 26-bit).", offset
);
1772 GEN_B ((uint32_t *) jjump_pad_insn
, offset
);
1773 *jjump_pad_insn_size
= 4;
1778 /* Returns the minimum instruction length for installing a tracepoint. */
1781 ppc_get_min_fast_tracepoint_insn_len (void)
1786 /* Emits a given buffer into the target at current_insn_ptr. Length
1787 is in units of 32-bit words. */
1790 emit_insns (uint32_t *buf
, int n
)
1792 n
= n
* sizeof (uint32_t);
1793 target_write_memory (current_insn_ptr
, (unsigned char *) buf
, n
);
1794 current_insn_ptr
+= n
;
1797 #define __EMIT_ASM(NAME, INSNS) \
1800 extern uint32_t start_bcax_ ## NAME []; \
1801 extern uint32_t end_bcax_ ## NAME []; \
1802 emit_insns (start_bcax_ ## NAME, \
1803 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1804 __asm__ (".section .text.__ppcbcax\n\t" \
1805 "start_bcax_" #NAME ":\n\t" \
1807 "end_bcax_" #NAME ":\n\t" \
1811 #define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1812 #define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1816 Bytecode execution stack frame - 32-bit
1818 | LR save area (SP + 4)
1819 SP' -> +- Back chain (SP + 0)
1820 | Save r31 for access saved arguments
1821 | Save r30 for bytecode stack pointer
1822 | Save r4 for incoming argument *value
1823 | Save r3 for incoming argument regs
1824 r30 -> +- Bytecode execution stack
1826 | 64-byte (8 doublewords) at initial.
1827 | Expand stack as needed.
1830 | Some padding for minimum stack frame and 16-byte alignment.
1832 SP +- Back-chain (SP')
1838 r30 is the stack-pointer for bytecode machine.
1839 It should point to next-empty, so we can use LDU for pop.
1840 r3 is used for cache of the high part of TOP value.
1841 It was the first argument, pointer to regs.
1842 r4 is used for cache of the low part of TOP value.
1843 It was the second argument, pointer to the result.
1844 We should set *result = TOP after leaving this function.
1847 * To restore stack at epilogue
1849 * To check stack is big enough for bytecode execution.
1851 * To return execution result.
1856 /* Regardless of endian, register 3 is always high part, 4 is low part.
1857 These defines are used when the register pair is stored/loaded.
1858 Likewise, to simplify code, have a similiar define for 5:6. */
1860 #if __BYTE_ORDER == __LITTLE_ENDIAN
1861 #define TOP_FIRST "4"
1862 #define TOP_SECOND "3"
1863 #define TMP_FIRST "6"
1864 #define TMP_SECOND "5"
1866 #define TOP_FIRST "3"
1867 #define TOP_SECOND "4"
1868 #define TMP_FIRST "5"
1869 #define TMP_SECOND "6"
1872 /* Emit prologue in inferior memory. See above comments. */
1875 ppc_emit_prologue (void)
1877 EMIT_ASM (/* Save return address. */
1880 /* Adjust SP. 96 is the initial frame size. */
1882 /* Save r30 and incoming arguments. */
1883 "stw 31, 96-4(1) \n"
1884 "stw 30, 96-8(1) \n"
1885 "stw 4, 96-12(1) \n"
1886 "stw 3, 96-16(1) \n"
1887 /* Point r31 to original r1 for access arguments. */
1889 /* Set r30 to pointing stack-top. */
1891 /* Initial r3/TOP to 0. */
1896 /* Emit epilogue in inferior memory. See above comments. */
1899 ppc_emit_epilogue (void)
1901 EMIT_ASM (/* *result = TOP */
1903 "stw " TOP_FIRST
", 0(5) \n"
1904 "stw " TOP_SECOND
", 4(5) \n"
1905 /* Restore registers. */
1912 /* Return 0 for no-error. */
1918 /* TOP = stack[--sp] + TOP */
1923 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1924 "lwz " TMP_SECOND
", 4(30)\n"
1929 /* TOP = stack[--sp] - TOP */
1934 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1935 "lwz " TMP_SECOND
", 4(30) \n"
1937 "subfe 3, 3, 5 \n");
1940 /* TOP = stack[--sp] * TOP */
1945 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1946 "lwz " TMP_SECOND
", 4(30) \n"
1955 /* TOP = stack[--sp] << TOP */
1960 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1961 "lwz " TMP_SECOND
", 4(30) \n"
1962 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1963 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1964 "slw 5, 5, 4\n" /* Shift high part left */
1965 "slw 4, 6, 4\n" /* Shift low part left */
1966 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
1967 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
1969 "or 3, 7, 3\n"); /* Assemble high part */
1972 /* Top = stack[--sp] >> TOP
1973 (Arithmetic shift right) */
1976 ppc_emit_rsh_signed (void)
1978 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1979 "lwz " TMP_SECOND
", 4(30) \n"
1980 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1981 "sraw 3, 5, 4\n" /* Shift high part right */
1983 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
1984 "sraw 4, 5, 7\n" /* Shift high to low */
1987 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
1988 "srw 4, 6, 4\n" /* Shift low part right */
1989 "slw 5, 5, 7\n" /* Shift high to low */
1990 "or 4, 4, 5\n" /* Assemble low part */
1994 /* Top = stack[--sp] >> TOP
1995 (Logical shift right) */
1998 ppc_emit_rsh_unsigned (void)
2000 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2001 "lwz " TMP_SECOND
", 4(30) \n"
2002 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
2003 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
2004 "srw 6, 6, 4\n" /* Shift low part right */
2005 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
2006 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
2008 "srw 3, 5, 4\n" /* Shift high part right */
2009 "or 4, 6, 7\n"); /* Assemble low part */
2012 /* Emit code for signed-extension specified by ARG. */
2015 ppc_emit_ext (int arg
)
2020 EMIT_ASM ("extsb 4, 4\n"
2024 EMIT_ASM ("extsh 4, 4\n"
2028 EMIT_ASM ("srawi 3, 4, 31");
2035 /* Emit code for zero-extension specified by ARG. */
2038 ppc_emit_zero_ext (int arg
)
2043 EMIT_ASM ("clrlwi 4,4,24\n"
2047 EMIT_ASM ("clrlwi 4,4,16\n"
2051 EMIT_ASM ("li 3, 0");
2059 i.e., TOP = (TOP == 0) ? 1 : 0; */
2062 ppc_emit_log_not (void)
2064 EMIT_ASM ("or 4, 3, 4 \n"
2070 /* TOP = stack[--sp] & TOP */
2073 ppc_emit_bit_and (void)
2075 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2076 "lwz " TMP_SECOND
", 4(30) \n"
2081 /* TOP = stack[--sp] | TOP */
2084 ppc_emit_bit_or (void)
2086 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2087 "lwz " TMP_SECOND
", 4(30) \n"
2092 /* TOP = stack[--sp] ^ TOP */
2095 ppc_emit_bit_xor (void)
2097 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2098 "lwz " TMP_SECOND
", 4(30) \n"
2104 i.e., TOP = ~(TOP | TOP) */
2107 ppc_emit_bit_not (void)
2109 EMIT_ASM ("nor 3, 3, 3 \n"
2113 /* TOP = stack[--sp] == TOP */
2116 ppc_emit_equal (void)
2118 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2119 "lwz " TMP_SECOND
", 4(30) \n"
2128 /* TOP = stack[--sp] < TOP
2129 (Signed comparison) */
2132 ppc_emit_less_signed (void)
2134 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2135 "lwz " TMP_SECOND
", 4(30) \n"
2138 /* CR6 bit 0 = low less and high equal */
2139 "crand 6*4+0, 6*4+0, 7*4+2\n"
2140 /* CR7 bit 0 = (low less and high equal) or high less */
2141 "cror 7*4+0, 7*4+0, 6*4+0\n"
2143 "rlwinm 4, 4, 29, 31, 31 \n"
2147 /* TOP = stack[--sp] < TOP
2148 (Unsigned comparison) */
2151 ppc_emit_less_unsigned (void)
2153 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2154 "lwz " TMP_SECOND
", 4(30) \n"
2157 /* CR6 bit 0 = low less and high equal */
2158 "crand 6*4+0, 6*4+0, 7*4+2\n"
2159 /* CR7 bit 0 = (low less and high equal) or high less */
2160 "cror 7*4+0, 7*4+0, 6*4+0\n"
2162 "rlwinm 4, 4, 29, 31, 31 \n"
2166 /* Access the memory address in TOP in size of SIZE.
2167 Zero-extend the read value. */
2170 ppc_emit_ref (int size
)
2175 EMIT_ASM ("lbz 4, 0(4)\n"
2179 EMIT_ASM ("lhz 4, 0(4)\n"
2183 EMIT_ASM ("lwz 4, 0(4)\n"
2187 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2188 EMIT_ASM ("lwz 3, 4(4)\n"
2191 EMIT_ASM ("lwz 3, 0(4)\n"
2200 ppc_emit_const (LONGEST num
)
2205 p
+= gen_limm (p
, 3, num
>> 32 & 0xffffffff, 0);
2206 p
+= gen_limm (p
, 4, num
& 0xffffffff, 0);
2208 emit_insns (buf
, p
- buf
);
2209 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2212 /* Set TOP to the value of register REG by calling get_raw_reg function
2213 with two argument, collected buffer and register number. */
2216 ppc_emit_reg (int reg
)
2221 /* fctx->regs is passed in r3 and then saved in -16(31). */
2222 p
+= GEN_LWZ (p
, 3, 31, -16);
2223 p
+= GEN_LI (p
, 4, reg
); /* li r4, reg */
2224 p
+= gen_call (p
, get_raw_reg_func_addr (), 0, 0);
2226 emit_insns (buf
, p
- buf
);
2227 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2229 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2231 EMIT_ASM ("mr 5, 4\n"
2237 /* TOP = stack[--sp] */
2242 EMIT_ASM ("lwzu " TOP_FIRST
", 8(30) \n"
2243 "lwz " TOP_SECOND
", 4(30) \n");
2246 /* stack[sp++] = TOP
2248 Because we may use up bytecode stack, expand 8 doublewords more
2252 ppc_emit_stack_flush (void)
2254 /* Make sure bytecode stack is big enough before push.
2255 Otherwise, expand 64-byte more. */
2257 EMIT_ASM (" stw " TOP_FIRST
", 0(30) \n"
2258 " stw " TOP_SECOND
", 4(30)\n"
2259 " addi 5, 30, -(8 + 8) \n"
2262 " stwu 31, -64(1) \n"
2263 "1:addi 30, 30, -8 \n");
2266 /* Swap TOP and stack[sp-1] */
2269 ppc_emit_swap (void)
2271 EMIT_ASM ("lwz " TMP_FIRST
", 8(30) \n"
2272 "lwz " TMP_SECOND
", 12(30) \n"
2273 "stw " TOP_FIRST
", 8(30) \n"
2274 "stw " TOP_SECOND
", 12(30) \n"
2279 /* Discard N elements in the stack. Also used for ppc64. */
2282 ppc_emit_stack_adjust (int n
)
2294 p
+= GEN_ADDI (p
, 30, 30, n
);
2296 emit_insns (buf
, p
- buf
);
2297 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2300 /* Call function FN. */
2303 ppc_emit_call (CORE_ADDR fn
)
2308 p
+= gen_call (p
, fn
, 0, 0);
2310 emit_insns (buf
, p
- buf
);
2311 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2314 /* FN's prototype is `LONGEST(*fn)(int)'.
2319 ppc_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2324 /* Setup argument. arg1 is a 16-bit value. */
2325 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2326 p
+= gen_call (p
, fn
, 0, 0);
2328 emit_insns (buf
, p
- buf
);
2329 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2331 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2333 EMIT_ASM ("mr 5, 4\n"
2339 /* FN's prototype is `void(*fn)(int,LONGEST)'.
2342 TOP should be preserved/restored before/after the call. */
2345 ppc_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2350 /* Save TOP. 0(30) is next-empty. */
2351 p
+= GEN_STW (p
, 3, 30, 0);
2352 p
+= GEN_STW (p
, 4, 30, 4);
2354 /* Setup argument. arg1 is a 16-bit value. */
2355 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2357 p
+= GEN_MR (p
, 5, 4);
2358 p
+= GEN_MR (p
, 6, 3);
2362 p
+= GEN_MR (p
, 5, 3);
2363 p
+= GEN_MR (p
, 6, 4);
2365 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2366 p
+= gen_call (p
, fn
, 0, 0);
2369 p
+= GEN_LWZ (p
, 3, 30, 0);
2370 p
+= GEN_LWZ (p
, 4, 30, 4);
2372 emit_insns (buf
, p
- buf
);
2373 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2376 /* Note in the following goto ops:
2378 When emitting goto, the target address is later relocated by
2379 write_goto_address. OFFSET_P is the offset of the branch instruction
2380 in the code sequence, and SIZE_P is how to relocate the instruction,
2381 recognized by ppc_write_goto_address. In current implementation,
2382 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2385 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2388 ppc_emit_if_goto (int *offset_p
, int *size_p
)
2390 EMIT_ASM ("or. 3, 3, 4 \n"
2391 "lwzu " TOP_FIRST
", 8(30) \n"
2392 "lwz " TOP_SECOND
", 4(30) \n"
2401 /* Unconditional goto. Also used for ppc64. */
2404 ppc_emit_goto (int *offset_p
, int *size_p
)
2406 EMIT_ASM ("1:b 1b");
2414 /* Goto if stack[--sp] == TOP */
2417 ppc_emit_eq_goto (int *offset_p
, int *size_p
)
2419 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2420 "lwz " TMP_SECOND
", 4(30) \n"
2424 "lwzu " TOP_FIRST
", 8(30) \n"
2425 "lwz " TOP_SECOND
", 4(30) \n"
2434 /* Goto if stack[--sp] != TOP */
2437 ppc_emit_ne_goto (int *offset_p
, int *size_p
)
2439 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2440 "lwz " TMP_SECOND
", 4(30) \n"
2444 "lwzu " TOP_FIRST
", 8(30) \n"
2445 "lwz " TOP_SECOND
", 4(30) \n"
2454 /* Goto if stack[--sp] < TOP */
2457 ppc_emit_lt_goto (int *offset_p
, int *size_p
)
2459 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2460 "lwz " TMP_SECOND
", 4(30) \n"
2463 /* CR6 bit 0 = low less and high equal */
2464 "crand 6*4+0, 6*4+0, 7*4+2\n"
2465 /* CR7 bit 0 = (low less and high equal) or high less */
2466 "cror 7*4+0, 7*4+0, 6*4+0\n"
2467 "lwzu " TOP_FIRST
", 8(30) \n"
2468 "lwz " TOP_SECOND
", 4(30)\n"
2477 /* Goto if stack[--sp] <= TOP */
2480 ppc_emit_le_goto (int *offset_p
, int *size_p
)
2482 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2483 "lwz " TMP_SECOND
", 4(30) \n"
2486 /* CR6 bit 0 = low less/equal and high equal */
2487 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2488 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2489 "cror 7*4+0, 7*4+0, 6*4+0\n"
2490 "lwzu " TOP_FIRST
", 8(30) \n"
2491 "lwz " TOP_SECOND
", 4(30)\n"
2500 /* Goto if stack[--sp] > TOP */
2503 ppc_emit_gt_goto (int *offset_p
, int *size_p
)
2505 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2506 "lwz " TMP_SECOND
", 4(30) \n"
2509 /* CR6 bit 0 = low greater and high equal */
2510 "crand 6*4+0, 6*4+1, 7*4+2\n"
2511 /* CR7 bit 0 = (low greater and high equal) or high greater */
2512 "cror 7*4+0, 7*4+1, 6*4+0\n"
2513 "lwzu " TOP_FIRST
", 8(30) \n"
2514 "lwz " TOP_SECOND
", 4(30)\n"
2523 /* Goto if stack[--sp] >= TOP */
2526 ppc_emit_ge_goto (int *offset_p
, int *size_p
)
2528 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2529 "lwz " TMP_SECOND
", 4(30) \n"
2532 /* CR6 bit 0 = low ge and high equal */
2533 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2534 /* CR7 bit 0 = (low ge and high equal) or high greater */
2535 "cror 7*4+0, 7*4+1, 6*4+0\n"
2536 "lwzu " TOP_FIRST
", 8(30)\n"
2537 "lwz " TOP_SECOND
", 4(30)\n"
2546 /* Relocate previous emitted branch instruction. FROM is the address
2547 of the branch instruction, TO is the goto target address, and SIZE
2548 if the value we set by *SIZE_P before. Currently, it is either
2549 24 or 14 of branch and conditional-branch instruction.
2550 Also used for ppc64. */
2553 ppc_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2555 long rel
= to
- from
;
2559 read_inferior_memory (from
, (unsigned char *) &insn
, 4);
2560 opcd
= (insn
>> 26) & 0x3f;
2566 || (rel
>= (1 << 15) || rel
< -(1 << 15)))
2568 insn
= (insn
& ~0xfffc) | (rel
& 0xfffc);
2572 || (rel
>= (1 << 25) || rel
< -(1 << 25)))
2574 insn
= (insn
& ~0x3fffffc) | (rel
& 0x3fffffc);
2581 target_write_memory (from
, (unsigned char *) &insn
, 4);
2584 /* Table of emit ops for 32-bit. */
2586 static struct emit_ops ppc_emit_ops_impl
=
2594 ppc_emit_rsh_signed
,
2595 ppc_emit_rsh_unsigned
,
2603 ppc_emit_less_signed
,
2604 ppc_emit_less_unsigned
,
2608 ppc_write_goto_address
,
2613 ppc_emit_stack_flush
,
2616 ppc_emit_stack_adjust
,
2617 ppc_emit_int_call_1
,
2618 ppc_emit_void_call_2
,
2627 #ifdef __powerpc64__
2631 Bytecode execution stack frame - 64-bit
2633 | LR save area (SP + 16)
2634 | CR save area (SP + 8)
2635 SP' -> +- Back chain (SP + 0)
2636 | Save r31 for access saved arguments
2637 | Save r30 for bytecode stack pointer
2638 | Save r4 for incoming argument *value
2639 | Save r3 for incoming argument regs
2640 r30 -> +- Bytecode execution stack
2642 | 64-byte (8 doublewords) at initial.
2643 | Expand stack as needed.
2646 | Some padding for minimum stack frame.
2648 SP +- Back-chain (SP')
2651 = 112 + (4 * 8) + 64
2654 r30 is the stack-pointer for bytecode machine.
2655 It should point to next-empty, so we can use LDU for pop.
2656 r3 is used for cache of TOP value.
2657 It was the first argument, pointer to regs.
2658 r4 is the second argument, pointer to the result.
2659 We should set *result = TOP after leaving this function.
2662 * To restore stack at epilogue
2664 * To check stack is big enough for bytecode execution.
2665 => r30 - 8 > SP + 112
2666 * To return execution result.
2671 /* Emit prologue in inferior memory. See above comments. */
2674 ppc64v1_emit_prologue (void)
2676 /* On ELFv1, function pointers really point to function descriptor,
2677 so emit one here. We don't care about contents of words 1 and 2,
2678 so let them just overlap out code. */
2679 uint64_t opd
= current_insn_ptr
+ 8;
2682 /* Mind the strict aliasing rules. */
2683 memcpy (buf
, &opd
, sizeof buf
);
2685 EMIT_ASM (/* Save return address. */
2688 /* Save r30 and incoming arguments. */
2693 /* Point r31 to current r1 for access arguments. */
2695 /* Adjust SP. 208 is the initial frame size. */
2696 "stdu 1, -208(1) \n"
2697 /* Set r30 to pointing stack-top. */
2698 "addi 30, 1, 168 \n"
2699 /* Initial r3/TOP to 0. */
2703 /* Emit prologue in inferior memory. See above comments. */
2706 ppc64v2_emit_prologue (void)
2708 EMIT_ASM (/* Save return address. */
2711 /* Save r30 and incoming arguments. */
2716 /* Point r31 to current r1 for access arguments. */
2718 /* Adjust SP. 208 is the initial frame size. */
2719 "stdu 1, -208(1) \n"
2720 /* Set r30 to pointing stack-top. */
2721 "addi 30, 1, 168 \n"
2722 /* Initial r3/TOP to 0. */
2726 /* Emit epilogue in inferior memory. See above comments. */
2729 ppc64_emit_epilogue (void)
2731 EMIT_ASM (/* Restore SP. */
2736 /* Restore registers. */
2741 /* Return 0 for no-error. */
2747 /* TOP = stack[--sp] + TOP */
2750 ppc64_emit_add (void)
2752 EMIT_ASM ("ldu 4, 8(30) \n"
2756 /* TOP = stack[--sp] - TOP */
2759 ppc64_emit_sub (void)
2761 EMIT_ASM ("ldu 4, 8(30) \n"
2765 /* TOP = stack[--sp] * TOP */
2768 ppc64_emit_mul (void)
2770 EMIT_ASM ("ldu 4, 8(30) \n"
2771 "mulld 3, 4, 3 \n");
2774 /* TOP = stack[--sp] << TOP */
2777 ppc64_emit_lsh (void)
2779 EMIT_ASM ("ldu 4, 8(30) \n"
2783 /* Top = stack[--sp] >> TOP
2784 (Arithmetic shift right) */
2787 ppc64_emit_rsh_signed (void)
2789 EMIT_ASM ("ldu 4, 8(30) \n"
2793 /* Top = stack[--sp] >> TOP
2794 (Logical shift right) */
2797 ppc64_emit_rsh_unsigned (void)
2799 EMIT_ASM ("ldu 4, 8(30) \n"
2803 /* Emit code for signed-extension specified by ARG. */
2806 ppc64_emit_ext (int arg
)
2811 EMIT_ASM ("extsb 3, 3");
2814 EMIT_ASM ("extsh 3, 3");
2817 EMIT_ASM ("extsw 3, 3");
2824 /* Emit code for zero-extension specified by ARG. */
2827 ppc64_emit_zero_ext (int arg
)
2832 EMIT_ASM ("rldicl 3,3,0,56");
2835 EMIT_ASM ("rldicl 3,3,0,48");
2838 EMIT_ASM ("rldicl 3,3,0,32");
2846 i.e., TOP = (TOP == 0) ? 1 : 0; */
2849 ppc64_emit_log_not (void)
2851 EMIT_ASM ("cntlzd 3, 3 \n"
2855 /* TOP = stack[--sp] & TOP */
2858 ppc64_emit_bit_and (void)
2860 EMIT_ASM ("ldu 4, 8(30) \n"
2864 /* TOP = stack[--sp] | TOP */
2867 ppc64_emit_bit_or (void)
2869 EMIT_ASM ("ldu 4, 8(30) \n"
2873 /* TOP = stack[--sp] ^ TOP */
2876 ppc64_emit_bit_xor (void)
2878 EMIT_ASM ("ldu 4, 8(30) \n"
2883 i.e., TOP = ~(TOP | TOP) */
2886 ppc64_emit_bit_not (void)
2888 EMIT_ASM ("nor 3, 3, 3 \n");
2891 /* TOP = stack[--sp] == TOP */
2894 ppc64_emit_equal (void)
2896 EMIT_ASM ("ldu 4, 8(30) \n"
2902 /* TOP = stack[--sp] < TOP
2903 (Signed comparison) */
2906 ppc64_emit_less_signed (void)
2908 EMIT_ASM ("ldu 4, 8(30) \n"
2911 "rlwinm 3, 3, 29, 31, 31 \n");
2914 /* TOP = stack[--sp] < TOP
2915 (Unsigned comparison) */
2918 ppc64_emit_less_unsigned (void)
2920 EMIT_ASM ("ldu 4, 8(30) \n"
2923 "rlwinm 3, 3, 29, 31, 31 \n");
2926 /* Access the memory address in TOP in size of SIZE.
2927 Zero-extend the read value. */
2930 ppc64_emit_ref (int size
)
2935 EMIT_ASM ("lbz 3, 0(3)");
2938 EMIT_ASM ("lhz 3, 0(3)");
2941 EMIT_ASM ("lwz 3, 0(3)");
2944 EMIT_ASM ("ld 3, 0(3)");
2952 ppc64_emit_const (LONGEST num
)
2957 p
+= gen_limm (p
, 3, num
, 1);
2959 emit_insns (buf
, p
- buf
);
2960 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2963 /* Set TOP to the value of register REG by calling get_raw_reg function
2964 with two argument, collected buffer and register number. */
2967 ppc64v1_emit_reg (int reg
)
2972 /* fctx->regs is passed in r3 and then saved in 176(1). */
2973 p
+= GEN_LD (p
, 3, 31, -32);
2974 p
+= GEN_LI (p
, 4, reg
);
2975 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2976 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 1);
2977 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2979 emit_insns (buf
, p
- buf
);
2980 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2983 /* Likewise, for ELFv2. */
2986 ppc64v2_emit_reg (int reg
)
2991 /* fctx->regs is passed in r3 and then saved in 176(1). */
2992 p
+= GEN_LD (p
, 3, 31, -32);
2993 p
+= GEN_LI (p
, 4, reg
);
2994 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
2995 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 0);
2996 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
2998 emit_insns (buf
, p
- buf
);
2999 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3002 /* TOP = stack[--sp] */
3005 ppc64_emit_pop (void)
3007 EMIT_ASM ("ldu 3, 8(30)");
3010 /* stack[sp++] = TOP
3012 Because we may use up bytecode stack, expand 8 doublewords more
3016 ppc64_emit_stack_flush (void)
3018 /* Make sure bytecode stack is big enough before push.
3019 Otherwise, expand 64-byte more. */
3021 EMIT_ASM (" std 3, 0(30) \n"
3022 " addi 4, 30, -(112 + 8) \n"
3025 " stdu 31, -64(1) \n"
3026 "1:addi 30, 30, -8 \n");
3029 /* Swap TOP and stack[sp-1] */
3032 ppc64_emit_swap (void)
3034 EMIT_ASM ("ld 4, 8(30) \n"
3039 /* Call function FN - ELFv1. */
3042 ppc64v1_emit_call (CORE_ADDR fn
)
3047 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3048 p
+= gen_call (p
, fn
, 1, 1);
3049 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3051 emit_insns (buf
, p
- buf
);
3052 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3055 /* Call function FN - ELFv2. */
3058 ppc64v2_emit_call (CORE_ADDR fn
)
3063 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3064 p
+= gen_call (p
, fn
, 1, 0);
3065 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3067 emit_insns (buf
, p
- buf
);
3068 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3071 /* FN's prototype is `LONGEST(*fn)(int)'.
3076 ppc64v1_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
3081 /* Setup argument. arg1 is a 16-bit value. */
3082 p
+= gen_limm (p
, 3, arg1
, 1);
3083 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3084 p
+= gen_call (p
, fn
, 1, 1);
3085 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3087 emit_insns (buf
, p
- buf
);
3088 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3091 /* Likewise for ELFv2. */
3094 ppc64v2_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
3099 /* Setup argument. arg1 is a 16-bit value. */
3100 p
+= gen_limm (p
, 3, arg1
, 1);
3101 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3102 p
+= gen_call (p
, fn
, 1, 0);
3103 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3105 emit_insns (buf
, p
- buf
);
3106 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3109 /* FN's prototype is `void(*fn)(int,LONGEST)'.
3112 TOP should be preserved/restored before/after the call. */
3115 ppc64v1_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3120 /* Save TOP. 0(30) is next-empty. */
3121 p
+= GEN_STD (p
, 3, 30, 0);
3123 /* Setup argument. arg1 is a 16-bit value. */
3124 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
3125 p
+= gen_limm (p
, 3, arg1
, 1);
3126 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3127 p
+= gen_call (p
, fn
, 1, 1);
3128 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3131 p
+= GEN_LD (p
, 3, 30, 0);
3133 emit_insns (buf
, p
- buf
);
3134 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3137 /* Likewise for ELFv2. */
3140 ppc64v2_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3145 /* Save TOP. 0(30) is next-empty. */
3146 p
+= GEN_STD (p
, 3, 30, 0);
3148 /* Setup argument. arg1 is a 16-bit value. */
3149 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
3150 p
+= gen_limm (p
, 3, arg1
, 1);
3151 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3152 p
+= gen_call (p
, fn
, 1, 0);
3153 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3156 p
+= GEN_LD (p
, 3, 30, 0);
3158 emit_insns (buf
, p
- buf
);
3159 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3162 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
3165 ppc64_emit_if_goto (int *offset_p
, int *size_p
)
3167 EMIT_ASM ("cmpdi 7, 3, 0 \n"
3177 /* Goto if stack[--sp] == TOP */
3180 ppc64_emit_eq_goto (int *offset_p
, int *size_p
)
3182 EMIT_ASM ("ldu 4, 8(30) \n"
3193 /* Goto if stack[--sp] != TOP */
3196 ppc64_emit_ne_goto (int *offset_p
, int *size_p
)
3198 EMIT_ASM ("ldu 4, 8(30) \n"
3209 /* Goto if stack[--sp] < TOP */
3212 ppc64_emit_lt_goto (int *offset_p
, int *size_p
)
3214 EMIT_ASM ("ldu 4, 8(30) \n"
3225 /* Goto if stack[--sp] <= TOP */
3228 ppc64_emit_le_goto (int *offset_p
, int *size_p
)
3230 EMIT_ASM ("ldu 4, 8(30) \n"
3241 /* Goto if stack[--sp] > TOP */
3244 ppc64_emit_gt_goto (int *offset_p
, int *size_p
)
3246 EMIT_ASM ("ldu 4, 8(30) \n"
3257 /* Goto if stack[--sp] >= TOP */
3260 ppc64_emit_ge_goto (int *offset_p
, int *size_p
)
3262 EMIT_ASM ("ldu 4, 8(30) \n"
3273 /* Table of emit ops for 64-bit ELFv1. */
3275 static struct emit_ops ppc64v1_emit_ops_impl
=
3277 ppc64v1_emit_prologue
,
3278 ppc64_emit_epilogue
,
3283 ppc64_emit_rsh_signed
,
3284 ppc64_emit_rsh_unsigned
,
3292 ppc64_emit_less_signed
,
3293 ppc64_emit_less_unsigned
,
3297 ppc_write_goto_address
,
3302 ppc64_emit_stack_flush
,
3303 ppc64_emit_zero_ext
,
3305 ppc_emit_stack_adjust
,
3306 ppc64v1_emit_int_call_1
,
3307 ppc64v1_emit_void_call_2
,
3316 /* Table of emit ops for 64-bit ELFv2. */
3318 static struct emit_ops ppc64v2_emit_ops_impl
=
3320 ppc64v2_emit_prologue
,
3321 ppc64_emit_epilogue
,
3326 ppc64_emit_rsh_signed
,
3327 ppc64_emit_rsh_unsigned
,
3335 ppc64_emit_less_signed
,
3336 ppc64_emit_less_unsigned
,
3340 ppc_write_goto_address
,
3345 ppc64_emit_stack_flush
,
3346 ppc64_emit_zero_ext
,
3348 ppc_emit_stack_adjust
,
3349 ppc64v2_emit_int_call_1
,
3350 ppc64v2_emit_void_call_2
,
3361 /* Implementation of linux_target_ops method "emit_ops". */
3363 static struct emit_ops
*
3366 #ifdef __powerpc64__
3367 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3369 if (register_size (regcache
->tdesc
, 0) == 8)
3371 if (is_elfv2_inferior ())
3372 return &ppc64v2_emit_ops_impl
;
3374 return &ppc64v1_emit_ops_impl
;
3377 return &ppc_emit_ops_impl
;
3380 /* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3383 ppc_get_ipa_tdesc_idx (void)
3385 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3386 const struct target_desc
*tdesc
= regcache
->tdesc
;
3388 #ifdef __powerpc64__
3389 if (tdesc
== tdesc_powerpc_64l
)
3390 return PPC_TDESC_BASE
;
3391 if (tdesc
== tdesc_powerpc_altivec64l
)
3392 return PPC_TDESC_ALTIVEC
;
3393 if (tdesc
== tdesc_powerpc_vsx64l
)
3394 return PPC_TDESC_VSX
;
3395 if (tdesc
== tdesc_powerpc_isa205_64l
)
3396 return PPC_TDESC_ISA205
;
3397 if (tdesc
== tdesc_powerpc_isa205_altivec64l
)
3398 return PPC_TDESC_ISA205_ALTIVEC
;
3399 if (tdesc
== tdesc_powerpc_isa205_vsx64l
)
3400 return PPC_TDESC_ISA205_VSX
;
3401 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx64l
)
3402 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3403 if (tdesc
== tdesc_powerpc_isa207_vsx64l
)
3404 return PPC_TDESC_ISA207_VSX
;
3405 if (tdesc
== tdesc_powerpc_isa207_htm_vsx64l
)
3406 return PPC_TDESC_ISA207_HTM_VSX
;
3409 if (tdesc
== tdesc_powerpc_32l
)
3410 return PPC_TDESC_BASE
;
3411 if (tdesc
== tdesc_powerpc_altivec32l
)
3412 return PPC_TDESC_ALTIVEC
;
3413 if (tdesc
== tdesc_powerpc_vsx32l
)
3414 return PPC_TDESC_VSX
;
3415 if (tdesc
== tdesc_powerpc_isa205_32l
)
3416 return PPC_TDESC_ISA205
;
3417 if (tdesc
== tdesc_powerpc_isa205_altivec32l
)
3418 return PPC_TDESC_ISA205_ALTIVEC
;
3419 if (tdesc
== tdesc_powerpc_isa205_vsx32l
)
3420 return PPC_TDESC_ISA205_VSX
;
3421 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx32l
)
3422 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3423 if (tdesc
== tdesc_powerpc_isa207_vsx32l
)
3424 return PPC_TDESC_ISA207_VSX
;
3425 if (tdesc
== tdesc_powerpc_isa207_htm_vsx32l
)
3426 return PPC_TDESC_ISA207_HTM_VSX
;
3427 if (tdesc
== tdesc_powerpc_e500l
)
3428 return PPC_TDESC_E500
;
3433 struct linux_target_ops the_low_target
= {
3434 ppc_get_thread_area
,
3435 ppc_install_fast_tracepoint_jump_pad
,
3437 ppc_get_min_fast_tracepoint_insn_len
,
3438 NULL
, /* supports_range_stepping */
3439 ppc_supports_hardware_single_step
,
3440 NULL
, /* get_syscall_trapinfo */
3441 ppc_get_ipa_tdesc_idx
,
3444 /* The linux target ops object. */
3446 linux_process_target
*the_linux_target
= &the_ppc_target
;
3449 initialize_low_arch (void)
3451 /* Initialize the Linux target descriptions. */
3453 init_registers_powerpc_32l ();
3454 init_registers_powerpc_altivec32l ();
3455 init_registers_powerpc_vsx32l ();
3456 init_registers_powerpc_isa205_32l ();
3457 init_registers_powerpc_isa205_altivec32l ();
3458 init_registers_powerpc_isa205_vsx32l ();
3459 init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
3460 init_registers_powerpc_isa207_vsx32l ();
3461 init_registers_powerpc_isa207_htm_vsx32l ();
3462 init_registers_powerpc_e500l ();
3464 init_registers_powerpc_64l ();
3465 init_registers_powerpc_altivec64l ();
3466 init_registers_powerpc_vsx64l ();
3467 init_registers_powerpc_isa205_64l ();
3468 init_registers_powerpc_isa205_altivec64l ();
3469 init_registers_powerpc_isa205_vsx64l ();
3470 init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
3471 init_registers_powerpc_isa207_vsx64l ();
3472 init_registers_powerpc_isa207_htm_vsx64l ();
3475 initialize_regsets_info (&ppc_regsets_info
);