1 /* GNU/Linux/PowerPC specific low level interface, for the remote server for
3 Copyright (C) 1995-2020 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "linux-low.h"
23 #include "elf/common.h"
26 #include <asm/ptrace.h>
28 #include "arch/ppc-linux-common.h"
29 #include "arch/ppc-linux-tdesc.h"
30 #include "nat/ppc-linux.h"
31 #include "nat/linux-ptrace.h"
32 #include "linux-ppc-tdesc-init.h"
34 #include "tracepoint.h"
36 #define PPC_FIELD(value, from, len) \
37 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
38 #define PPC_SEXT(v, bs) \
39 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
40 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
41 - ((CORE_ADDR) 1 << ((bs) - 1)))
42 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
43 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
44 #define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
45 #define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
47 /* Linux target op definitions for the PowerPC architecture. */
49 class ppc_target
: public linux_process_target
55 void low_arch_setup () override
;
58 /* The singleton target ops object. */
60 static ppc_target the_ppc_target
;
62 /* Holds the AT_HWCAP auxv entry. */
64 static unsigned long ppc_hwcap
;
66 /* Holds the AT_HWCAP2 auxv entry. */
68 static unsigned long ppc_hwcap2
;
71 #define ppc_num_regs 73
74 /* We use a constant for FPSCR instead of PT_FPSCR, because
75 many shipped PPC64 kernels had the wrong value in ptrace.h. */
76 static int ppc_regmap
[] =
77 {PT_R0
* 8, PT_R1
* 8, PT_R2
* 8, PT_R3
* 8,
78 PT_R4
* 8, PT_R5
* 8, PT_R6
* 8, PT_R7
* 8,
79 PT_R8
* 8, PT_R9
* 8, PT_R10
* 8, PT_R11
* 8,
80 PT_R12
* 8, PT_R13
* 8, PT_R14
* 8, PT_R15
* 8,
81 PT_R16
* 8, PT_R17
* 8, PT_R18
* 8, PT_R19
* 8,
82 PT_R20
* 8, PT_R21
* 8, PT_R22
* 8, PT_R23
* 8,
83 PT_R24
* 8, PT_R25
* 8, PT_R26
* 8, PT_R27
* 8,
84 PT_R28
* 8, PT_R29
* 8, PT_R30
* 8, PT_R31
* 8,
85 PT_FPR0
*8, PT_FPR0
*8 + 8, PT_FPR0
*8+16, PT_FPR0
*8+24,
86 PT_FPR0
*8+32, PT_FPR0
*8+40, PT_FPR0
*8+48, PT_FPR0
*8+56,
87 PT_FPR0
*8+64, PT_FPR0
*8+72, PT_FPR0
*8+80, PT_FPR0
*8+88,
88 PT_FPR0
*8+96, PT_FPR0
*8+104, PT_FPR0
*8+112, PT_FPR0
*8+120,
89 PT_FPR0
*8+128, PT_FPR0
*8+136, PT_FPR0
*8+144, PT_FPR0
*8+152,
90 PT_FPR0
*8+160, PT_FPR0
*8+168, PT_FPR0
*8+176, PT_FPR0
*8+184,
91 PT_FPR0
*8+192, PT_FPR0
*8+200, PT_FPR0
*8+208, PT_FPR0
*8+216,
92 PT_FPR0
*8+224, PT_FPR0
*8+232, PT_FPR0
*8+240, PT_FPR0
*8+248,
93 PT_NIP
* 8, PT_MSR
* 8, PT_CCR
* 8, PT_LNK
* 8,
94 PT_CTR
* 8, PT_XER
* 8, PT_FPR0
*8 + 256,
95 PT_ORIG_R3
* 8, PT_TRAP
* 8 };
97 /* Currently, don't check/send MQ. */
98 static int ppc_regmap
[] =
99 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
100 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
101 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
102 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
103 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
104 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
105 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
106 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
107 PT_FPR0
*4, PT_FPR0
*4 + 8, PT_FPR0
*4+16, PT_FPR0
*4+24,
108 PT_FPR0
*4+32, PT_FPR0
*4+40, PT_FPR0
*4+48, PT_FPR0
*4+56,
109 PT_FPR0
*4+64, PT_FPR0
*4+72, PT_FPR0
*4+80, PT_FPR0
*4+88,
110 PT_FPR0
*4+96, PT_FPR0
*4+104, PT_FPR0
*4+112, PT_FPR0
*4+120,
111 PT_FPR0
*4+128, PT_FPR0
*4+136, PT_FPR0
*4+144, PT_FPR0
*4+152,
112 PT_FPR0
*4+160, PT_FPR0
*4+168, PT_FPR0
*4+176, PT_FPR0
*4+184,
113 PT_FPR0
*4+192, PT_FPR0
*4+200, PT_FPR0
*4+208, PT_FPR0
*4+216,
114 PT_FPR0
*4+224, PT_FPR0
*4+232, PT_FPR0
*4+240, PT_FPR0
*4+248,
115 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
116 PT_CTR
* 4, PT_XER
* 4, PT_FPSCR
* 4,
117 PT_ORIG_R3
* 4, PT_TRAP
* 4
120 static int ppc_regmap_e500
[] =
121 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
122 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
123 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
124 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
125 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
126 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
127 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
128 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
137 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
138 PT_CTR
* 4, PT_XER
* 4, -1,
139 PT_ORIG_R3
* 4, PT_TRAP
* 4
143 /* Check whether the kernel provides a register set with number
144 REGSET_ID of size REGSETSIZE for process/thread TID. */
147 ppc_check_regset (int tid
, int regset_id
, int regsetsize
)
149 void *buf
= alloca (regsetsize
);
153 iov
.iov_len
= regsetsize
;
155 if (ptrace (PTRACE_GETREGSET
, tid
, regset_id
, &iov
) >= 0
162 ppc_cannot_store_register (int regno
)
164 const struct target_desc
*tdesc
= current_process ()->tdesc
;
166 #ifndef __powerpc64__
167 /* Some kernels do not allow us to store fpscr. */
168 if (!(ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
169 && regno
== find_regno (tdesc
, "fpscr"))
173 /* Some kernels do not allow us to store orig_r3 or trap. */
174 if (regno
== find_regno (tdesc
, "orig_r3")
175 || regno
== find_regno (tdesc
, "trap"))
182 ppc_cannot_fetch_register (int regno
)
188 ppc_collect_ptrace_register (struct regcache
*regcache
, int regno
, char *buf
)
190 memset (buf
, 0, sizeof (long));
192 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
194 /* Little-endian values always sit at the left end of the buffer. */
195 collect_register (regcache
, regno
, buf
);
197 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
199 /* Big-endian values sit at the right end of the buffer. In case of
200 registers whose sizes are smaller than sizeof (long), we must use a
201 padding to access them correctly. */
202 int size
= register_size (regcache
->tdesc
, regno
);
204 if (size
< sizeof (long))
205 collect_register (regcache
, regno
, buf
+ sizeof (long) - size
);
207 collect_register (regcache
, regno
, buf
);
210 perror_with_name ("Unexpected byte order");
214 ppc_supply_ptrace_register (struct regcache
*regcache
,
215 int regno
, const char *buf
)
217 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
219 /* Little-endian values always sit at the left end of the buffer. */
220 supply_register (regcache
, regno
, buf
);
222 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
224 /* Big-endian values sit at the right end of the buffer. In case of
225 registers whose sizes are smaller than sizeof (long), we must use a
226 padding to access them correctly. */
227 int size
= register_size (regcache
->tdesc
, regno
);
229 if (size
< sizeof (long))
230 supply_register (regcache
, regno
, buf
+ sizeof (long) - size
);
232 supply_register (regcache
, regno
, buf
);
235 perror_with_name ("Unexpected byte order");
239 ppc_get_pc (struct regcache
*regcache
)
241 if (register_size (regcache
->tdesc
, 0) == 4)
244 collect_register_by_name (regcache
, "pc", &pc
);
245 return (CORE_ADDR
) pc
;
250 collect_register_by_name (regcache
, "pc", &pc
);
251 return (CORE_ADDR
) pc
;
256 ppc_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
258 if (register_size (regcache
->tdesc
, 0) == 4)
260 unsigned int newpc
= pc
;
261 supply_register_by_name (regcache
, "pc", &newpc
);
265 unsigned long newpc
= pc
;
266 supply_register_by_name (regcache
, "pc", &newpc
);
270 #ifndef __powerpc64__
271 static int ppc_regmap_adjusted
;
275 /* Correct in either endianness.
276 This instruction is "twge r2, r2", which GDB uses as a software
278 static const unsigned int ppc_breakpoint
= 0x7d821008;
279 #define ppc_breakpoint_len 4
281 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
283 static const gdb_byte
*
284 ppc_sw_breakpoint_from_kind (int kind
, int *size
)
286 *size
= ppc_breakpoint_len
;
287 return (const gdb_byte
*) &ppc_breakpoint
;
291 ppc_breakpoint_at (CORE_ADDR where
)
295 the_target
->read_memory (where
, (unsigned char *) &insn
, 4);
296 if (insn
== ppc_breakpoint
)
298 /* If necessary, recognize more trap instructions here. GDB only uses
304 /* Implement supports_z_point_type target-ops.
305 Returns true if type Z_TYPE breakpoint is supported.
307 Handling software breakpoint at server side, so tracepoints
308 and breakpoints can be inserted at the same location. */
311 ppc_supports_z_point_type (char z_type
)
318 case Z_PACKET_WRITE_WP
:
319 case Z_PACKET_ACCESS_WP
:
325 /* Implement insert_point target-ops.
326 Returns 0 on success, -1 on failure and 1 on unsupported. */
329 ppc_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
330 int size
, struct raw_breakpoint
*bp
)
334 case raw_bkpt_type_sw
:
335 return insert_memory_breakpoint (bp
);
337 case raw_bkpt_type_hw
:
338 case raw_bkpt_type_write_wp
:
339 case raw_bkpt_type_access_wp
:
346 /* Implement remove_point target-ops.
347 Returns 0 on success, -1 on failure and 1 on unsupported. */
350 ppc_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
351 int size
, struct raw_breakpoint
*bp
)
355 case raw_bkpt_type_sw
:
356 return remove_memory_breakpoint (bp
);
358 case raw_bkpt_type_hw
:
359 case raw_bkpt_type_write_wp
:
360 case raw_bkpt_type_access_wp
:
367 /* Provide only a fill function for the general register set. ps_lgetregs
368 will use this for NPTL support. */
370 static void ppc_fill_gregset (struct regcache
*regcache
, void *buf
)
374 for (i
= 0; i
< 32; i
++)
375 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
377 for (i
= 64; i
< 70; i
++)
378 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
380 for (i
= 71; i
< 73; i
++)
381 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
384 /* Program Priority Register regset fill function. */
387 ppc_fill_pprregset (struct regcache
*regcache
, void *buf
)
389 char *ppr
= (char *) buf
;
391 collect_register_by_name (regcache
, "ppr", ppr
);
394 /* Program Priority Register regset store function. */
397 ppc_store_pprregset (struct regcache
*regcache
, const void *buf
)
399 const char *ppr
= (const char *) buf
;
401 supply_register_by_name (regcache
, "ppr", ppr
);
404 /* Data Stream Control Register regset fill function. */
407 ppc_fill_dscrregset (struct regcache
*regcache
, void *buf
)
409 char *dscr
= (char *) buf
;
411 collect_register_by_name (regcache
, "dscr", dscr
);
414 /* Data Stream Control Register regset store function. */
417 ppc_store_dscrregset (struct regcache
*regcache
, const void *buf
)
419 const char *dscr
= (const char *) buf
;
421 supply_register_by_name (regcache
, "dscr", dscr
);
424 /* Target Address Register regset fill function. */
427 ppc_fill_tarregset (struct regcache
*regcache
, void *buf
)
429 char *tar
= (char *) buf
;
431 collect_register_by_name (regcache
, "tar", tar
);
434 /* Target Address Register regset store function. */
437 ppc_store_tarregset (struct regcache
*regcache
, const void *buf
)
439 const char *tar
= (const char *) buf
;
441 supply_register_by_name (regcache
, "tar", tar
);
444 /* Event-Based Branching regset store function. Unless the inferior
445 has a perf event open, ptrace can return in error when reading and
446 writing to the regset, with ENODATA. For reading, the registers
447 will correctly show as unavailable. For writing, gdbserver
448 currently only caches any register writes from P and G packets and
449 the stub always tries to write all the regsets when resuming the
450 inferior, which would result in frequent warnings. For this
451 reason, we don't define a fill function. This also means that the
452 client-side regcache will be dirty if the user tries to write to
453 the EBB registers. G packets that the client sends to write to
454 unrelated registers will also include data for EBB registers, even
455 if they are unavailable. */
458 ppc_store_ebbregset (struct regcache
*regcache
, const void *buf
)
460 const char *regset
= (const char *) buf
;
462 /* The order in the kernel regset is: EBBRR, EBBHR, BESCR. In the
463 .dat file is BESCR, EBBHR, EBBRR. */
464 supply_register_by_name (regcache
, "ebbrr", ®set
[0]);
465 supply_register_by_name (regcache
, "ebbhr", ®set
[8]);
466 supply_register_by_name (regcache
, "bescr", ®set
[16]);
469 /* Performance Monitoring Unit regset fill function. */
472 ppc_fill_pmuregset (struct regcache
*regcache
, void *buf
)
474 char *regset
= (char *) buf
;
476 /* The order in the kernel regset is SIAR, SDAR, SIER, MMCR2, MMCR0.
477 In the .dat file is MMCR0, MMCR2, SIAR, SDAR, SIER. */
478 collect_register_by_name (regcache
, "siar", ®set
[0]);
479 collect_register_by_name (regcache
, "sdar", ®set
[8]);
480 collect_register_by_name (regcache
, "sier", ®set
[16]);
481 collect_register_by_name (regcache
, "mmcr2", ®set
[24]);
482 collect_register_by_name (regcache
, "mmcr0", ®set
[32]);
485 /* Performance Monitoring Unit regset store function. */
488 ppc_store_pmuregset (struct regcache
*regcache
, const void *buf
)
490 const char *regset
= (const char *) buf
;
492 supply_register_by_name (regcache
, "siar", ®set
[0]);
493 supply_register_by_name (regcache
, "sdar", ®set
[8]);
494 supply_register_by_name (regcache
, "sier", ®set
[16]);
495 supply_register_by_name (regcache
, "mmcr2", ®set
[24]);
496 supply_register_by_name (regcache
, "mmcr0", ®set
[32]);
499 /* Hardware Transactional Memory special-purpose register regset fill
503 ppc_fill_tm_sprregset (struct regcache
*regcache
, void *buf
)
506 char *regset
= (char *) buf
;
508 base
= find_regno (regcache
->tdesc
, "tfhar");
509 for (i
= 0; i
< 3; i
++)
510 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
513 /* Hardware Transactional Memory special-purpose register regset store
517 ppc_store_tm_sprregset (struct regcache
*regcache
, const void *buf
)
520 const char *regset
= (const char *) buf
;
522 base
= find_regno (regcache
->tdesc
, "tfhar");
523 for (i
= 0; i
< 3; i
++)
524 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
527 /* For the same reasons as the EBB regset, none of the HTM
528 checkpointed regsets have a fill function. These registers are
529 only available if the inferior is in a transaction. */
531 /* Hardware Transactional Memory checkpointed general-purpose regset
535 ppc_store_tm_cgprregset (struct regcache
*regcache
, const void *buf
)
537 int i
, base
, size
, endian_offset
;
538 const char *regset
= (const char *) buf
;
540 base
= find_regno (regcache
->tdesc
, "cr0");
541 size
= register_size (regcache
->tdesc
, base
);
543 gdb_assert (size
== 4 || size
== 8);
545 for (i
= 0; i
< 32; i
++)
546 supply_register (regcache
, base
+ i
, ®set
[i
* size
]);
550 if ((size
== 8) && (__BYTE_ORDER
== __BIG_ENDIAN
))
553 supply_register_by_name (regcache
, "ccr",
554 ®set
[PT_CCR
* size
+ endian_offset
]);
556 supply_register_by_name (regcache
, "cxer",
557 ®set
[PT_XER
* size
+ endian_offset
]);
559 supply_register_by_name (regcache
, "clr", ®set
[PT_LNK
* size
]);
560 supply_register_by_name (regcache
, "cctr", ®set
[PT_CTR
* size
]);
563 /* Hardware Transactional Memory checkpointed floating-point regset
567 ppc_store_tm_cfprregset (struct regcache
*regcache
, const void *buf
)
570 const char *regset
= (const char *) buf
;
572 base
= find_regno (regcache
->tdesc
, "cf0");
574 for (i
= 0; i
< 32; i
++)
575 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
577 supply_register_by_name (regcache
, "cfpscr", ®set
[32 * 8]);
580 /* Hardware Transactional Memory checkpointed vector regset store
584 ppc_store_tm_cvrregset (struct regcache
*regcache
, const void *buf
)
587 const char *regset
= (const char *) buf
;
590 base
= find_regno (regcache
->tdesc
, "cvr0");
592 for (i
= 0; i
< 32; i
++)
593 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
595 if (__BYTE_ORDER
== __BIG_ENDIAN
)
598 supply_register_by_name (regcache
, "cvscr",
599 ®set
[32 * 16 + vscr_offset
]);
601 supply_register_by_name (regcache
, "cvrsave", ®set
[33 * 16]);
604 /* Hardware Transactional Memory checkpointed vector-scalar regset
608 ppc_store_tm_cvsxregset (struct regcache
*regcache
, const void *buf
)
611 const char *regset
= (const char *) buf
;
613 base
= find_regno (regcache
->tdesc
, "cvs0h");
614 for (i
= 0; i
< 32; i
++)
615 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
618 /* Hardware Transactional Memory checkpointed Program Priority
619 Register regset store function. */
622 ppc_store_tm_cpprregset (struct regcache
*regcache
, const void *buf
)
624 const char *cppr
= (const char *) buf
;
626 supply_register_by_name (regcache
, "cppr", cppr
);
629 /* Hardware Transactional Memory checkpointed Data Stream Control
630 Register regset store function. */
633 ppc_store_tm_cdscrregset (struct regcache
*regcache
, const void *buf
)
635 const char *cdscr
= (const char *) buf
;
637 supply_register_by_name (regcache
, "cdscr", cdscr
);
640 /* Hardware Transactional Memory checkpointed Target Address Register
641 regset store function. */
644 ppc_store_tm_ctarregset (struct regcache
*regcache
, const void *buf
)
646 const char *ctar
= (const char *) buf
;
648 supply_register_by_name (regcache
, "ctar", ctar
);
652 ppc_fill_vsxregset (struct regcache
*regcache
, void *buf
)
655 char *regset
= (char *) buf
;
657 base
= find_regno (regcache
->tdesc
, "vs0h");
658 for (i
= 0; i
< 32; i
++)
659 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
663 ppc_store_vsxregset (struct regcache
*regcache
, const void *buf
)
666 const char *regset
= (const char *) buf
;
668 base
= find_regno (regcache
->tdesc
, "vs0h");
669 for (i
= 0; i
< 32; i
++)
670 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
674 ppc_fill_vrregset (struct regcache
*regcache
, void *buf
)
677 char *regset
= (char *) buf
;
680 base
= find_regno (regcache
->tdesc
, "vr0");
681 for (i
= 0; i
< 32; i
++)
682 collect_register (regcache
, base
+ i
, ®set
[i
* 16]);
684 if (__BYTE_ORDER
== __BIG_ENDIAN
)
687 collect_register_by_name (regcache
, "vscr",
688 ®set
[32 * 16 + vscr_offset
]);
690 collect_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
694 ppc_store_vrregset (struct regcache
*regcache
, const void *buf
)
697 const char *regset
= (const char *) buf
;
700 base
= find_regno (regcache
->tdesc
, "vr0");
701 for (i
= 0; i
< 32; i
++)
702 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
704 if (__BYTE_ORDER
== __BIG_ENDIAN
)
707 supply_register_by_name (regcache
, "vscr",
708 ®set
[32 * 16 + vscr_offset
]);
709 supply_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
712 struct gdb_evrregset_t
714 unsigned long evr
[32];
715 unsigned long long acc
;
716 unsigned long spefscr
;
720 ppc_fill_evrregset (struct regcache
*regcache
, void *buf
)
723 struct gdb_evrregset_t
*regset
= (struct gdb_evrregset_t
*) buf
;
725 ev0
= find_regno (regcache
->tdesc
, "ev0h");
726 for (i
= 0; i
< 32; i
++)
727 collect_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
729 collect_register_by_name (regcache
, "acc", ®set
->acc
);
730 collect_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
734 ppc_store_evrregset (struct regcache
*regcache
, const void *buf
)
737 const struct gdb_evrregset_t
*regset
= (const struct gdb_evrregset_t
*) buf
;
739 ev0
= find_regno (regcache
->tdesc
, "ev0h");
740 for (i
= 0; i
< 32; i
++)
741 supply_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
743 supply_register_by_name (regcache
, "acc", ®set
->acc
);
744 supply_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
747 /* Support for hardware single step. */
750 ppc_supports_hardware_single_step (void)
755 static struct regset_info ppc_regsets
[] = {
756 /* List the extra register sets before GENERAL_REGS. That way we will
757 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
758 general registers. Some kernels support these, but not the newer
759 PPC_PTRACE_GETREGS. */
760 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CTAR
, 0, EXTENDED_REGS
,
761 NULL
, ppc_store_tm_ctarregset
},
762 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CDSCR
, 0, EXTENDED_REGS
,
763 NULL
, ppc_store_tm_cdscrregset
},
764 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CPPR
, 0, EXTENDED_REGS
,
765 NULL
, ppc_store_tm_cpprregset
},
766 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CVSX
, 0, EXTENDED_REGS
,
767 NULL
, ppc_store_tm_cvsxregset
},
768 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CVMX
, 0, EXTENDED_REGS
,
769 NULL
, ppc_store_tm_cvrregset
},
770 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CFPR
, 0, EXTENDED_REGS
,
771 NULL
, ppc_store_tm_cfprregset
},
772 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CGPR
, 0, EXTENDED_REGS
,
773 NULL
, ppc_store_tm_cgprregset
},
774 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_SPR
, 0, EXTENDED_REGS
,
775 ppc_fill_tm_sprregset
, ppc_store_tm_sprregset
},
776 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_EBB
, 0, EXTENDED_REGS
,
777 NULL
, ppc_store_ebbregset
},
778 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PMU
, 0, EXTENDED_REGS
,
779 ppc_fill_pmuregset
, ppc_store_pmuregset
},
780 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TAR
, 0, EXTENDED_REGS
,
781 ppc_fill_tarregset
, ppc_store_tarregset
},
782 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PPR
, 0, EXTENDED_REGS
,
783 ppc_fill_pprregset
, ppc_store_pprregset
},
784 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_DSCR
, 0, EXTENDED_REGS
,
785 ppc_fill_dscrregset
, ppc_store_dscrregset
},
786 { PTRACE_GETVSXREGS
, PTRACE_SETVSXREGS
, 0, 0, EXTENDED_REGS
,
787 ppc_fill_vsxregset
, ppc_store_vsxregset
},
788 { PTRACE_GETVRREGS
, PTRACE_SETVRREGS
, 0, 0, EXTENDED_REGS
,
789 ppc_fill_vrregset
, ppc_store_vrregset
},
790 { PTRACE_GETEVRREGS
, PTRACE_SETEVRREGS
, 0, 0, EXTENDED_REGS
,
791 ppc_fill_evrregset
, ppc_store_evrregset
},
792 { 0, 0, 0, 0, GENERAL_REGS
, ppc_fill_gregset
, NULL
},
796 static struct usrregs_info ppc_usrregs_info
=
802 static struct regsets_info ppc_regsets_info
=
804 ppc_regsets
, /* regsets */
806 NULL
, /* disabled_regsets */
809 static struct regs_info regs_info
=
811 NULL
, /* regset_bitmap */
816 static const struct regs_info
*
823 ppc_target::low_arch_setup ()
825 const struct target_desc
*tdesc
;
826 struct regset_info
*regset
;
827 struct ppc_linux_features features
= ppc_linux_no_features
;
829 int tid
= lwpid_of (current_thread
);
831 features
.wordsize
= ppc_linux_target_wordsize (tid
);
833 if (features
.wordsize
== 4)
834 tdesc
= tdesc_powerpc_32l
;
836 tdesc
= tdesc_powerpc_64l
;
838 current_process ()->tdesc
= tdesc
;
840 /* The value of current_process ()->tdesc needs to be set for this
842 ppc_hwcap
= linux_get_hwcap (features
.wordsize
);
843 ppc_hwcap2
= linux_get_hwcap2 (features
.wordsize
);
845 features
.isa205
= ppc_linux_has_isa205 (ppc_hwcap
);
847 if (ppc_hwcap
& PPC_FEATURE_HAS_VSX
)
850 if (ppc_hwcap
& PPC_FEATURE_HAS_ALTIVEC
)
851 features
.altivec
= true;
853 if ((ppc_hwcap2
& PPC_FEATURE2_DSCR
)
854 && ppc_check_regset (tid
, NT_PPC_DSCR
, PPC_LINUX_SIZEOF_DSCRREGSET
)
855 && ppc_check_regset (tid
, NT_PPC_PPR
, PPC_LINUX_SIZEOF_PPRREGSET
))
857 features
.ppr_dscr
= true;
858 if ((ppc_hwcap2
& PPC_FEATURE2_ARCH_2_07
)
859 && (ppc_hwcap2
& PPC_FEATURE2_TAR
)
860 && (ppc_hwcap2
& PPC_FEATURE2_EBB
)
861 && ppc_check_regset (tid
, NT_PPC_TAR
,
862 PPC_LINUX_SIZEOF_TARREGSET
)
863 && ppc_check_regset (tid
, NT_PPC_EBB
,
864 PPC_LINUX_SIZEOF_EBBREGSET
)
865 && ppc_check_regset (tid
, NT_PPC_PMU
,
866 PPC_LINUX_SIZEOF_PMUREGSET
))
868 features
.isa207
= true;
869 if ((ppc_hwcap2
& PPC_FEATURE2_HTM
)
870 && ppc_check_regset (tid
, NT_PPC_TM_SPR
,
871 PPC_LINUX_SIZEOF_TM_SPRREGSET
))
876 tdesc
= ppc_linux_match_description (features
);
878 /* On 32-bit machines, check for SPE registers.
879 Set the low target's regmap field as appropriately. */
880 #ifndef __powerpc64__
881 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
882 tdesc
= tdesc_powerpc_e500l
;
884 if (!ppc_regmap_adjusted
)
886 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
887 ppc_usrregs_info
.regmap
= ppc_regmap_e500
;
889 /* If the FPSCR is 64-bit wide, we need to fetch the whole
890 64-bit slot and not just its second word. The PT_FPSCR
891 supplied in a 32-bit GDB compilation doesn't reflect
893 if (register_size (tdesc
, 70) == 8)
894 ppc_regmap
[70] = (48 + 2*32) * sizeof (long);
896 ppc_regmap_adjusted
= 1;
900 current_process ()->tdesc
= tdesc
;
902 for (regset
= ppc_regsets
; regset
->size
>= 0; regset
++)
903 switch (regset
->get_request
)
905 case PTRACE_GETVRREGS
:
906 regset
->size
= features
.altivec
? PPC_LINUX_SIZEOF_VRREGSET
: 0;
908 case PTRACE_GETVSXREGS
:
909 regset
->size
= features
.vsx
? PPC_LINUX_SIZEOF_VSXREGSET
: 0;
911 case PTRACE_GETEVRREGS
:
912 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
913 regset
->size
= 32 * 4 + 8 + 4;
917 case PTRACE_GETREGSET
:
918 switch (regset
->nt_type
)
921 regset
->size
= (features
.ppr_dscr
?
922 PPC_LINUX_SIZEOF_PPRREGSET
: 0);
925 regset
->size
= (features
.ppr_dscr
?
926 PPC_LINUX_SIZEOF_DSCRREGSET
: 0);
929 regset
->size
= (features
.isa207
?
930 PPC_LINUX_SIZEOF_TARREGSET
: 0);
933 regset
->size
= (features
.isa207
?
934 PPC_LINUX_SIZEOF_EBBREGSET
: 0);
937 regset
->size
= (features
.isa207
?
938 PPC_LINUX_SIZEOF_PMUREGSET
: 0);
941 regset
->size
= (features
.htm
?
942 PPC_LINUX_SIZEOF_TM_SPRREGSET
: 0);
945 if (features
.wordsize
== 4)
946 regset
->size
= (features
.htm
?
947 PPC32_LINUX_SIZEOF_CGPRREGSET
: 0);
949 regset
->size
= (features
.htm
?
950 PPC64_LINUX_SIZEOF_CGPRREGSET
: 0);
953 regset
->size
= (features
.htm
?
954 PPC_LINUX_SIZEOF_CFPRREGSET
: 0);
957 regset
->size
= (features
.htm
?
958 PPC_LINUX_SIZEOF_CVMXREGSET
: 0);
961 regset
->size
= (features
.htm
?
962 PPC_LINUX_SIZEOF_CVSXREGSET
: 0);
965 regset
->size
= (features
.htm
?
966 PPC_LINUX_SIZEOF_CPPRREGSET
: 0);
968 case NT_PPC_TM_CDSCR
:
969 regset
->size
= (features
.htm
?
970 PPC_LINUX_SIZEOF_CDSCRREGSET
: 0);
973 regset
->size
= (features
.htm
?
974 PPC_LINUX_SIZEOF_CTARREGSET
: 0);
985 /* Implementation of linux_target_ops method "supports_tracepoints". */
988 ppc_supports_tracepoints (void)
993 /* Get the thread area address. This is used to recognize which
994 thread is which when tracing with the in-process agent library. We
995 don't read anything from the address, and treat it as opaque; it's
996 the address itself that we assume is unique per-thread. */
999 ppc_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
1001 struct lwp_info
*lwp
= find_lwp_pid (ptid_t (lwpid
));
1002 struct thread_info
*thr
= get_lwp_thread (lwp
);
1003 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
1006 #ifdef __powerpc64__
1007 if (register_size (regcache
->tdesc
, 0) == 8)
1008 collect_register_by_name (regcache
, "r13", &tp
);
1011 collect_register_by_name (regcache
, "r2", &tp
);
1018 #ifdef __powerpc64__
1020 /* Older glibc doesn't provide this. */
1022 #ifndef EF_PPC64_ABI
1023 #define EF_PPC64_ABI 3
1026 /* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
1030 is_elfv2_inferior (void)
1032 /* To be used as fallback if we're unable to determine the right result -
1033 assume inferior uses the same ABI as gdbserver. */
1035 const int def_res
= 1;
1037 const int def_res
= 0;
1042 const struct target_desc
*tdesc
= current_process ()->tdesc
;
1043 int wordsize
= register_size (tdesc
, 0);
1045 if (!linux_get_auxv (wordsize
, AT_PHDR
, &phdr
))
1048 /* Assume ELF header is at the beginning of the page where program headers
1049 are located. If it doesn't look like one, bail. */
1051 read_inferior_memory (phdr
& ~0xfff, (unsigned char *) &ehdr
, sizeof ehdr
);
1052 if (memcmp(ehdr
.e_ident
, ELFMAG
, SELFMAG
))
1055 return (ehdr
.e_flags
& EF_PPC64_ABI
) == 2;
1060 /* Generate a ds-form instruction in BUF and return the number of bytes written
1063 | OPCD | RST | RA | DS |XO| */
1065 __attribute__((unused
)) /* Maybe unused due to conditional compilation. */
1067 gen_ds_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int ds
, int xo
)
1071 gdb_assert ((opcd
& ~0x3f) == 0);
1072 gdb_assert ((rst
& ~0x1f) == 0);
1073 gdb_assert ((ra
& ~0x1f) == 0);
1074 gdb_assert ((xo
& ~0x3) == 0);
1076 insn
= (rst
<< 21) | (ra
<< 16) | (ds
& 0xfffc) | (xo
& 0x3);
1077 *buf
= (opcd
<< 26) | insn
;
1081 /* Followings are frequently used ds-form instructions. */
1083 #define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
1084 #define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
1085 #define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
1086 #define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
1088 /* Generate a d-form instruction in BUF.
1091 | OPCD | RST | RA | D | */
1094 gen_d_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int si
)
1098 gdb_assert ((opcd
& ~0x3f) == 0);
1099 gdb_assert ((rst
& ~0x1f) == 0);
1100 gdb_assert ((ra
& ~0x1f) == 0);
1102 insn
= (rst
<< 21) | (ra
<< 16) | (si
& 0xffff);
1103 *buf
= (opcd
<< 26) | insn
;
1107 /* Followings are frequently used d-form instructions. */
1109 #define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
1110 #define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
1111 #define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
1112 #define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
1113 #define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
1114 #define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
1115 #define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
1116 #define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
1117 #define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
1119 /* Generate a xfx-form instruction in BUF and return the number of bytes
1123 | OPCD | RST | RI | XO |/| */
1126 gen_xfx_form (uint32_t *buf
, int opcd
, int rst
, int ri
, int xo
)
1129 unsigned int n
= ((ri
& 0x1f) << 5) | ((ri
>> 5) & 0x1f);
1131 gdb_assert ((opcd
& ~0x3f) == 0);
1132 gdb_assert ((rst
& ~0x1f) == 0);
1133 gdb_assert ((xo
& ~0x3ff) == 0);
1135 insn
= (rst
<< 21) | (n
<< 11) | (xo
<< 1);
1136 *buf
= (opcd
<< 26) | insn
;
1140 /* Followings are frequently used xfx-form instructions. */
1142 #define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
1143 #define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
1144 #define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
1145 #define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
1146 #define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
1148 #define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
1151 /* Generate a x-form instruction in BUF and return the number of bytes written.
1154 | OPCD | RST | RA | RB | XO |RC| */
1157 gen_x_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int rb
, int xo
, int rc
)
1161 gdb_assert ((opcd
& ~0x3f) == 0);
1162 gdb_assert ((rst
& ~0x1f) == 0);
1163 gdb_assert ((ra
& ~0x1f) == 0);
1164 gdb_assert ((rb
& ~0x1f) == 0);
1165 gdb_assert ((xo
& ~0x3ff) == 0);
1166 gdb_assert ((rc
& ~1) == 0);
1168 insn
= (rst
<< 21) | (ra
<< 16) | (rb
<< 11) | (xo
<< 1) | rc
;
1169 *buf
= (opcd
<< 26) | insn
;
1173 /* Followings are frequently used x-form instructions. */
1175 #define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
1176 #define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
1177 #define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
1178 #define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
1179 /* Assume bf = cr7. */
1180 #define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
1183 /* Generate a md-form instruction in BUF and return the number of bytes written.
1185 0 6 11 16 21 27 30 31 32
1186 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
1189 gen_md_form (uint32_t *buf
, int opcd
, int rs
, int ra
, int sh
, int mb
,
1193 unsigned int n
= ((mb
& 0x1f) << 1) | ((mb
>> 5) & 0x1);
1194 unsigned int sh0_4
= sh
& 0x1f;
1195 unsigned int sh5
= (sh
>> 5) & 1;
1197 gdb_assert ((opcd
& ~0x3f) == 0);
1198 gdb_assert ((rs
& ~0x1f) == 0);
1199 gdb_assert ((ra
& ~0x1f) == 0);
1200 gdb_assert ((sh
& ~0x3f) == 0);
1201 gdb_assert ((mb
& ~0x3f) == 0);
1202 gdb_assert ((xo
& ~0x7) == 0);
1203 gdb_assert ((rc
& ~0x1) == 0);
1205 insn
= (rs
<< 21) | (ra
<< 16) | (sh0_4
<< 11) | (n
<< 5)
1206 | (sh5
<< 1) | (xo
<< 2) | (rc
& 1);
1207 *buf
= (opcd
<< 26) | insn
;
1211 /* The following are frequently used md-form instructions. */
1213 #define GEN_RLDICL(buf, ra, rs ,sh, mb) \
1214 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
1215 #define GEN_RLDICR(buf, ra, rs ,sh, mb) \
1216 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
1218 /* Generate a i-form instruction in BUF and return the number of bytes written.
1221 | OPCD | LI |AA|LK| */
1224 gen_i_form (uint32_t *buf
, int opcd
, int li
, int aa
, int lk
)
1228 gdb_assert ((opcd
& ~0x3f) == 0);
1230 insn
= (li
& 0x3fffffc) | (aa
& 1) | (lk
& 1);
1231 *buf
= (opcd
<< 26) | insn
;
1235 /* The following are frequently used i-form instructions. */
1237 #define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
1238 #define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
1240 /* Generate a b-form instruction in BUF and return the number of bytes written.
1243 | OPCD | BO | BI | BD |AA|LK| */
1246 gen_b_form (uint32_t *buf
, int opcd
, int bo
, int bi
, int bd
,
1251 gdb_assert ((opcd
& ~0x3f) == 0);
1252 gdb_assert ((bo
& ~0x1f) == 0);
1253 gdb_assert ((bi
& ~0x1f) == 0);
1255 insn
= (bo
<< 21) | (bi
<< 16) | (bd
& 0xfffc) | (aa
& 1) | (lk
& 1);
1256 *buf
= (opcd
<< 26) | insn
;
1260 /* The following are frequently used b-form instructions. */
1261 /* Assume bi = cr7. */
1262 #define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
1264 /* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
1265 respectively. They are primary used for save/restore GPRs in jump-pad,
1266 not used for bytecode compiling. */
1268 #ifdef __powerpc64__
1269 #define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
1270 GEN_LD (buf, rt, ra, si) : \
1271 GEN_LWZ (buf, rt, ra, si))
1272 #define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
1273 GEN_STD (buf, rt, ra, si) : \
1274 GEN_STW (buf, rt, ra, si))
1276 #define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
1277 #define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
1280 /* Generate a sequence of instructions to load IMM in the register REG.
1281 Write the instructions in BUF and return the number of bytes written. */
1284 gen_limm (uint32_t *buf
, int reg
, uint64_t imm
, int is_64
)
1288 if ((imm
+ 32768) < 65536)
1290 /* li reg, imm[15:0] */
1291 p
+= GEN_LI (p
, reg
, imm
);
1293 else if ((imm
>> 32) == 0)
1295 /* lis reg, imm[31:16]
1296 ori reg, reg, imm[15:0]
1297 rldicl reg, reg, 0, 32 */
1298 p
+= GEN_LIS (p
, reg
, (imm
>> 16) & 0xffff);
1299 if ((imm
& 0xffff) != 0)
1300 p
+= GEN_ORI (p
, reg
, reg
, imm
& 0xffff);
1301 /* Clear upper 32-bit if sign-bit is set. */
1302 if (imm
& (1u << 31) && is_64
)
1303 p
+= GEN_RLDICL (p
, reg
, reg
, 0, 32);
1308 /* lis reg, <imm[63:48]>
1309 ori reg, reg, <imm[48:32]>
1310 rldicr reg, reg, 32, 31
1311 oris reg, reg, <imm[31:16]>
1312 ori reg, reg, <imm[15:0]> */
1313 p
+= GEN_LIS (p
, reg
, ((imm
>> 48) & 0xffff));
1314 if (((imm
>> 32) & 0xffff) != 0)
1315 p
+= GEN_ORI (p
, reg
, reg
, ((imm
>> 32) & 0xffff));
1316 p
+= GEN_RLDICR (p
, reg
, reg
, 32, 31);
1317 if (((imm
>> 16) & 0xffff) != 0)
1318 p
+= GEN_ORIS (p
, reg
, reg
, ((imm
>> 16) & 0xffff));
1319 if ((imm
& 0xffff) != 0)
1320 p
+= GEN_ORI (p
, reg
, reg
, (imm
& 0xffff));
1326 /* Generate a sequence for atomically exchange at location LOCK.
1327 This code sequence clobbers r6, r7, r8. LOCK is the location for
1328 the atomic-xchg, OLD_VALUE is expected old value stored in the
1329 location, and R_NEW is a register for the new value. */
1332 gen_atomic_xchg (uint32_t *buf
, CORE_ADDR lock
, int old_value
, int r_new
,
1335 const int r_lock
= 6;
1336 const int r_old
= 7;
1337 const int r_tmp
= 8;
1341 1: lwarx TMP, 0, LOCK
1347 p
+= gen_limm (p
, r_lock
, lock
, is_64
);
1348 p
+= gen_limm (p
, r_old
, old_value
, is_64
);
1350 p
+= GEN_LWARX (p
, r_tmp
, 0, r_lock
);
1351 p
+= GEN_CMPW (p
, r_tmp
, r_old
);
1352 p
+= GEN_BNE (p
, -8);
1353 p
+= GEN_STWCX (p
, r_new
, 0, r_lock
);
1354 p
+= GEN_BNE (p
, -16);
1359 /* Generate a sequence of instructions for calling a function
1360 at address of FN. Return the number of bytes are written in BUF. */
1363 gen_call (uint32_t *buf
, CORE_ADDR fn
, int is_64
, int is_opd
)
1367 /* Must be called by r12 for caller to calculate TOC address. */
1368 p
+= gen_limm (p
, 12, fn
, is_64
);
1371 p
+= GEN_LOAD (p
, 11, 12, 16, is_64
);
1372 p
+= GEN_LOAD (p
, 2, 12, 8, is_64
);
1373 p
+= GEN_LOAD (p
, 12, 12, 0, is_64
);
1375 p
+= GEN_MTSPR (p
, 12, 9); /* mtctr r12 */
1376 *p
++ = 0x4e800421; /* bctrl */
1381 /* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1382 of instruction. This function is used to adjust pc-relative instructions
1386 ppc_relocate_instruction (CORE_ADDR
*to
, CORE_ADDR oldloc
)
1391 read_inferior_memory (oldloc
, (unsigned char *) &insn
, 4);
1392 op6
= PPC_OP6 (insn
);
1394 if (op6
== 18 && (insn
& 2) == 0)
1396 /* branch && AA = 0 */
1397 rel
= PPC_LI (insn
);
1398 newrel
= (oldloc
- *to
) + rel
;
1400 /* Out of range. Cannot relocate instruction. */
1401 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1404 insn
= (insn
& ~0x3fffffc) | (newrel
& 0x3fffffc);
1406 else if (op6
== 16 && (insn
& 2) == 0)
1408 /* conditional branch && AA = 0 */
1410 /* If the new relocation is too big for even a 26-bit unconditional
1411 branch, there is nothing we can do. Just abort.
1413 Otherwise, if it can be fit in 16-bit conditional branch, just
1414 copy the instruction and relocate the address.
1416 If the it's big for conditional-branch (16-bit), try to invert the
1417 condition and jump with 26-bit branch. For example,
1428 After this transform, we are actually jump from *TO+4 instead of *TO,
1429 so check the relocation again because it will be 1-insn farther then
1430 before if *TO is after OLDLOC.
1433 For BDNZT (or so) is transformed from
1445 See also "BO field encodings". */
1447 rel
= PPC_BD (insn
);
1448 newrel
= (oldloc
- *to
) + rel
;
1450 if (newrel
< (1 << 15) && newrel
>= -(1 << 15))
1451 insn
= (insn
& ~0xfffc) | (newrel
& 0xfffc);
1452 else if ((PPC_BO (insn
) & 0x14) == 0x4 || (PPC_BO (insn
) & 0x14) == 0x10)
1456 /* Out of range. Cannot relocate instruction. */
1457 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1460 if ((PPC_BO (insn
) & 0x14) == 0x4)
1462 else if ((PPC_BO (insn
) & 0x14) == 0x10)
1465 /* Jump over the unconditional branch. */
1466 insn
= (insn
& ~0xfffc) | 0x8;
1467 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1470 /* Build a unconditional branch and copy LK bit. */
1471 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1472 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1477 else if ((PPC_BO (insn
) & 0x14) == 0)
1479 uint32_t bdnz_insn
= (16 << 26) | (0x10 << 21) | 12;
1480 uint32_t bf_insn
= (16 << 26) | (0x4 << 21) | 8;
1484 /* Out of range. Cannot relocate instruction. */
1485 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1488 /* Copy BI field. */
1489 bf_insn
|= (insn
& 0x1f0000);
1491 /* Invert condition. */
1492 bdnz_insn
|= (insn
^ (1 << 22)) & (1 << 22);
1493 bf_insn
|= (insn
^ (1 << 24)) & (1 << 24);
1495 target_write_memory (*to
, (unsigned char *) &bdnz_insn
, 4);
1497 target_write_memory (*to
, (unsigned char *) &bf_insn
, 4);
1500 /* Build a unconditional branch and copy LK bit. */
1501 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1502 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1507 else /* (BO & 0x14) == 0x14, branch always. */
1509 /* Out of range. Cannot relocate instruction. */
1510 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1513 /* Build a unconditional branch and copy LK bit. */
1514 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1515 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1522 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1526 /* Implement install_fast_tracepoint_jump_pad of target_ops.
1527 See target.h for details. */
1530 ppc_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1531 CORE_ADDR collector
,
1534 CORE_ADDR
*jump_entry
,
1535 CORE_ADDR
*trampoline
,
1536 ULONGEST
*trampoline_size
,
1537 unsigned char *jjump_pad_insn
,
1538 ULONGEST
*jjump_pad_insn_size
,
1539 CORE_ADDR
*adjusted_insn_addr
,
1540 CORE_ADDR
*adjusted_insn_addr_end
,
1546 CORE_ADDR buildaddr
= *jump_entry
;
1547 const CORE_ADDR entryaddr
= *jump_entry
;
1548 int rsz
, min_frame
, frame_size
, tp_reg
;
1549 #ifdef __powerpc64__
1550 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
1551 int is_64
= register_size (regcache
->tdesc
, 0) == 8;
1552 int is_opd
= is_64
&& !is_elfv2_inferior ();
1554 int is_64
= 0, is_opd
= 0;
1557 #ifdef __powerpc64__
1560 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1563 frame_size
= (40 * rsz
) + min_frame
;
1571 frame_size
= (40 * rsz
) + min_frame
;
1573 #ifdef __powerpc64__
1577 /* Stack frame layout for this jump pad,
1579 High thread_area (r13/r2) |
1580 tpoint - collecting_t obj
1590 R0 - collected registers
1596 The code flow of this jump pad,
1601 4. Call gdb_collector
1602 5. Restore GPR and SPR
1604 7. Build a jump for back to the program
1605 8. Copy/relocate original instruction
1606 9. Build a jump for replacing original instruction. */
1608 /* Adjust stack pointer. */
1610 p
+= GEN_STDU (p
, 1, 1, -frame_size
); /* stdu r1,-frame_size(r1) */
1612 p
+= GEN_STWU (p
, 1, 1, -frame_size
); /* stwu r1,-frame_size(r1) */
1614 /* Store GPRs. Save R1 later, because it had just been modified, but
1615 we want the original value. */
1616 for (j
= 2; j
< 32; j
++)
1617 p
+= GEN_STORE (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1618 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1619 /* Set r0 to the original value of r1 before adjusting stack frame,
1620 and then save it. */
1621 p
+= GEN_ADDI (p
, 0, 1, frame_size
);
1622 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 1 * rsz
, is_64
);
1624 /* Save CR, XER, LR, and CTR. */
1625 p
+= GEN_MFCR (p
, 3); /* mfcr r3 */
1626 p
+= GEN_MFSPR (p
, 4, 1); /* mfxer r4 */
1627 p
+= GEN_MFSPR (p
, 5, 8); /* mflr r5 */
1628 p
+= GEN_MFSPR (p
, 6, 9); /* mfctr r6 */
1629 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
);/* std r3, 32(r1) */
1630 p
+= GEN_STORE (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
);/* std r4, 33(r1) */
1631 p
+= GEN_STORE (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
);/* std r5, 34(r1) */
1632 p
+= GEN_STORE (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
);/* std r6, 35(r1) */
1634 /* Save PC<tpaddr> */
1635 p
+= gen_limm (p
, 3, tpaddr
, is_64
);
1636 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 36 * rsz
, is_64
);
1639 /* Setup arguments to collector. */
1640 /* Set r4 to collected registers. */
1641 p
+= GEN_ADDI (p
, 4, 1, min_frame
);
1642 /* Set r3 to TPOINT. */
1643 p
+= gen_limm (p
, 3, tpoint
, is_64
);
1645 /* Prepare collecting_t object for lock. */
1646 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 37 * rsz
, is_64
);
1647 p
+= GEN_STORE (p
, tp_reg
, 1, min_frame
+ 38 * rsz
, is_64
);
1648 /* Set R5 to collecting object. */
1649 p
+= GEN_ADDI (p
, 5, 1, 37 * rsz
);
1651 p
+= GEN_LWSYNC (p
);
1652 p
+= gen_atomic_xchg (p
, lockaddr
, 0, 5, is_64
);
1653 p
+= GEN_LWSYNC (p
);
1655 /* Call to collector. */
1656 p
+= gen_call (p
, collector
, is_64
, is_opd
);
1658 /* Simply write 0 to release the lock. */
1659 p
+= gen_limm (p
, 3, lockaddr
, is_64
);
1660 p
+= gen_limm (p
, 4, 0, is_64
);
1661 p
+= GEN_LWSYNC (p
);
1662 p
+= GEN_STORE (p
, 4, 3, 0, is_64
);
1664 /* Restore stack and registers. */
1665 p
+= GEN_LOAD (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
); /* ld r3, 32(r1) */
1666 p
+= GEN_LOAD (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
); /* ld r4, 33(r1) */
1667 p
+= GEN_LOAD (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
); /* ld r5, 34(r1) */
1668 p
+= GEN_LOAD (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
); /* ld r6, 35(r1) */
1669 p
+= GEN_MTCR (p
, 3); /* mtcr r3 */
1670 p
+= GEN_MTSPR (p
, 4, 1); /* mtxer r4 */
1671 p
+= GEN_MTSPR (p
, 5, 8); /* mtlr r5 */
1672 p
+= GEN_MTSPR (p
, 6, 9); /* mtctr r6 */
1675 for (j
= 2; j
< 32; j
++)
1676 p
+= GEN_LOAD (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1677 p
+= GEN_LOAD (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1679 p
+= GEN_ADDI (p
, 1, 1, frame_size
);
1681 /* Flush instructions to inferior memory. */
1682 target_write_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1684 /* Now, insert the original instruction to execute in the jump pad. */
1685 *adjusted_insn_addr
= buildaddr
+ (p
- buf
) * 4;
1686 *adjusted_insn_addr_end
= *adjusted_insn_addr
;
1687 ppc_relocate_instruction (adjusted_insn_addr_end
, tpaddr
);
1689 /* Verify the relocation size. If should be 4 for normal copy,
1690 8 or 12 for some conditional branch. */
1691 if ((*adjusted_insn_addr_end
- *adjusted_insn_addr
== 0)
1692 || (*adjusted_insn_addr_end
- *adjusted_insn_addr
> 12))
1694 sprintf (err
, "E.Unexpected instruction length = %d"
1695 "when relocate instruction.",
1696 (int) (*adjusted_insn_addr_end
- *adjusted_insn_addr
));
1700 buildaddr
= *adjusted_insn_addr_end
;
1702 /* Finally, write a jump back to the program. */
1703 offset
= (tpaddr
+ 4) - buildaddr
;
1704 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1706 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1707 "(offset 0x%x > 26-bit).", offset
);
1711 p
+= GEN_B (p
, offset
);
1712 target_write_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1713 *jump_entry
= buildaddr
+ (p
- buf
) * 4;
1715 /* The jump pad is now built. Wire in a jump to our jump pad. This
1716 is always done last (by our caller actually), so that we can
1717 install fast tracepoints with threads running. This relies on
1718 the agent's atomic write support. */
1719 offset
= entryaddr
- tpaddr
;
1720 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1722 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1723 "(offset 0x%x > 26-bit).", offset
);
1727 GEN_B ((uint32_t *) jjump_pad_insn
, offset
);
1728 *jjump_pad_insn_size
= 4;
1733 /* Returns the minimum instruction length for installing a tracepoint. */
1736 ppc_get_min_fast_tracepoint_insn_len (void)
1741 /* Emits a given buffer into the target at current_insn_ptr. Length
1742 is in units of 32-bit words. */
1745 emit_insns (uint32_t *buf
, int n
)
1747 n
= n
* sizeof (uint32_t);
1748 target_write_memory (current_insn_ptr
, (unsigned char *) buf
, n
);
1749 current_insn_ptr
+= n
;
1752 #define __EMIT_ASM(NAME, INSNS) \
1755 extern uint32_t start_bcax_ ## NAME []; \
1756 extern uint32_t end_bcax_ ## NAME []; \
1757 emit_insns (start_bcax_ ## NAME, \
1758 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1759 __asm__ (".section .text.__ppcbcax\n\t" \
1760 "start_bcax_" #NAME ":\n\t" \
1762 "end_bcax_" #NAME ":\n\t" \
1766 #define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1767 #define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1771 Bytecode execution stack frame - 32-bit
1773 | LR save area (SP + 4)
1774 SP' -> +- Back chain (SP + 0)
1775 | Save r31 for access saved arguments
1776 | Save r30 for bytecode stack pointer
1777 | Save r4 for incoming argument *value
1778 | Save r3 for incoming argument regs
1779 r30 -> +- Bytecode execution stack
1781 | 64-byte (8 doublewords) at initial.
1782 | Expand stack as needed.
1785 | Some padding for minimum stack frame and 16-byte alignment.
1787 SP +- Back-chain (SP')
1793 r30 is the stack-pointer for bytecode machine.
1794 It should point to next-empty, so we can use LDU for pop.
1795 r3 is used for cache of the high part of TOP value.
1796 It was the first argument, pointer to regs.
1797 r4 is used for cache of the low part of TOP value.
1798 It was the second argument, pointer to the result.
1799 We should set *result = TOP after leaving this function.
1802 * To restore stack at epilogue
1804 * To check stack is big enough for bytecode execution.
1806 * To return execution result.
1811 /* Regardless of endian, register 3 is always high part, 4 is low part.
1812 These defines are used when the register pair is stored/loaded.
1813 Likewise, to simplify code, have a similiar define for 5:6. */
1815 #if __BYTE_ORDER == __LITTLE_ENDIAN
1816 #define TOP_FIRST "4"
1817 #define TOP_SECOND "3"
1818 #define TMP_FIRST "6"
1819 #define TMP_SECOND "5"
1821 #define TOP_FIRST "3"
1822 #define TOP_SECOND "4"
1823 #define TMP_FIRST "5"
1824 #define TMP_SECOND "6"
1827 /* Emit prologue in inferior memory. See above comments. */
1830 ppc_emit_prologue (void)
1832 EMIT_ASM (/* Save return address. */
1835 /* Adjust SP. 96 is the initial frame size. */
1837 /* Save r30 and incoming arguments. */
1838 "stw 31, 96-4(1) \n"
1839 "stw 30, 96-8(1) \n"
1840 "stw 4, 96-12(1) \n"
1841 "stw 3, 96-16(1) \n"
1842 /* Point r31 to original r1 for access arguments. */
1844 /* Set r30 to pointing stack-top. */
1846 /* Initial r3/TOP to 0. */
1851 /* Emit epilogue in inferior memory. See above comments. */
1854 ppc_emit_epilogue (void)
1856 EMIT_ASM (/* *result = TOP */
1858 "stw " TOP_FIRST
", 0(5) \n"
1859 "stw " TOP_SECOND
", 4(5) \n"
1860 /* Restore registers. */
1867 /* Return 0 for no-error. */
1873 /* TOP = stack[--sp] + TOP */
1878 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1879 "lwz " TMP_SECOND
", 4(30)\n"
1884 /* TOP = stack[--sp] - TOP */
1889 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1890 "lwz " TMP_SECOND
", 4(30) \n"
1892 "subfe 3, 3, 5 \n");
1895 /* TOP = stack[--sp] * TOP */
1900 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1901 "lwz " TMP_SECOND
", 4(30) \n"
1910 /* TOP = stack[--sp] << TOP */
1915 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1916 "lwz " TMP_SECOND
", 4(30) \n"
1917 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1918 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1919 "slw 5, 5, 4\n" /* Shift high part left */
1920 "slw 4, 6, 4\n" /* Shift low part left */
1921 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
1922 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
1924 "or 3, 7, 3\n"); /* Assemble high part */
1927 /* Top = stack[--sp] >> TOP
1928 (Arithmetic shift right) */
1931 ppc_emit_rsh_signed (void)
1933 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1934 "lwz " TMP_SECOND
", 4(30) \n"
1935 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1936 "sraw 3, 5, 4\n" /* Shift high part right */
1938 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
1939 "sraw 4, 5, 7\n" /* Shift high to low */
1942 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
1943 "srw 4, 6, 4\n" /* Shift low part right */
1944 "slw 5, 5, 7\n" /* Shift high to low */
1945 "or 4, 4, 5\n" /* Assemble low part */
1949 /* Top = stack[--sp] >> TOP
1950 (Logical shift right) */
1953 ppc_emit_rsh_unsigned (void)
1955 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1956 "lwz " TMP_SECOND
", 4(30) \n"
1957 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1958 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1959 "srw 6, 6, 4\n" /* Shift low part right */
1960 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
1961 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
1963 "srw 3, 5, 4\n" /* Shift high part right */
1964 "or 4, 6, 7\n"); /* Assemble low part */
1967 /* Emit code for signed-extension specified by ARG. */
1970 ppc_emit_ext (int arg
)
1975 EMIT_ASM ("extsb 4, 4\n"
1979 EMIT_ASM ("extsh 4, 4\n"
1983 EMIT_ASM ("srawi 3, 4, 31");
1990 /* Emit code for zero-extension specified by ARG. */
1993 ppc_emit_zero_ext (int arg
)
1998 EMIT_ASM ("clrlwi 4,4,24\n"
2002 EMIT_ASM ("clrlwi 4,4,16\n"
2006 EMIT_ASM ("li 3, 0");
2014 i.e., TOP = (TOP == 0) ? 1 : 0; */
2017 ppc_emit_log_not (void)
2019 EMIT_ASM ("or 4, 3, 4 \n"
2025 /* TOP = stack[--sp] & TOP */
2028 ppc_emit_bit_and (void)
2030 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2031 "lwz " TMP_SECOND
", 4(30) \n"
2036 /* TOP = stack[--sp] | TOP */
2039 ppc_emit_bit_or (void)
2041 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2042 "lwz " TMP_SECOND
", 4(30) \n"
2047 /* TOP = stack[--sp] ^ TOP */
2050 ppc_emit_bit_xor (void)
2052 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2053 "lwz " TMP_SECOND
", 4(30) \n"
2059 i.e., TOP = ~(TOP | TOP) */
2062 ppc_emit_bit_not (void)
2064 EMIT_ASM ("nor 3, 3, 3 \n"
2068 /* TOP = stack[--sp] == TOP */
2071 ppc_emit_equal (void)
2073 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2074 "lwz " TMP_SECOND
", 4(30) \n"
2083 /* TOP = stack[--sp] < TOP
2084 (Signed comparison) */
2087 ppc_emit_less_signed (void)
2089 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2090 "lwz " TMP_SECOND
", 4(30) \n"
2093 /* CR6 bit 0 = low less and high equal */
2094 "crand 6*4+0, 6*4+0, 7*4+2\n"
2095 /* CR7 bit 0 = (low less and high equal) or high less */
2096 "cror 7*4+0, 7*4+0, 6*4+0\n"
2098 "rlwinm 4, 4, 29, 31, 31 \n"
2102 /* TOP = stack[--sp] < TOP
2103 (Unsigned comparison) */
2106 ppc_emit_less_unsigned (void)
2108 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2109 "lwz " TMP_SECOND
", 4(30) \n"
2112 /* CR6 bit 0 = low less and high equal */
2113 "crand 6*4+0, 6*4+0, 7*4+2\n"
2114 /* CR7 bit 0 = (low less and high equal) or high less */
2115 "cror 7*4+0, 7*4+0, 6*4+0\n"
2117 "rlwinm 4, 4, 29, 31, 31 \n"
2121 /* Access the memory address in TOP in size of SIZE.
2122 Zero-extend the read value. */
2125 ppc_emit_ref (int size
)
2130 EMIT_ASM ("lbz 4, 0(4)\n"
2134 EMIT_ASM ("lhz 4, 0(4)\n"
2138 EMIT_ASM ("lwz 4, 0(4)\n"
2142 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2143 EMIT_ASM ("lwz 3, 4(4)\n"
2146 EMIT_ASM ("lwz 3, 0(4)\n"
2155 ppc_emit_const (LONGEST num
)
2160 p
+= gen_limm (p
, 3, num
>> 32 & 0xffffffff, 0);
2161 p
+= gen_limm (p
, 4, num
& 0xffffffff, 0);
2163 emit_insns (buf
, p
- buf
);
2164 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2167 /* Set TOP to the value of register REG by calling get_raw_reg function
2168 with two argument, collected buffer and register number. */
2171 ppc_emit_reg (int reg
)
2176 /* fctx->regs is passed in r3 and then saved in -16(31). */
2177 p
+= GEN_LWZ (p
, 3, 31, -16);
2178 p
+= GEN_LI (p
, 4, reg
); /* li r4, reg */
2179 p
+= gen_call (p
, get_raw_reg_func_addr (), 0, 0);
2181 emit_insns (buf
, p
- buf
);
2182 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2184 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2186 EMIT_ASM ("mr 5, 4\n"
2192 /* TOP = stack[--sp] */
2197 EMIT_ASM ("lwzu " TOP_FIRST
", 8(30) \n"
2198 "lwz " TOP_SECOND
", 4(30) \n");
2201 /* stack[sp++] = TOP
2203 Because we may use up bytecode stack, expand 8 doublewords more
2207 ppc_emit_stack_flush (void)
2209 /* Make sure bytecode stack is big enough before push.
2210 Otherwise, expand 64-byte more. */
2212 EMIT_ASM (" stw " TOP_FIRST
", 0(30) \n"
2213 " stw " TOP_SECOND
", 4(30)\n"
2214 " addi 5, 30, -(8 + 8) \n"
2217 " stwu 31, -64(1) \n"
2218 "1:addi 30, 30, -8 \n");
2221 /* Swap TOP and stack[sp-1] */
2224 ppc_emit_swap (void)
2226 EMIT_ASM ("lwz " TMP_FIRST
", 8(30) \n"
2227 "lwz " TMP_SECOND
", 12(30) \n"
2228 "stw " TOP_FIRST
", 8(30) \n"
2229 "stw " TOP_SECOND
", 12(30) \n"
2234 /* Discard N elements in the stack. Also used for ppc64. */
2237 ppc_emit_stack_adjust (int n
)
2249 p
+= GEN_ADDI (p
, 30, 30, n
);
2251 emit_insns (buf
, p
- buf
);
2252 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2255 /* Call function FN. */
2258 ppc_emit_call (CORE_ADDR fn
)
2263 p
+= gen_call (p
, fn
, 0, 0);
2265 emit_insns (buf
, p
- buf
);
2266 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2269 /* FN's prototype is `LONGEST(*fn)(int)'.
2274 ppc_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2279 /* Setup argument. arg1 is a 16-bit value. */
2280 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2281 p
+= gen_call (p
, fn
, 0, 0);
2283 emit_insns (buf
, p
- buf
);
2284 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2286 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2288 EMIT_ASM ("mr 5, 4\n"
2294 /* FN's prototype is `void(*fn)(int,LONGEST)'.
2297 TOP should be preserved/restored before/after the call. */
2300 ppc_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2305 /* Save TOP. 0(30) is next-empty. */
2306 p
+= GEN_STW (p
, 3, 30, 0);
2307 p
+= GEN_STW (p
, 4, 30, 4);
2309 /* Setup argument. arg1 is a 16-bit value. */
2310 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2312 p
+= GEN_MR (p
, 5, 4);
2313 p
+= GEN_MR (p
, 6, 3);
2317 p
+= GEN_MR (p
, 5, 3);
2318 p
+= GEN_MR (p
, 6, 4);
2320 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2321 p
+= gen_call (p
, fn
, 0, 0);
2324 p
+= GEN_LWZ (p
, 3, 30, 0);
2325 p
+= GEN_LWZ (p
, 4, 30, 4);
2327 emit_insns (buf
, p
- buf
);
2328 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2331 /* Note in the following goto ops:
2333 When emitting goto, the target address is later relocated by
2334 write_goto_address. OFFSET_P is the offset of the branch instruction
2335 in the code sequence, and SIZE_P is how to relocate the instruction,
2336 recognized by ppc_write_goto_address. In current implementation,
2337 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2340 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2343 ppc_emit_if_goto (int *offset_p
, int *size_p
)
2345 EMIT_ASM ("or. 3, 3, 4 \n"
2346 "lwzu " TOP_FIRST
", 8(30) \n"
2347 "lwz " TOP_SECOND
", 4(30) \n"
2356 /* Unconditional goto. Also used for ppc64. */
2359 ppc_emit_goto (int *offset_p
, int *size_p
)
2361 EMIT_ASM ("1:b 1b");
2369 /* Goto if stack[--sp] == TOP */
2372 ppc_emit_eq_goto (int *offset_p
, int *size_p
)
2374 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2375 "lwz " TMP_SECOND
", 4(30) \n"
2379 "lwzu " TOP_FIRST
", 8(30) \n"
2380 "lwz " TOP_SECOND
", 4(30) \n"
2389 /* Goto if stack[--sp] != TOP */
2392 ppc_emit_ne_goto (int *offset_p
, int *size_p
)
2394 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2395 "lwz " TMP_SECOND
", 4(30) \n"
2399 "lwzu " TOP_FIRST
", 8(30) \n"
2400 "lwz " TOP_SECOND
", 4(30) \n"
2409 /* Goto if stack[--sp] < TOP */
2412 ppc_emit_lt_goto (int *offset_p
, int *size_p
)
2414 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2415 "lwz " TMP_SECOND
", 4(30) \n"
2418 /* CR6 bit 0 = low less and high equal */
2419 "crand 6*4+0, 6*4+0, 7*4+2\n"
2420 /* CR7 bit 0 = (low less and high equal) or high less */
2421 "cror 7*4+0, 7*4+0, 6*4+0\n"
2422 "lwzu " TOP_FIRST
", 8(30) \n"
2423 "lwz " TOP_SECOND
", 4(30)\n"
2432 /* Goto if stack[--sp] <= TOP */
2435 ppc_emit_le_goto (int *offset_p
, int *size_p
)
2437 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2438 "lwz " TMP_SECOND
", 4(30) \n"
2441 /* CR6 bit 0 = low less/equal and high equal */
2442 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2443 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2444 "cror 7*4+0, 7*4+0, 6*4+0\n"
2445 "lwzu " TOP_FIRST
", 8(30) \n"
2446 "lwz " TOP_SECOND
", 4(30)\n"
2455 /* Goto if stack[--sp] > TOP */
2458 ppc_emit_gt_goto (int *offset_p
, int *size_p
)
2460 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2461 "lwz " TMP_SECOND
", 4(30) \n"
2464 /* CR6 bit 0 = low greater and high equal */
2465 "crand 6*4+0, 6*4+1, 7*4+2\n"
2466 /* CR7 bit 0 = (low greater and high equal) or high greater */
2467 "cror 7*4+0, 7*4+1, 6*4+0\n"
2468 "lwzu " TOP_FIRST
", 8(30) \n"
2469 "lwz " TOP_SECOND
", 4(30)\n"
2478 /* Goto if stack[--sp] >= TOP */
2481 ppc_emit_ge_goto (int *offset_p
, int *size_p
)
2483 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2484 "lwz " TMP_SECOND
", 4(30) \n"
2487 /* CR6 bit 0 = low ge and high equal */
2488 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2489 /* CR7 bit 0 = (low ge and high equal) or high greater */
2490 "cror 7*4+0, 7*4+1, 6*4+0\n"
2491 "lwzu " TOP_FIRST
", 8(30)\n"
2492 "lwz " TOP_SECOND
", 4(30)\n"
2501 /* Relocate previous emitted branch instruction. FROM is the address
2502 of the branch instruction, TO is the goto target address, and SIZE
2503 if the value we set by *SIZE_P before. Currently, it is either
2504 24 or 14 of branch and conditional-branch instruction.
2505 Also used for ppc64. */
2508 ppc_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2510 long rel
= to
- from
;
2514 read_inferior_memory (from
, (unsigned char *) &insn
, 4);
2515 opcd
= (insn
>> 26) & 0x3f;
2521 || (rel
>= (1 << 15) || rel
< -(1 << 15)))
2523 insn
= (insn
& ~0xfffc) | (rel
& 0xfffc);
2527 || (rel
>= (1 << 25) || rel
< -(1 << 25)))
2529 insn
= (insn
& ~0x3fffffc) | (rel
& 0x3fffffc);
2536 target_write_memory (from
, (unsigned char *) &insn
, 4);
2539 /* Table of emit ops for 32-bit. */
2541 static struct emit_ops ppc_emit_ops_impl
=
2549 ppc_emit_rsh_signed
,
2550 ppc_emit_rsh_unsigned
,
2558 ppc_emit_less_signed
,
2559 ppc_emit_less_unsigned
,
2563 ppc_write_goto_address
,
2568 ppc_emit_stack_flush
,
2571 ppc_emit_stack_adjust
,
2572 ppc_emit_int_call_1
,
2573 ppc_emit_void_call_2
,
2582 #ifdef __powerpc64__
2586 Bytecode execution stack frame - 64-bit
2588 | LR save area (SP + 16)
2589 | CR save area (SP + 8)
2590 SP' -> +- Back chain (SP + 0)
2591 | Save r31 for access saved arguments
2592 | Save r30 for bytecode stack pointer
2593 | Save r4 for incoming argument *value
2594 | Save r3 for incoming argument regs
2595 r30 -> +- Bytecode execution stack
2597 | 64-byte (8 doublewords) at initial.
2598 | Expand stack as needed.
2601 | Some padding for minimum stack frame.
2603 SP +- Back-chain (SP')
2606 = 112 + (4 * 8) + 64
2609 r30 is the stack-pointer for bytecode machine.
2610 It should point to next-empty, so we can use LDU for pop.
2611 r3 is used for cache of TOP value.
2612 It was the first argument, pointer to regs.
2613 r4 is the second argument, pointer to the result.
2614 We should set *result = TOP after leaving this function.
2617 * To restore stack at epilogue
2619 * To check stack is big enough for bytecode execution.
2620 => r30 - 8 > SP + 112
2621 * To return execution result.
2626 /* Emit prologue in inferior memory. See above comments. */
2629 ppc64v1_emit_prologue (void)
2631 /* On ELFv1, function pointers really point to function descriptor,
2632 so emit one here. We don't care about contents of words 1 and 2,
2633 so let them just overlap out code. */
2634 uint64_t opd
= current_insn_ptr
+ 8;
2637 /* Mind the strict aliasing rules. */
2638 memcpy (buf
, &opd
, sizeof buf
);
2640 EMIT_ASM (/* Save return address. */
2643 /* Save r30 and incoming arguments. */
2648 /* Point r31 to current r1 for access arguments. */
2650 /* Adjust SP. 208 is the initial frame size. */
2651 "stdu 1, -208(1) \n"
2652 /* Set r30 to pointing stack-top. */
2653 "addi 30, 1, 168 \n"
2654 /* Initial r3/TOP to 0. */
2658 /* Emit prologue in inferior memory. See above comments. */
2661 ppc64v2_emit_prologue (void)
2663 EMIT_ASM (/* Save return address. */
2666 /* Save r30 and incoming arguments. */
2671 /* Point r31 to current r1 for access arguments. */
2673 /* Adjust SP. 208 is the initial frame size. */
2674 "stdu 1, -208(1) \n"
2675 /* Set r30 to pointing stack-top. */
2676 "addi 30, 1, 168 \n"
2677 /* Initial r3/TOP to 0. */
2681 /* Emit epilogue in inferior memory. See above comments. */
2684 ppc64_emit_epilogue (void)
2686 EMIT_ASM (/* Restore SP. */
2691 /* Restore registers. */
2696 /* Return 0 for no-error. */
2702 /* TOP = stack[--sp] + TOP */
2705 ppc64_emit_add (void)
2707 EMIT_ASM ("ldu 4, 8(30) \n"
2711 /* TOP = stack[--sp] - TOP */
2714 ppc64_emit_sub (void)
2716 EMIT_ASM ("ldu 4, 8(30) \n"
2720 /* TOP = stack[--sp] * TOP */
2723 ppc64_emit_mul (void)
2725 EMIT_ASM ("ldu 4, 8(30) \n"
2726 "mulld 3, 4, 3 \n");
2729 /* TOP = stack[--sp] << TOP */
2732 ppc64_emit_lsh (void)
2734 EMIT_ASM ("ldu 4, 8(30) \n"
2738 /* Top = stack[--sp] >> TOP
2739 (Arithmetic shift right) */
2742 ppc64_emit_rsh_signed (void)
2744 EMIT_ASM ("ldu 4, 8(30) \n"
2748 /* Top = stack[--sp] >> TOP
2749 (Logical shift right) */
2752 ppc64_emit_rsh_unsigned (void)
2754 EMIT_ASM ("ldu 4, 8(30) \n"
2758 /* Emit code for signed-extension specified by ARG. */
2761 ppc64_emit_ext (int arg
)
2766 EMIT_ASM ("extsb 3, 3");
2769 EMIT_ASM ("extsh 3, 3");
2772 EMIT_ASM ("extsw 3, 3");
2779 /* Emit code for zero-extension specified by ARG. */
2782 ppc64_emit_zero_ext (int arg
)
2787 EMIT_ASM ("rldicl 3,3,0,56");
2790 EMIT_ASM ("rldicl 3,3,0,48");
2793 EMIT_ASM ("rldicl 3,3,0,32");
2801 i.e., TOP = (TOP == 0) ? 1 : 0; */
2804 ppc64_emit_log_not (void)
2806 EMIT_ASM ("cntlzd 3, 3 \n"
2810 /* TOP = stack[--sp] & TOP */
2813 ppc64_emit_bit_and (void)
2815 EMIT_ASM ("ldu 4, 8(30) \n"
2819 /* TOP = stack[--sp] | TOP */
2822 ppc64_emit_bit_or (void)
2824 EMIT_ASM ("ldu 4, 8(30) \n"
2828 /* TOP = stack[--sp] ^ TOP */
2831 ppc64_emit_bit_xor (void)
2833 EMIT_ASM ("ldu 4, 8(30) \n"
2838 i.e., TOP = ~(TOP | TOP) */
2841 ppc64_emit_bit_not (void)
2843 EMIT_ASM ("nor 3, 3, 3 \n");
2846 /* TOP = stack[--sp] == TOP */
2849 ppc64_emit_equal (void)
2851 EMIT_ASM ("ldu 4, 8(30) \n"
2857 /* TOP = stack[--sp] < TOP
2858 (Signed comparison) */
2861 ppc64_emit_less_signed (void)
2863 EMIT_ASM ("ldu 4, 8(30) \n"
2866 "rlwinm 3, 3, 29, 31, 31 \n");
2869 /* TOP = stack[--sp] < TOP
2870 (Unsigned comparison) */
2873 ppc64_emit_less_unsigned (void)
2875 EMIT_ASM ("ldu 4, 8(30) \n"
2878 "rlwinm 3, 3, 29, 31, 31 \n");
2881 /* Access the memory address in TOP in size of SIZE.
2882 Zero-extend the read value. */
2885 ppc64_emit_ref (int size
)
2890 EMIT_ASM ("lbz 3, 0(3)");
2893 EMIT_ASM ("lhz 3, 0(3)");
2896 EMIT_ASM ("lwz 3, 0(3)");
2899 EMIT_ASM ("ld 3, 0(3)");
2907 ppc64_emit_const (LONGEST num
)
2912 p
+= gen_limm (p
, 3, num
, 1);
2914 emit_insns (buf
, p
- buf
);
2915 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2918 /* Set TOP to the value of register REG by calling get_raw_reg function
2919 with two argument, collected buffer and register number. */
2922 ppc64v1_emit_reg (int reg
)
2927 /* fctx->regs is passed in r3 and then saved in 176(1). */
2928 p
+= GEN_LD (p
, 3, 31, -32);
2929 p
+= GEN_LI (p
, 4, reg
);
2930 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2931 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 1);
2932 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2934 emit_insns (buf
, p
- buf
);
2935 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2938 /* Likewise, for ELFv2. */
2941 ppc64v2_emit_reg (int reg
)
2946 /* fctx->regs is passed in r3 and then saved in 176(1). */
2947 p
+= GEN_LD (p
, 3, 31, -32);
2948 p
+= GEN_LI (p
, 4, reg
);
2949 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
2950 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 0);
2951 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
2953 emit_insns (buf
, p
- buf
);
2954 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2957 /* TOP = stack[--sp] */
2960 ppc64_emit_pop (void)
2962 EMIT_ASM ("ldu 3, 8(30)");
2965 /* stack[sp++] = TOP
2967 Because we may use up bytecode stack, expand 8 doublewords more
2971 ppc64_emit_stack_flush (void)
2973 /* Make sure bytecode stack is big enough before push.
2974 Otherwise, expand 64-byte more. */
2976 EMIT_ASM (" std 3, 0(30) \n"
2977 " addi 4, 30, -(112 + 8) \n"
2980 " stdu 31, -64(1) \n"
2981 "1:addi 30, 30, -8 \n");
2984 /* Swap TOP and stack[sp-1] */
2987 ppc64_emit_swap (void)
2989 EMIT_ASM ("ld 4, 8(30) \n"
2994 /* Call function FN - ELFv1. */
2997 ppc64v1_emit_call (CORE_ADDR fn
)
3002 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3003 p
+= gen_call (p
, fn
, 1, 1);
3004 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3006 emit_insns (buf
, p
- buf
);
3007 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3010 /* Call function FN - ELFv2. */
3013 ppc64v2_emit_call (CORE_ADDR fn
)
3018 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3019 p
+= gen_call (p
, fn
, 1, 0);
3020 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3022 emit_insns (buf
, p
- buf
);
3023 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3026 /* FN's prototype is `LONGEST(*fn)(int)'.
3031 ppc64v1_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
3036 /* Setup argument. arg1 is a 16-bit value. */
3037 p
+= gen_limm (p
, 3, arg1
, 1);
3038 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3039 p
+= gen_call (p
, fn
, 1, 1);
3040 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3042 emit_insns (buf
, p
- buf
);
3043 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3046 /* Likewise for ELFv2. */
3049 ppc64v2_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
3054 /* Setup argument. arg1 is a 16-bit value. */
3055 p
+= gen_limm (p
, 3, arg1
, 1);
3056 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3057 p
+= gen_call (p
, fn
, 1, 0);
3058 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3060 emit_insns (buf
, p
- buf
);
3061 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3064 /* FN's prototype is `void(*fn)(int,LONGEST)'.
3067 TOP should be preserved/restored before/after the call. */
3070 ppc64v1_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3075 /* Save TOP. 0(30) is next-empty. */
3076 p
+= GEN_STD (p
, 3, 30, 0);
3078 /* Setup argument. arg1 is a 16-bit value. */
3079 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
3080 p
+= gen_limm (p
, 3, arg1
, 1);
3081 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3082 p
+= gen_call (p
, fn
, 1, 1);
3083 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3086 p
+= GEN_LD (p
, 3, 30, 0);
3088 emit_insns (buf
, p
- buf
);
3089 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3092 /* Likewise for ELFv2. */
3095 ppc64v2_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3100 /* Save TOP. 0(30) is next-empty. */
3101 p
+= GEN_STD (p
, 3, 30, 0);
3103 /* Setup argument. arg1 is a 16-bit value. */
3104 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
3105 p
+= gen_limm (p
, 3, arg1
, 1);
3106 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3107 p
+= gen_call (p
, fn
, 1, 0);
3108 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3111 p
+= GEN_LD (p
, 3, 30, 0);
3113 emit_insns (buf
, p
- buf
);
3114 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3117 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
3120 ppc64_emit_if_goto (int *offset_p
, int *size_p
)
3122 EMIT_ASM ("cmpdi 7, 3, 0 \n"
3132 /* Goto if stack[--sp] == TOP */
3135 ppc64_emit_eq_goto (int *offset_p
, int *size_p
)
3137 EMIT_ASM ("ldu 4, 8(30) \n"
3148 /* Goto if stack[--sp] != TOP */
3151 ppc64_emit_ne_goto (int *offset_p
, int *size_p
)
3153 EMIT_ASM ("ldu 4, 8(30) \n"
3164 /* Goto if stack[--sp] < TOP */
3167 ppc64_emit_lt_goto (int *offset_p
, int *size_p
)
3169 EMIT_ASM ("ldu 4, 8(30) \n"
3180 /* Goto if stack[--sp] <= TOP */
3183 ppc64_emit_le_goto (int *offset_p
, int *size_p
)
3185 EMIT_ASM ("ldu 4, 8(30) \n"
3196 /* Goto if stack[--sp] > TOP */
3199 ppc64_emit_gt_goto (int *offset_p
, int *size_p
)
3201 EMIT_ASM ("ldu 4, 8(30) \n"
3212 /* Goto if stack[--sp] >= TOP */
3215 ppc64_emit_ge_goto (int *offset_p
, int *size_p
)
3217 EMIT_ASM ("ldu 4, 8(30) \n"
3228 /* Table of emit ops for 64-bit ELFv1. */
3230 static struct emit_ops ppc64v1_emit_ops_impl
=
3232 ppc64v1_emit_prologue
,
3233 ppc64_emit_epilogue
,
3238 ppc64_emit_rsh_signed
,
3239 ppc64_emit_rsh_unsigned
,
3247 ppc64_emit_less_signed
,
3248 ppc64_emit_less_unsigned
,
3252 ppc_write_goto_address
,
3257 ppc64_emit_stack_flush
,
3258 ppc64_emit_zero_ext
,
3260 ppc_emit_stack_adjust
,
3261 ppc64v1_emit_int_call_1
,
3262 ppc64v1_emit_void_call_2
,
3271 /* Table of emit ops for 64-bit ELFv2. */
3273 static struct emit_ops ppc64v2_emit_ops_impl
=
3275 ppc64v2_emit_prologue
,
3276 ppc64_emit_epilogue
,
3281 ppc64_emit_rsh_signed
,
3282 ppc64_emit_rsh_unsigned
,
3290 ppc64_emit_less_signed
,
3291 ppc64_emit_less_unsigned
,
3295 ppc_write_goto_address
,
3300 ppc64_emit_stack_flush
,
3301 ppc64_emit_zero_ext
,
3303 ppc_emit_stack_adjust
,
3304 ppc64v2_emit_int_call_1
,
3305 ppc64v2_emit_void_call_2
,
3316 /* Implementation of linux_target_ops method "emit_ops". */
3318 static struct emit_ops
*
3321 #ifdef __powerpc64__
3322 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3324 if (register_size (regcache
->tdesc
, 0) == 8)
3326 if (is_elfv2_inferior ())
3327 return &ppc64v2_emit_ops_impl
;
3329 return &ppc64v1_emit_ops_impl
;
3332 return &ppc_emit_ops_impl
;
3335 /* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3338 ppc_get_ipa_tdesc_idx (void)
3340 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3341 const struct target_desc
*tdesc
= regcache
->tdesc
;
3343 #ifdef __powerpc64__
3344 if (tdesc
== tdesc_powerpc_64l
)
3345 return PPC_TDESC_BASE
;
3346 if (tdesc
== tdesc_powerpc_altivec64l
)
3347 return PPC_TDESC_ALTIVEC
;
3348 if (tdesc
== tdesc_powerpc_vsx64l
)
3349 return PPC_TDESC_VSX
;
3350 if (tdesc
== tdesc_powerpc_isa205_64l
)
3351 return PPC_TDESC_ISA205
;
3352 if (tdesc
== tdesc_powerpc_isa205_altivec64l
)
3353 return PPC_TDESC_ISA205_ALTIVEC
;
3354 if (tdesc
== tdesc_powerpc_isa205_vsx64l
)
3355 return PPC_TDESC_ISA205_VSX
;
3356 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx64l
)
3357 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3358 if (tdesc
== tdesc_powerpc_isa207_vsx64l
)
3359 return PPC_TDESC_ISA207_VSX
;
3360 if (tdesc
== tdesc_powerpc_isa207_htm_vsx64l
)
3361 return PPC_TDESC_ISA207_HTM_VSX
;
3364 if (tdesc
== tdesc_powerpc_32l
)
3365 return PPC_TDESC_BASE
;
3366 if (tdesc
== tdesc_powerpc_altivec32l
)
3367 return PPC_TDESC_ALTIVEC
;
3368 if (tdesc
== tdesc_powerpc_vsx32l
)
3369 return PPC_TDESC_VSX
;
3370 if (tdesc
== tdesc_powerpc_isa205_32l
)
3371 return PPC_TDESC_ISA205
;
3372 if (tdesc
== tdesc_powerpc_isa205_altivec32l
)
3373 return PPC_TDESC_ISA205_ALTIVEC
;
3374 if (tdesc
== tdesc_powerpc_isa205_vsx32l
)
3375 return PPC_TDESC_ISA205_VSX
;
3376 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx32l
)
3377 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3378 if (tdesc
== tdesc_powerpc_isa207_vsx32l
)
3379 return PPC_TDESC_ISA207_VSX
;
3380 if (tdesc
== tdesc_powerpc_isa207_htm_vsx32l
)
3381 return PPC_TDESC_ISA207_HTM_VSX
;
3382 if (tdesc
== tdesc_powerpc_e500l
)
3383 return PPC_TDESC_E500
;
3388 struct linux_target_ops the_low_target
= {
3390 ppc_cannot_fetch_register
,
3391 ppc_cannot_store_register
,
3392 NULL
, /* fetch_register */
3395 NULL
, /* breakpoint_kind_from_pc */
3396 ppc_sw_breakpoint_from_kind
,
3400 ppc_supports_z_point_type
,
3405 ppc_collect_ptrace_register
,
3406 ppc_supply_ptrace_register
,
3407 NULL
, /* siginfo_fixup */
3408 NULL
, /* new_process */
3409 NULL
, /* delete_process */
3410 NULL
, /* new_thread */
3411 NULL
, /* delete_thread */
3412 NULL
, /* new_fork */
3413 NULL
, /* prepare_to_resume */
3414 NULL
, /* process_qsupported */
3415 ppc_supports_tracepoints
,
3416 ppc_get_thread_area
,
3417 ppc_install_fast_tracepoint_jump_pad
,
3419 ppc_get_min_fast_tracepoint_insn_len
,
3420 NULL
, /* supports_range_stepping */
3421 NULL
, /* breakpoint_kind_from_current_state */
3422 ppc_supports_hardware_single_step
,
3423 NULL
, /* get_syscall_trapinfo */
3424 ppc_get_ipa_tdesc_idx
,
3427 /* The linux target ops object. */
3429 linux_process_target
*the_linux_target
= &the_ppc_target
;
3432 initialize_low_arch (void)
3434 /* Initialize the Linux target descriptions. */
3436 init_registers_powerpc_32l ();
3437 init_registers_powerpc_altivec32l ();
3438 init_registers_powerpc_vsx32l ();
3439 init_registers_powerpc_isa205_32l ();
3440 init_registers_powerpc_isa205_altivec32l ();
3441 init_registers_powerpc_isa205_vsx32l ();
3442 init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
3443 init_registers_powerpc_isa207_vsx32l ();
3444 init_registers_powerpc_isa207_htm_vsx32l ();
3445 init_registers_powerpc_e500l ();
3447 init_registers_powerpc_64l ();
3448 init_registers_powerpc_altivec64l ();
3449 init_registers_powerpc_vsx64l ();
3450 init_registers_powerpc_isa205_64l ();
3451 init_registers_powerpc_isa205_altivec64l ();
3452 init_registers_powerpc_isa205_vsx64l ();
3453 init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
3454 init_registers_powerpc_isa207_vsx64l ();
3455 init_registers_powerpc_isa207_htm_vsx64l ();
3458 initialize_regsets_info (&ppc_regsets_info
);