1 /* GNU/Linux/PowerPC specific low level interface, for the remote server for
3 Copyright (C) 1995-2020 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "linux-low.h"
23 #include "elf/common.h"
26 #include <asm/ptrace.h>
28 #include "arch/ppc-linux-common.h"
29 #include "arch/ppc-linux-tdesc.h"
30 #include "nat/ppc-linux.h"
31 #include "nat/linux-ptrace.h"
32 #include "linux-ppc-tdesc-init.h"
34 #include "tracepoint.h"
36 #define PPC_FIELD(value, from, len) \
37 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
38 #define PPC_SEXT(v, bs) \
39 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
40 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
41 - ((CORE_ADDR) 1 << ((bs) - 1)))
42 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
43 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
44 #define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
45 #define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
47 /* Linux target op definitions for the PowerPC architecture. */
49 class ppc_target
: public linux_process_target
55 /* The singleton target ops object. */
57 static ppc_target the_ppc_target
;
59 /* Holds the AT_HWCAP auxv entry. */
61 static unsigned long ppc_hwcap
;
63 /* Holds the AT_HWCAP2 auxv entry. */
65 static unsigned long ppc_hwcap2
;
68 #define ppc_num_regs 73
71 /* We use a constant for FPSCR instead of PT_FPSCR, because
72 many shipped PPC64 kernels had the wrong value in ptrace.h. */
73 static int ppc_regmap
[] =
74 {PT_R0
* 8, PT_R1
* 8, PT_R2
* 8, PT_R3
* 8,
75 PT_R4
* 8, PT_R5
* 8, PT_R6
* 8, PT_R7
* 8,
76 PT_R8
* 8, PT_R9
* 8, PT_R10
* 8, PT_R11
* 8,
77 PT_R12
* 8, PT_R13
* 8, PT_R14
* 8, PT_R15
* 8,
78 PT_R16
* 8, PT_R17
* 8, PT_R18
* 8, PT_R19
* 8,
79 PT_R20
* 8, PT_R21
* 8, PT_R22
* 8, PT_R23
* 8,
80 PT_R24
* 8, PT_R25
* 8, PT_R26
* 8, PT_R27
* 8,
81 PT_R28
* 8, PT_R29
* 8, PT_R30
* 8, PT_R31
* 8,
82 PT_FPR0
*8, PT_FPR0
*8 + 8, PT_FPR0
*8+16, PT_FPR0
*8+24,
83 PT_FPR0
*8+32, PT_FPR0
*8+40, PT_FPR0
*8+48, PT_FPR0
*8+56,
84 PT_FPR0
*8+64, PT_FPR0
*8+72, PT_FPR0
*8+80, PT_FPR0
*8+88,
85 PT_FPR0
*8+96, PT_FPR0
*8+104, PT_FPR0
*8+112, PT_FPR0
*8+120,
86 PT_FPR0
*8+128, PT_FPR0
*8+136, PT_FPR0
*8+144, PT_FPR0
*8+152,
87 PT_FPR0
*8+160, PT_FPR0
*8+168, PT_FPR0
*8+176, PT_FPR0
*8+184,
88 PT_FPR0
*8+192, PT_FPR0
*8+200, PT_FPR0
*8+208, PT_FPR0
*8+216,
89 PT_FPR0
*8+224, PT_FPR0
*8+232, PT_FPR0
*8+240, PT_FPR0
*8+248,
90 PT_NIP
* 8, PT_MSR
* 8, PT_CCR
* 8, PT_LNK
* 8,
91 PT_CTR
* 8, PT_XER
* 8, PT_FPR0
*8 + 256,
92 PT_ORIG_R3
* 8, PT_TRAP
* 8 };
94 /* Currently, don't check/send MQ. */
95 static int ppc_regmap
[] =
96 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
97 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
98 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
99 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
100 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
101 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
102 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
103 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
104 PT_FPR0
*4, PT_FPR0
*4 + 8, PT_FPR0
*4+16, PT_FPR0
*4+24,
105 PT_FPR0
*4+32, PT_FPR0
*4+40, PT_FPR0
*4+48, PT_FPR0
*4+56,
106 PT_FPR0
*4+64, PT_FPR0
*4+72, PT_FPR0
*4+80, PT_FPR0
*4+88,
107 PT_FPR0
*4+96, PT_FPR0
*4+104, PT_FPR0
*4+112, PT_FPR0
*4+120,
108 PT_FPR0
*4+128, PT_FPR0
*4+136, PT_FPR0
*4+144, PT_FPR0
*4+152,
109 PT_FPR0
*4+160, PT_FPR0
*4+168, PT_FPR0
*4+176, PT_FPR0
*4+184,
110 PT_FPR0
*4+192, PT_FPR0
*4+200, PT_FPR0
*4+208, PT_FPR0
*4+216,
111 PT_FPR0
*4+224, PT_FPR0
*4+232, PT_FPR0
*4+240, PT_FPR0
*4+248,
112 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
113 PT_CTR
* 4, PT_XER
* 4, PT_FPSCR
* 4,
114 PT_ORIG_R3
* 4, PT_TRAP
* 4
117 static int ppc_regmap_e500
[] =
118 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
119 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
120 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
121 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
122 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
123 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
124 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
125 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
134 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
135 PT_CTR
* 4, PT_XER
* 4, -1,
136 PT_ORIG_R3
* 4, PT_TRAP
* 4
140 /* Check whether the kernel provides a register set with number
141 REGSET_ID of size REGSETSIZE for process/thread TID. */
144 ppc_check_regset (int tid
, int regset_id
, int regsetsize
)
146 void *buf
= alloca (regsetsize
);
150 iov
.iov_len
= regsetsize
;
152 if (ptrace (PTRACE_GETREGSET
, tid
, regset_id
, &iov
) >= 0
159 ppc_cannot_store_register (int regno
)
161 const struct target_desc
*tdesc
= current_process ()->tdesc
;
163 #ifndef __powerpc64__
164 /* Some kernels do not allow us to store fpscr. */
165 if (!(ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
166 && regno
== find_regno (tdesc
, "fpscr"))
170 /* Some kernels do not allow us to store orig_r3 or trap. */
171 if (regno
== find_regno (tdesc
, "orig_r3")
172 || regno
== find_regno (tdesc
, "trap"))
179 ppc_cannot_fetch_register (int regno
)
185 ppc_collect_ptrace_register (struct regcache
*regcache
, int regno
, char *buf
)
187 memset (buf
, 0, sizeof (long));
189 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
191 /* Little-endian values always sit at the left end of the buffer. */
192 collect_register (regcache
, regno
, buf
);
194 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
196 /* Big-endian values sit at the right end of the buffer. In case of
197 registers whose sizes are smaller than sizeof (long), we must use a
198 padding to access them correctly. */
199 int size
= register_size (regcache
->tdesc
, regno
);
201 if (size
< sizeof (long))
202 collect_register (regcache
, regno
, buf
+ sizeof (long) - size
);
204 collect_register (regcache
, regno
, buf
);
207 perror_with_name ("Unexpected byte order");
211 ppc_supply_ptrace_register (struct regcache
*regcache
,
212 int regno
, const char *buf
)
214 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
216 /* Little-endian values always sit at the left end of the buffer. */
217 supply_register (regcache
, regno
, buf
);
219 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
221 /* Big-endian values sit at the right end of the buffer. In case of
222 registers whose sizes are smaller than sizeof (long), we must use a
223 padding to access them correctly. */
224 int size
= register_size (regcache
->tdesc
, regno
);
226 if (size
< sizeof (long))
227 supply_register (regcache
, regno
, buf
+ sizeof (long) - size
);
229 supply_register (regcache
, regno
, buf
);
232 perror_with_name ("Unexpected byte order");
236 ppc_get_pc (struct regcache
*regcache
)
238 if (register_size (regcache
->tdesc
, 0) == 4)
241 collect_register_by_name (regcache
, "pc", &pc
);
242 return (CORE_ADDR
) pc
;
247 collect_register_by_name (regcache
, "pc", &pc
);
248 return (CORE_ADDR
) pc
;
253 ppc_set_pc (struct regcache
*regcache
, CORE_ADDR pc
)
255 if (register_size (regcache
->tdesc
, 0) == 4)
257 unsigned int newpc
= pc
;
258 supply_register_by_name (regcache
, "pc", &newpc
);
262 unsigned long newpc
= pc
;
263 supply_register_by_name (regcache
, "pc", &newpc
);
267 #ifndef __powerpc64__
268 static int ppc_regmap_adjusted
;
272 /* Correct in either endianness.
273 This instruction is "twge r2, r2", which GDB uses as a software
275 static const unsigned int ppc_breakpoint
= 0x7d821008;
276 #define ppc_breakpoint_len 4
278 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
280 static const gdb_byte
*
281 ppc_sw_breakpoint_from_kind (int kind
, int *size
)
283 *size
= ppc_breakpoint_len
;
284 return (const gdb_byte
*) &ppc_breakpoint
;
288 ppc_breakpoint_at (CORE_ADDR where
)
292 the_target
->read_memory (where
, (unsigned char *) &insn
, 4);
293 if (insn
== ppc_breakpoint
)
295 /* If necessary, recognize more trap instructions here. GDB only uses
301 /* Implement supports_z_point_type target-ops.
302 Returns true if type Z_TYPE breakpoint is supported.
304 Handling software breakpoint at server side, so tracepoints
305 and breakpoints can be inserted at the same location. */
308 ppc_supports_z_point_type (char z_type
)
315 case Z_PACKET_WRITE_WP
:
316 case Z_PACKET_ACCESS_WP
:
322 /* Implement insert_point target-ops.
323 Returns 0 on success, -1 on failure and 1 on unsupported. */
326 ppc_insert_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
327 int size
, struct raw_breakpoint
*bp
)
331 case raw_bkpt_type_sw
:
332 return insert_memory_breakpoint (bp
);
334 case raw_bkpt_type_hw
:
335 case raw_bkpt_type_write_wp
:
336 case raw_bkpt_type_access_wp
:
343 /* Implement remove_point target-ops.
344 Returns 0 on success, -1 on failure and 1 on unsupported. */
347 ppc_remove_point (enum raw_bkpt_type type
, CORE_ADDR addr
,
348 int size
, struct raw_breakpoint
*bp
)
352 case raw_bkpt_type_sw
:
353 return remove_memory_breakpoint (bp
);
355 case raw_bkpt_type_hw
:
356 case raw_bkpt_type_write_wp
:
357 case raw_bkpt_type_access_wp
:
364 /* Provide only a fill function for the general register set. ps_lgetregs
365 will use this for NPTL support. */
367 static void ppc_fill_gregset (struct regcache
*regcache
, void *buf
)
371 for (i
= 0; i
< 32; i
++)
372 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
374 for (i
= 64; i
< 70; i
++)
375 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
377 for (i
= 71; i
< 73; i
++)
378 ppc_collect_ptrace_register (regcache
, i
, (char *) buf
+ ppc_regmap
[i
]);
381 /* Program Priority Register regset fill function. */
384 ppc_fill_pprregset (struct regcache
*regcache
, void *buf
)
386 char *ppr
= (char *) buf
;
388 collect_register_by_name (regcache
, "ppr", ppr
);
391 /* Program Priority Register regset store function. */
394 ppc_store_pprregset (struct regcache
*regcache
, const void *buf
)
396 const char *ppr
= (const char *) buf
;
398 supply_register_by_name (regcache
, "ppr", ppr
);
401 /* Data Stream Control Register regset fill function. */
404 ppc_fill_dscrregset (struct regcache
*regcache
, void *buf
)
406 char *dscr
= (char *) buf
;
408 collect_register_by_name (regcache
, "dscr", dscr
);
411 /* Data Stream Control Register regset store function. */
414 ppc_store_dscrregset (struct regcache
*regcache
, const void *buf
)
416 const char *dscr
= (const char *) buf
;
418 supply_register_by_name (regcache
, "dscr", dscr
);
421 /* Target Address Register regset fill function. */
424 ppc_fill_tarregset (struct regcache
*regcache
, void *buf
)
426 char *tar
= (char *) buf
;
428 collect_register_by_name (regcache
, "tar", tar
);
431 /* Target Address Register regset store function. */
434 ppc_store_tarregset (struct regcache
*regcache
, const void *buf
)
436 const char *tar
= (const char *) buf
;
438 supply_register_by_name (regcache
, "tar", tar
);
441 /* Event-Based Branching regset store function. Unless the inferior
442 has a perf event open, ptrace can return in error when reading and
443 writing to the regset, with ENODATA. For reading, the registers
444 will correctly show as unavailable. For writing, gdbserver
445 currently only caches any register writes from P and G packets and
446 the stub always tries to write all the regsets when resuming the
447 inferior, which would result in frequent warnings. For this
448 reason, we don't define a fill function. This also means that the
449 client-side regcache will be dirty if the user tries to write to
450 the EBB registers. G packets that the client sends to write to
451 unrelated registers will also include data for EBB registers, even
452 if they are unavailable. */
455 ppc_store_ebbregset (struct regcache
*regcache
, const void *buf
)
457 const char *regset
= (const char *) buf
;
459 /* The order in the kernel regset is: EBBRR, EBBHR, BESCR. In the
460 .dat file is BESCR, EBBHR, EBBRR. */
461 supply_register_by_name (regcache
, "ebbrr", ®set
[0]);
462 supply_register_by_name (regcache
, "ebbhr", ®set
[8]);
463 supply_register_by_name (regcache
, "bescr", ®set
[16]);
466 /* Performance Monitoring Unit regset fill function. */
469 ppc_fill_pmuregset (struct regcache
*regcache
, void *buf
)
471 char *regset
= (char *) buf
;
473 /* The order in the kernel regset is SIAR, SDAR, SIER, MMCR2, MMCR0.
474 In the .dat file is MMCR0, MMCR2, SIAR, SDAR, SIER. */
475 collect_register_by_name (regcache
, "siar", ®set
[0]);
476 collect_register_by_name (regcache
, "sdar", ®set
[8]);
477 collect_register_by_name (regcache
, "sier", ®set
[16]);
478 collect_register_by_name (regcache
, "mmcr2", ®set
[24]);
479 collect_register_by_name (regcache
, "mmcr0", ®set
[32]);
482 /* Performance Monitoring Unit regset store function. */
485 ppc_store_pmuregset (struct regcache
*regcache
, const void *buf
)
487 const char *regset
= (const char *) buf
;
489 supply_register_by_name (regcache
, "siar", ®set
[0]);
490 supply_register_by_name (regcache
, "sdar", ®set
[8]);
491 supply_register_by_name (regcache
, "sier", ®set
[16]);
492 supply_register_by_name (regcache
, "mmcr2", ®set
[24]);
493 supply_register_by_name (regcache
, "mmcr0", ®set
[32]);
496 /* Hardware Transactional Memory special-purpose register regset fill
500 ppc_fill_tm_sprregset (struct regcache
*regcache
, void *buf
)
503 char *regset
= (char *) buf
;
505 base
= find_regno (regcache
->tdesc
, "tfhar");
506 for (i
= 0; i
< 3; i
++)
507 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
510 /* Hardware Transactional Memory special-purpose register regset store
514 ppc_store_tm_sprregset (struct regcache
*regcache
, const void *buf
)
517 const char *regset
= (const char *) buf
;
519 base
= find_regno (regcache
->tdesc
, "tfhar");
520 for (i
= 0; i
< 3; i
++)
521 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
524 /* For the same reasons as the EBB regset, none of the HTM
525 checkpointed regsets have a fill function. These registers are
526 only available if the inferior is in a transaction. */
528 /* Hardware Transactional Memory checkpointed general-purpose regset
532 ppc_store_tm_cgprregset (struct regcache
*regcache
, const void *buf
)
534 int i
, base
, size
, endian_offset
;
535 const char *regset
= (const char *) buf
;
537 base
= find_regno (regcache
->tdesc
, "cr0");
538 size
= register_size (regcache
->tdesc
, base
);
540 gdb_assert (size
== 4 || size
== 8);
542 for (i
= 0; i
< 32; i
++)
543 supply_register (regcache
, base
+ i
, ®set
[i
* size
]);
547 if ((size
== 8) && (__BYTE_ORDER
== __BIG_ENDIAN
))
550 supply_register_by_name (regcache
, "ccr",
551 ®set
[PT_CCR
* size
+ endian_offset
]);
553 supply_register_by_name (regcache
, "cxer",
554 ®set
[PT_XER
* size
+ endian_offset
]);
556 supply_register_by_name (regcache
, "clr", ®set
[PT_LNK
* size
]);
557 supply_register_by_name (regcache
, "cctr", ®set
[PT_CTR
* size
]);
560 /* Hardware Transactional Memory checkpointed floating-point regset
564 ppc_store_tm_cfprregset (struct regcache
*regcache
, const void *buf
)
567 const char *regset
= (const char *) buf
;
569 base
= find_regno (regcache
->tdesc
, "cf0");
571 for (i
= 0; i
< 32; i
++)
572 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
574 supply_register_by_name (regcache
, "cfpscr", ®set
[32 * 8]);
577 /* Hardware Transactional Memory checkpointed vector regset store
581 ppc_store_tm_cvrregset (struct regcache
*regcache
, const void *buf
)
584 const char *regset
= (const char *) buf
;
587 base
= find_regno (regcache
->tdesc
, "cvr0");
589 for (i
= 0; i
< 32; i
++)
590 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
592 if (__BYTE_ORDER
== __BIG_ENDIAN
)
595 supply_register_by_name (regcache
, "cvscr",
596 ®set
[32 * 16 + vscr_offset
]);
598 supply_register_by_name (regcache
, "cvrsave", ®set
[33 * 16]);
601 /* Hardware Transactional Memory checkpointed vector-scalar regset
605 ppc_store_tm_cvsxregset (struct regcache
*regcache
, const void *buf
)
608 const char *regset
= (const char *) buf
;
610 base
= find_regno (regcache
->tdesc
, "cvs0h");
611 for (i
= 0; i
< 32; i
++)
612 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
615 /* Hardware Transactional Memory checkpointed Program Priority
616 Register regset store function. */
619 ppc_store_tm_cpprregset (struct regcache
*regcache
, const void *buf
)
621 const char *cppr
= (const char *) buf
;
623 supply_register_by_name (regcache
, "cppr", cppr
);
626 /* Hardware Transactional Memory checkpointed Data Stream Control
627 Register regset store function. */
630 ppc_store_tm_cdscrregset (struct regcache
*regcache
, const void *buf
)
632 const char *cdscr
= (const char *) buf
;
634 supply_register_by_name (regcache
, "cdscr", cdscr
);
637 /* Hardware Transactional Memory checkpointed Target Address Register
638 regset store function. */
641 ppc_store_tm_ctarregset (struct regcache
*regcache
, const void *buf
)
643 const char *ctar
= (const char *) buf
;
645 supply_register_by_name (regcache
, "ctar", ctar
);
649 ppc_fill_vsxregset (struct regcache
*regcache
, void *buf
)
652 char *regset
= (char *) buf
;
654 base
= find_regno (regcache
->tdesc
, "vs0h");
655 for (i
= 0; i
< 32; i
++)
656 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
660 ppc_store_vsxregset (struct regcache
*regcache
, const void *buf
)
663 const char *regset
= (const char *) buf
;
665 base
= find_regno (regcache
->tdesc
, "vs0h");
666 for (i
= 0; i
< 32; i
++)
667 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
671 ppc_fill_vrregset (struct regcache
*regcache
, void *buf
)
674 char *regset
= (char *) buf
;
677 base
= find_regno (regcache
->tdesc
, "vr0");
678 for (i
= 0; i
< 32; i
++)
679 collect_register (regcache
, base
+ i
, ®set
[i
* 16]);
681 if (__BYTE_ORDER
== __BIG_ENDIAN
)
684 collect_register_by_name (regcache
, "vscr",
685 ®set
[32 * 16 + vscr_offset
]);
687 collect_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
691 ppc_store_vrregset (struct regcache
*regcache
, const void *buf
)
694 const char *regset
= (const char *) buf
;
697 base
= find_regno (regcache
->tdesc
, "vr0");
698 for (i
= 0; i
< 32; i
++)
699 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
701 if (__BYTE_ORDER
== __BIG_ENDIAN
)
704 supply_register_by_name (regcache
, "vscr",
705 ®set
[32 * 16 + vscr_offset
]);
706 supply_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
709 struct gdb_evrregset_t
711 unsigned long evr
[32];
712 unsigned long long acc
;
713 unsigned long spefscr
;
717 ppc_fill_evrregset (struct regcache
*regcache
, void *buf
)
720 struct gdb_evrregset_t
*regset
= (struct gdb_evrregset_t
*) buf
;
722 ev0
= find_regno (regcache
->tdesc
, "ev0h");
723 for (i
= 0; i
< 32; i
++)
724 collect_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
726 collect_register_by_name (regcache
, "acc", ®set
->acc
);
727 collect_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
731 ppc_store_evrregset (struct regcache
*regcache
, const void *buf
)
734 const struct gdb_evrregset_t
*regset
= (const struct gdb_evrregset_t
*) buf
;
736 ev0
= find_regno (regcache
->tdesc
, "ev0h");
737 for (i
= 0; i
< 32; i
++)
738 supply_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
740 supply_register_by_name (regcache
, "acc", ®set
->acc
);
741 supply_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
744 /* Support for hardware single step. */
747 ppc_supports_hardware_single_step (void)
752 static struct regset_info ppc_regsets
[] = {
753 /* List the extra register sets before GENERAL_REGS. That way we will
754 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
755 general registers. Some kernels support these, but not the newer
756 PPC_PTRACE_GETREGS. */
757 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CTAR
, 0, EXTENDED_REGS
,
758 NULL
, ppc_store_tm_ctarregset
},
759 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CDSCR
, 0, EXTENDED_REGS
,
760 NULL
, ppc_store_tm_cdscrregset
},
761 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CPPR
, 0, EXTENDED_REGS
,
762 NULL
, ppc_store_tm_cpprregset
},
763 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CVSX
, 0, EXTENDED_REGS
,
764 NULL
, ppc_store_tm_cvsxregset
},
765 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CVMX
, 0, EXTENDED_REGS
,
766 NULL
, ppc_store_tm_cvrregset
},
767 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CFPR
, 0, EXTENDED_REGS
,
768 NULL
, ppc_store_tm_cfprregset
},
769 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CGPR
, 0, EXTENDED_REGS
,
770 NULL
, ppc_store_tm_cgprregset
},
771 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_SPR
, 0, EXTENDED_REGS
,
772 ppc_fill_tm_sprregset
, ppc_store_tm_sprregset
},
773 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_EBB
, 0, EXTENDED_REGS
,
774 NULL
, ppc_store_ebbregset
},
775 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PMU
, 0, EXTENDED_REGS
,
776 ppc_fill_pmuregset
, ppc_store_pmuregset
},
777 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TAR
, 0, EXTENDED_REGS
,
778 ppc_fill_tarregset
, ppc_store_tarregset
},
779 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PPR
, 0, EXTENDED_REGS
,
780 ppc_fill_pprregset
, ppc_store_pprregset
},
781 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_DSCR
, 0, EXTENDED_REGS
,
782 ppc_fill_dscrregset
, ppc_store_dscrregset
},
783 { PTRACE_GETVSXREGS
, PTRACE_SETVSXREGS
, 0, 0, EXTENDED_REGS
,
784 ppc_fill_vsxregset
, ppc_store_vsxregset
},
785 { PTRACE_GETVRREGS
, PTRACE_SETVRREGS
, 0, 0, EXTENDED_REGS
,
786 ppc_fill_vrregset
, ppc_store_vrregset
},
787 { PTRACE_GETEVRREGS
, PTRACE_SETEVRREGS
, 0, 0, EXTENDED_REGS
,
788 ppc_fill_evrregset
, ppc_store_evrregset
},
789 { 0, 0, 0, 0, GENERAL_REGS
, ppc_fill_gregset
, NULL
},
793 static struct usrregs_info ppc_usrregs_info
=
799 static struct regsets_info ppc_regsets_info
=
801 ppc_regsets
, /* regsets */
803 NULL
, /* disabled_regsets */
806 static struct regs_info regs_info
=
808 NULL
, /* regset_bitmap */
813 static const struct regs_info
*
820 ppc_arch_setup (void)
822 const struct target_desc
*tdesc
;
823 struct regset_info
*regset
;
824 struct ppc_linux_features features
= ppc_linux_no_features
;
826 int tid
= lwpid_of (current_thread
);
828 features
.wordsize
= ppc_linux_target_wordsize (tid
);
830 if (features
.wordsize
== 4)
831 tdesc
= tdesc_powerpc_32l
;
833 tdesc
= tdesc_powerpc_64l
;
835 current_process ()->tdesc
= tdesc
;
837 /* The value of current_process ()->tdesc needs to be set for this
839 ppc_hwcap
= linux_get_hwcap (features
.wordsize
);
840 ppc_hwcap2
= linux_get_hwcap2 (features
.wordsize
);
842 features
.isa205
= ppc_linux_has_isa205 (ppc_hwcap
);
844 if (ppc_hwcap
& PPC_FEATURE_HAS_VSX
)
847 if (ppc_hwcap
& PPC_FEATURE_HAS_ALTIVEC
)
848 features
.altivec
= true;
850 if ((ppc_hwcap2
& PPC_FEATURE2_DSCR
)
851 && ppc_check_regset (tid
, NT_PPC_DSCR
, PPC_LINUX_SIZEOF_DSCRREGSET
)
852 && ppc_check_regset (tid
, NT_PPC_PPR
, PPC_LINUX_SIZEOF_PPRREGSET
))
854 features
.ppr_dscr
= true;
855 if ((ppc_hwcap2
& PPC_FEATURE2_ARCH_2_07
)
856 && (ppc_hwcap2
& PPC_FEATURE2_TAR
)
857 && (ppc_hwcap2
& PPC_FEATURE2_EBB
)
858 && ppc_check_regset (tid
, NT_PPC_TAR
,
859 PPC_LINUX_SIZEOF_TARREGSET
)
860 && ppc_check_regset (tid
, NT_PPC_EBB
,
861 PPC_LINUX_SIZEOF_EBBREGSET
)
862 && ppc_check_regset (tid
, NT_PPC_PMU
,
863 PPC_LINUX_SIZEOF_PMUREGSET
))
865 features
.isa207
= true;
866 if ((ppc_hwcap2
& PPC_FEATURE2_HTM
)
867 && ppc_check_regset (tid
, NT_PPC_TM_SPR
,
868 PPC_LINUX_SIZEOF_TM_SPRREGSET
))
873 tdesc
= ppc_linux_match_description (features
);
875 /* On 32-bit machines, check for SPE registers.
876 Set the low target's regmap field as appropriately. */
877 #ifndef __powerpc64__
878 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
879 tdesc
= tdesc_powerpc_e500l
;
881 if (!ppc_regmap_adjusted
)
883 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
884 ppc_usrregs_info
.regmap
= ppc_regmap_e500
;
886 /* If the FPSCR is 64-bit wide, we need to fetch the whole
887 64-bit slot and not just its second word. The PT_FPSCR
888 supplied in a 32-bit GDB compilation doesn't reflect
890 if (register_size (tdesc
, 70) == 8)
891 ppc_regmap
[70] = (48 + 2*32) * sizeof (long);
893 ppc_regmap_adjusted
= 1;
897 current_process ()->tdesc
= tdesc
;
899 for (regset
= ppc_regsets
; regset
->size
>= 0; regset
++)
900 switch (regset
->get_request
)
902 case PTRACE_GETVRREGS
:
903 regset
->size
= features
.altivec
? PPC_LINUX_SIZEOF_VRREGSET
: 0;
905 case PTRACE_GETVSXREGS
:
906 regset
->size
= features
.vsx
? PPC_LINUX_SIZEOF_VSXREGSET
: 0;
908 case PTRACE_GETEVRREGS
:
909 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
910 regset
->size
= 32 * 4 + 8 + 4;
914 case PTRACE_GETREGSET
:
915 switch (regset
->nt_type
)
918 regset
->size
= (features
.ppr_dscr
?
919 PPC_LINUX_SIZEOF_PPRREGSET
: 0);
922 regset
->size
= (features
.ppr_dscr
?
923 PPC_LINUX_SIZEOF_DSCRREGSET
: 0);
926 regset
->size
= (features
.isa207
?
927 PPC_LINUX_SIZEOF_TARREGSET
: 0);
930 regset
->size
= (features
.isa207
?
931 PPC_LINUX_SIZEOF_EBBREGSET
: 0);
934 regset
->size
= (features
.isa207
?
935 PPC_LINUX_SIZEOF_PMUREGSET
: 0);
938 regset
->size
= (features
.htm
?
939 PPC_LINUX_SIZEOF_TM_SPRREGSET
: 0);
942 if (features
.wordsize
== 4)
943 regset
->size
= (features
.htm
?
944 PPC32_LINUX_SIZEOF_CGPRREGSET
: 0);
946 regset
->size
= (features
.htm
?
947 PPC64_LINUX_SIZEOF_CGPRREGSET
: 0);
950 regset
->size
= (features
.htm
?
951 PPC_LINUX_SIZEOF_CFPRREGSET
: 0);
954 regset
->size
= (features
.htm
?
955 PPC_LINUX_SIZEOF_CVMXREGSET
: 0);
958 regset
->size
= (features
.htm
?
959 PPC_LINUX_SIZEOF_CVSXREGSET
: 0);
962 regset
->size
= (features
.htm
?
963 PPC_LINUX_SIZEOF_CPPRREGSET
: 0);
965 case NT_PPC_TM_CDSCR
:
966 regset
->size
= (features
.htm
?
967 PPC_LINUX_SIZEOF_CDSCRREGSET
: 0);
970 regset
->size
= (features
.htm
?
971 PPC_LINUX_SIZEOF_CTARREGSET
: 0);
982 /* Implementation of linux_target_ops method "supports_tracepoints". */
985 ppc_supports_tracepoints (void)
990 /* Get the thread area address. This is used to recognize which
991 thread is which when tracing with the in-process agent library. We
992 don't read anything from the address, and treat it as opaque; it's
993 the address itself that we assume is unique per-thread. */
996 ppc_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
998 struct lwp_info
*lwp
= find_lwp_pid (ptid_t (lwpid
));
999 struct thread_info
*thr
= get_lwp_thread (lwp
);
1000 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
1003 #ifdef __powerpc64__
1004 if (register_size (regcache
->tdesc
, 0) == 8)
1005 collect_register_by_name (regcache
, "r13", &tp
);
1008 collect_register_by_name (regcache
, "r2", &tp
);
1015 #ifdef __powerpc64__
1017 /* Older glibc doesn't provide this. */
1019 #ifndef EF_PPC64_ABI
1020 #define EF_PPC64_ABI 3
1023 /* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
1027 is_elfv2_inferior (void)
1029 /* To be used as fallback if we're unable to determine the right result -
1030 assume inferior uses the same ABI as gdbserver. */
1032 const int def_res
= 1;
1034 const int def_res
= 0;
1039 const struct target_desc
*tdesc
= current_process ()->tdesc
;
1040 int wordsize
= register_size (tdesc
, 0);
1042 if (!linux_get_auxv (wordsize
, AT_PHDR
, &phdr
))
1045 /* Assume ELF header is at the beginning of the page where program headers
1046 are located. If it doesn't look like one, bail. */
1048 read_inferior_memory (phdr
& ~0xfff, (unsigned char *) &ehdr
, sizeof ehdr
);
1049 if (memcmp(ehdr
.e_ident
, ELFMAG
, SELFMAG
))
1052 return (ehdr
.e_flags
& EF_PPC64_ABI
) == 2;
1057 /* Generate a ds-form instruction in BUF and return the number of bytes written
1060 | OPCD | RST | RA | DS |XO| */
1062 __attribute__((unused
)) /* Maybe unused due to conditional compilation. */
1064 gen_ds_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int ds
, int xo
)
1068 gdb_assert ((opcd
& ~0x3f) == 0);
1069 gdb_assert ((rst
& ~0x1f) == 0);
1070 gdb_assert ((ra
& ~0x1f) == 0);
1071 gdb_assert ((xo
& ~0x3) == 0);
1073 insn
= (rst
<< 21) | (ra
<< 16) | (ds
& 0xfffc) | (xo
& 0x3);
1074 *buf
= (opcd
<< 26) | insn
;
1078 /* Followings are frequently used ds-form instructions. */
1080 #define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
1081 #define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
1082 #define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
1083 #define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
1085 /* Generate a d-form instruction in BUF.
1088 | OPCD | RST | RA | D | */
1091 gen_d_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int si
)
1095 gdb_assert ((opcd
& ~0x3f) == 0);
1096 gdb_assert ((rst
& ~0x1f) == 0);
1097 gdb_assert ((ra
& ~0x1f) == 0);
1099 insn
= (rst
<< 21) | (ra
<< 16) | (si
& 0xffff);
1100 *buf
= (opcd
<< 26) | insn
;
1104 /* Followings are frequently used d-form instructions. */
1106 #define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
1107 #define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
1108 #define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
1109 #define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
1110 #define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
1111 #define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
1112 #define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
1113 #define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
1114 #define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
1116 /* Generate a xfx-form instruction in BUF and return the number of bytes
1120 | OPCD | RST | RI | XO |/| */
1123 gen_xfx_form (uint32_t *buf
, int opcd
, int rst
, int ri
, int xo
)
1126 unsigned int n
= ((ri
& 0x1f) << 5) | ((ri
>> 5) & 0x1f);
1128 gdb_assert ((opcd
& ~0x3f) == 0);
1129 gdb_assert ((rst
& ~0x1f) == 0);
1130 gdb_assert ((xo
& ~0x3ff) == 0);
1132 insn
= (rst
<< 21) | (n
<< 11) | (xo
<< 1);
1133 *buf
= (opcd
<< 26) | insn
;
1137 /* Followings are frequently used xfx-form instructions. */
1139 #define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
1140 #define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
1141 #define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
1142 #define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
1143 #define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
1145 #define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
1148 /* Generate a x-form instruction in BUF and return the number of bytes written.
1151 | OPCD | RST | RA | RB | XO |RC| */
1154 gen_x_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int rb
, int xo
, int rc
)
1158 gdb_assert ((opcd
& ~0x3f) == 0);
1159 gdb_assert ((rst
& ~0x1f) == 0);
1160 gdb_assert ((ra
& ~0x1f) == 0);
1161 gdb_assert ((rb
& ~0x1f) == 0);
1162 gdb_assert ((xo
& ~0x3ff) == 0);
1163 gdb_assert ((rc
& ~1) == 0);
1165 insn
= (rst
<< 21) | (ra
<< 16) | (rb
<< 11) | (xo
<< 1) | rc
;
1166 *buf
= (opcd
<< 26) | insn
;
1170 /* Followings are frequently used x-form instructions. */
1172 #define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
1173 #define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
1174 #define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
1175 #define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
1176 /* Assume bf = cr7. */
1177 #define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
1180 /* Generate a md-form instruction in BUF and return the number of bytes written.
1182 0 6 11 16 21 27 30 31 32
1183 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
1186 gen_md_form (uint32_t *buf
, int opcd
, int rs
, int ra
, int sh
, int mb
,
1190 unsigned int n
= ((mb
& 0x1f) << 1) | ((mb
>> 5) & 0x1);
1191 unsigned int sh0_4
= sh
& 0x1f;
1192 unsigned int sh5
= (sh
>> 5) & 1;
1194 gdb_assert ((opcd
& ~0x3f) == 0);
1195 gdb_assert ((rs
& ~0x1f) == 0);
1196 gdb_assert ((ra
& ~0x1f) == 0);
1197 gdb_assert ((sh
& ~0x3f) == 0);
1198 gdb_assert ((mb
& ~0x3f) == 0);
1199 gdb_assert ((xo
& ~0x7) == 0);
1200 gdb_assert ((rc
& ~0x1) == 0);
1202 insn
= (rs
<< 21) | (ra
<< 16) | (sh0_4
<< 11) | (n
<< 5)
1203 | (sh5
<< 1) | (xo
<< 2) | (rc
& 1);
1204 *buf
= (opcd
<< 26) | insn
;
1208 /* The following are frequently used md-form instructions. */
1210 #define GEN_RLDICL(buf, ra, rs ,sh, mb) \
1211 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
1212 #define GEN_RLDICR(buf, ra, rs ,sh, mb) \
1213 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
1215 /* Generate a i-form instruction in BUF and return the number of bytes written.
1218 | OPCD | LI |AA|LK| */
1221 gen_i_form (uint32_t *buf
, int opcd
, int li
, int aa
, int lk
)
1225 gdb_assert ((opcd
& ~0x3f) == 0);
1227 insn
= (li
& 0x3fffffc) | (aa
& 1) | (lk
& 1);
1228 *buf
= (opcd
<< 26) | insn
;
1232 /* The following are frequently used i-form instructions. */
1234 #define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
1235 #define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
1237 /* Generate a b-form instruction in BUF and return the number of bytes written.
1240 | OPCD | BO | BI | BD |AA|LK| */
1243 gen_b_form (uint32_t *buf
, int opcd
, int bo
, int bi
, int bd
,
1248 gdb_assert ((opcd
& ~0x3f) == 0);
1249 gdb_assert ((bo
& ~0x1f) == 0);
1250 gdb_assert ((bi
& ~0x1f) == 0);
1252 insn
= (bo
<< 21) | (bi
<< 16) | (bd
& 0xfffc) | (aa
& 1) | (lk
& 1);
1253 *buf
= (opcd
<< 26) | insn
;
1257 /* The following are frequently used b-form instructions. */
1258 /* Assume bi = cr7. */
1259 #define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
1261 /* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
1262 respectively. They are primary used for save/restore GPRs in jump-pad,
1263 not used for bytecode compiling. */
1265 #ifdef __powerpc64__
1266 #define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
1267 GEN_LD (buf, rt, ra, si) : \
1268 GEN_LWZ (buf, rt, ra, si))
1269 #define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
1270 GEN_STD (buf, rt, ra, si) : \
1271 GEN_STW (buf, rt, ra, si))
1273 #define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
1274 #define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
1277 /* Generate a sequence of instructions to load IMM in the register REG.
1278 Write the instructions in BUF and return the number of bytes written. */
1281 gen_limm (uint32_t *buf
, int reg
, uint64_t imm
, int is_64
)
1285 if ((imm
+ 32768) < 65536)
1287 /* li reg, imm[15:0] */
1288 p
+= GEN_LI (p
, reg
, imm
);
1290 else if ((imm
>> 32) == 0)
1292 /* lis reg, imm[31:16]
1293 ori reg, reg, imm[15:0]
1294 rldicl reg, reg, 0, 32 */
1295 p
+= GEN_LIS (p
, reg
, (imm
>> 16) & 0xffff);
1296 if ((imm
& 0xffff) != 0)
1297 p
+= GEN_ORI (p
, reg
, reg
, imm
& 0xffff);
1298 /* Clear upper 32-bit if sign-bit is set. */
1299 if (imm
& (1u << 31) && is_64
)
1300 p
+= GEN_RLDICL (p
, reg
, reg
, 0, 32);
1305 /* lis reg, <imm[63:48]>
1306 ori reg, reg, <imm[48:32]>
1307 rldicr reg, reg, 32, 31
1308 oris reg, reg, <imm[31:16]>
1309 ori reg, reg, <imm[15:0]> */
1310 p
+= GEN_LIS (p
, reg
, ((imm
>> 48) & 0xffff));
1311 if (((imm
>> 32) & 0xffff) != 0)
1312 p
+= GEN_ORI (p
, reg
, reg
, ((imm
>> 32) & 0xffff));
1313 p
+= GEN_RLDICR (p
, reg
, reg
, 32, 31);
1314 if (((imm
>> 16) & 0xffff) != 0)
1315 p
+= GEN_ORIS (p
, reg
, reg
, ((imm
>> 16) & 0xffff));
1316 if ((imm
& 0xffff) != 0)
1317 p
+= GEN_ORI (p
, reg
, reg
, (imm
& 0xffff));
1323 /* Generate a sequence for atomically exchange at location LOCK.
1324 This code sequence clobbers r6, r7, r8. LOCK is the location for
1325 the atomic-xchg, OLD_VALUE is expected old value stored in the
1326 location, and R_NEW is a register for the new value. */
1329 gen_atomic_xchg (uint32_t *buf
, CORE_ADDR lock
, int old_value
, int r_new
,
1332 const int r_lock
= 6;
1333 const int r_old
= 7;
1334 const int r_tmp
= 8;
1338 1: lwarx TMP, 0, LOCK
1344 p
+= gen_limm (p
, r_lock
, lock
, is_64
);
1345 p
+= gen_limm (p
, r_old
, old_value
, is_64
);
1347 p
+= GEN_LWARX (p
, r_tmp
, 0, r_lock
);
1348 p
+= GEN_CMPW (p
, r_tmp
, r_old
);
1349 p
+= GEN_BNE (p
, -8);
1350 p
+= GEN_STWCX (p
, r_new
, 0, r_lock
);
1351 p
+= GEN_BNE (p
, -16);
1356 /* Generate a sequence of instructions for calling a function
1357 at address of FN. Return the number of bytes are written in BUF. */
1360 gen_call (uint32_t *buf
, CORE_ADDR fn
, int is_64
, int is_opd
)
1364 /* Must be called by r12 for caller to calculate TOC address. */
1365 p
+= gen_limm (p
, 12, fn
, is_64
);
1368 p
+= GEN_LOAD (p
, 11, 12, 16, is_64
);
1369 p
+= GEN_LOAD (p
, 2, 12, 8, is_64
);
1370 p
+= GEN_LOAD (p
, 12, 12, 0, is_64
);
1372 p
+= GEN_MTSPR (p
, 12, 9); /* mtctr r12 */
1373 *p
++ = 0x4e800421; /* bctrl */
1378 /* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1379 of instruction. This function is used to adjust pc-relative instructions
1383 ppc_relocate_instruction (CORE_ADDR
*to
, CORE_ADDR oldloc
)
1388 read_inferior_memory (oldloc
, (unsigned char *) &insn
, 4);
1389 op6
= PPC_OP6 (insn
);
1391 if (op6
== 18 && (insn
& 2) == 0)
1393 /* branch && AA = 0 */
1394 rel
= PPC_LI (insn
);
1395 newrel
= (oldloc
- *to
) + rel
;
1397 /* Out of range. Cannot relocate instruction. */
1398 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1401 insn
= (insn
& ~0x3fffffc) | (newrel
& 0x3fffffc);
1403 else if (op6
== 16 && (insn
& 2) == 0)
1405 /* conditional branch && AA = 0 */
1407 /* If the new relocation is too big for even a 26-bit unconditional
1408 branch, there is nothing we can do. Just abort.
1410 Otherwise, if it can be fit in 16-bit conditional branch, just
1411 copy the instruction and relocate the address.
1413 If the it's big for conditional-branch (16-bit), try to invert the
1414 condition and jump with 26-bit branch. For example,
1425 After this transform, we are actually jump from *TO+4 instead of *TO,
1426 so check the relocation again because it will be 1-insn farther then
1427 before if *TO is after OLDLOC.
1430 For BDNZT (or so) is transformed from
1442 See also "BO field encodings". */
1444 rel
= PPC_BD (insn
);
1445 newrel
= (oldloc
- *to
) + rel
;
1447 if (newrel
< (1 << 15) && newrel
>= -(1 << 15))
1448 insn
= (insn
& ~0xfffc) | (newrel
& 0xfffc);
1449 else if ((PPC_BO (insn
) & 0x14) == 0x4 || (PPC_BO (insn
) & 0x14) == 0x10)
1453 /* Out of range. Cannot relocate instruction. */
1454 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1457 if ((PPC_BO (insn
) & 0x14) == 0x4)
1459 else if ((PPC_BO (insn
) & 0x14) == 0x10)
1462 /* Jump over the unconditional branch. */
1463 insn
= (insn
& ~0xfffc) | 0x8;
1464 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1467 /* Build a unconditional branch and copy LK bit. */
1468 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1469 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1474 else if ((PPC_BO (insn
) & 0x14) == 0)
1476 uint32_t bdnz_insn
= (16 << 26) | (0x10 << 21) | 12;
1477 uint32_t bf_insn
= (16 << 26) | (0x4 << 21) | 8;
1481 /* Out of range. Cannot relocate instruction. */
1482 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1485 /* Copy BI field. */
1486 bf_insn
|= (insn
& 0x1f0000);
1488 /* Invert condition. */
1489 bdnz_insn
|= (insn
^ (1 << 22)) & (1 << 22);
1490 bf_insn
|= (insn
^ (1 << 24)) & (1 << 24);
1492 target_write_memory (*to
, (unsigned char *) &bdnz_insn
, 4);
1494 target_write_memory (*to
, (unsigned char *) &bf_insn
, 4);
1497 /* Build a unconditional branch and copy LK bit. */
1498 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1499 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1504 else /* (BO & 0x14) == 0x14, branch always. */
1506 /* Out of range. Cannot relocate instruction. */
1507 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1510 /* Build a unconditional branch and copy LK bit. */
1511 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1512 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1519 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1523 /* Implement install_fast_tracepoint_jump_pad of target_ops.
1524 See target.h for details. */
1527 ppc_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1528 CORE_ADDR collector
,
1531 CORE_ADDR
*jump_entry
,
1532 CORE_ADDR
*trampoline
,
1533 ULONGEST
*trampoline_size
,
1534 unsigned char *jjump_pad_insn
,
1535 ULONGEST
*jjump_pad_insn_size
,
1536 CORE_ADDR
*adjusted_insn_addr
,
1537 CORE_ADDR
*adjusted_insn_addr_end
,
1543 CORE_ADDR buildaddr
= *jump_entry
;
1544 const CORE_ADDR entryaddr
= *jump_entry
;
1545 int rsz
, min_frame
, frame_size
, tp_reg
;
1546 #ifdef __powerpc64__
1547 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
1548 int is_64
= register_size (regcache
->tdesc
, 0) == 8;
1549 int is_opd
= is_64
&& !is_elfv2_inferior ();
1551 int is_64
= 0, is_opd
= 0;
1554 #ifdef __powerpc64__
1557 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1560 frame_size
= (40 * rsz
) + min_frame
;
1568 frame_size
= (40 * rsz
) + min_frame
;
1570 #ifdef __powerpc64__
1574 /* Stack frame layout for this jump pad,
1576 High thread_area (r13/r2) |
1577 tpoint - collecting_t obj
1587 R0 - collected registers
1593 The code flow of this jump pad,
1598 4. Call gdb_collector
1599 5. Restore GPR and SPR
1601 7. Build a jump for back to the program
1602 8. Copy/relocate original instruction
1603 9. Build a jump for replacing original instruction. */
1605 /* Adjust stack pointer. */
1607 p
+= GEN_STDU (p
, 1, 1, -frame_size
); /* stdu r1,-frame_size(r1) */
1609 p
+= GEN_STWU (p
, 1, 1, -frame_size
); /* stwu r1,-frame_size(r1) */
1611 /* Store GPRs. Save R1 later, because it had just been modified, but
1612 we want the original value. */
1613 for (j
= 2; j
< 32; j
++)
1614 p
+= GEN_STORE (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1615 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1616 /* Set r0 to the original value of r1 before adjusting stack frame,
1617 and then save it. */
1618 p
+= GEN_ADDI (p
, 0, 1, frame_size
);
1619 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 1 * rsz
, is_64
);
1621 /* Save CR, XER, LR, and CTR. */
1622 p
+= GEN_MFCR (p
, 3); /* mfcr r3 */
1623 p
+= GEN_MFSPR (p
, 4, 1); /* mfxer r4 */
1624 p
+= GEN_MFSPR (p
, 5, 8); /* mflr r5 */
1625 p
+= GEN_MFSPR (p
, 6, 9); /* mfctr r6 */
1626 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
);/* std r3, 32(r1) */
1627 p
+= GEN_STORE (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
);/* std r4, 33(r1) */
1628 p
+= GEN_STORE (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
);/* std r5, 34(r1) */
1629 p
+= GEN_STORE (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
);/* std r6, 35(r1) */
1631 /* Save PC<tpaddr> */
1632 p
+= gen_limm (p
, 3, tpaddr
, is_64
);
1633 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 36 * rsz
, is_64
);
1636 /* Setup arguments to collector. */
1637 /* Set r4 to collected registers. */
1638 p
+= GEN_ADDI (p
, 4, 1, min_frame
);
1639 /* Set r3 to TPOINT. */
1640 p
+= gen_limm (p
, 3, tpoint
, is_64
);
1642 /* Prepare collecting_t object for lock. */
1643 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 37 * rsz
, is_64
);
1644 p
+= GEN_STORE (p
, tp_reg
, 1, min_frame
+ 38 * rsz
, is_64
);
1645 /* Set R5 to collecting object. */
1646 p
+= GEN_ADDI (p
, 5, 1, 37 * rsz
);
1648 p
+= GEN_LWSYNC (p
);
1649 p
+= gen_atomic_xchg (p
, lockaddr
, 0, 5, is_64
);
1650 p
+= GEN_LWSYNC (p
);
1652 /* Call to collector. */
1653 p
+= gen_call (p
, collector
, is_64
, is_opd
);
1655 /* Simply write 0 to release the lock. */
1656 p
+= gen_limm (p
, 3, lockaddr
, is_64
);
1657 p
+= gen_limm (p
, 4, 0, is_64
);
1658 p
+= GEN_LWSYNC (p
);
1659 p
+= GEN_STORE (p
, 4, 3, 0, is_64
);
1661 /* Restore stack and registers. */
1662 p
+= GEN_LOAD (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
); /* ld r3, 32(r1) */
1663 p
+= GEN_LOAD (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
); /* ld r4, 33(r1) */
1664 p
+= GEN_LOAD (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
); /* ld r5, 34(r1) */
1665 p
+= GEN_LOAD (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
); /* ld r6, 35(r1) */
1666 p
+= GEN_MTCR (p
, 3); /* mtcr r3 */
1667 p
+= GEN_MTSPR (p
, 4, 1); /* mtxer r4 */
1668 p
+= GEN_MTSPR (p
, 5, 8); /* mtlr r5 */
1669 p
+= GEN_MTSPR (p
, 6, 9); /* mtctr r6 */
1672 for (j
= 2; j
< 32; j
++)
1673 p
+= GEN_LOAD (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1674 p
+= GEN_LOAD (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1676 p
+= GEN_ADDI (p
, 1, 1, frame_size
);
1678 /* Flush instructions to inferior memory. */
1679 target_write_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1681 /* Now, insert the original instruction to execute in the jump pad. */
1682 *adjusted_insn_addr
= buildaddr
+ (p
- buf
) * 4;
1683 *adjusted_insn_addr_end
= *adjusted_insn_addr
;
1684 ppc_relocate_instruction (adjusted_insn_addr_end
, tpaddr
);
1686 /* Verify the relocation size. If should be 4 for normal copy,
1687 8 or 12 for some conditional branch. */
1688 if ((*adjusted_insn_addr_end
- *adjusted_insn_addr
== 0)
1689 || (*adjusted_insn_addr_end
- *adjusted_insn_addr
> 12))
1691 sprintf (err
, "E.Unexpected instruction length = %d"
1692 "when relocate instruction.",
1693 (int) (*adjusted_insn_addr_end
- *adjusted_insn_addr
));
1697 buildaddr
= *adjusted_insn_addr_end
;
1699 /* Finally, write a jump back to the program. */
1700 offset
= (tpaddr
+ 4) - buildaddr
;
1701 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1703 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1704 "(offset 0x%x > 26-bit).", offset
);
1708 p
+= GEN_B (p
, offset
);
1709 target_write_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1710 *jump_entry
= buildaddr
+ (p
- buf
) * 4;
1712 /* The jump pad is now built. Wire in a jump to our jump pad. This
1713 is always done last (by our caller actually), so that we can
1714 install fast tracepoints with threads running. This relies on
1715 the agent's atomic write support. */
1716 offset
= entryaddr
- tpaddr
;
1717 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1719 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1720 "(offset 0x%x > 26-bit).", offset
);
1724 GEN_B ((uint32_t *) jjump_pad_insn
, offset
);
1725 *jjump_pad_insn_size
= 4;
1730 /* Returns the minimum instruction length for installing a tracepoint. */
1733 ppc_get_min_fast_tracepoint_insn_len (void)
1738 /* Emits a given buffer into the target at current_insn_ptr. Length
1739 is in units of 32-bit words. */
1742 emit_insns (uint32_t *buf
, int n
)
1744 n
= n
* sizeof (uint32_t);
1745 target_write_memory (current_insn_ptr
, (unsigned char *) buf
, n
);
1746 current_insn_ptr
+= n
;
1749 #define __EMIT_ASM(NAME, INSNS) \
1752 extern uint32_t start_bcax_ ## NAME []; \
1753 extern uint32_t end_bcax_ ## NAME []; \
1754 emit_insns (start_bcax_ ## NAME, \
1755 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1756 __asm__ (".section .text.__ppcbcax\n\t" \
1757 "start_bcax_" #NAME ":\n\t" \
1759 "end_bcax_" #NAME ":\n\t" \
1763 #define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1764 #define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1768 Bytecode execution stack frame - 32-bit
1770 | LR save area (SP + 4)
1771 SP' -> +- Back chain (SP + 0)
1772 | Save r31 for access saved arguments
1773 | Save r30 for bytecode stack pointer
1774 | Save r4 for incoming argument *value
1775 | Save r3 for incoming argument regs
1776 r30 -> +- Bytecode execution stack
1778 | 64-byte (8 doublewords) at initial.
1779 | Expand stack as needed.
1782 | Some padding for minimum stack frame and 16-byte alignment.
1784 SP +- Back-chain (SP')
1790 r30 is the stack-pointer for bytecode machine.
1791 It should point to next-empty, so we can use LDU for pop.
1792 r3 is used for cache of the high part of TOP value.
1793 It was the first argument, pointer to regs.
1794 r4 is used for cache of the low part of TOP value.
1795 It was the second argument, pointer to the result.
1796 We should set *result = TOP after leaving this function.
1799 * To restore stack at epilogue
1801 * To check stack is big enough for bytecode execution.
1803 * To return execution result.
1808 /* Regardless of endian, register 3 is always high part, 4 is low part.
1809 These defines are used when the register pair is stored/loaded.
1810 Likewise, to simplify code, have a similiar define for 5:6. */
1812 #if __BYTE_ORDER == __LITTLE_ENDIAN
1813 #define TOP_FIRST "4"
1814 #define TOP_SECOND "3"
1815 #define TMP_FIRST "6"
1816 #define TMP_SECOND "5"
1818 #define TOP_FIRST "3"
1819 #define TOP_SECOND "4"
1820 #define TMP_FIRST "5"
1821 #define TMP_SECOND "6"
1824 /* Emit prologue in inferior memory. See above comments. */
1827 ppc_emit_prologue (void)
1829 EMIT_ASM (/* Save return address. */
1832 /* Adjust SP. 96 is the initial frame size. */
1834 /* Save r30 and incoming arguments. */
1835 "stw 31, 96-4(1) \n"
1836 "stw 30, 96-8(1) \n"
1837 "stw 4, 96-12(1) \n"
1838 "stw 3, 96-16(1) \n"
1839 /* Point r31 to original r1 for access arguments. */
1841 /* Set r30 to pointing stack-top. */
1843 /* Initial r3/TOP to 0. */
1848 /* Emit epilogue in inferior memory. See above comments. */
1851 ppc_emit_epilogue (void)
1853 EMIT_ASM (/* *result = TOP */
1855 "stw " TOP_FIRST
", 0(5) \n"
1856 "stw " TOP_SECOND
", 4(5) \n"
1857 /* Restore registers. */
1864 /* Return 0 for no-error. */
1870 /* TOP = stack[--sp] + TOP */
1875 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1876 "lwz " TMP_SECOND
", 4(30)\n"
1881 /* TOP = stack[--sp] - TOP */
1886 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1887 "lwz " TMP_SECOND
", 4(30) \n"
1889 "subfe 3, 3, 5 \n");
1892 /* TOP = stack[--sp] * TOP */
1897 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1898 "lwz " TMP_SECOND
", 4(30) \n"
1907 /* TOP = stack[--sp] << TOP */
1912 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1913 "lwz " TMP_SECOND
", 4(30) \n"
1914 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1915 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1916 "slw 5, 5, 4\n" /* Shift high part left */
1917 "slw 4, 6, 4\n" /* Shift low part left */
1918 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
1919 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
1921 "or 3, 7, 3\n"); /* Assemble high part */
1924 /* Top = stack[--sp] >> TOP
1925 (Arithmetic shift right) */
1928 ppc_emit_rsh_signed (void)
1930 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1931 "lwz " TMP_SECOND
", 4(30) \n"
1932 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1933 "sraw 3, 5, 4\n" /* Shift high part right */
1935 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
1936 "sraw 4, 5, 7\n" /* Shift high to low */
1939 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
1940 "srw 4, 6, 4\n" /* Shift low part right */
1941 "slw 5, 5, 7\n" /* Shift high to low */
1942 "or 4, 4, 5\n" /* Assemble low part */
1946 /* Top = stack[--sp] >> TOP
1947 (Logical shift right) */
1950 ppc_emit_rsh_unsigned (void)
1952 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1953 "lwz " TMP_SECOND
", 4(30) \n"
1954 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1955 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1956 "srw 6, 6, 4\n" /* Shift low part right */
1957 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
1958 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
1960 "srw 3, 5, 4\n" /* Shift high part right */
1961 "or 4, 6, 7\n"); /* Assemble low part */
1964 /* Emit code for signed-extension specified by ARG. */
1967 ppc_emit_ext (int arg
)
1972 EMIT_ASM ("extsb 4, 4\n"
1976 EMIT_ASM ("extsh 4, 4\n"
1980 EMIT_ASM ("srawi 3, 4, 31");
1987 /* Emit code for zero-extension specified by ARG. */
1990 ppc_emit_zero_ext (int arg
)
1995 EMIT_ASM ("clrlwi 4,4,24\n"
1999 EMIT_ASM ("clrlwi 4,4,16\n"
2003 EMIT_ASM ("li 3, 0");
2011 i.e., TOP = (TOP == 0) ? 1 : 0; */
2014 ppc_emit_log_not (void)
2016 EMIT_ASM ("or 4, 3, 4 \n"
2022 /* TOP = stack[--sp] & TOP */
2025 ppc_emit_bit_and (void)
2027 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2028 "lwz " TMP_SECOND
", 4(30) \n"
2033 /* TOP = stack[--sp] | TOP */
2036 ppc_emit_bit_or (void)
2038 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2039 "lwz " TMP_SECOND
", 4(30) \n"
2044 /* TOP = stack[--sp] ^ TOP */
2047 ppc_emit_bit_xor (void)
2049 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2050 "lwz " TMP_SECOND
", 4(30) \n"
2056 i.e., TOP = ~(TOP | TOP) */
2059 ppc_emit_bit_not (void)
2061 EMIT_ASM ("nor 3, 3, 3 \n"
2065 /* TOP = stack[--sp] == TOP */
2068 ppc_emit_equal (void)
2070 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2071 "lwz " TMP_SECOND
", 4(30) \n"
2080 /* TOP = stack[--sp] < TOP
2081 (Signed comparison) */
2084 ppc_emit_less_signed (void)
2086 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2087 "lwz " TMP_SECOND
", 4(30) \n"
2090 /* CR6 bit 0 = low less and high equal */
2091 "crand 6*4+0, 6*4+0, 7*4+2\n"
2092 /* CR7 bit 0 = (low less and high equal) or high less */
2093 "cror 7*4+0, 7*4+0, 6*4+0\n"
2095 "rlwinm 4, 4, 29, 31, 31 \n"
2099 /* TOP = stack[--sp] < TOP
2100 (Unsigned comparison) */
2103 ppc_emit_less_unsigned (void)
2105 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2106 "lwz " TMP_SECOND
", 4(30) \n"
2109 /* CR6 bit 0 = low less and high equal */
2110 "crand 6*4+0, 6*4+0, 7*4+2\n"
2111 /* CR7 bit 0 = (low less and high equal) or high less */
2112 "cror 7*4+0, 7*4+0, 6*4+0\n"
2114 "rlwinm 4, 4, 29, 31, 31 \n"
2118 /* Access the memory address in TOP in size of SIZE.
2119 Zero-extend the read value. */
2122 ppc_emit_ref (int size
)
2127 EMIT_ASM ("lbz 4, 0(4)\n"
2131 EMIT_ASM ("lhz 4, 0(4)\n"
2135 EMIT_ASM ("lwz 4, 0(4)\n"
2139 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2140 EMIT_ASM ("lwz 3, 4(4)\n"
2143 EMIT_ASM ("lwz 3, 0(4)\n"
2152 ppc_emit_const (LONGEST num
)
2157 p
+= gen_limm (p
, 3, num
>> 32 & 0xffffffff, 0);
2158 p
+= gen_limm (p
, 4, num
& 0xffffffff, 0);
2160 emit_insns (buf
, p
- buf
);
2161 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2164 /* Set TOP to the value of register REG by calling get_raw_reg function
2165 with two argument, collected buffer and register number. */
2168 ppc_emit_reg (int reg
)
2173 /* fctx->regs is passed in r3 and then saved in -16(31). */
2174 p
+= GEN_LWZ (p
, 3, 31, -16);
2175 p
+= GEN_LI (p
, 4, reg
); /* li r4, reg */
2176 p
+= gen_call (p
, get_raw_reg_func_addr (), 0, 0);
2178 emit_insns (buf
, p
- buf
);
2179 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2181 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2183 EMIT_ASM ("mr 5, 4\n"
2189 /* TOP = stack[--sp] */
2194 EMIT_ASM ("lwzu " TOP_FIRST
", 8(30) \n"
2195 "lwz " TOP_SECOND
", 4(30) \n");
2198 /* stack[sp++] = TOP
2200 Because we may use up bytecode stack, expand 8 doublewords more
2204 ppc_emit_stack_flush (void)
2206 /* Make sure bytecode stack is big enough before push.
2207 Otherwise, expand 64-byte more. */
2209 EMIT_ASM (" stw " TOP_FIRST
", 0(30) \n"
2210 " stw " TOP_SECOND
", 4(30)\n"
2211 " addi 5, 30, -(8 + 8) \n"
2214 " stwu 31, -64(1) \n"
2215 "1:addi 30, 30, -8 \n");
2218 /* Swap TOP and stack[sp-1] */
2221 ppc_emit_swap (void)
2223 EMIT_ASM ("lwz " TMP_FIRST
", 8(30) \n"
2224 "lwz " TMP_SECOND
", 12(30) \n"
2225 "stw " TOP_FIRST
", 8(30) \n"
2226 "stw " TOP_SECOND
", 12(30) \n"
2231 /* Discard N elements in the stack. Also used for ppc64. */
2234 ppc_emit_stack_adjust (int n
)
2246 p
+= GEN_ADDI (p
, 30, 30, n
);
2248 emit_insns (buf
, p
- buf
);
2249 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2252 /* Call function FN. */
2255 ppc_emit_call (CORE_ADDR fn
)
2260 p
+= gen_call (p
, fn
, 0, 0);
2262 emit_insns (buf
, p
- buf
);
2263 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2266 /* FN's prototype is `LONGEST(*fn)(int)'.
2271 ppc_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2276 /* Setup argument. arg1 is a 16-bit value. */
2277 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2278 p
+= gen_call (p
, fn
, 0, 0);
2280 emit_insns (buf
, p
- buf
);
2281 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2283 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2285 EMIT_ASM ("mr 5, 4\n"
2291 /* FN's prototype is `void(*fn)(int,LONGEST)'.
2294 TOP should be preserved/restored before/after the call. */
2297 ppc_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2302 /* Save TOP. 0(30) is next-empty. */
2303 p
+= GEN_STW (p
, 3, 30, 0);
2304 p
+= GEN_STW (p
, 4, 30, 4);
2306 /* Setup argument. arg1 is a 16-bit value. */
2307 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2309 p
+= GEN_MR (p
, 5, 4);
2310 p
+= GEN_MR (p
, 6, 3);
2314 p
+= GEN_MR (p
, 5, 3);
2315 p
+= GEN_MR (p
, 6, 4);
2317 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2318 p
+= gen_call (p
, fn
, 0, 0);
2321 p
+= GEN_LWZ (p
, 3, 30, 0);
2322 p
+= GEN_LWZ (p
, 4, 30, 4);
2324 emit_insns (buf
, p
- buf
);
2325 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2328 /* Note in the following goto ops:
2330 When emitting goto, the target address is later relocated by
2331 write_goto_address. OFFSET_P is the offset of the branch instruction
2332 in the code sequence, and SIZE_P is how to relocate the instruction,
2333 recognized by ppc_write_goto_address. In current implementation,
2334 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2337 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2340 ppc_emit_if_goto (int *offset_p
, int *size_p
)
2342 EMIT_ASM ("or. 3, 3, 4 \n"
2343 "lwzu " TOP_FIRST
", 8(30) \n"
2344 "lwz " TOP_SECOND
", 4(30) \n"
2353 /* Unconditional goto. Also used for ppc64. */
2356 ppc_emit_goto (int *offset_p
, int *size_p
)
2358 EMIT_ASM ("1:b 1b");
2366 /* Goto if stack[--sp] == TOP */
2369 ppc_emit_eq_goto (int *offset_p
, int *size_p
)
2371 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2372 "lwz " TMP_SECOND
", 4(30) \n"
2376 "lwzu " TOP_FIRST
", 8(30) \n"
2377 "lwz " TOP_SECOND
", 4(30) \n"
2386 /* Goto if stack[--sp] != TOP */
2389 ppc_emit_ne_goto (int *offset_p
, int *size_p
)
2391 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2392 "lwz " TMP_SECOND
", 4(30) \n"
2396 "lwzu " TOP_FIRST
", 8(30) \n"
2397 "lwz " TOP_SECOND
", 4(30) \n"
2406 /* Goto if stack[--sp] < TOP */
2409 ppc_emit_lt_goto (int *offset_p
, int *size_p
)
2411 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2412 "lwz " TMP_SECOND
", 4(30) \n"
2415 /* CR6 bit 0 = low less and high equal */
2416 "crand 6*4+0, 6*4+0, 7*4+2\n"
2417 /* CR7 bit 0 = (low less and high equal) or high less */
2418 "cror 7*4+0, 7*4+0, 6*4+0\n"
2419 "lwzu " TOP_FIRST
", 8(30) \n"
2420 "lwz " TOP_SECOND
", 4(30)\n"
2429 /* Goto if stack[--sp] <= TOP */
2432 ppc_emit_le_goto (int *offset_p
, int *size_p
)
2434 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2435 "lwz " TMP_SECOND
", 4(30) \n"
2438 /* CR6 bit 0 = low less/equal and high equal */
2439 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2440 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2441 "cror 7*4+0, 7*4+0, 6*4+0\n"
2442 "lwzu " TOP_FIRST
", 8(30) \n"
2443 "lwz " TOP_SECOND
", 4(30)\n"
2452 /* Goto if stack[--sp] > TOP */
2455 ppc_emit_gt_goto (int *offset_p
, int *size_p
)
2457 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2458 "lwz " TMP_SECOND
", 4(30) \n"
2461 /* CR6 bit 0 = low greater and high equal */
2462 "crand 6*4+0, 6*4+1, 7*4+2\n"
2463 /* CR7 bit 0 = (low greater and high equal) or high greater */
2464 "cror 7*4+0, 7*4+1, 6*4+0\n"
2465 "lwzu " TOP_FIRST
", 8(30) \n"
2466 "lwz " TOP_SECOND
", 4(30)\n"
2475 /* Goto if stack[--sp] >= TOP */
2478 ppc_emit_ge_goto (int *offset_p
, int *size_p
)
2480 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2481 "lwz " TMP_SECOND
", 4(30) \n"
2484 /* CR6 bit 0 = low ge and high equal */
2485 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2486 /* CR7 bit 0 = (low ge and high equal) or high greater */
2487 "cror 7*4+0, 7*4+1, 6*4+0\n"
2488 "lwzu " TOP_FIRST
", 8(30)\n"
2489 "lwz " TOP_SECOND
", 4(30)\n"
2498 /* Relocate previous emitted branch instruction. FROM is the address
2499 of the branch instruction, TO is the goto target address, and SIZE
2500 if the value we set by *SIZE_P before. Currently, it is either
2501 24 or 14 of branch and conditional-branch instruction.
2502 Also used for ppc64. */
2505 ppc_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2507 long rel
= to
- from
;
2511 read_inferior_memory (from
, (unsigned char *) &insn
, 4);
2512 opcd
= (insn
>> 26) & 0x3f;
2518 || (rel
>= (1 << 15) || rel
< -(1 << 15)))
2520 insn
= (insn
& ~0xfffc) | (rel
& 0xfffc);
2524 || (rel
>= (1 << 25) || rel
< -(1 << 25)))
2526 insn
= (insn
& ~0x3fffffc) | (rel
& 0x3fffffc);
2533 target_write_memory (from
, (unsigned char *) &insn
, 4);
2536 /* Table of emit ops for 32-bit. */
2538 static struct emit_ops ppc_emit_ops_impl
=
2546 ppc_emit_rsh_signed
,
2547 ppc_emit_rsh_unsigned
,
2555 ppc_emit_less_signed
,
2556 ppc_emit_less_unsigned
,
2560 ppc_write_goto_address
,
2565 ppc_emit_stack_flush
,
2568 ppc_emit_stack_adjust
,
2569 ppc_emit_int_call_1
,
2570 ppc_emit_void_call_2
,
2579 #ifdef __powerpc64__
2583 Bytecode execution stack frame - 64-bit
2585 | LR save area (SP + 16)
2586 | CR save area (SP + 8)
2587 SP' -> +- Back chain (SP + 0)
2588 | Save r31 for access saved arguments
2589 | Save r30 for bytecode stack pointer
2590 | Save r4 for incoming argument *value
2591 | Save r3 for incoming argument regs
2592 r30 -> +- Bytecode execution stack
2594 | 64-byte (8 doublewords) at initial.
2595 | Expand stack as needed.
2598 | Some padding for minimum stack frame.
2600 SP +- Back-chain (SP')
2603 = 112 + (4 * 8) + 64
2606 r30 is the stack-pointer for bytecode machine.
2607 It should point to next-empty, so we can use LDU for pop.
2608 r3 is used for cache of TOP value.
2609 It was the first argument, pointer to regs.
2610 r4 is the second argument, pointer to the result.
2611 We should set *result = TOP after leaving this function.
2614 * To restore stack at epilogue
2616 * To check stack is big enough for bytecode execution.
2617 => r30 - 8 > SP + 112
2618 * To return execution result.
2623 /* Emit prologue in inferior memory. See above comments. */
2626 ppc64v1_emit_prologue (void)
2628 /* On ELFv1, function pointers really point to function descriptor,
2629 so emit one here. We don't care about contents of words 1 and 2,
2630 so let them just overlap out code. */
2631 uint64_t opd
= current_insn_ptr
+ 8;
2634 /* Mind the strict aliasing rules. */
2635 memcpy (buf
, &opd
, sizeof buf
);
2637 EMIT_ASM (/* Save return address. */
2640 /* Save r30 and incoming arguments. */
2645 /* Point r31 to current r1 for access arguments. */
2647 /* Adjust SP. 208 is the initial frame size. */
2648 "stdu 1, -208(1) \n"
2649 /* Set r30 to pointing stack-top. */
2650 "addi 30, 1, 168 \n"
2651 /* Initial r3/TOP to 0. */
2655 /* Emit prologue in inferior memory. See above comments. */
2658 ppc64v2_emit_prologue (void)
2660 EMIT_ASM (/* Save return address. */
2663 /* Save r30 and incoming arguments. */
2668 /* Point r31 to current r1 for access arguments. */
2670 /* Adjust SP. 208 is the initial frame size. */
2671 "stdu 1, -208(1) \n"
2672 /* Set r30 to pointing stack-top. */
2673 "addi 30, 1, 168 \n"
2674 /* Initial r3/TOP to 0. */
2678 /* Emit epilogue in inferior memory. See above comments. */
2681 ppc64_emit_epilogue (void)
2683 EMIT_ASM (/* Restore SP. */
2688 /* Restore registers. */
2693 /* Return 0 for no-error. */
2699 /* TOP = stack[--sp] + TOP */
2702 ppc64_emit_add (void)
2704 EMIT_ASM ("ldu 4, 8(30) \n"
2708 /* TOP = stack[--sp] - TOP */
2711 ppc64_emit_sub (void)
2713 EMIT_ASM ("ldu 4, 8(30) \n"
2717 /* TOP = stack[--sp] * TOP */
2720 ppc64_emit_mul (void)
2722 EMIT_ASM ("ldu 4, 8(30) \n"
2723 "mulld 3, 4, 3 \n");
2726 /* TOP = stack[--sp] << TOP */
2729 ppc64_emit_lsh (void)
2731 EMIT_ASM ("ldu 4, 8(30) \n"
2735 /* Top = stack[--sp] >> TOP
2736 (Arithmetic shift right) */
2739 ppc64_emit_rsh_signed (void)
2741 EMIT_ASM ("ldu 4, 8(30) \n"
2745 /* Top = stack[--sp] >> TOP
2746 (Logical shift right) */
2749 ppc64_emit_rsh_unsigned (void)
2751 EMIT_ASM ("ldu 4, 8(30) \n"
2755 /* Emit code for signed-extension specified by ARG. */
2758 ppc64_emit_ext (int arg
)
2763 EMIT_ASM ("extsb 3, 3");
2766 EMIT_ASM ("extsh 3, 3");
2769 EMIT_ASM ("extsw 3, 3");
2776 /* Emit code for zero-extension specified by ARG. */
2779 ppc64_emit_zero_ext (int arg
)
2784 EMIT_ASM ("rldicl 3,3,0,56");
2787 EMIT_ASM ("rldicl 3,3,0,48");
2790 EMIT_ASM ("rldicl 3,3,0,32");
2798 i.e., TOP = (TOP == 0) ? 1 : 0; */
2801 ppc64_emit_log_not (void)
2803 EMIT_ASM ("cntlzd 3, 3 \n"
2807 /* TOP = stack[--sp] & TOP */
2810 ppc64_emit_bit_and (void)
2812 EMIT_ASM ("ldu 4, 8(30) \n"
2816 /* TOP = stack[--sp] | TOP */
2819 ppc64_emit_bit_or (void)
2821 EMIT_ASM ("ldu 4, 8(30) \n"
2825 /* TOP = stack[--sp] ^ TOP */
2828 ppc64_emit_bit_xor (void)
2830 EMIT_ASM ("ldu 4, 8(30) \n"
2835 i.e., TOP = ~(TOP | TOP) */
2838 ppc64_emit_bit_not (void)
2840 EMIT_ASM ("nor 3, 3, 3 \n");
2843 /* TOP = stack[--sp] == TOP */
2846 ppc64_emit_equal (void)
2848 EMIT_ASM ("ldu 4, 8(30) \n"
2854 /* TOP = stack[--sp] < TOP
2855 (Signed comparison) */
2858 ppc64_emit_less_signed (void)
2860 EMIT_ASM ("ldu 4, 8(30) \n"
2863 "rlwinm 3, 3, 29, 31, 31 \n");
2866 /* TOP = stack[--sp] < TOP
2867 (Unsigned comparison) */
2870 ppc64_emit_less_unsigned (void)
2872 EMIT_ASM ("ldu 4, 8(30) \n"
2875 "rlwinm 3, 3, 29, 31, 31 \n");
2878 /* Access the memory address in TOP in size of SIZE.
2879 Zero-extend the read value. */
2882 ppc64_emit_ref (int size
)
2887 EMIT_ASM ("lbz 3, 0(3)");
2890 EMIT_ASM ("lhz 3, 0(3)");
2893 EMIT_ASM ("lwz 3, 0(3)");
2896 EMIT_ASM ("ld 3, 0(3)");
2904 ppc64_emit_const (LONGEST num
)
2909 p
+= gen_limm (p
, 3, num
, 1);
2911 emit_insns (buf
, p
- buf
);
2912 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2915 /* Set TOP to the value of register REG by calling get_raw_reg function
2916 with two argument, collected buffer and register number. */
2919 ppc64v1_emit_reg (int reg
)
2924 /* fctx->regs is passed in r3 and then saved in 176(1). */
2925 p
+= GEN_LD (p
, 3, 31, -32);
2926 p
+= GEN_LI (p
, 4, reg
);
2927 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2928 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 1);
2929 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2931 emit_insns (buf
, p
- buf
);
2932 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2935 /* Likewise, for ELFv2. */
2938 ppc64v2_emit_reg (int reg
)
2943 /* fctx->regs is passed in r3 and then saved in 176(1). */
2944 p
+= GEN_LD (p
, 3, 31, -32);
2945 p
+= GEN_LI (p
, 4, reg
);
2946 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
2947 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 0);
2948 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
2950 emit_insns (buf
, p
- buf
);
2951 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2954 /* TOP = stack[--sp] */
2957 ppc64_emit_pop (void)
2959 EMIT_ASM ("ldu 3, 8(30)");
2962 /* stack[sp++] = TOP
2964 Because we may use up bytecode stack, expand 8 doublewords more
2968 ppc64_emit_stack_flush (void)
2970 /* Make sure bytecode stack is big enough before push.
2971 Otherwise, expand 64-byte more. */
2973 EMIT_ASM (" std 3, 0(30) \n"
2974 " addi 4, 30, -(112 + 8) \n"
2977 " stdu 31, -64(1) \n"
2978 "1:addi 30, 30, -8 \n");
2981 /* Swap TOP and stack[sp-1] */
2984 ppc64_emit_swap (void)
2986 EMIT_ASM ("ld 4, 8(30) \n"
2991 /* Call function FN - ELFv1. */
2994 ppc64v1_emit_call (CORE_ADDR fn
)
2999 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3000 p
+= gen_call (p
, fn
, 1, 1);
3001 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3003 emit_insns (buf
, p
- buf
);
3004 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3007 /* Call function FN - ELFv2. */
3010 ppc64v2_emit_call (CORE_ADDR fn
)
3015 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3016 p
+= gen_call (p
, fn
, 1, 0);
3017 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3019 emit_insns (buf
, p
- buf
);
3020 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3023 /* FN's prototype is `LONGEST(*fn)(int)'.
3028 ppc64v1_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
3033 /* Setup argument. arg1 is a 16-bit value. */
3034 p
+= gen_limm (p
, 3, arg1
, 1);
3035 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3036 p
+= gen_call (p
, fn
, 1, 1);
3037 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3039 emit_insns (buf
, p
- buf
);
3040 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3043 /* Likewise for ELFv2. */
3046 ppc64v2_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
3051 /* Setup argument. arg1 is a 16-bit value. */
3052 p
+= gen_limm (p
, 3, arg1
, 1);
3053 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3054 p
+= gen_call (p
, fn
, 1, 0);
3055 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3057 emit_insns (buf
, p
- buf
);
3058 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3061 /* FN's prototype is `void(*fn)(int,LONGEST)'.
3064 TOP should be preserved/restored before/after the call. */
3067 ppc64v1_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3072 /* Save TOP. 0(30) is next-empty. */
3073 p
+= GEN_STD (p
, 3, 30, 0);
3075 /* Setup argument. arg1 is a 16-bit value. */
3076 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
3077 p
+= gen_limm (p
, 3, arg1
, 1);
3078 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3079 p
+= gen_call (p
, fn
, 1, 1);
3080 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3083 p
+= GEN_LD (p
, 3, 30, 0);
3085 emit_insns (buf
, p
- buf
);
3086 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3089 /* Likewise for ELFv2. */
3092 ppc64v2_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3097 /* Save TOP. 0(30) is next-empty. */
3098 p
+= GEN_STD (p
, 3, 30, 0);
3100 /* Setup argument. arg1 is a 16-bit value. */
3101 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
3102 p
+= gen_limm (p
, 3, arg1
, 1);
3103 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3104 p
+= gen_call (p
, fn
, 1, 0);
3105 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3108 p
+= GEN_LD (p
, 3, 30, 0);
3110 emit_insns (buf
, p
- buf
);
3111 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3114 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
3117 ppc64_emit_if_goto (int *offset_p
, int *size_p
)
3119 EMIT_ASM ("cmpdi 7, 3, 0 \n"
3129 /* Goto if stack[--sp] == TOP */
3132 ppc64_emit_eq_goto (int *offset_p
, int *size_p
)
3134 EMIT_ASM ("ldu 4, 8(30) \n"
3145 /* Goto if stack[--sp] != TOP */
3148 ppc64_emit_ne_goto (int *offset_p
, int *size_p
)
3150 EMIT_ASM ("ldu 4, 8(30) \n"
3161 /* Goto if stack[--sp] < TOP */
3164 ppc64_emit_lt_goto (int *offset_p
, int *size_p
)
3166 EMIT_ASM ("ldu 4, 8(30) \n"
3177 /* Goto if stack[--sp] <= TOP */
3180 ppc64_emit_le_goto (int *offset_p
, int *size_p
)
3182 EMIT_ASM ("ldu 4, 8(30) \n"
3193 /* Goto if stack[--sp] > TOP */
3196 ppc64_emit_gt_goto (int *offset_p
, int *size_p
)
3198 EMIT_ASM ("ldu 4, 8(30) \n"
3209 /* Goto if stack[--sp] >= TOP */
3212 ppc64_emit_ge_goto (int *offset_p
, int *size_p
)
3214 EMIT_ASM ("ldu 4, 8(30) \n"
3225 /* Table of emit ops for 64-bit ELFv1. */
3227 static struct emit_ops ppc64v1_emit_ops_impl
=
3229 ppc64v1_emit_prologue
,
3230 ppc64_emit_epilogue
,
3235 ppc64_emit_rsh_signed
,
3236 ppc64_emit_rsh_unsigned
,
3244 ppc64_emit_less_signed
,
3245 ppc64_emit_less_unsigned
,
3249 ppc_write_goto_address
,
3254 ppc64_emit_stack_flush
,
3255 ppc64_emit_zero_ext
,
3257 ppc_emit_stack_adjust
,
3258 ppc64v1_emit_int_call_1
,
3259 ppc64v1_emit_void_call_2
,
3268 /* Table of emit ops for 64-bit ELFv2. */
3270 static struct emit_ops ppc64v2_emit_ops_impl
=
3272 ppc64v2_emit_prologue
,
3273 ppc64_emit_epilogue
,
3278 ppc64_emit_rsh_signed
,
3279 ppc64_emit_rsh_unsigned
,
3287 ppc64_emit_less_signed
,
3288 ppc64_emit_less_unsigned
,
3292 ppc_write_goto_address
,
3297 ppc64_emit_stack_flush
,
3298 ppc64_emit_zero_ext
,
3300 ppc_emit_stack_adjust
,
3301 ppc64v2_emit_int_call_1
,
3302 ppc64v2_emit_void_call_2
,
3313 /* Implementation of linux_target_ops method "emit_ops". */
3315 static struct emit_ops
*
3318 #ifdef __powerpc64__
3319 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3321 if (register_size (regcache
->tdesc
, 0) == 8)
3323 if (is_elfv2_inferior ())
3324 return &ppc64v2_emit_ops_impl
;
3326 return &ppc64v1_emit_ops_impl
;
3329 return &ppc_emit_ops_impl
;
3332 /* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3335 ppc_get_ipa_tdesc_idx (void)
3337 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3338 const struct target_desc
*tdesc
= regcache
->tdesc
;
3340 #ifdef __powerpc64__
3341 if (tdesc
== tdesc_powerpc_64l
)
3342 return PPC_TDESC_BASE
;
3343 if (tdesc
== tdesc_powerpc_altivec64l
)
3344 return PPC_TDESC_ALTIVEC
;
3345 if (tdesc
== tdesc_powerpc_vsx64l
)
3346 return PPC_TDESC_VSX
;
3347 if (tdesc
== tdesc_powerpc_isa205_64l
)
3348 return PPC_TDESC_ISA205
;
3349 if (tdesc
== tdesc_powerpc_isa205_altivec64l
)
3350 return PPC_TDESC_ISA205_ALTIVEC
;
3351 if (tdesc
== tdesc_powerpc_isa205_vsx64l
)
3352 return PPC_TDESC_ISA205_VSX
;
3353 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx64l
)
3354 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3355 if (tdesc
== tdesc_powerpc_isa207_vsx64l
)
3356 return PPC_TDESC_ISA207_VSX
;
3357 if (tdesc
== tdesc_powerpc_isa207_htm_vsx64l
)
3358 return PPC_TDESC_ISA207_HTM_VSX
;
3361 if (tdesc
== tdesc_powerpc_32l
)
3362 return PPC_TDESC_BASE
;
3363 if (tdesc
== tdesc_powerpc_altivec32l
)
3364 return PPC_TDESC_ALTIVEC
;
3365 if (tdesc
== tdesc_powerpc_vsx32l
)
3366 return PPC_TDESC_VSX
;
3367 if (tdesc
== tdesc_powerpc_isa205_32l
)
3368 return PPC_TDESC_ISA205
;
3369 if (tdesc
== tdesc_powerpc_isa205_altivec32l
)
3370 return PPC_TDESC_ISA205_ALTIVEC
;
3371 if (tdesc
== tdesc_powerpc_isa205_vsx32l
)
3372 return PPC_TDESC_ISA205_VSX
;
3373 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx32l
)
3374 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3375 if (tdesc
== tdesc_powerpc_isa207_vsx32l
)
3376 return PPC_TDESC_ISA207_VSX
;
3377 if (tdesc
== tdesc_powerpc_isa207_htm_vsx32l
)
3378 return PPC_TDESC_ISA207_HTM_VSX
;
3379 if (tdesc
== tdesc_powerpc_e500l
)
3380 return PPC_TDESC_E500
;
3385 struct linux_target_ops the_low_target
= {
3388 ppc_cannot_fetch_register
,
3389 ppc_cannot_store_register
,
3390 NULL
, /* fetch_register */
3393 NULL
, /* breakpoint_kind_from_pc */
3394 ppc_sw_breakpoint_from_kind
,
3398 ppc_supports_z_point_type
,
3403 ppc_collect_ptrace_register
,
3404 ppc_supply_ptrace_register
,
3405 NULL
, /* siginfo_fixup */
3406 NULL
, /* new_process */
3407 NULL
, /* delete_process */
3408 NULL
, /* new_thread */
3409 NULL
, /* delete_thread */
3410 NULL
, /* new_fork */
3411 NULL
, /* prepare_to_resume */
3412 NULL
, /* process_qsupported */
3413 ppc_supports_tracepoints
,
3414 ppc_get_thread_area
,
3415 ppc_install_fast_tracepoint_jump_pad
,
3417 ppc_get_min_fast_tracepoint_insn_len
,
3418 NULL
, /* supports_range_stepping */
3419 NULL
, /* breakpoint_kind_from_current_state */
3420 ppc_supports_hardware_single_step
,
3421 NULL
, /* get_syscall_trapinfo */
3422 ppc_get_ipa_tdesc_idx
,
3425 /* The linux target ops object. */
3427 linux_process_target
*the_linux_target
= &the_ppc_target
;
3430 initialize_low_arch (void)
3432 /* Initialize the Linux target descriptions. */
3434 init_registers_powerpc_32l ();
3435 init_registers_powerpc_altivec32l ();
3436 init_registers_powerpc_vsx32l ();
3437 init_registers_powerpc_isa205_32l ();
3438 init_registers_powerpc_isa205_altivec32l ();
3439 init_registers_powerpc_isa205_vsx32l ();
3440 init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
3441 init_registers_powerpc_isa207_vsx32l ();
3442 init_registers_powerpc_isa207_htm_vsx32l ();
3443 init_registers_powerpc_e500l ();
3445 init_registers_powerpc_64l ();
3446 init_registers_powerpc_altivec64l ();
3447 init_registers_powerpc_vsx64l ();
3448 init_registers_powerpc_isa205_64l ();
3449 init_registers_powerpc_isa205_altivec64l ();
3450 init_registers_powerpc_isa205_vsx64l ();
3451 init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
3452 init_registers_powerpc_isa207_vsx64l ();
3453 init_registers_powerpc_isa207_htm_vsx64l ();
3456 initialize_regsets_info (&ppc_regsets_info
);