1 /* GNU/Linux/x86-64 specific low level interface, for the remote server
3 Copyright (C) 2002-2020 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "linux-low.h"
27 #include "gdbsupport/x86-xstate.h"
28 #include "nat/gdb_ptrace.h"
31 #include "nat/amd64-linux-siginfo.h"
34 #include "gdb_proc_service.h"
35 /* Don't include elf/common.h if linux/elf.h got included by
36 gdb_proc_service.h. */
38 #include "elf/common.h"
41 #include "gdbsupport/agent.h"
43 #include "tracepoint.h"
45 #include "nat/linux-nat.h"
46 #include "nat/x86-linux.h"
47 #include "nat/x86-linux-dregs.h"
48 #include "linux-x86-tdesc.h"
51 static struct target_desc
*tdesc_amd64_linux_no_xml
;
53 static struct target_desc
*tdesc_i386_linux_no_xml
;
56 static unsigned char jump_insn
[] = { 0xe9, 0, 0, 0, 0 };
57 static unsigned char small_jump_insn
[] = { 0x66, 0xe9, 0, 0 };
59 /* Backward compatibility for gdb without XML support. */
61 static const char *xmltarget_i386_linux_no_xml
= "@<target>\
62 <architecture>i386</architecture>\
63 <osabi>GNU/Linux</osabi>\
67 static const char *xmltarget_amd64_linux_no_xml
= "@<target>\
68 <architecture>i386:x86-64</architecture>\
69 <osabi>GNU/Linux</osabi>\
74 #include <sys/procfs.h>
77 #ifndef PTRACE_GET_THREAD_AREA
78 #define PTRACE_GET_THREAD_AREA 25
81 /* This definition comes from prctl.h, but some kernels may not have it. */
82 #ifndef PTRACE_ARCH_PRCTL
83 #define PTRACE_ARCH_PRCTL 30
86 /* The following definitions come from prctl.h, but may be absent
87 for certain configurations. */
89 #define ARCH_SET_GS 0x1001
90 #define ARCH_SET_FS 0x1002
91 #define ARCH_GET_FS 0x1003
92 #define ARCH_GET_GS 0x1004
95 /* Linux target op definitions for the x86 architecture.
96 This is initialized assuming an amd64 target.
97 'low_arch_setup' will correct it for i386 or amd64 targets. */
99 class x86_target
: public linux_process_target
103 /* Update all the target description of all processes; a new GDB
104 connected, and it may or not support xml target descriptions. */
105 void update_xmltarget ();
107 const regs_info
*get_regs_info () override
;
109 const gdb_byte
*sw_breakpoint_from_kind (int kind
, int *size
) override
;
111 bool supports_z_point_type (char z_type
) override
;
115 void low_arch_setup () override
;
117 bool low_cannot_fetch_register (int regno
) override
;
119 bool low_cannot_store_register (int regno
) override
;
121 bool low_supports_breakpoints () override
;
123 CORE_ADDR
low_get_pc (regcache
*regcache
) override
;
125 void low_set_pc (regcache
*regcache
, CORE_ADDR newpc
) override
;
127 int low_decr_pc_after_break () override
;
129 bool low_breakpoint_at (CORE_ADDR pc
) override
;
131 int low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
132 int size
, raw_breakpoint
*bp
) override
;
134 int low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
135 int size
, raw_breakpoint
*bp
) override
;
137 bool low_stopped_by_watchpoint () override
;
139 CORE_ADDR
low_stopped_data_address () override
;
141 /* collect_ptrace_register/supply_ptrace_register are not needed in the
142 native i386 case (no registers smaller than an xfer unit), and are not
143 used in the biarch case (HAVE_LINUX_USRREGS is not defined). */
146 /* The singleton target ops object. */
148 static x86_target the_x86_target
;
150 /* Per-process arch-specific data we want to keep. */
152 struct arch_process_info
154 struct x86_debug_reg_state debug_reg_state
;
159 /* Mapping between the general-purpose registers in `struct user'
160 format and GDB's register array layout.
161 Note that the transfer layout uses 64-bit regs. */
162 static /*const*/ int i386_regmap
[] =
164 RAX
* 8, RCX
* 8, RDX
* 8, RBX
* 8,
165 RSP
* 8, RBP
* 8, RSI
* 8, RDI
* 8,
166 RIP
* 8, EFLAGS
* 8, CS
* 8, SS
* 8,
167 DS
* 8, ES
* 8, FS
* 8, GS
* 8
170 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
172 /* So code below doesn't have to care, i386 or amd64. */
173 #define ORIG_EAX ORIG_RAX
176 static const int x86_64_regmap
[] =
178 RAX
* 8, RBX
* 8, RCX
* 8, RDX
* 8,
179 RSI
* 8, RDI
* 8, RBP
* 8, RSP
* 8,
180 R8
* 8, R9
* 8, R10
* 8, R11
* 8,
181 R12
* 8, R13
* 8, R14
* 8, R15
* 8,
182 RIP
* 8, EFLAGS
* 8, CS
* 8, SS
* 8,
183 DS
* 8, ES
* 8, FS
* 8, GS
* 8,
184 -1, -1, -1, -1, -1, -1, -1, -1,
185 -1, -1, -1, -1, -1, -1, -1, -1,
186 -1, -1, -1, -1, -1, -1, -1, -1,
188 -1, -1, -1, -1, -1, -1, -1, -1,
190 #ifdef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE
195 -1, -1, -1, -1, /* MPX registers BND0 ... BND3. */
196 -1, -1, /* MPX registers BNDCFGU, BNDSTATUS. */
197 -1, -1, -1, -1, -1, -1, -1, -1, /* xmm16 ... xmm31 (AVX512) */
198 -1, -1, -1, -1, -1, -1, -1, -1,
199 -1, -1, -1, -1, -1, -1, -1, -1, /* ymm16 ... ymm31 (AVX512) */
200 -1, -1, -1, -1, -1, -1, -1, -1,
201 -1, -1, -1, -1, -1, -1, -1, -1, /* k0 ... k7 (AVX512) */
202 -1, -1, -1, -1, -1, -1, -1, -1, /* zmm0 ... zmm31 (AVX512) */
203 -1, -1, -1, -1, -1, -1, -1, -1,
204 -1, -1, -1, -1, -1, -1, -1, -1,
205 -1, -1, -1, -1, -1, -1, -1, -1,
209 #define X86_64_NUM_REGS (sizeof (x86_64_regmap) / sizeof (x86_64_regmap[0]))
210 #define X86_64_USER_REGS (GS + 1)
212 #else /* ! __x86_64__ */
214 /* Mapping between the general-purpose registers in `struct user'
215 format and GDB's register array layout. */
216 static /*const*/ int i386_regmap
[] =
218 EAX
* 4, ECX
* 4, EDX
* 4, EBX
* 4,
219 UESP
* 4, EBP
* 4, ESI
* 4, EDI
* 4,
220 EIP
* 4, EFL
* 4, CS
* 4, SS
* 4,
221 DS
* 4, ES
* 4, FS
* 4, GS
* 4
224 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0]))
232 /* Returns true if the current inferior belongs to a x86-64 process,
236 is_64bit_tdesc (void)
238 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
240 return register_size (regcache
->tdesc
, 0) == 8;
246 /* Called by libthread_db. */
249 ps_get_thread_area (struct ps_prochandle
*ph
,
250 lwpid_t lwpid
, int idx
, void **base
)
253 int use_64bit
= is_64bit_tdesc ();
260 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, base
, ARCH_GET_FS
) == 0)
264 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, base
, ARCH_GET_GS
) == 0)
275 unsigned int desc
[4];
277 if (ptrace (PTRACE_GET_THREAD_AREA
, lwpid
,
278 (void *) (intptr_t) idx
, (unsigned long) &desc
) < 0)
281 /* Ensure we properly extend the value to 64-bits for x86_64. */
282 *base
= (void *) (uintptr_t) desc
[1];
287 /* Get the thread area address. This is used to recognize which
288 thread is which when tracing with the in-process agent library. We
289 don't read anything from the address, and treat it as opaque; it's
290 the address itself that we assume is unique per-thread. */
293 x86_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
296 int use_64bit
= is_64bit_tdesc ();
301 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_FS
) == 0)
303 *addr
= (CORE_ADDR
) (uintptr_t) base
;
312 struct lwp_info
*lwp
= find_lwp_pid (ptid_t (lwpid
));
313 struct thread_info
*thr
= get_lwp_thread (lwp
);
314 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
315 unsigned int desc
[4];
317 const int reg_thread_area
= 3; /* bits to scale down register value. */
320 collect_register_by_name (regcache
, "gs", &gs
);
322 idx
= gs
>> reg_thread_area
;
324 if (ptrace (PTRACE_GET_THREAD_AREA
,
326 (void *) (long) idx
, (unsigned long) &desc
) < 0)
337 x86_target::low_cannot_store_register (int regno
)
340 if (is_64bit_tdesc ())
344 return regno
>= I386_NUM_REGS
;
348 x86_target::low_cannot_fetch_register (int regno
)
351 if (is_64bit_tdesc ())
355 return regno
>= I386_NUM_REGS
;
359 x86_fill_gregset (struct regcache
*regcache
, void *buf
)
364 if (register_size (regcache
->tdesc
, 0) == 8)
366 for (i
= 0; i
< X86_64_NUM_REGS
; i
++)
367 if (x86_64_regmap
[i
] != -1)
368 collect_register (regcache
, i
, ((char *) buf
) + x86_64_regmap
[i
]);
370 #ifndef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE
373 int lwpid
= lwpid_of (current_thread
);
375 collect_register_by_name (regcache
, "fs_base", &base
);
376 ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_SET_FS
);
378 collect_register_by_name (regcache
, "gs_base", &base
);
379 ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_SET_GS
);
386 /* 32-bit inferior registers need to be zero-extended.
387 Callers would read uninitialized memory otherwise. */
388 memset (buf
, 0x00, X86_64_USER_REGS
* 8);
391 for (i
= 0; i
< I386_NUM_REGS
; i
++)
392 collect_register (regcache
, i
, ((char *) buf
) + i386_regmap
[i
]);
394 collect_register_by_name (regcache
, "orig_eax",
395 ((char *) buf
) + ORIG_EAX
* REGSIZE
);
398 /* Sign extend EAX value to avoid potential syscall restart
401 See amd64_linux_collect_native_gregset() in gdb/amd64-linux-nat.c
402 for a detailed explanation. */
403 if (register_size (regcache
->tdesc
, 0) == 4)
405 void *ptr
= ((gdb_byte
*) buf
406 + i386_regmap
[find_regno (regcache
->tdesc
, "eax")]);
408 *(int64_t *) ptr
= *(int32_t *) ptr
;
414 x86_store_gregset (struct regcache
*regcache
, const void *buf
)
419 if (register_size (regcache
->tdesc
, 0) == 8)
421 for (i
= 0; i
< X86_64_NUM_REGS
; i
++)
422 if (x86_64_regmap
[i
] != -1)
423 supply_register (regcache
, i
, ((char *) buf
) + x86_64_regmap
[i
]);
425 #ifndef HAVE_STRUCT_USER_REGS_STRUCT_FS_BASE
428 int lwpid
= lwpid_of (current_thread
);
430 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_FS
) == 0)
431 supply_register_by_name (regcache
, "fs_base", &base
);
433 if (ptrace (PTRACE_ARCH_PRCTL
, lwpid
, &base
, ARCH_GET_GS
) == 0)
434 supply_register_by_name (regcache
, "gs_base", &base
);
441 for (i
= 0; i
< I386_NUM_REGS
; i
++)
442 supply_register (regcache
, i
, ((char *) buf
) + i386_regmap
[i
]);
444 supply_register_by_name (regcache
, "orig_eax",
445 ((char *) buf
) + ORIG_EAX
* REGSIZE
);
449 x86_fill_fpregset (struct regcache
*regcache
, void *buf
)
452 i387_cache_to_fxsave (regcache
, buf
);
454 i387_cache_to_fsave (regcache
, buf
);
459 x86_store_fpregset (struct regcache
*regcache
, const void *buf
)
462 i387_fxsave_to_cache (regcache
, buf
);
464 i387_fsave_to_cache (regcache
, buf
);
471 x86_fill_fpxregset (struct regcache
*regcache
, void *buf
)
473 i387_cache_to_fxsave (regcache
, buf
);
477 x86_store_fpxregset (struct regcache
*regcache
, const void *buf
)
479 i387_fxsave_to_cache (regcache
, buf
);
485 x86_fill_xstateregset (struct regcache
*regcache
, void *buf
)
487 i387_cache_to_xsave (regcache
, buf
);
491 x86_store_xstateregset (struct regcache
*regcache
, const void *buf
)
493 i387_xsave_to_cache (regcache
, buf
);
496 /* ??? The non-biarch i386 case stores all the i387 regs twice.
497 Once in i387_.*fsave.* and once in i387_.*fxsave.*.
498 This is, presumably, to handle the case where PTRACE_[GS]ETFPXREGS
499 doesn't work. IWBN to avoid the duplication in the case where it
500 does work. Maybe the arch_setup routine could check whether it works
501 and update the supported regsets accordingly. */
503 static struct regset_info x86_regsets
[] =
505 #ifdef HAVE_PTRACE_GETREGS
506 { PTRACE_GETREGS
, PTRACE_SETREGS
, 0, sizeof (elf_gregset_t
),
508 x86_fill_gregset
, x86_store_gregset
},
509 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_X86_XSTATE
, 0,
510 EXTENDED_REGS
, x86_fill_xstateregset
, x86_store_xstateregset
},
512 # ifdef HAVE_PTRACE_GETFPXREGS
513 { PTRACE_GETFPXREGS
, PTRACE_SETFPXREGS
, 0, sizeof (elf_fpxregset_t
),
515 x86_fill_fpxregset
, x86_store_fpxregset
},
518 { PTRACE_GETFPREGS
, PTRACE_SETFPREGS
, 0, sizeof (elf_fpregset_t
),
520 x86_fill_fpregset
, x86_store_fpregset
},
521 #endif /* HAVE_PTRACE_GETREGS */
526 x86_target::low_supports_breakpoints ()
532 x86_target::low_get_pc (regcache
*regcache
)
534 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
540 collect_register_by_name (regcache
, "rip", &pc
);
541 return (CORE_ADDR
) pc
;
547 collect_register_by_name (regcache
, "eip", &pc
);
548 return (CORE_ADDR
) pc
;
553 x86_target::low_set_pc (regcache
*regcache
, CORE_ADDR pc
)
555 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
561 supply_register_by_name (regcache
, "rip", &newpc
);
567 supply_register_by_name (regcache
, "eip", &newpc
);
572 x86_target::low_decr_pc_after_break ()
578 static const gdb_byte x86_breakpoint
[] = { 0xCC };
579 #define x86_breakpoint_len 1
582 x86_target::low_breakpoint_at (CORE_ADDR pc
)
586 read_memory (pc
, &c
, 1);
593 /* Low-level function vector. */
594 struct x86_dr_low_type x86_dr_low
=
596 x86_linux_dr_set_control
,
597 x86_linux_dr_set_addr
,
598 x86_linux_dr_get_addr
,
599 x86_linux_dr_get_status
,
600 x86_linux_dr_get_control
,
604 /* Breakpoint/Watchpoint support. */
607 x86_target::supports_z_point_type (char z_type
)
613 case Z_PACKET_WRITE_WP
:
614 case Z_PACKET_ACCESS_WP
:
622 x86_target::low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
623 int size
, raw_breakpoint
*bp
)
625 struct process_info
*proc
= current_process ();
629 case raw_bkpt_type_hw
:
630 case raw_bkpt_type_write_wp
:
631 case raw_bkpt_type_access_wp
:
633 enum target_hw_bp_type hw_type
634 = raw_bkpt_type_to_target_hw_bp_type (type
);
635 struct x86_debug_reg_state
*state
636 = &proc
->priv
->arch_private
->debug_reg_state
;
638 return x86_dr_insert_watchpoint (state
, hw_type
, addr
, size
);
648 x86_target::low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
649 int size
, raw_breakpoint
*bp
)
651 struct process_info
*proc
= current_process ();
655 case raw_bkpt_type_hw
:
656 case raw_bkpt_type_write_wp
:
657 case raw_bkpt_type_access_wp
:
659 enum target_hw_bp_type hw_type
660 = raw_bkpt_type_to_target_hw_bp_type (type
);
661 struct x86_debug_reg_state
*state
662 = &proc
->priv
->arch_private
->debug_reg_state
;
664 return x86_dr_remove_watchpoint (state
, hw_type
, addr
, size
);
673 x86_target::low_stopped_by_watchpoint ()
675 struct process_info
*proc
= current_process ();
676 return x86_dr_stopped_by_watchpoint (&proc
->priv
->arch_private
->debug_reg_state
);
680 x86_target::low_stopped_data_address ()
682 struct process_info
*proc
= current_process ();
684 if (x86_dr_stopped_data_address (&proc
->priv
->arch_private
->debug_reg_state
,
690 /* Called when a new process is created. */
692 static struct arch_process_info
*
693 x86_linux_new_process (void)
695 struct arch_process_info
*info
= XCNEW (struct arch_process_info
);
697 x86_low_init_dregs (&info
->debug_reg_state
);
702 /* Called when a process is being deleted. */
705 x86_linux_delete_process (struct arch_process_info
*info
)
710 /* Target routine for linux_new_fork. */
713 x86_linux_new_fork (struct process_info
*parent
, struct process_info
*child
)
715 /* These are allocated by linux_add_process. */
716 gdb_assert (parent
->priv
!= NULL
717 && parent
->priv
->arch_private
!= NULL
);
718 gdb_assert (child
->priv
!= NULL
719 && child
->priv
->arch_private
!= NULL
);
721 /* Linux kernel before 2.6.33 commit
722 72f674d203cd230426437cdcf7dd6f681dad8b0d
723 will inherit hardware debug registers from parent
724 on fork/vfork/clone. Newer Linux kernels create such tasks with
725 zeroed debug registers.
727 GDB core assumes the child inherits the watchpoints/hw
728 breakpoints of the parent, and will remove them all from the
729 forked off process. Copy the debug registers mirrors into the
730 new process so that all breakpoints and watchpoints can be
731 removed together. The debug registers mirror will become zeroed
732 in the end before detaching the forked off process, thus making
733 this compatible with older Linux kernels too. */
735 *child
->priv
->arch_private
= *parent
->priv
->arch_private
;
738 /* See nat/x86-dregs.h. */
740 struct x86_debug_reg_state
*
741 x86_debug_reg_state (pid_t pid
)
743 struct process_info
*proc
= find_process_pid (pid
);
745 return &proc
->priv
->arch_private
->debug_reg_state
;
748 /* When GDBSERVER is built as a 64-bit application on linux, the
749 PTRACE_GETSIGINFO data is always presented in 64-bit layout. Since
750 debugging a 32-bit inferior with a 64-bit GDBSERVER should look the same
751 as debugging it with a 32-bit GDBSERVER, we do the 32-bit <-> 64-bit
752 conversion in-place ourselves. */
754 /* Convert a ptrace/host siginfo object, into/from the siginfo in the
755 layout of the inferiors' architecture. Returns true if any
756 conversion was done; false otherwise. If DIRECTION is 1, then copy
757 from INF to PTRACE. If DIRECTION is 0, copy from PTRACE to
761 x86_siginfo_fixup (siginfo_t
*ptrace
, gdb_byte
*inf
, int direction
)
764 unsigned int machine
;
765 int tid
= lwpid_of (current_thread
);
766 int is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
768 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
769 if (!is_64bit_tdesc ())
770 return amd64_linux_siginfo_fixup_common (ptrace
, inf
, direction
,
772 /* No fixup for native x32 GDB. */
773 else if (!is_elf64
&& sizeof (void *) == 8)
774 return amd64_linux_siginfo_fixup_common (ptrace
, inf
, direction
,
783 /* Format of XSAVE extended state is:
787 sw_usable_bytes[464..511]
788 xstate_hdr_bytes[512..575]
793 Same memory layout will be used for the coredump NT_X86_XSTATE
794 representing the XSAVE extended state registers.
796 The first 8 bytes of the sw_usable_bytes[464..467] is the OS enabled
797 extended state mask, which is the same as the extended control register
798 0 (the XFEATURE_ENABLED_MASK register), XCR0. We can use this mask
799 together with the mask saved in the xstate_hdr_bytes to determine what
800 states the processor/OS supports and what state, used or initialized,
801 the process/thread is in. */
802 #define I386_LINUX_XSAVE_XCR0_OFFSET 464
804 /* Does the current host support the GETFPXREGS request? The header
805 file may or may not define it, and even if it is defined, the
806 kernel will return EIO if it's running on a pre-SSE processor. */
807 int have_ptrace_getfpxregs
=
808 #ifdef HAVE_PTRACE_GETFPXREGS
815 /* Get Linux/x86 target description from running target. */
817 static const struct target_desc
*
818 x86_linux_read_description (void)
820 unsigned int machine
;
824 static uint64_t xcr0
;
825 struct regset_info
*regset
;
827 tid
= lwpid_of (current_thread
);
829 is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
831 if (sizeof (void *) == 4)
834 error (_("Can't debug 64-bit process with 32-bit GDBserver"));
836 else if (machine
== EM_X86_64
)
837 error (_("Can't debug x86-64 process with 32-bit GDBserver"));
841 #if !defined __x86_64__ && defined HAVE_PTRACE_GETFPXREGS
842 if (machine
== EM_386
&& have_ptrace_getfpxregs
== -1)
844 elf_fpxregset_t fpxregs
;
846 if (ptrace (PTRACE_GETFPXREGS
, tid
, 0, (long) &fpxregs
) < 0)
848 have_ptrace_getfpxregs
= 0;
849 have_ptrace_getregset
= 0;
850 return i386_linux_read_description (X86_XSTATE_X87
);
853 have_ptrace_getfpxregs
= 1;
859 x86_xcr0
= X86_XSTATE_SSE_MASK
;
863 if (machine
== EM_X86_64
)
864 return tdesc_amd64_linux_no_xml
;
867 return tdesc_i386_linux_no_xml
;
870 if (have_ptrace_getregset
== -1)
872 uint64_t xstateregs
[(X86_XSTATE_SSE_SIZE
/ sizeof (uint64_t))];
875 iov
.iov_base
= xstateregs
;
876 iov
.iov_len
= sizeof (xstateregs
);
878 /* Check if PTRACE_GETREGSET works. */
879 if (ptrace (PTRACE_GETREGSET
, tid
,
880 (unsigned int) NT_X86_XSTATE
, (long) &iov
) < 0)
881 have_ptrace_getregset
= 0;
884 have_ptrace_getregset
= 1;
886 /* Get XCR0 from XSAVE extended state. */
887 xcr0
= xstateregs
[(I386_LINUX_XSAVE_XCR0_OFFSET
888 / sizeof (uint64_t))];
890 /* Use PTRACE_GETREGSET if it is available. */
891 for (regset
= x86_regsets
;
892 regset
->fill_function
!= NULL
; regset
++)
893 if (regset
->get_request
== PTRACE_GETREGSET
)
894 regset
->size
= X86_XSTATE_SIZE (xcr0
);
895 else if (regset
->type
!= GENERAL_REGS
)
900 /* Check the native XCR0 only if PTRACE_GETREGSET is available. */
901 xcr0_features
= (have_ptrace_getregset
902 && (xcr0
& X86_XSTATE_ALL_MASK
));
907 if (machine
== EM_X86_64
)
910 const target_desc
*tdesc
= NULL
;
914 tdesc
= amd64_linux_read_description (xcr0
& X86_XSTATE_ALL_MASK
,
919 tdesc
= amd64_linux_read_description (X86_XSTATE_SSE_MASK
, !is_elf64
);
925 const target_desc
*tdesc
= NULL
;
928 tdesc
= i386_linux_read_description (xcr0
& X86_XSTATE_ALL_MASK
);
931 tdesc
= i386_linux_read_description (X86_XSTATE_SSE
);
936 gdb_assert_not_reached ("failed to return tdesc");
939 /* Update all the target description of all processes; a new GDB
940 connected, and it may or not support xml target descriptions. */
943 x86_target::update_xmltarget ()
945 struct thread_info
*saved_thread
= current_thread
;
947 /* Before changing the register cache's internal layout, flush the
948 contents of the current valid caches back to the threads, and
949 release the current regcache objects. */
952 for_each_process ([this] (process_info
*proc
) {
955 /* Look up any thread of this process. */
956 current_thread
= find_any_thread_of_pid (pid
);
961 current_thread
= saved_thread
;
964 /* Process qSupported query, "xmlRegisters=". Update the buffer size for
968 x86_linux_process_qsupported (char **features
, int count
)
972 /* Return if gdb doesn't support XML. If gdb sends "xmlRegisters="
973 with "i386" in qSupported query, it supports x86 XML target
976 for (i
= 0; i
< count
; i
++)
978 const char *feature
= features
[i
];
980 if (startswith (feature
, "xmlRegisters="))
982 char *copy
= xstrdup (feature
+ 13);
985 for (char *p
= strtok_r (copy
, ",", &saveptr
);
987 p
= strtok_r (NULL
, ",", &saveptr
))
989 if (strcmp (p
, "i386") == 0)
999 the_x86_target
.update_xmltarget ();
1002 /* Common for x86/x86-64. */
1004 static struct regsets_info x86_regsets_info
=
1006 x86_regsets
, /* regsets */
1007 0, /* num_regsets */
1008 NULL
, /* disabled_regsets */
1012 static struct regs_info amd64_linux_regs_info
=
1014 NULL
, /* regset_bitmap */
1015 NULL
, /* usrregs_info */
1019 static struct usrregs_info i386_linux_usrregs_info
=
1025 static struct regs_info i386_linux_regs_info
=
1027 NULL
, /* regset_bitmap */
1028 &i386_linux_usrregs_info
,
1033 x86_target::get_regs_info ()
1036 if (is_64bit_tdesc ())
1037 return &amd64_linux_regs_info
;
1040 return &i386_linux_regs_info
;
1043 /* Initialize the target description for the architecture of the
1047 x86_target::low_arch_setup ()
1049 current_process ()->tdesc
= x86_linux_read_description ();
1052 /* Fill *SYSNO and *SYSRET with the syscall nr trapped and the syscall return
1053 code. This should only be called if LWP got a SYSCALL_SIGTRAP. */
1056 x86_get_syscall_trapinfo (struct regcache
*regcache
, int *sysno
)
1058 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
1064 collect_register_by_name (regcache
, "orig_rax", &l_sysno
);
1065 *sysno
= (int) l_sysno
;
1068 collect_register_by_name (regcache
, "orig_eax", sysno
);
1072 x86_supports_tracepoints (void)
1078 append_insns (CORE_ADDR
*to
, size_t len
, const unsigned char *buf
)
1080 target_write_memory (*to
, buf
, len
);
1085 push_opcode (unsigned char *buf
, const char *op
)
1087 unsigned char *buf_org
= buf
;
1092 unsigned long ul
= strtoul (op
, &endptr
, 16);
1101 return buf
- buf_org
;
1106 /* Build a jump pad that saves registers and calls a collection
1107 function. Writes a jump instruction to the jump pad to
1108 JJUMPAD_INSN. The caller is responsible to write it in at the
1109 tracepoint address. */
1112 amd64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1113 CORE_ADDR collector
,
1116 CORE_ADDR
*jump_entry
,
1117 CORE_ADDR
*trampoline
,
1118 ULONGEST
*trampoline_size
,
1119 unsigned char *jjump_pad_insn
,
1120 ULONGEST
*jjump_pad_insn_size
,
1121 CORE_ADDR
*adjusted_insn_addr
,
1122 CORE_ADDR
*adjusted_insn_addr_end
,
1125 unsigned char buf
[40];
1129 CORE_ADDR buildaddr
= *jump_entry
;
1131 /* Build the jump pad. */
1133 /* First, do tracepoint data collection. Save registers. */
1135 /* Need to ensure stack pointer saved first. */
1136 buf
[i
++] = 0x54; /* push %rsp */
1137 buf
[i
++] = 0x55; /* push %rbp */
1138 buf
[i
++] = 0x57; /* push %rdi */
1139 buf
[i
++] = 0x56; /* push %rsi */
1140 buf
[i
++] = 0x52; /* push %rdx */
1141 buf
[i
++] = 0x51; /* push %rcx */
1142 buf
[i
++] = 0x53; /* push %rbx */
1143 buf
[i
++] = 0x50; /* push %rax */
1144 buf
[i
++] = 0x41; buf
[i
++] = 0x57; /* push %r15 */
1145 buf
[i
++] = 0x41; buf
[i
++] = 0x56; /* push %r14 */
1146 buf
[i
++] = 0x41; buf
[i
++] = 0x55; /* push %r13 */
1147 buf
[i
++] = 0x41; buf
[i
++] = 0x54; /* push %r12 */
1148 buf
[i
++] = 0x41; buf
[i
++] = 0x53; /* push %r11 */
1149 buf
[i
++] = 0x41; buf
[i
++] = 0x52; /* push %r10 */
1150 buf
[i
++] = 0x41; buf
[i
++] = 0x51; /* push %r9 */
1151 buf
[i
++] = 0x41; buf
[i
++] = 0x50; /* push %r8 */
1152 buf
[i
++] = 0x9c; /* pushfq */
1153 buf
[i
++] = 0x48; /* movabs <addr>,%rdi */
1155 memcpy (buf
+ i
, &tpaddr
, 8);
1157 buf
[i
++] = 0x57; /* push %rdi */
1158 append_insns (&buildaddr
, i
, buf
);
1160 /* Stack space for the collecting_t object. */
1162 i
+= push_opcode (&buf
[i
], "48 83 ec 18"); /* sub $0x18,%rsp */
1163 i
+= push_opcode (&buf
[i
], "48 b8"); /* mov <tpoint>,%rax */
1164 memcpy (buf
+ i
, &tpoint
, 8);
1166 i
+= push_opcode (&buf
[i
], "48 89 04 24"); /* mov %rax,(%rsp) */
1167 i
+= push_opcode (&buf
[i
],
1168 "64 48 8b 04 25 00 00 00 00"); /* mov %fs:0x0,%rax */
1169 i
+= push_opcode (&buf
[i
], "48 89 44 24 08"); /* mov %rax,0x8(%rsp) */
1170 append_insns (&buildaddr
, i
, buf
);
1174 i
+= push_opcode (&buf
[i
], "48 be"); /* movl <lockaddr>,%rsi */
1175 memcpy (&buf
[i
], (void *) &lockaddr
, 8);
1177 i
+= push_opcode (&buf
[i
], "48 89 e1"); /* mov %rsp,%rcx */
1178 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1179 i
+= push_opcode (&buf
[i
], "f0 48 0f b1 0e"); /* lock cmpxchg %rcx,(%rsi) */
1180 i
+= push_opcode (&buf
[i
], "48 85 c0"); /* test %rax,%rax */
1181 i
+= push_opcode (&buf
[i
], "75 f4"); /* jne <again> */
1182 append_insns (&buildaddr
, i
, buf
);
1184 /* Set up the gdb_collect call. */
1185 /* At this point, (stack pointer + 0x18) is the base of our saved
1189 i
+= push_opcode (&buf
[i
], "48 89 e6"); /* mov %rsp,%rsi */
1190 i
+= push_opcode (&buf
[i
], "48 83 c6 18"); /* add $0x18,%rsi */
1192 /* tpoint address may be 64-bit wide. */
1193 i
+= push_opcode (&buf
[i
], "48 bf"); /* movl <addr>,%rdi */
1194 memcpy (buf
+ i
, &tpoint
, 8);
1196 append_insns (&buildaddr
, i
, buf
);
1198 /* The collector function being in the shared library, may be
1199 >31-bits away off the jump pad. */
1201 i
+= push_opcode (&buf
[i
], "48 b8"); /* mov $collector,%rax */
1202 memcpy (buf
+ i
, &collector
, 8);
1204 i
+= push_opcode (&buf
[i
], "ff d0"); /* callq *%rax */
1205 append_insns (&buildaddr
, i
, buf
);
1207 /* Clear the spin-lock. */
1209 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1210 i
+= push_opcode (&buf
[i
], "48 a3"); /* mov %rax, lockaddr */
1211 memcpy (buf
+ i
, &lockaddr
, 8);
1213 append_insns (&buildaddr
, i
, buf
);
1215 /* Remove stack that had been used for the collect_t object. */
1217 i
+= push_opcode (&buf
[i
], "48 83 c4 18"); /* add $0x18,%rsp */
1218 append_insns (&buildaddr
, i
, buf
);
1220 /* Restore register state. */
1222 buf
[i
++] = 0x48; /* add $0x8,%rsp */
1226 buf
[i
++] = 0x9d; /* popfq */
1227 buf
[i
++] = 0x41; buf
[i
++] = 0x58; /* pop %r8 */
1228 buf
[i
++] = 0x41; buf
[i
++] = 0x59; /* pop %r9 */
1229 buf
[i
++] = 0x41; buf
[i
++] = 0x5a; /* pop %r10 */
1230 buf
[i
++] = 0x41; buf
[i
++] = 0x5b; /* pop %r11 */
1231 buf
[i
++] = 0x41; buf
[i
++] = 0x5c; /* pop %r12 */
1232 buf
[i
++] = 0x41; buf
[i
++] = 0x5d; /* pop %r13 */
1233 buf
[i
++] = 0x41; buf
[i
++] = 0x5e; /* pop %r14 */
1234 buf
[i
++] = 0x41; buf
[i
++] = 0x5f; /* pop %r15 */
1235 buf
[i
++] = 0x58; /* pop %rax */
1236 buf
[i
++] = 0x5b; /* pop %rbx */
1237 buf
[i
++] = 0x59; /* pop %rcx */
1238 buf
[i
++] = 0x5a; /* pop %rdx */
1239 buf
[i
++] = 0x5e; /* pop %rsi */
1240 buf
[i
++] = 0x5f; /* pop %rdi */
1241 buf
[i
++] = 0x5d; /* pop %rbp */
1242 buf
[i
++] = 0x5c; /* pop %rsp */
1243 append_insns (&buildaddr
, i
, buf
);
1245 /* Now, adjust the original instruction to execute in the jump
1247 *adjusted_insn_addr
= buildaddr
;
1248 relocate_instruction (&buildaddr
, tpaddr
);
1249 *adjusted_insn_addr_end
= buildaddr
;
1251 /* Finally, write a jump back to the program. */
1253 loffset
= (tpaddr
+ orig_size
) - (buildaddr
+ sizeof (jump_insn
));
1254 if (loffset
> INT_MAX
|| loffset
< INT_MIN
)
1257 "E.Jump back from jump pad too far from tracepoint "
1258 "(offset 0x%" PRIx64
" > int32).", loffset
);
1262 offset
= (int) loffset
;
1263 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1264 memcpy (buf
+ 1, &offset
, 4);
1265 append_insns (&buildaddr
, sizeof (jump_insn
), buf
);
1267 /* The jump pad is now built. Wire in a jump to our jump pad. This
1268 is always done last (by our caller actually), so that we can
1269 install fast tracepoints with threads running. This relies on
1270 the agent's atomic write support. */
1271 loffset
= *jump_entry
- (tpaddr
+ sizeof (jump_insn
));
1272 if (loffset
> INT_MAX
|| loffset
< INT_MIN
)
1275 "E.Jump pad too far from tracepoint "
1276 "(offset 0x%" PRIx64
" > int32).", loffset
);
1280 offset
= (int) loffset
;
1282 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1283 memcpy (buf
+ 1, &offset
, 4);
1284 memcpy (jjump_pad_insn
, buf
, sizeof (jump_insn
));
1285 *jjump_pad_insn_size
= sizeof (jump_insn
);
1287 /* Return the end address of our pad. */
1288 *jump_entry
= buildaddr
;
1293 #endif /* __x86_64__ */
1295 /* Build a jump pad that saves registers and calls a collection
1296 function. Writes a jump instruction to the jump pad to
1297 JJUMPAD_INSN. The caller is responsible to write it in at the
1298 tracepoint address. */
1301 i386_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1302 CORE_ADDR collector
,
1305 CORE_ADDR
*jump_entry
,
1306 CORE_ADDR
*trampoline
,
1307 ULONGEST
*trampoline_size
,
1308 unsigned char *jjump_pad_insn
,
1309 ULONGEST
*jjump_pad_insn_size
,
1310 CORE_ADDR
*adjusted_insn_addr
,
1311 CORE_ADDR
*adjusted_insn_addr_end
,
1314 unsigned char buf
[0x100];
1316 CORE_ADDR buildaddr
= *jump_entry
;
1318 /* Build the jump pad. */
1320 /* First, do tracepoint data collection. Save registers. */
1322 buf
[i
++] = 0x60; /* pushad */
1323 buf
[i
++] = 0x68; /* push tpaddr aka $pc */
1324 *((int *)(buf
+ i
)) = (int) tpaddr
;
1326 buf
[i
++] = 0x9c; /* pushf */
1327 buf
[i
++] = 0x1e; /* push %ds */
1328 buf
[i
++] = 0x06; /* push %es */
1329 buf
[i
++] = 0x0f; /* push %fs */
1331 buf
[i
++] = 0x0f; /* push %gs */
1333 buf
[i
++] = 0x16; /* push %ss */
1334 buf
[i
++] = 0x0e; /* push %cs */
1335 append_insns (&buildaddr
, i
, buf
);
1337 /* Stack space for the collecting_t object. */
1339 i
+= push_opcode (&buf
[i
], "83 ec 08"); /* sub $0x8,%esp */
1341 /* Build the object. */
1342 i
+= push_opcode (&buf
[i
], "b8"); /* mov <tpoint>,%eax */
1343 memcpy (buf
+ i
, &tpoint
, 4);
1345 i
+= push_opcode (&buf
[i
], "89 04 24"); /* mov %eax,(%esp) */
1347 i
+= push_opcode (&buf
[i
], "65 a1 00 00 00 00"); /* mov %gs:0x0,%eax */
1348 i
+= push_opcode (&buf
[i
], "89 44 24 04"); /* mov %eax,0x4(%esp) */
1349 append_insns (&buildaddr
, i
, buf
);
1351 /* spin-lock. Note this is using cmpxchg, which leaves i386 behind.
1352 If we cared for it, this could be using xchg alternatively. */
1355 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1356 i
+= push_opcode (&buf
[i
], "f0 0f b1 25"); /* lock cmpxchg
1358 memcpy (&buf
[i
], (void *) &lockaddr
, 4);
1360 i
+= push_opcode (&buf
[i
], "85 c0"); /* test %eax,%eax */
1361 i
+= push_opcode (&buf
[i
], "75 f2"); /* jne <again> */
1362 append_insns (&buildaddr
, i
, buf
);
1365 /* Set up arguments to the gdb_collect call. */
1367 i
+= push_opcode (&buf
[i
], "89 e0"); /* mov %esp,%eax */
1368 i
+= push_opcode (&buf
[i
], "83 c0 08"); /* add $0x08,%eax */
1369 i
+= push_opcode (&buf
[i
], "89 44 24 fc"); /* mov %eax,-0x4(%esp) */
1370 append_insns (&buildaddr
, i
, buf
);
1373 i
+= push_opcode (&buf
[i
], "83 ec 08"); /* sub $0x8,%esp */
1374 append_insns (&buildaddr
, i
, buf
);
1377 i
+= push_opcode (&buf
[i
], "c7 04 24"); /* movl <addr>,(%esp) */
1378 memcpy (&buf
[i
], (void *) &tpoint
, 4);
1380 append_insns (&buildaddr
, i
, buf
);
1382 buf
[0] = 0xe8; /* call <reladdr> */
1383 offset
= collector
- (buildaddr
+ sizeof (jump_insn
));
1384 memcpy (buf
+ 1, &offset
, 4);
1385 append_insns (&buildaddr
, 5, buf
);
1386 /* Clean up after the call. */
1387 buf
[0] = 0x83; /* add $0x8,%esp */
1390 append_insns (&buildaddr
, 3, buf
);
1393 /* Clear the spin-lock. This would need the LOCK prefix on older
1396 i
+= push_opcode (&buf
[i
], "31 c0"); /* xor %eax,%eax */
1397 i
+= push_opcode (&buf
[i
], "a3"); /* mov %eax, lockaddr */
1398 memcpy (buf
+ i
, &lockaddr
, 4);
1400 append_insns (&buildaddr
, i
, buf
);
1403 /* Remove stack that had been used for the collect_t object. */
1405 i
+= push_opcode (&buf
[i
], "83 c4 08"); /* add $0x08,%esp */
1406 append_insns (&buildaddr
, i
, buf
);
1409 buf
[i
++] = 0x83; /* add $0x4,%esp (no pop of %cs, assume unchanged) */
1412 buf
[i
++] = 0x17; /* pop %ss */
1413 buf
[i
++] = 0x0f; /* pop %gs */
1415 buf
[i
++] = 0x0f; /* pop %fs */
1417 buf
[i
++] = 0x07; /* pop %es */
1418 buf
[i
++] = 0x1f; /* pop %ds */
1419 buf
[i
++] = 0x9d; /* popf */
1420 buf
[i
++] = 0x83; /* add $0x4,%esp (pop of tpaddr aka $pc) */
1423 buf
[i
++] = 0x61; /* popad */
1424 append_insns (&buildaddr
, i
, buf
);
1426 /* Now, adjust the original instruction to execute in the jump
1428 *adjusted_insn_addr
= buildaddr
;
1429 relocate_instruction (&buildaddr
, tpaddr
);
1430 *adjusted_insn_addr_end
= buildaddr
;
1432 /* Write the jump back to the program. */
1433 offset
= (tpaddr
+ orig_size
) - (buildaddr
+ sizeof (jump_insn
));
1434 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1435 memcpy (buf
+ 1, &offset
, 4);
1436 append_insns (&buildaddr
, sizeof (jump_insn
), buf
);
1438 /* The jump pad is now built. Wire in a jump to our jump pad. This
1439 is always done last (by our caller actually), so that we can
1440 install fast tracepoints with threads running. This relies on
1441 the agent's atomic write support. */
1444 /* Create a trampoline. */
1445 *trampoline_size
= sizeof (jump_insn
);
1446 if (!claim_trampoline_space (*trampoline_size
, trampoline
))
1448 /* No trampoline space available. */
1450 "E.Cannot allocate trampoline space needed for fast "
1451 "tracepoints on 4-byte instructions.");
1455 offset
= *jump_entry
- (*trampoline
+ sizeof (jump_insn
));
1456 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1457 memcpy (buf
+ 1, &offset
, 4);
1458 target_write_memory (*trampoline
, buf
, sizeof (jump_insn
));
1460 /* Use a 16-bit relative jump instruction to jump to the trampoline. */
1461 offset
= (*trampoline
- (tpaddr
+ sizeof (small_jump_insn
))) & 0xffff;
1462 memcpy (buf
, small_jump_insn
, sizeof (small_jump_insn
));
1463 memcpy (buf
+ 2, &offset
, 2);
1464 memcpy (jjump_pad_insn
, buf
, sizeof (small_jump_insn
));
1465 *jjump_pad_insn_size
= sizeof (small_jump_insn
);
1469 /* Else use a 32-bit relative jump instruction. */
1470 offset
= *jump_entry
- (tpaddr
+ sizeof (jump_insn
));
1471 memcpy (buf
, jump_insn
, sizeof (jump_insn
));
1472 memcpy (buf
+ 1, &offset
, 4);
1473 memcpy (jjump_pad_insn
, buf
, sizeof (jump_insn
));
1474 *jjump_pad_insn_size
= sizeof (jump_insn
);
1477 /* Return the end address of our pad. */
1478 *jump_entry
= buildaddr
;
1484 x86_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
, CORE_ADDR tpaddr
,
1485 CORE_ADDR collector
,
1488 CORE_ADDR
*jump_entry
,
1489 CORE_ADDR
*trampoline
,
1490 ULONGEST
*trampoline_size
,
1491 unsigned char *jjump_pad_insn
,
1492 ULONGEST
*jjump_pad_insn_size
,
1493 CORE_ADDR
*adjusted_insn_addr
,
1494 CORE_ADDR
*adjusted_insn_addr_end
,
1498 if (is_64bit_tdesc ())
1499 return amd64_install_fast_tracepoint_jump_pad (tpoint
, tpaddr
,
1500 collector
, lockaddr
,
1501 orig_size
, jump_entry
,
1502 trampoline
, trampoline_size
,
1504 jjump_pad_insn_size
,
1506 adjusted_insn_addr_end
,
1510 return i386_install_fast_tracepoint_jump_pad (tpoint
, tpaddr
,
1511 collector
, lockaddr
,
1512 orig_size
, jump_entry
,
1513 trampoline
, trampoline_size
,
1515 jjump_pad_insn_size
,
1517 adjusted_insn_addr_end
,
1521 /* Return the minimum instruction length for fast tracepoints on x86/x86-64
1525 x86_get_min_fast_tracepoint_insn_len (void)
1527 static int warned_about_fast_tracepoints
= 0;
1530 /* On x86-64, 5-byte jump instructions with a 4-byte offset are always
1531 used for fast tracepoints. */
1532 if (is_64bit_tdesc ())
1536 if (agent_loaded_p ())
1538 char errbuf
[IPA_BUFSIZ
];
1542 /* On x86, if trampolines are available, then 4-byte jump instructions
1543 with a 2-byte offset may be used, otherwise 5-byte jump instructions
1544 with a 4-byte offset are used instead. */
1545 if (have_fast_tracepoint_trampoline_buffer (errbuf
))
1549 /* GDB has no channel to explain to user why a shorter fast
1550 tracepoint is not possible, but at least make GDBserver
1551 mention that something has gone awry. */
1552 if (!warned_about_fast_tracepoints
)
1554 warning ("4-byte fast tracepoints not available; %s", errbuf
);
1555 warned_about_fast_tracepoints
= 1;
1562 /* Indicate that the minimum length is currently unknown since the IPA
1563 has not loaded yet. */
1569 add_insns (unsigned char *start
, int len
)
1571 CORE_ADDR buildaddr
= current_insn_ptr
;
1574 debug_printf ("Adding %d bytes of insn at %s\n",
1575 len
, paddress (buildaddr
));
1577 append_insns (&buildaddr
, len
, start
);
1578 current_insn_ptr
= buildaddr
;
1581 /* Our general strategy for emitting code is to avoid specifying raw
1582 bytes whenever possible, and instead copy a block of inline asm
1583 that is embedded in the function. This is a little messy, because
1584 we need to keep the compiler from discarding what looks like dead
1585 code, plus suppress various warnings. */
1587 #define EMIT_ASM(NAME, INSNS) \
1590 extern unsigned char start_ ## NAME, end_ ## NAME; \
1591 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
1592 __asm__ ("jmp end_" #NAME "\n" \
1593 "\t" "start_" #NAME ":" \
1595 "\t" "end_" #NAME ":"); \
1600 #define EMIT_ASM32(NAME,INSNS) \
1603 extern unsigned char start_ ## NAME, end_ ## NAME; \
1604 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \
1605 __asm__ (".code32\n" \
1606 "\t" "jmp end_" #NAME "\n" \
1607 "\t" "start_" #NAME ":\n" \
1609 "\t" "end_" #NAME ":\n" \
1615 #define EMIT_ASM32(NAME,INSNS) EMIT_ASM(NAME,INSNS)
1622 amd64_emit_prologue (void)
1624 EMIT_ASM (amd64_prologue
,
1626 "movq %rsp,%rbp\n\t"
1627 "sub $0x20,%rsp\n\t"
1628 "movq %rdi,-8(%rbp)\n\t"
1629 "movq %rsi,-16(%rbp)");
1634 amd64_emit_epilogue (void)
1636 EMIT_ASM (amd64_epilogue
,
1637 "movq -16(%rbp),%rdi\n\t"
1638 "movq %rax,(%rdi)\n\t"
1645 amd64_emit_add (void)
1647 EMIT_ASM (amd64_add
,
1648 "add (%rsp),%rax\n\t"
1649 "lea 0x8(%rsp),%rsp");
1653 amd64_emit_sub (void)
1655 EMIT_ASM (amd64_sub
,
1656 "sub %rax,(%rsp)\n\t"
1661 amd64_emit_mul (void)
1667 amd64_emit_lsh (void)
1673 amd64_emit_rsh_signed (void)
1679 amd64_emit_rsh_unsigned (void)
1685 amd64_emit_ext (int arg
)
1690 EMIT_ASM (amd64_ext_8
,
1696 EMIT_ASM (amd64_ext_16
,
1701 EMIT_ASM (amd64_ext_32
,
1710 amd64_emit_log_not (void)
1712 EMIT_ASM (amd64_log_not
,
1713 "test %rax,%rax\n\t"
1719 amd64_emit_bit_and (void)
1721 EMIT_ASM (amd64_and
,
1722 "and (%rsp),%rax\n\t"
1723 "lea 0x8(%rsp),%rsp");
1727 amd64_emit_bit_or (void)
1730 "or (%rsp),%rax\n\t"
1731 "lea 0x8(%rsp),%rsp");
1735 amd64_emit_bit_xor (void)
1737 EMIT_ASM (amd64_xor
,
1738 "xor (%rsp),%rax\n\t"
1739 "lea 0x8(%rsp),%rsp");
1743 amd64_emit_bit_not (void)
1745 EMIT_ASM (amd64_bit_not
,
1746 "xorq $0xffffffffffffffff,%rax");
1750 amd64_emit_equal (void)
1752 EMIT_ASM (amd64_equal
,
1753 "cmp %rax,(%rsp)\n\t"
1754 "je .Lamd64_equal_true\n\t"
1756 "jmp .Lamd64_equal_end\n\t"
1757 ".Lamd64_equal_true:\n\t"
1759 ".Lamd64_equal_end:\n\t"
1760 "lea 0x8(%rsp),%rsp");
1764 amd64_emit_less_signed (void)
1766 EMIT_ASM (amd64_less_signed
,
1767 "cmp %rax,(%rsp)\n\t"
1768 "jl .Lamd64_less_signed_true\n\t"
1770 "jmp .Lamd64_less_signed_end\n\t"
1771 ".Lamd64_less_signed_true:\n\t"
1773 ".Lamd64_less_signed_end:\n\t"
1774 "lea 0x8(%rsp),%rsp");
1778 amd64_emit_less_unsigned (void)
1780 EMIT_ASM (amd64_less_unsigned
,
1781 "cmp %rax,(%rsp)\n\t"
1782 "jb .Lamd64_less_unsigned_true\n\t"
1784 "jmp .Lamd64_less_unsigned_end\n\t"
1785 ".Lamd64_less_unsigned_true:\n\t"
1787 ".Lamd64_less_unsigned_end:\n\t"
1788 "lea 0x8(%rsp),%rsp");
1792 amd64_emit_ref (int size
)
1797 EMIT_ASM (amd64_ref1
,
1801 EMIT_ASM (amd64_ref2
,
1805 EMIT_ASM (amd64_ref4
,
1806 "movl (%rax),%eax");
1809 EMIT_ASM (amd64_ref8
,
1810 "movq (%rax),%rax");
1816 amd64_emit_if_goto (int *offset_p
, int *size_p
)
1818 EMIT_ASM (amd64_if_goto
,
1822 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
1830 amd64_emit_goto (int *offset_p
, int *size_p
)
1832 EMIT_ASM (amd64_goto
,
1833 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
1841 amd64_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
1843 int diff
= (to
- (from
+ size
));
1844 unsigned char buf
[sizeof (int)];
1852 memcpy (buf
, &diff
, sizeof (int));
1853 target_write_memory (from
, buf
, sizeof (int));
1857 amd64_emit_const (LONGEST num
)
1859 unsigned char buf
[16];
1861 CORE_ADDR buildaddr
= current_insn_ptr
;
1864 buf
[i
++] = 0x48; buf
[i
++] = 0xb8; /* mov $<n>,%rax */
1865 memcpy (&buf
[i
], &num
, sizeof (num
));
1867 append_insns (&buildaddr
, i
, buf
);
1868 current_insn_ptr
= buildaddr
;
1872 amd64_emit_call (CORE_ADDR fn
)
1874 unsigned char buf
[16];
1876 CORE_ADDR buildaddr
;
1879 /* The destination function being in the shared library, may be
1880 >31-bits away off the compiled code pad. */
1882 buildaddr
= current_insn_ptr
;
1884 offset64
= fn
- (buildaddr
+ 1 /* call op */ + 4 /* 32-bit offset */);
1888 if (offset64
> INT_MAX
|| offset64
< INT_MIN
)
1890 /* Offset is too large for a call. Use callq, but that requires
1891 a register, so avoid it if possible. Use r10, since it is
1892 call-clobbered, we don't have to push/pop it. */
1893 buf
[i
++] = 0x48; /* mov $fn,%r10 */
1895 memcpy (buf
+ i
, &fn
, 8);
1897 buf
[i
++] = 0xff; /* callq *%r10 */
1902 int offset32
= offset64
; /* we know we can't overflow here. */
1904 buf
[i
++] = 0xe8; /* call <reladdr> */
1905 memcpy (buf
+ i
, &offset32
, 4);
1909 append_insns (&buildaddr
, i
, buf
);
1910 current_insn_ptr
= buildaddr
;
1914 amd64_emit_reg (int reg
)
1916 unsigned char buf
[16];
1918 CORE_ADDR buildaddr
;
1920 /* Assume raw_regs is still in %rdi. */
1921 buildaddr
= current_insn_ptr
;
1923 buf
[i
++] = 0xbe; /* mov $<n>,%esi */
1924 memcpy (&buf
[i
], ®
, sizeof (reg
));
1926 append_insns (&buildaddr
, i
, buf
);
1927 current_insn_ptr
= buildaddr
;
1928 amd64_emit_call (get_raw_reg_func_addr ());
1932 amd64_emit_pop (void)
1934 EMIT_ASM (amd64_pop
,
1939 amd64_emit_stack_flush (void)
1941 EMIT_ASM (amd64_stack_flush
,
1946 amd64_emit_zero_ext (int arg
)
1951 EMIT_ASM (amd64_zero_ext_8
,
1955 EMIT_ASM (amd64_zero_ext_16
,
1956 "and $0xffff,%rax");
1959 EMIT_ASM (amd64_zero_ext_32
,
1960 "mov $0xffffffff,%rcx\n\t"
1969 amd64_emit_swap (void)
1971 EMIT_ASM (amd64_swap
,
1978 amd64_emit_stack_adjust (int n
)
1980 unsigned char buf
[16];
1982 CORE_ADDR buildaddr
= current_insn_ptr
;
1985 buf
[i
++] = 0x48; /* lea $<n>(%rsp),%rsp */
1989 /* This only handles adjustments up to 16, but we don't expect any more. */
1991 append_insns (&buildaddr
, i
, buf
);
1992 current_insn_ptr
= buildaddr
;
1995 /* FN's prototype is `LONGEST(*fn)(int)'. */
1998 amd64_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2000 unsigned char buf
[16];
2002 CORE_ADDR buildaddr
;
2004 buildaddr
= current_insn_ptr
;
2006 buf
[i
++] = 0xbf; /* movl $<n>,%edi */
2007 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2009 append_insns (&buildaddr
, i
, buf
);
2010 current_insn_ptr
= buildaddr
;
2011 amd64_emit_call (fn
);
2014 /* FN's prototype is `void(*fn)(int,LONGEST)'. */
2017 amd64_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2019 unsigned char buf
[16];
2021 CORE_ADDR buildaddr
;
2023 buildaddr
= current_insn_ptr
;
2025 buf
[i
++] = 0xbf; /* movl $<n>,%edi */
2026 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2028 append_insns (&buildaddr
, i
, buf
);
2029 current_insn_ptr
= buildaddr
;
2030 EMIT_ASM (amd64_void_call_2_a
,
2031 /* Save away a copy of the stack top. */
2033 /* Also pass top as the second argument. */
2035 amd64_emit_call (fn
);
2036 EMIT_ASM (amd64_void_call_2_b
,
2037 /* Restore the stack top, %rax may have been trashed. */
2042 amd64_emit_eq_goto (int *offset_p
, int *size_p
)
2045 "cmp %rax,(%rsp)\n\t"
2046 "jne .Lamd64_eq_fallthru\n\t"
2047 "lea 0x8(%rsp),%rsp\n\t"
2049 /* jmp, but don't trust the assembler to choose the right jump */
2050 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2051 ".Lamd64_eq_fallthru:\n\t"
2052 "lea 0x8(%rsp),%rsp\n\t"
2062 amd64_emit_ne_goto (int *offset_p
, int *size_p
)
2065 "cmp %rax,(%rsp)\n\t"
2066 "je .Lamd64_ne_fallthru\n\t"
2067 "lea 0x8(%rsp),%rsp\n\t"
2069 /* jmp, but don't trust the assembler to choose the right jump */
2070 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2071 ".Lamd64_ne_fallthru:\n\t"
2072 "lea 0x8(%rsp),%rsp\n\t"
2082 amd64_emit_lt_goto (int *offset_p
, int *size_p
)
2085 "cmp %rax,(%rsp)\n\t"
2086 "jnl .Lamd64_lt_fallthru\n\t"
2087 "lea 0x8(%rsp),%rsp\n\t"
2089 /* jmp, but don't trust the assembler to choose the right jump */
2090 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2091 ".Lamd64_lt_fallthru:\n\t"
2092 "lea 0x8(%rsp),%rsp\n\t"
2102 amd64_emit_le_goto (int *offset_p
, int *size_p
)
2105 "cmp %rax,(%rsp)\n\t"
2106 "jnle .Lamd64_le_fallthru\n\t"
2107 "lea 0x8(%rsp),%rsp\n\t"
2109 /* jmp, but don't trust the assembler to choose the right jump */
2110 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2111 ".Lamd64_le_fallthru:\n\t"
2112 "lea 0x8(%rsp),%rsp\n\t"
2122 amd64_emit_gt_goto (int *offset_p
, int *size_p
)
2125 "cmp %rax,(%rsp)\n\t"
2126 "jng .Lamd64_gt_fallthru\n\t"
2127 "lea 0x8(%rsp),%rsp\n\t"
2129 /* jmp, but don't trust the assembler to choose the right jump */
2130 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2131 ".Lamd64_gt_fallthru:\n\t"
2132 "lea 0x8(%rsp),%rsp\n\t"
2142 amd64_emit_ge_goto (int *offset_p
, int *size_p
)
2145 "cmp %rax,(%rsp)\n\t"
2146 "jnge .Lamd64_ge_fallthru\n\t"
2147 ".Lamd64_ge_jump:\n\t"
2148 "lea 0x8(%rsp),%rsp\n\t"
2150 /* jmp, but don't trust the assembler to choose the right jump */
2151 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2152 ".Lamd64_ge_fallthru:\n\t"
2153 "lea 0x8(%rsp),%rsp\n\t"
2162 struct emit_ops amd64_emit_ops
=
2164 amd64_emit_prologue
,
2165 amd64_emit_epilogue
,
2170 amd64_emit_rsh_signed
,
2171 amd64_emit_rsh_unsigned
,
2179 amd64_emit_less_signed
,
2180 amd64_emit_less_unsigned
,
2184 amd64_write_goto_address
,
2189 amd64_emit_stack_flush
,
2190 amd64_emit_zero_ext
,
2192 amd64_emit_stack_adjust
,
2193 amd64_emit_int_call_1
,
2194 amd64_emit_void_call_2
,
2203 #endif /* __x86_64__ */
2206 i386_emit_prologue (void)
2208 EMIT_ASM32 (i386_prologue
,
2212 /* At this point, the raw regs base address is at 8(%ebp), and the
2213 value pointer is at 12(%ebp). */
2217 i386_emit_epilogue (void)
2219 EMIT_ASM32 (i386_epilogue
,
2220 "mov 12(%ebp),%ecx\n\t"
2221 "mov %eax,(%ecx)\n\t"
2222 "mov %ebx,0x4(%ecx)\n\t"
2230 i386_emit_add (void)
2232 EMIT_ASM32 (i386_add
,
2233 "add (%esp),%eax\n\t"
2234 "adc 0x4(%esp),%ebx\n\t"
2235 "lea 0x8(%esp),%esp");
2239 i386_emit_sub (void)
2241 EMIT_ASM32 (i386_sub
,
2242 "subl %eax,(%esp)\n\t"
2243 "sbbl %ebx,4(%esp)\n\t"
2249 i386_emit_mul (void)
2255 i386_emit_lsh (void)
2261 i386_emit_rsh_signed (void)
2267 i386_emit_rsh_unsigned (void)
2273 i386_emit_ext (int arg
)
2278 EMIT_ASM32 (i386_ext_8
,
2281 "movl %eax,%ebx\n\t"
2285 EMIT_ASM32 (i386_ext_16
,
2287 "movl %eax,%ebx\n\t"
2291 EMIT_ASM32 (i386_ext_32
,
2292 "movl %eax,%ebx\n\t"
2301 i386_emit_log_not (void)
2303 EMIT_ASM32 (i386_log_not
,
2305 "test %eax,%eax\n\t"
2312 i386_emit_bit_and (void)
2314 EMIT_ASM32 (i386_and
,
2315 "and (%esp),%eax\n\t"
2316 "and 0x4(%esp),%ebx\n\t"
2317 "lea 0x8(%esp),%esp");
2321 i386_emit_bit_or (void)
2323 EMIT_ASM32 (i386_or
,
2324 "or (%esp),%eax\n\t"
2325 "or 0x4(%esp),%ebx\n\t"
2326 "lea 0x8(%esp),%esp");
2330 i386_emit_bit_xor (void)
2332 EMIT_ASM32 (i386_xor
,
2333 "xor (%esp),%eax\n\t"
2334 "xor 0x4(%esp),%ebx\n\t"
2335 "lea 0x8(%esp),%esp");
2339 i386_emit_bit_not (void)
2341 EMIT_ASM32 (i386_bit_not
,
2342 "xor $0xffffffff,%eax\n\t"
2343 "xor $0xffffffff,%ebx\n\t");
2347 i386_emit_equal (void)
2349 EMIT_ASM32 (i386_equal
,
2350 "cmpl %ebx,4(%esp)\n\t"
2351 "jne .Li386_equal_false\n\t"
2352 "cmpl %eax,(%esp)\n\t"
2353 "je .Li386_equal_true\n\t"
2354 ".Li386_equal_false:\n\t"
2356 "jmp .Li386_equal_end\n\t"
2357 ".Li386_equal_true:\n\t"
2359 ".Li386_equal_end:\n\t"
2361 "lea 0x8(%esp),%esp");
2365 i386_emit_less_signed (void)
2367 EMIT_ASM32 (i386_less_signed
,
2368 "cmpl %ebx,4(%esp)\n\t"
2369 "jl .Li386_less_signed_true\n\t"
2370 "jne .Li386_less_signed_false\n\t"
2371 "cmpl %eax,(%esp)\n\t"
2372 "jl .Li386_less_signed_true\n\t"
2373 ".Li386_less_signed_false:\n\t"
2375 "jmp .Li386_less_signed_end\n\t"
2376 ".Li386_less_signed_true:\n\t"
2378 ".Li386_less_signed_end:\n\t"
2380 "lea 0x8(%esp),%esp");
2384 i386_emit_less_unsigned (void)
2386 EMIT_ASM32 (i386_less_unsigned
,
2387 "cmpl %ebx,4(%esp)\n\t"
2388 "jb .Li386_less_unsigned_true\n\t"
2389 "jne .Li386_less_unsigned_false\n\t"
2390 "cmpl %eax,(%esp)\n\t"
2391 "jb .Li386_less_unsigned_true\n\t"
2392 ".Li386_less_unsigned_false:\n\t"
2394 "jmp .Li386_less_unsigned_end\n\t"
2395 ".Li386_less_unsigned_true:\n\t"
2397 ".Li386_less_unsigned_end:\n\t"
2399 "lea 0x8(%esp),%esp");
2403 i386_emit_ref (int size
)
2408 EMIT_ASM32 (i386_ref1
,
2412 EMIT_ASM32 (i386_ref2
,
2416 EMIT_ASM32 (i386_ref4
,
2417 "movl (%eax),%eax");
2420 EMIT_ASM32 (i386_ref8
,
2421 "movl 4(%eax),%ebx\n\t"
2422 "movl (%eax),%eax");
2428 i386_emit_if_goto (int *offset_p
, int *size_p
)
2430 EMIT_ASM32 (i386_if_goto
,
2436 /* Don't trust the assembler to choose the right jump */
2437 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0");
2440 *offset_p
= 11; /* be sure that this matches the sequence above */
2446 i386_emit_goto (int *offset_p
, int *size_p
)
2448 EMIT_ASM32 (i386_goto
,
2449 /* Don't trust the assembler to choose the right jump */
2450 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0");
2458 i386_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2460 int diff
= (to
- (from
+ size
));
2461 unsigned char buf
[sizeof (int)];
2463 /* We're only doing 4-byte sizes at the moment. */
2470 memcpy (buf
, &diff
, sizeof (int));
2471 target_write_memory (from
, buf
, sizeof (int));
2475 i386_emit_const (LONGEST num
)
2477 unsigned char buf
[16];
2479 CORE_ADDR buildaddr
= current_insn_ptr
;
2482 buf
[i
++] = 0xb8; /* mov $<n>,%eax */
2483 lo
= num
& 0xffffffff;
2484 memcpy (&buf
[i
], &lo
, sizeof (lo
));
2486 hi
= ((num
>> 32) & 0xffffffff);
2489 buf
[i
++] = 0xbb; /* mov $<n>,%ebx */
2490 memcpy (&buf
[i
], &hi
, sizeof (hi
));
2495 buf
[i
++] = 0x31; buf
[i
++] = 0xdb; /* xor %ebx,%ebx */
2497 append_insns (&buildaddr
, i
, buf
);
2498 current_insn_ptr
= buildaddr
;
2502 i386_emit_call (CORE_ADDR fn
)
2504 unsigned char buf
[16];
2506 CORE_ADDR buildaddr
;
2508 buildaddr
= current_insn_ptr
;
2510 buf
[i
++] = 0xe8; /* call <reladdr> */
2511 offset
= ((int) fn
) - (buildaddr
+ 5);
2512 memcpy (buf
+ 1, &offset
, 4);
2513 append_insns (&buildaddr
, 5, buf
);
2514 current_insn_ptr
= buildaddr
;
2518 i386_emit_reg (int reg
)
2520 unsigned char buf
[16];
2522 CORE_ADDR buildaddr
;
2524 EMIT_ASM32 (i386_reg_a
,
2526 buildaddr
= current_insn_ptr
;
2528 buf
[i
++] = 0xb8; /* mov $<n>,%eax */
2529 memcpy (&buf
[i
], ®
, sizeof (reg
));
2531 append_insns (&buildaddr
, i
, buf
);
2532 current_insn_ptr
= buildaddr
;
2533 EMIT_ASM32 (i386_reg_b
,
2534 "mov %eax,4(%esp)\n\t"
2535 "mov 8(%ebp),%eax\n\t"
2537 i386_emit_call (get_raw_reg_func_addr ());
2538 EMIT_ASM32 (i386_reg_c
,
2540 "lea 0x8(%esp),%esp");
2544 i386_emit_pop (void)
2546 EMIT_ASM32 (i386_pop
,
2552 i386_emit_stack_flush (void)
2554 EMIT_ASM32 (i386_stack_flush
,
2560 i386_emit_zero_ext (int arg
)
2565 EMIT_ASM32 (i386_zero_ext_8
,
2566 "and $0xff,%eax\n\t"
2570 EMIT_ASM32 (i386_zero_ext_16
,
2571 "and $0xffff,%eax\n\t"
2575 EMIT_ASM32 (i386_zero_ext_32
,
2584 i386_emit_swap (void)
2586 EMIT_ASM32 (i386_swap
,
2596 i386_emit_stack_adjust (int n
)
2598 unsigned char buf
[16];
2600 CORE_ADDR buildaddr
= current_insn_ptr
;
2603 buf
[i
++] = 0x8d; /* lea $<n>(%esp),%esp */
2607 append_insns (&buildaddr
, i
, buf
);
2608 current_insn_ptr
= buildaddr
;
2611 /* FN's prototype is `LONGEST(*fn)(int)'. */
2614 i386_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2616 unsigned char buf
[16];
2618 CORE_ADDR buildaddr
;
2620 EMIT_ASM32 (i386_int_call_1_a
,
2621 /* Reserve a bit of stack space. */
2623 /* Put the one argument on the stack. */
2624 buildaddr
= current_insn_ptr
;
2626 buf
[i
++] = 0xc7; /* movl $<arg1>,(%esp) */
2629 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2631 append_insns (&buildaddr
, i
, buf
);
2632 current_insn_ptr
= buildaddr
;
2633 i386_emit_call (fn
);
2634 EMIT_ASM32 (i386_int_call_1_c
,
2636 "lea 0x8(%esp),%esp");
2639 /* FN's prototype is `void(*fn)(int,LONGEST)'. */
2642 i386_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2644 unsigned char buf
[16];
2646 CORE_ADDR buildaddr
;
2648 EMIT_ASM32 (i386_void_call_2_a
,
2649 /* Preserve %eax only; we don't have to worry about %ebx. */
2651 /* Reserve a bit of stack space for arguments. */
2652 "sub $0x10,%esp\n\t"
2653 /* Copy "top" to the second argument position. (Note that
2654 we can't assume function won't scribble on its
2655 arguments, so don't try to restore from this.) */
2656 "mov %eax,4(%esp)\n\t"
2657 "mov %ebx,8(%esp)");
2658 /* Put the first argument on the stack. */
2659 buildaddr
= current_insn_ptr
;
2661 buf
[i
++] = 0xc7; /* movl $<arg1>,(%esp) */
2664 memcpy (&buf
[i
], &arg1
, sizeof (arg1
));
2666 append_insns (&buildaddr
, i
, buf
);
2667 current_insn_ptr
= buildaddr
;
2668 i386_emit_call (fn
);
2669 EMIT_ASM32 (i386_void_call_2_b
,
2670 "lea 0x10(%esp),%esp\n\t"
2671 /* Restore original stack top. */
2677 i386_emit_eq_goto (int *offset_p
, int *size_p
)
2680 /* Check low half first, more likely to be decider */
2681 "cmpl %eax,(%esp)\n\t"
2682 "jne .Leq_fallthru\n\t"
2683 "cmpl %ebx,4(%esp)\n\t"
2684 "jne .Leq_fallthru\n\t"
2685 "lea 0x8(%esp),%esp\n\t"
2688 /* jmp, but don't trust the assembler to choose the right jump */
2689 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2690 ".Leq_fallthru:\n\t"
2691 "lea 0x8(%esp),%esp\n\t"
2702 i386_emit_ne_goto (int *offset_p
, int *size_p
)
2705 /* Check low half first, more likely to be decider */
2706 "cmpl %eax,(%esp)\n\t"
2708 "cmpl %ebx,4(%esp)\n\t"
2709 "je .Lne_fallthru\n\t"
2711 "lea 0x8(%esp),%esp\n\t"
2714 /* jmp, but don't trust the assembler to choose the right jump */
2715 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2716 ".Lne_fallthru:\n\t"
2717 "lea 0x8(%esp),%esp\n\t"
2728 i386_emit_lt_goto (int *offset_p
, int *size_p
)
2731 "cmpl %ebx,4(%esp)\n\t"
2733 "jne .Llt_fallthru\n\t"
2734 "cmpl %eax,(%esp)\n\t"
2735 "jnl .Llt_fallthru\n\t"
2737 "lea 0x8(%esp),%esp\n\t"
2740 /* jmp, but don't trust the assembler to choose the right jump */
2741 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2742 ".Llt_fallthru:\n\t"
2743 "lea 0x8(%esp),%esp\n\t"
2754 i386_emit_le_goto (int *offset_p
, int *size_p
)
2757 "cmpl %ebx,4(%esp)\n\t"
2759 "jne .Lle_fallthru\n\t"
2760 "cmpl %eax,(%esp)\n\t"
2761 "jnle .Lle_fallthru\n\t"
2763 "lea 0x8(%esp),%esp\n\t"
2766 /* jmp, but don't trust the assembler to choose the right jump */
2767 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2768 ".Lle_fallthru:\n\t"
2769 "lea 0x8(%esp),%esp\n\t"
2780 i386_emit_gt_goto (int *offset_p
, int *size_p
)
2783 "cmpl %ebx,4(%esp)\n\t"
2785 "jne .Lgt_fallthru\n\t"
2786 "cmpl %eax,(%esp)\n\t"
2787 "jng .Lgt_fallthru\n\t"
2789 "lea 0x8(%esp),%esp\n\t"
2792 /* jmp, but don't trust the assembler to choose the right jump */
2793 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2794 ".Lgt_fallthru:\n\t"
2795 "lea 0x8(%esp),%esp\n\t"
2806 i386_emit_ge_goto (int *offset_p
, int *size_p
)
2809 "cmpl %ebx,4(%esp)\n\t"
2811 "jne .Lge_fallthru\n\t"
2812 "cmpl %eax,(%esp)\n\t"
2813 "jnge .Lge_fallthru\n\t"
2815 "lea 0x8(%esp),%esp\n\t"
2818 /* jmp, but don't trust the assembler to choose the right jump */
2819 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t"
2820 ".Lge_fallthru:\n\t"
2821 "lea 0x8(%esp),%esp\n\t"
2831 struct emit_ops i386_emit_ops
=
2839 i386_emit_rsh_signed
,
2840 i386_emit_rsh_unsigned
,
2848 i386_emit_less_signed
,
2849 i386_emit_less_unsigned
,
2853 i386_write_goto_address
,
2858 i386_emit_stack_flush
,
2861 i386_emit_stack_adjust
,
2862 i386_emit_int_call_1
,
2863 i386_emit_void_call_2
,
2873 static struct emit_ops
*
2877 if (is_64bit_tdesc ())
2878 return &amd64_emit_ops
;
2881 return &i386_emit_ops
;
2884 /* Implementation of target ops method "sw_breakpoint_from_kind". */
2887 x86_target::sw_breakpoint_from_kind (int kind
, int *size
)
2889 *size
= x86_breakpoint_len
;
2890 return x86_breakpoint
;
2894 x86_supports_range_stepping (void)
2899 /* Implementation of linux_target_ops method "supports_hardware_single_step".
2903 x86_supports_hardware_single_step (void)
2909 x86_get_ipa_tdesc_idx (void)
2911 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
2912 const struct target_desc
*tdesc
= regcache
->tdesc
;
2915 return amd64_get_ipa_tdesc_idx (tdesc
);
2918 if (tdesc
== tdesc_i386_linux_no_xml
)
2919 return X86_TDESC_SSE
;
2921 return i386_get_ipa_tdesc_idx (tdesc
);
2924 /* This is initialized assuming an amd64 target.
2925 x86_arch_setup will correct it for i386 or amd64 targets. */
2927 struct linux_target_ops the_low_target
=
2929 /* need to fix up i386 siginfo if host is amd64 */
2931 x86_linux_new_process
,
2932 x86_linux_delete_process
,
2933 x86_linux_new_thread
,
2934 x86_linux_delete_thread
,
2936 x86_linux_prepare_to_resume
,
2937 x86_linux_process_qsupported
,
2938 x86_supports_tracepoints
,
2939 x86_get_thread_area
,
2940 x86_install_fast_tracepoint_jump_pad
,
2942 x86_get_min_fast_tracepoint_insn_len
,
2943 x86_supports_range_stepping
,
2944 x86_supports_hardware_single_step
,
2945 x86_get_syscall_trapinfo
,
2946 x86_get_ipa_tdesc_idx
,
2949 /* The linux target ops object. */
2951 linux_process_target
*the_linux_target
= &the_x86_target
;
2954 initialize_low_arch (void)
2956 /* Initialize the Linux target descriptions. */
2958 tdesc_amd64_linux_no_xml
= allocate_target_description ();
2959 copy_target_description (tdesc_amd64_linux_no_xml
,
2960 amd64_linux_read_description (X86_XSTATE_SSE_MASK
,
2962 tdesc_amd64_linux_no_xml
->xmltarget
= xmltarget_amd64_linux_no_xml
;
2965 tdesc_i386_linux_no_xml
= allocate_target_description ();
2966 copy_target_description (tdesc_i386_linux_no_xml
,
2967 i386_linux_read_description (X86_XSTATE_SSE_MASK
));
2968 tdesc_i386_linux_no_xml
->xmltarget
= xmltarget_i386_linux_no_xml
;
2970 initialize_regsets_info (&x86_regsets_info
);