1 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
3 * opcode/aarch64.h (enum aarch64_insn_class): Add sve_shift_tsz_bhsd
6 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
8 * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22
10 (enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass.
12 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
14 * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_013 iclass.
16 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
18 * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_bh iclass.
20 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
22 * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_sd2 iclass.
24 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
26 * opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand.
28 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
30 * opcode/aarch64.h (enum aarch64_opnd): New SVE_Zm3_11_INDEX operand.
32 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
34 * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_hsd2 iclass.
36 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
38 * opcode/aarch64.h (enum aarch64_opnd): New SVE_IMM_ROT3 operand.
40 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
42 * opcode/aarch64.h (AARCH64_FEATURE_SVE2
43 AARCH64_FEATURE_SVE2_AES, AARCH64_FEATURE_SVE2_BITPERM,
44 AARCH64_FEATURE_SVE2_SM4, AARCH64_FEATURE_SVE2_SHA3): New
47 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
48 Faraz Shahbazker <fshahbazker@wavecomp.com>
50 * opcode/mips.h (ASE_EVA_R6): New macro.
51 (M_LLWPE_AB, M_SCWPE_AB): New enum values.
53 2019-05-01 Sudakshina Das <sudi.das@arm.com>
55 * opcode/aarch64.h (AARCH64_FEATURE_TME): New.
56 (enum aarch64_opnd): Add AARCH64_OPND_TME_UIMM16.
58 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
59 Faraz Shahbazker <fshahbazker@wavecomp.com>
61 * opcode/mips.h (M_LLWP_AB, M_LLDP_AB): New enum values.
62 (M_SCWP_AB, M_SCDP_AB): Likewise.
64 2019-04-25 Maciej W. Rozycki <macro@linux-mips.org>
66 * opcode/mips.h: Update comment for MIPS32 CODE20 operand.
68 2019-04-15 Sudakshina Das <sudi.das@arm.com>
70 * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF12.
72 2019-04-15 Sudakshina Das <sudi.das@arm.com>
74 * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF18.
76 2019-04-15 Sudakshina Das <sudi.das@arm.com>
78 * elf/arm.h (START_RELOC_NUMBERS): New entry for R_ARM_THM_BF16.
80 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
82 * elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro.
83 (MAX_TAG_CPU_ARCH): Set value to above macro.
84 * opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro.
85 (ARM_AEXT_V8_1M_MAIN): Likewise.
86 (ARM_AEXT2_V8_1M_MAIN): Likewise.
87 (ARM_ARCH_V8_1M_MAIN): Likewise.
89 2019-04-11 Sudakshina Das <sudi.das@arm.com>
91 * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_Rt_SP.
93 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
95 * elf/common.h (GNU_PROPERTY_X86_ISA_1_AVX512_BF16): New.
97 2019-04-07 Alan Modra <amodra@gmail.com>
100 2019-04-03 Vineet Gupta <vgupta@synopsys.com>
102 * longlong.h [__arc__] (add_ssaaaa): Add cc clobber.
103 (sub_ddmmss): Likewise.
105 2019-04-06 H.J. Lu <hongjiu.lu@intel.com>
107 * bfdlink.h (bfd_link_info): Remove x86-specific linker options.
109 2019-04-01 Andre Vieira <andre.simoesdiasvieira@arm.com>
111 * opcode/arm.h (FPU_NEON_ARMV8_1): New.
112 (FPU_ARCH_NEON_VFP_ARMV8_1): Use FPU_NEON_ARMV8_1.
113 (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): Likewise.
114 (FPU_ARCH_DOTPROD_NEON_VFP_ARMV8): Likewise.
115 (FPU_ARCH_NEON_VFP_ARMV8_2_FP16): New.
116 (FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML): New.
117 (FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML): New.
118 (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4): New.
120 2019-03-28 Alan Modra <amodra@gmail.com>
123 * opcode/ppc.h (PPC_OPERAND_CR_REG): Comment.
125 2019-03-25 Tamar Christina <tamar.christina@arm.com>
127 * dis-asm.h (struct disassemble_info): Add stop_offset.
129 2019-03-13 Sudakshina Das <sudi.das@arm.com>
131 * elf/aarch64.h (DT_AARCH64_PAC_PLT): New.
133 2019-03-13 Sudakshina Das <sudi.das@arm.com>
134 Szabolcs Nagy <szabolcs.nagy@arm.com>
136 * elf/aarch64.h (DT_AARCH64_BTI_PLT): New.
138 2019-03-13 Sudakshina Das <sudi.das@arm.com>
140 * elf/common.h (GNU_PROPERTY_AARCH64_FEATURE_1_AND): New.
141 (GNU_PROPERTY_AARCH64_FEATURE_1_BTI): New.
142 (GNU_PROPERTY_AARCH64_FEATURE_1_PAC): New.
144 2019-02-20 Alan Hayward <alan.hayward@arm.com>
146 * elf/common.h (NT_ARM_PAC_MASK): Add define.
148 2019-02-15 Saagar Jha <saagar@saagarjha.com>
150 * mach-o/loader.h: Use new OS names in comments.
152 2019-02-11 Philippe Waroquiers <philippe.waroquiers@skynet.be>
154 * splay-tree.h (splay_tree_delete_key_fn): Update comment.
155 (splay_tree_delete_value_fn): Likewise.
157 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
159 * opcode/s390.h (enum s390_opcode_cpu_val): Add
162 2019-01-25 Sudakshina Das <sudi.das@arm.com>
163 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
165 * opcode/aarch64.h (enum aarch64_opnd): Remove
166 AARCH64_OPND_ADDR_SIMPLE_2.
167 (enum aarch64_insn_class): Remove ldstgv_indexed.
169 2019-01-22 Tom Tromey <tom@tromey.com>
171 * coff/ecoff.h: Include coff/sym.h.
173 2018-06-24 Nick Clifton <nickc@redhat.com>
177 2019-01-16 Kito Cheng <kito@andestech.com>
179 * elf/riscv.h (SHT_RISCV_ATTRIBUTES): Define.
180 (Tag_RISCV_arch): Likewise.
181 (Tag_RISCV_priv_spec): Likewise.
182 (Tag_RISCV_priv_spec_minor): Likewise.
183 (Tag_RISCV_priv_spec_revision): Likewise.
184 (Tag_RISCV_unaligned_access): Likewise.
185 (Tag_RISCV_stack_align): Likewise.
187 2019-01-14 Pavel I. Kryukov <kryukov@frtk.ru>
189 * dis-asm.h: include <string.h>
191 2019-01-10 Nick Clifton <nickc@redhat.com>
194 2018-12-22 Jason Merrill <jason@redhat.com>
196 * demangle.h: Remove support for ancient GNU (pre-3.0), Lucid,
197 ARM, HP, and EDG demangling styles.
199 2019-01-09 Sandra Loosemore <sandra@codesourcery.com>
204 * libiberty.h: Mechanically replace "can not" with "cannot".
205 * plugin-api.h: Likewise.
207 2018-12-25 Yoshinori Sato <ysato@users.sourceforge.jp>
209 * elf/rx.h (EF_RX_CPU_MASK): Update new bits.
210 (E_FLAG_RX_V3): New RXv3 type.
211 * opcode/rx.h (RX_Size): Add double size.
212 (RX_Operand_Type): Add double FPU registers.
213 (RX_Opcode_ID): Add new instuctions.
215 2019-01-01 Alan Modra <amodra@gmail.com>
217 Update year range in copyright notice of all files.
219 For older changes see ChangeLog-2018
221 Copyright (C) 2019 Free Software Foundation, Inc.
223 Copying and distribution of this file, with or without modification,
224 are permitted in any medium without royalty provided the copyright
225 notice and this notice are preserved.
231 version-control: never