2 * linux/include/asm-arm/atomic.h
4 * Copyright (C) 1996 Russell King.
5 * Copyright (C) 2002 Deep Blue Solutions Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #ifndef __ASM_ARM_ATOMIC_H
12 #define __ASM_ARM_ATOMIC_H
14 #include <linux/config.h>
15 #include <linux/compiler.h>
17 typedef struct { volatile int counter
; } atomic_t
;
19 #define ATOMIC_INIT(i) { (i) }
23 #define atomic_read(v) ((v)->counter)
25 #if __LINUX_ARM_ARCH__ >= 6
28 * ARMv6 UP and SMP safe atomic ops. We use load exclusive and
29 * store exclusive to ensure that these are atomic. We may loop
30 * to ensure that the update happens. Writing to 'v->counter'
31 * without using the following operations WILL break the atomic
32 * nature of these ops.
34 static inline void atomic_set(atomic_t
*v
, int i
)
38 __asm__
__volatile__("@ atomic_set\n"
40 " strex %0, %2, [%1]\n"
44 : "r" (&v
->counter
), "r" (i
)
48 static inline int atomic_add_return(int i
, atomic_t
*v
)
53 __asm__
__volatile__("@ atomic_add_return\n"
56 " strex %1, %0, [%2]\n"
59 : "=&r" (result
), "=&r" (tmp
)
60 : "r" (&v
->counter
), "Ir" (i
)
66 static inline int atomic_sub_return(int i
, atomic_t
*v
)
71 __asm__
__volatile__("@ atomic_sub_return\n"
74 " strex %1, %0, [%2]\n"
77 : "=&r" (result
), "=&r" (tmp
)
78 : "r" (&v
->counter
), "Ir" (i
)
84 static inline int atomic_cmpxchg(atomic_t
*ptr
, int old
, int new)
86 unsigned long oldval
, res
;
89 __asm__
__volatile__("@ atomic_cmpxchg\n"
93 "strexeq %0, %4, [%2]\n"
94 : "=&r" (res
), "=&r" (oldval
)
95 : "r" (&ptr
->counter
), "Ir" (old
), "r" (new)
102 static inline void atomic_clear_mask(unsigned long mask
, unsigned long *addr
)
104 unsigned long tmp
, tmp2
;
106 __asm__
__volatile__("@ atomic_clear_mask\n"
109 " strex %1, %0, %2\n"
112 : "=&r" (tmp
), "=&r" (tmp2
)
113 : "r" (addr
), "Ir" (mask
)
117 #else /* ARM_ARCH_6 */
119 #include <asm/system.h>
122 #error SMP not supported on pre-ARMv6 CPUs
125 #define atomic_set(v,i) (((v)->counter) = (i))
127 static inline int atomic_add_return(int i
, atomic_t
*v
)
132 local_irq_save(flags
);
134 v
->counter
= val
+= i
;
135 local_irq_restore(flags
);
140 static inline int atomic_sub_return(int i
, atomic_t
*v
)
145 local_irq_save(flags
);
147 v
->counter
= val
-= i
;
148 local_irq_restore(flags
);
153 static inline int atomic_cmpxchg(atomic_t
*v
, int old
, int new)
158 local_irq_save(flags
);
160 if (likely(ret
== old
))
162 local_irq_restore(flags
);
167 static inline void atomic_clear_mask(unsigned long mask
, unsigned long *addr
)
171 local_irq_save(flags
);
173 local_irq_restore(flags
);
176 #endif /* __LINUX_ARM_ARCH__ */
178 static inline int atomic_add_unless(atomic_t
*v
, int a
, int u
)
183 while (c
!= u
&& (old
= atomic_cmpxchg((v
), c
, c
+ a
)) != c
)
187 #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
189 #define atomic_add(i, v) (void) atomic_add_return(i, v)
190 #define atomic_inc(v) (void) atomic_add_return(1, v)
191 #define atomic_sub(i, v) (void) atomic_sub_return(i, v)
192 #define atomic_dec(v) (void) atomic_sub_return(1, v)
194 #define atomic_inc_and_test(v) (atomic_add_return(1, v) == 0)
195 #define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0)
196 #define atomic_inc_return(v) (atomic_add_return(1, v))
197 #define atomic_dec_return(v) (atomic_sub_return(1, v))
198 #define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
200 #define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0)
202 /* Atomic operations are already serializing on ARM */
203 #define smp_mb__before_atomic_dec() barrier()
204 #define smp_mb__after_atomic_dec() barrier()
205 #define smp_mb__before_atomic_inc() barrier()
206 #define smp_mb__after_atomic_inc() barrier()
208 #include <asm-generic/atomic.h>
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