include/asm-ia64/spinlock.h

   1 #ifndef _ASM_IA64_SPINLOCK_H
   2 #define _ASM_IA64_SPINLOCK_H
   3
   4 /*
   5  * Copyright (C) 1998-2003 Hewlett-Packard Co
   6  *      David Mosberger-Tang <davidm@hpl.hp.com>
   7  * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
   8  *
   9  * This file is used for SMP configurations only.
  10  */
  11
  12 #include <linux/compiler.h>
  13 #include <linux/kernel.h>
  14
  15 #include <asm/atomic.h>
  16 #include <asm/bitops.h>
  17 #include <asm/intrinsics.h>
  18 #include <asm/system.h>
  19
  20 typedef struct {
  21         volatile unsigned int lock;
  22 #ifdef CONFIG_PREEMPT
  23         unsigned int break_lock;
  24 #endif
  25 } spinlock_t;
  26
  27 #define SPIN_LOCK_UNLOCKED                      (spinlock_t) { 0 }
  28 #define spin_lock_init(x)                       ((x)->lock = 0)
  29
  30 #ifdef ASM_SUPPORTED
  31 /*
  32  * Try to get the lock.  If we fail to get the lock, make a non-standard call to
  33  * ia64_spinlock_contention().  We do not use a normal call because that would force all
  34  * callers of spin_lock() to be non-leaf routines.  Instead, ia64_spinlock_contention() is
  35  * carefully coded to touch only those registers that spin_lock() marks "clobbered".
  36  */
  37
  38 #define IA64_SPINLOCK_CLOBBERS "ar.ccv", "ar.pfs", "p14", "p15", "r27", "r28", "r29", "r30", "b6", "memory"
  39
  40 static inline void
  41 _raw_spin_lock_flags (spinlock_t *lock, unsigned long flags)
  42 {
  43         register volatile unsigned int *ptr asm ("r31") = &lock->lock;
  44
  45 #if __GNUC__ < 3 || (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
  46 # ifdef CONFIG_ITANIUM
  47         /* don't use brl on Itanium... */
  48         asm volatile ("{\n\t"
  49                       "  mov ar.ccv = r0\n\t"
  50                       "  mov r28 = ip\n\t"
  51                       "  mov r30 = 1;;\n\t"
  52                       "}\n\t"
  53                       "cmpxchg4.acq r30 = [%1], r30, ar.ccv\n\t"
  54                       "movl r29 = ia64_spinlock_contention_pre3_4;;\n\t"
  55                       "cmp4.ne p14, p0 = r30, r0\n\t"
  56                       "mov b6 = r29;;\n\t"
  57                       "mov r27=%2\n\t"
  58                       "(p14) br.cond.spnt.many b6"
  59                       : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
  60 # else
  61         asm volatile ("{\n\t"
  62                       "  mov ar.ccv = r0\n\t"
  63                       "  mov r28 = ip\n\t"
  64                       "  mov r30 = 1;;\n\t"
  65                       "}\n\t"
  66                       "cmpxchg4.acq r30 = [%1], r30, ar.ccv;;\n\t"
  67                       "cmp4.ne p14, p0 = r30, r0\n\t"
  68                       "mov r27=%2\n\t"
  69                       "(p14) brl.cond.spnt.many ia64_spinlock_contention_pre3_4;;"
  70                       : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
  71 # endif /* CONFIG_MCKINLEY */
  72 #else
  73 # ifdef CONFIG_ITANIUM
  74         /* don't use brl on Itanium... */
  75         /* mis-declare, so we get the entry-point, not it's function descriptor: */
  76         asm volatile ("mov r30 = 1\n\t"
  77                       "mov r27=%2\n\t"
  78                       "mov ar.ccv = r0;;\n\t"
  79                       "cmpxchg4.acq r30 = [%0], r30, ar.ccv\n\t"
  80                       "movl r29 = ia64_spinlock_contention;;\n\t"
  81                       "cmp4.ne p14, p0 = r30, r0\n\t"
  82                       "mov b6 = r29;;\n\t"
  83                       "(p14) br.call.spnt.many b6 = b6"
  84                       : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
  85 # else
  86         asm volatile ("mov r30 = 1\n\t"
  87                       "mov r27=%2\n\t"
  88                       "mov ar.ccv = r0;;\n\t"
  89                       "cmpxchg4.acq r30 = [%0], r30, ar.ccv;;\n\t"
  90                       "cmp4.ne p14, p0 = r30, r0\n\t"
  91                       "(p14) brl.call.spnt.many b6=ia64_spinlock_contention;;"
  92                       : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
  93 # endif /* CONFIG_MCKINLEY */
  94 #endif
  95 }
  96
  97 #define _raw_spin_lock(lock) _raw_spin_lock_flags(lock, 0)
  98
  99 /* Unlock by doing an ordered store and releasing the cacheline with nta */
 100 static inline void _raw_spin_unlock(spinlock_t *x) {
 101         barrier();
 102         asm volatile ("st4.rel.nta [%0] = r0\n\t" :: "r"(x));
 103 }
 104
 105 #else /* !ASM_SUPPORTED */
 106 #define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock)
 107 # define _raw_spin_lock(x)                                                              \
 108 do {                                                                                    \
 109         __u32 *ia64_spinlock_ptr = (__u32 *) (x);                                       \
 110         __u64 ia64_spinlock_val;                                                        \
 111         ia64_spinlock_val = ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0);                 \
 112         if (unlikely(ia64_spinlock_val)) {                                              \
 113                 do {                                                                    \
 114                         while (*ia64_spinlock_ptr)                                      \
 115                                 ia64_barrier();                                         \
 116                         ia64_spinlock_val = ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0); \
 117                 } while (ia64_spinlock_val);                                            \
 118         }                                                                               \
 119 } while (0)
 120 #define _raw_spin_unlock(x)     do { barrier(); ((spinlock_t *) x)->lock = 0; } while (0)
 121 #endif /* !ASM_SUPPORTED */
 122
 123 #define spin_is_locked(x)       ((x)->lock != 0)
 124 #define _raw_spin_trylock(x)    (cmpxchg_acq(&(x)->lock, 0, 1) == 0)
 125 #define spin_unlock_wait(x)     do { barrier(); } while ((x)->lock)
 126
 127 typedef struct {
 128         volatile unsigned int read_counter      : 24;
 129         volatile unsigned int write_lock        :  8;
 130 #ifdef CONFIG_PREEMPT
 131         unsigned int break_lock;
 132 #endif
 133 } rwlock_t;
 134 #define RW_LOCK_UNLOCKED (rwlock_t) { 0, 0 }
 135
 136 #define rwlock_init(x)          do { *(x) = RW_LOCK_UNLOCKED; } while(0)
 137 #define read_can_lock(rw)       (*(volatile int *)(rw) >= 0)
 138 #define write_can_lock(rw)      (*(volatile int *)(rw) == 0)
 139
 140 #define _raw_read_lock(rw)                                                              \
 141 do {                                                                                    \
 142         rwlock_t *__read_lock_ptr = (rw);                                               \
 143                                                                                         \
 144         while (unlikely(ia64_fetchadd(1, (int *) __read_lock_ptr, acq) < 0)) {          \
 145                 ia64_fetchadd(-1, (int *) __read_lock_ptr, rel);                        \
 146                 while (*(volatile int *)__read_lock_ptr < 0)                            \
 147                         cpu_relax();                                                    \
 148         }                                                                               \
 149 } while (0)
 150
 151 #define _raw_read_unlock(rw)                                    \
 152 do {                                                            \
 153         rwlock_t *__read_lock_ptr = (rw);                       \
 154         ia64_fetchadd(-1, (int *) __read_lock_ptr, rel);        \
 155 } while (0)
 156
 157 #ifdef ASM_SUPPORTED
 158 #define _raw_write_lock(rw)                                                     \
 159 do {                                                                            \
 160         __asm__ __volatile__ (                                                  \
 161                 "mov ar.ccv = r0\n"                                             \
 162                 "dep r29 = -1, r0, 31, 1;;\n"                                   \
 163                 "1:\n"                                                          \
 164                 "ld4 r2 = [%0];;\n"                                             \
 165                 "cmp4.eq p0,p7 = r0,r2\n"                                       \
 166                 "(p7) br.cond.spnt.few 1b \n"                                   \
 167                 "cmpxchg4.acq r2 = [%0], r29, ar.ccv;;\n"                       \
 168                 "cmp4.eq p0,p7 = r0, r2\n"                                      \
 169                 "(p7) br.cond.spnt.few 1b;;\n"                                  \
 170                 :: "r"(rw) : "ar.ccv", "p7", "r2", "r29", "memory");            \
 171 } while(0)
 172
 173 #define _raw_write_trylock(rw)                                                  \
 174 ({                                                                              \
 175         register long result;                                                   \
 176                                                                                 \
 177         __asm__ __volatile__ (                                                  \
 178                 "mov ar.ccv = r0\n"                                             \
 179                 "dep r29 = -1, r0, 31, 1;;\n"                                   \
 180                 "cmpxchg4.acq %0 = [%1], r29, ar.ccv\n"                         \
 181                 : "=r"(result) : "r"(rw) : "ar.ccv", "r29", "memory");          \
 182         (result == 0);                                                          \
 183 })
 184
 185 static inline void _raw_write_unlock(rwlock_t *x)
 186 {
 187         u8 *y = (u8 *)x;
 188         barrier();
 189         asm volatile ("st1.rel.nta [%0] = r0\n\t" :: "r"(y+3) : "memory" );
 190 }
 191
 192 #else /* !ASM_SUPPORTED */
 193
 194 #define _raw_write_lock(l)                                                              \
 195 ({                                                                                      \
 196         __u64 ia64_val, ia64_set_val = ia64_dep_mi(-1, 0, 31, 1);                       \
 197         __u32 *ia64_write_lock_ptr = (__u32 *) (l);                                     \
 198         do {                                                                            \
 199                 while (*ia64_write_lock_ptr)                                            \
 200                         ia64_barrier();                                                 \
 201                 ia64_val = ia64_cmpxchg4_acq(ia64_write_lock_ptr, ia64_set_val, 0);     \
 202         } while (ia64_val);                                                             \
 203 })
 204
 205 #define _raw_write_trylock(rw)                                          \
 206 ({                                                                      \
 207         __u64 ia64_val;                                                 \
 208         __u64 ia64_set_val = ia64_dep_mi(-1, 0, 31,1);                  \
 209         ia64_val = ia64_cmpxchg4_acq((__u32 *)(rw), ia64_set_val, 0);   \
 210         (ia64_val == 0);                                                \
 211 })
 212
 213 static inline void _raw_write_unlock(rwlock_t *x)
 214 {
 215         barrier();
 216         x->write_lock = 0;
 217 }
 218
 219 #endif /* !ASM_SUPPORTED */
 220
 221 #define _raw_read_trylock(lock) generic_raw_read_trylock(lock)
 222
 223 #endif /*  _ASM_IA64_SPINLOCK_H */