2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (c) 1994 - 1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (c) 1999, 2000 Silicon Graphics, Inc.
12 #ifndef _LINUX_BITOPS_H
13 #error only <linux/bitops.h> can be included directly
16 #include <linux/compiler.h>
17 #include <linux/irqflags.h>
18 #include <linux/types.h>
19 #include <asm/barrier.h>
21 #include <asm/byteorder.h> /* sigh ... */
22 #include <asm/cpu-features.h>
23 #include <asm/sgidefs.h>
26 #if _MIPS_SZLONG == 32
28 #define SZLONG_MASK 31UL
33 #elif _MIPS_SZLONG == 64
35 #define SZLONG_MASK 63UL
43 * clear_bit() doesn't provide any barrier for the compiler.
45 #define smp_mb__before_clear_bit() smp_llsc_mb()
46 #define smp_mb__after_clear_bit() smp_llsc_mb()
49 * set_bit - Atomically set a bit in memory
51 * @addr: the address to start counting from
53 * This function is atomic and may not be reordered. See __set_bit()
54 * if you do not require the atomic guarantees.
55 * Note that @nr may be almost arbitrarily large; this function is not
56 * restricted to acting on a single-word quantity.
58 static inline void set_bit(unsigned long nr
, volatile unsigned long *addr
)
60 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
61 unsigned short bit
= nr
& SZLONG_MASK
;
64 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
67 "1: " __LL
"%0, %1 # set_bit \n"
72 : "=&r" (temp
), "=m" (*m
)
73 : "ir" (1UL << bit
), "m" (*m
));
74 #ifdef CONFIG_CPU_MIPSR2
75 } else if (__builtin_constant_p(bit
)) {
77 "1: " __LL
"%0, %1 # set_bit \n"
78 " " __INS
"%0, %4, %2, 1 \n"
84 : "=&r" (temp
), "=m" (*m
)
85 : "i" (bit
), "m" (*m
), "r" (~0));
86 #endif /* CONFIG_CPU_MIPSR2 */
87 } else if (cpu_has_llsc
) {
90 "1: " __LL
"%0, %1 # set_bit \n"
98 : "=&r" (temp
), "=m" (*m
)
99 : "ir" (1UL << bit
), "m" (*m
));
101 volatile unsigned long *a
= addr
;
105 a
+= nr
>> SZLONG_LOG
;
107 raw_local_irq_save(flags
);
109 raw_local_irq_restore(flags
);
114 * clear_bit - Clears a bit in memory
116 * @addr: Address to start counting from
118 * clear_bit() is atomic and may not be reordered. However, it does
119 * not contain a memory barrier, so if it is used for locking purposes,
120 * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
121 * in order to ensure changes are visible on other processors.
123 static inline void clear_bit(unsigned long nr
, volatile unsigned long *addr
)
125 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
126 unsigned short bit
= nr
& SZLONG_MASK
;
129 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
130 __asm__
__volatile__(
132 "1: " __LL
"%0, %1 # clear_bit \n"
137 : "=&r" (temp
), "=m" (*m
)
138 : "ir" (~(1UL << bit
)), "m" (*m
));
139 #ifdef CONFIG_CPU_MIPSR2
140 } else if (__builtin_constant_p(bit
)) {
141 __asm__
__volatile__(
142 "1: " __LL
"%0, %1 # clear_bit \n"
143 " " __INS
"%0, $0, %2, 1 \n"
149 : "=&r" (temp
), "=m" (*m
)
150 : "i" (bit
), "m" (*m
));
151 #endif /* CONFIG_CPU_MIPSR2 */
152 } else if (cpu_has_llsc
) {
153 __asm__
__volatile__(
155 "1: " __LL
"%0, %1 # clear_bit \n"
163 : "=&r" (temp
), "=m" (*m
)
164 : "ir" (~(1UL << bit
)), "m" (*m
));
166 volatile unsigned long *a
= addr
;
170 a
+= nr
>> SZLONG_LOG
;
172 raw_local_irq_save(flags
);
174 raw_local_irq_restore(flags
);
179 * clear_bit_unlock - Clears a bit in memory
181 * @addr: Address to start counting from
183 * clear_bit() is atomic and implies release semantics before the memory
184 * operation. It can be used for an unlock.
186 static inline void clear_bit_unlock(unsigned long nr
, volatile unsigned long *addr
)
188 smp_mb__before_clear_bit();
193 * change_bit - Toggle a bit in memory
195 * @addr: Address to start counting from
197 * change_bit() is atomic and may not be reordered.
198 * Note that @nr may be almost arbitrarily large; this function is not
199 * restricted to acting on a single-word quantity.
201 static inline void change_bit(unsigned long nr
, volatile unsigned long *addr
)
203 unsigned short bit
= nr
& SZLONG_MASK
;
205 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
206 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
209 __asm__
__volatile__(
211 "1: " __LL
"%0, %1 # change_bit \n"
216 : "=&r" (temp
), "=m" (*m
)
217 : "ir" (1UL << bit
), "m" (*m
));
218 } else if (cpu_has_llsc
) {
219 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
222 __asm__
__volatile__(
224 "1: " __LL
"%0, %1 # change_bit \n"
232 : "=&r" (temp
), "=m" (*m
)
233 : "ir" (1UL << bit
), "m" (*m
));
235 volatile unsigned long *a
= addr
;
239 a
+= nr
>> SZLONG_LOG
;
241 raw_local_irq_save(flags
);
243 raw_local_irq_restore(flags
);
248 * test_and_set_bit - Set a bit and return its old value
250 * @addr: Address to count from
252 * This operation is atomic and cannot be reordered.
253 * It also implies a memory barrier.
255 static inline int test_and_set_bit(unsigned long nr
,
256 volatile unsigned long *addr
)
258 unsigned short bit
= nr
& SZLONG_MASK
;
263 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
264 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
267 __asm__
__volatile__(
269 "1: " __LL
"%0, %1 # test_and_set_bit \n"
275 : "=&r" (temp
), "=m" (*m
), "=&r" (res
)
276 : "r" (1UL << bit
), "m" (*m
)
278 } else if (cpu_has_llsc
) {
279 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
282 __asm__
__volatile__(
286 "1: " __LL
"%0, %1 # test_and_set_bit \n"
296 : "=&r" (temp
), "=m" (*m
), "=&r" (res
)
297 : "r" (1UL << bit
), "m" (*m
)
300 volatile unsigned long *a
= addr
;
304 a
+= nr
>> SZLONG_LOG
;
306 raw_local_irq_save(flags
);
309 raw_local_irq_restore(flags
);
318 * test_and_set_bit_lock - Set a bit and return its old value
320 * @addr: Address to count from
322 * This operation is atomic and implies acquire ordering semantics
323 * after the memory operation.
325 static inline int test_and_set_bit_lock(unsigned long nr
,
326 volatile unsigned long *addr
)
328 unsigned short bit
= nr
& SZLONG_MASK
;
331 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
332 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
335 __asm__
__volatile__(
337 "1: " __LL
"%0, %1 # test_and_set_bit \n"
343 : "=&r" (temp
), "=m" (*m
), "=&r" (res
)
344 : "r" (1UL << bit
), "m" (*m
)
346 } else if (cpu_has_llsc
) {
347 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
350 __asm__
__volatile__(
354 "1: " __LL
"%0, %1 # test_and_set_bit \n"
364 : "=&r" (temp
), "=m" (*m
), "=&r" (res
)
365 : "r" (1UL << bit
), "m" (*m
)
368 volatile unsigned long *a
= addr
;
372 a
+= nr
>> SZLONG_LOG
;
374 raw_local_irq_save(flags
);
377 raw_local_irq_restore(flags
);
385 * test_and_clear_bit - Clear a bit and return its old value
387 * @addr: Address to count from
389 * This operation is atomic and cannot be reordered.
390 * It also implies a memory barrier.
392 static inline int test_and_clear_bit(unsigned long nr
,
393 volatile unsigned long *addr
)
395 unsigned short bit
= nr
& SZLONG_MASK
;
400 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
401 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
404 __asm__
__volatile__(
406 "1: " __LL
"%0, %1 # test_and_clear_bit \n"
413 : "=&r" (temp
), "=m" (*m
), "=&r" (res
)
414 : "r" (1UL << bit
), "m" (*m
)
416 #ifdef CONFIG_CPU_MIPSR2
417 } else if (__builtin_constant_p(nr
)) {
418 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
421 __asm__
__volatile__(
422 "1: " __LL
"%0, %1 # test_and_clear_bit \n"
423 " " __EXT
"%2, %0, %3, 1 \n"
424 " " __INS
"%0, $0, %3, 1 \n"
430 : "=&r" (temp
), "=m" (*m
), "=&r" (res
)
431 : "i" (bit
), "m" (*m
)
434 } else if (cpu_has_llsc
) {
435 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
438 __asm__
__volatile__(
442 "1: " __LL
"%0, %1 # test_and_clear_bit \n"
453 : "=&r" (temp
), "=m" (*m
), "=&r" (res
)
454 : "r" (1UL << bit
), "m" (*m
)
457 volatile unsigned long *a
= addr
;
461 a
+= nr
>> SZLONG_LOG
;
463 raw_local_irq_save(flags
);
466 raw_local_irq_restore(flags
);
475 * test_and_change_bit - Change a bit and return its old value
477 * @addr: Address to count from
479 * This operation is atomic and cannot be reordered.
480 * It also implies a memory barrier.
482 static inline int test_and_change_bit(unsigned long nr
,
483 volatile unsigned long *addr
)
485 unsigned short bit
= nr
& SZLONG_MASK
;
490 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
491 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
494 __asm__
__volatile__(
496 "1: " __LL
"%0, %1 # test_and_change_bit \n"
502 : "=&r" (temp
), "=m" (*m
), "=&r" (res
)
503 : "r" (1UL << bit
), "m" (*m
)
505 } else if (cpu_has_llsc
) {
506 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
509 __asm__
__volatile__(
513 "1: " __LL
"%0, %1 # test_and_change_bit \n"
515 " " __SC
"\t%2, %1 \n"
523 : "=&r" (temp
), "=m" (*m
), "=&r" (res
)
524 : "r" (1UL << bit
), "m" (*m
)
527 volatile unsigned long *a
= addr
;
531 a
+= nr
>> SZLONG_LOG
;
533 raw_local_irq_save(flags
);
536 raw_local_irq_restore(flags
);
544 #include <asm-generic/bitops/non-atomic.h>
547 * __clear_bit_unlock - Clears a bit in memory
549 * @addr: Address to start counting from
551 * __clear_bit() is non-atomic and implies release semantics before the memory
552 * operation. It can be used for an unlock if no other CPUs can concurrently
553 * modify other bits in the word.
555 static inline void __clear_bit_unlock(unsigned long nr
, volatile unsigned long *addr
)
558 __clear_bit(nr
, addr
);
561 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
564 * Return the bit position (0..63) of the most significant 1 bit in a word
565 * Returns -1 if no 1 bit exists
567 static inline unsigned long __fls(unsigned long x
)
571 if (sizeof(x
) == 4) {
583 BUG_ON(sizeof(x
) != 8);
597 * __ffs - find first bit in word.
598 * @word: The word to search
600 * Returns 0..SZLONG-1
601 * Undefined if no bit exists, so code should check against 0 first.
603 static inline unsigned long __ffs(unsigned long word
)
605 return __fls(word
& -word
);
609 * fls - find last bit set.
610 * @word: The word to search
612 * This is defined the same way as ffs.
613 * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
615 static inline int fls(int word
)
617 __asm__("clz %0, %1" : "=r" (word
) : "r" (word
));
622 #if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64)
623 static inline int fls64(__u64 word
)
625 __asm__("dclz %0, %1" : "=r" (word
) : "r" (word
));
630 #include <asm-generic/bitops/fls64.h>
634 * ffs - find first bit set.
635 * @word: The word to search
637 * This is defined the same way as
638 * the libc and compiler builtin ffs routines, therefore
639 * differs in spirit from the above ffz (man ffs).
641 static inline int ffs(int word
)
646 return fls(word
& -word
);
651 #include <asm-generic/bitops/__ffs.h>
652 #include <asm-generic/bitops/__fls.h>
653 #include <asm-generic/bitops/ffs.h>
654 #include <asm-generic/bitops/fls.h>
655 #include <asm-generic/bitops/fls64.h>
657 #endif /*defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) */
659 #include <asm-generic/bitops/ffz.h>
660 #include <asm-generic/bitops/find.h>
664 #include <asm-generic/bitops/sched.h>
665 #include <asm-generic/bitops/hweight.h>
666 #include <asm-generic/bitops/ext2-non-atomic.h>
667 #include <asm-generic/bitops/ext2-atomic.h>
668 #include <asm-generic/bitops/minix.h>
670 #endif /* __KERNEL__ */
672 #endif /* _ASM_BITOPS_H */
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