2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (c) 1994 - 1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (c) 1999, 2000 Silicon Graphics, Inc.
12 #include <linux/compiler.h>
13 #include <linux/irqflags.h>
14 #include <linux/types.h>
15 #include <asm/barrier.h>
17 #include <asm/byteorder.h> /* sigh ... */
18 #include <asm/cpu-features.h>
19 #include <asm/sgidefs.h>
22 #if (_MIPS_SZLONG == 32)
24 #define SZLONG_MASK 31UL
29 #elif (_MIPS_SZLONG == 64)
31 #define SZLONG_MASK 63UL
39 * clear_bit() doesn't provide any barrier for the compiler.
41 #define smp_mb__before_clear_bit() smp_mb()
42 #define smp_mb__after_clear_bit() smp_mb()
45 * set_bit - Atomically set a bit in memory
47 * @addr: the address to start counting from
49 * This function is atomic and may not be reordered. See __set_bit()
50 * if you do not require the atomic guarantees.
51 * Note that @nr may be almost arbitrarily large; this function is not
52 * restricted to acting on a single-word quantity.
54 static inline void set_bit(unsigned long nr
, volatile unsigned long *addr
)
56 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
57 unsigned short bit
= nr
& SZLONG_MASK
;
60 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
63 "1: " __LL
"%0, %1 # set_bit \n"
68 : "=&r" (temp
), "=m" (*m
)
69 : "ir" (1UL << bit
), "m" (*m
));
70 #ifdef CONFIG_CPU_MIPSR2
71 } else if (__builtin_constant_p(bit
)) {
73 "1: " __LL
"%0, %1 # set_bit \n"
74 " " __INS
"%0, %4, %2, 1 \n"
80 : "=&r" (temp
), "=m" (*m
)
81 : "ir" (bit
), "m" (*m
), "r" (~0));
82 #endif /* CONFIG_CPU_MIPSR2 */
83 } else if (cpu_has_llsc
) {
86 "1: " __LL
"%0, %1 # set_bit \n"
94 : "=&r" (temp
), "=m" (*m
)
95 : "ir" (1UL << bit
), "m" (*m
));
97 volatile unsigned long *a
= addr
;
101 a
+= nr
>> SZLONG_LOG
;
103 raw_local_irq_save(flags
);
105 raw_local_irq_restore(flags
);
110 * clear_bit - Clears a bit in memory
112 * @addr: Address to start counting from
114 * clear_bit() is atomic and may not be reordered. However, it does
115 * not contain a memory barrier, so if it is used for locking purposes,
116 * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
117 * in order to ensure changes are visible on other processors.
119 static inline void clear_bit(unsigned long nr
, volatile unsigned long *addr
)
121 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
122 unsigned short bit
= nr
& SZLONG_MASK
;
125 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
126 __asm__
__volatile__(
128 "1: " __LL
"%0, %1 # clear_bit \n"
133 : "=&r" (temp
), "=m" (*m
)
134 : "ir" (~(1UL << bit
)), "m" (*m
));
135 #ifdef CONFIG_CPU_MIPSR2
136 } else if (__builtin_constant_p(bit
)) {
137 __asm__
__volatile__(
138 "1: " __LL
"%0, %1 # clear_bit \n"
139 " " __INS
"%0, $0, %2, 1 \n"
145 : "=&r" (temp
), "=m" (*m
)
146 : "ir" (bit
), "m" (*m
));
147 #endif /* CONFIG_CPU_MIPSR2 */
148 } else if (cpu_has_llsc
) {
149 __asm__
__volatile__(
151 "1: " __LL
"%0, %1 # clear_bit \n"
159 : "=&r" (temp
), "=m" (*m
)
160 : "ir" (~(1UL << bit
)), "m" (*m
));
162 volatile unsigned long *a
= addr
;
166 a
+= nr
>> SZLONG_LOG
;
168 raw_local_irq_save(flags
);
170 raw_local_irq_restore(flags
);
175 * change_bit - Toggle a bit in memory
177 * @addr: Address to start counting from
179 * change_bit() is atomic and may not be reordered.
180 * Note that @nr may be almost arbitrarily large; this function is not
181 * restricted to acting on a single-word quantity.
183 static inline void change_bit(unsigned long nr
, volatile unsigned long *addr
)
185 unsigned short bit
= nr
& SZLONG_MASK
;
187 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
188 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
191 __asm__
__volatile__(
193 "1: " __LL
"%0, %1 # change_bit \n"
198 : "=&r" (temp
), "=m" (*m
)
199 : "ir" (1UL << bit
), "m" (*m
));
200 } else if (cpu_has_llsc
) {
201 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
204 __asm__
__volatile__(
206 "1: " __LL
"%0, %1 # change_bit \n"
214 : "=&r" (temp
), "=m" (*m
)
215 : "ir" (1UL << bit
), "m" (*m
));
217 volatile unsigned long *a
= addr
;
221 a
+= nr
>> SZLONG_LOG
;
223 raw_local_irq_save(flags
);
225 raw_local_irq_restore(flags
);
230 * test_and_set_bit - Set a bit and return its old value
232 * @addr: Address to count from
234 * This operation is atomic and cannot be reordered.
235 * It also implies a memory barrier.
237 static inline int test_and_set_bit(unsigned long nr
,
238 volatile unsigned long *addr
)
240 unsigned short bit
= nr
& SZLONG_MASK
;
242 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
243 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
244 unsigned long temp
, res
;
246 __asm__
__volatile__(
248 "1: " __LL
"%0, %1 # test_and_set_bit \n"
254 : "=&r" (temp
), "=m" (*m
), "=&r" (res
)
255 : "r" (1UL << bit
), "m" (*m
)
259 } else if (cpu_has_llsc
) {
260 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
261 unsigned long temp
, res
;
263 __asm__
__volatile__(
267 "1: " __LL
"%0, %1 # test_and_set_bit \n"
277 : "=&r" (temp
), "=m" (*m
), "=&r" (res
)
278 : "r" (1UL << bit
), "m" (*m
)
283 volatile unsigned long *a
= addr
;
288 a
+= nr
>> SZLONG_LOG
;
290 raw_local_irq_save(flags
);
291 retval
= (mask
& *a
) != 0;
293 raw_local_irq_restore(flags
);
302 * test_and_clear_bit - Clear a bit and return its old value
304 * @addr: Address to count from
306 * This operation is atomic and cannot be reordered.
307 * It also implies a memory barrier.
309 static inline int test_and_clear_bit(unsigned long nr
,
310 volatile unsigned long *addr
)
312 unsigned short bit
= nr
& SZLONG_MASK
;
314 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
315 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
316 unsigned long temp
, res
;
318 __asm__
__volatile__(
320 "1: " __LL
"%0, %1 # test_and_clear_bit \n"
327 : "=&r" (temp
), "=m" (*m
), "=&r" (res
)
328 : "r" (1UL << bit
), "m" (*m
)
332 #ifdef CONFIG_CPU_MIPSR2
333 } else if (__builtin_constant_p(nr
)) {
334 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
335 unsigned long temp
, res
;
337 __asm__
__volatile__(
338 "1: " __LL
"%0, %1 # test_and_clear_bit \n"
339 " " __EXT
"%2, %0, %3, 1 \n"
340 " " __INS
"%0, $0, %3, 1 \n"
346 : "=&r" (temp
), "=m" (*m
), "=&r" (res
)
347 : "ri" (bit
), "m" (*m
)
352 } else if (cpu_has_llsc
) {
353 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
354 unsigned long temp
, res
;
356 __asm__
__volatile__(
360 "1: " __LL
"%0, %1 # test_and_clear_bit \n"
371 : "=&r" (temp
), "=m" (*m
), "=&r" (res
)
372 : "r" (1UL << bit
), "m" (*m
)
377 volatile unsigned long *a
= addr
;
382 a
+= nr
>> SZLONG_LOG
;
384 raw_local_irq_save(flags
);
385 retval
= (mask
& *a
) != 0;
387 raw_local_irq_restore(flags
);
396 * test_and_change_bit - Change a bit and return its old value
398 * @addr: Address to count from
400 * This operation is atomic and cannot be reordered.
401 * It also implies a memory barrier.
403 static inline int test_and_change_bit(unsigned long nr
,
404 volatile unsigned long *addr
)
406 unsigned short bit
= nr
& SZLONG_MASK
;
408 if (cpu_has_llsc
&& R10000_LLSC_WAR
) {
409 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
410 unsigned long temp
, res
;
412 __asm__
__volatile__(
414 "1: " __LL
"%0, %1 # test_and_change_bit \n"
420 : "=&r" (temp
), "=m" (*m
), "=&r" (res
)
421 : "r" (1UL << bit
), "m" (*m
)
425 } else if (cpu_has_llsc
) {
426 unsigned long *m
= ((unsigned long *) addr
) + (nr
>> SZLONG_LOG
);
427 unsigned long temp
, res
;
429 __asm__
__volatile__(
433 "1: " __LL
"%0, %1 # test_and_change_bit \n"
435 " " __SC
"\t%2, %1 \n"
443 : "=&r" (temp
), "=m" (*m
), "=&r" (res
)
444 : "r" (1UL << bit
), "m" (*m
)
449 volatile unsigned long *a
= addr
;
450 unsigned long mask
, retval
;
453 a
+= nr
>> SZLONG_LOG
;
455 raw_local_irq_save(flags
);
456 retval
= (mask
& *a
) != 0;
458 raw_local_irq_restore(flags
);
466 #include <asm-generic/bitops/non-atomic.h>
469 * Return the bit position (0..63) of the most significant 1 bit in a word
470 * Returns -1 if no 1 bit exists
472 static inline int __ilog2(unsigned long x
)
476 if (sizeof(x
) == 4) {
488 BUG_ON(sizeof(x
) != 8);
501 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
504 * __ffs - find first bit in word.
505 * @word: The word to search
507 * Returns 0..SZLONG-1
508 * Undefined if no bit exists, so code should check against 0 first.
510 static inline unsigned long __ffs(unsigned long word
)
512 return __ilog2(word
& -word
);
516 * fls - find last bit set.
517 * @word: The word to search
519 * This is defined the same way as ffs.
520 * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
522 static inline int fls(int word
)
524 __asm__ ("clz %0, %1" : "=r" (word
) : "r" (word
));
529 #if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64)
530 static inline int fls64(__u64 word
)
532 __asm__ ("dclz %0, %1" : "=r" (word
) : "r" (word
));
537 #include <asm-generic/bitops/fls64.h>
541 * ffs - find first bit set.
542 * @word: The word to search
544 * This is defined the same way as
545 * the libc and compiler builtin ffs routines, therefore
546 * differs in spirit from the above ffz (man ffs).
548 static inline int ffs(int word
)
553 return fls(word
& -word
);
558 #include <asm-generic/bitops/__ffs.h>
559 #include <asm-generic/bitops/ffs.h>
560 #include <asm-generic/bitops/fls.h>
561 #include <asm-generic/bitops/fls64.h>
563 #endif /*defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) */
565 #include <asm-generic/bitops/ffz.h>
566 #include <asm-generic/bitops/find.h>
570 #include <asm-generic/bitops/sched.h>
571 #include <asm-generic/bitops/hweight.h>
572 #include <asm-generic/bitops/ext2-non-atomic.h>
573 #include <asm-generic/bitops/ext2-atomic.h>
574 #include <asm-generic/bitops/minix.h>
576 #endif /* __KERNEL__ */
578 #endif /* _ASM_BITOPS_H */
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