include/asm-mips/mach-au1x00/au1xxx_psc.h

   1 /*
   2  *
   3  * BRIEF MODULE DESCRIPTION
   4  *      Include file for Alchemy Semiconductor's Au1k CPU.
   5  *
   6  * Copyright 2004 Embedded Edge, LLC
   7  *      dan@embeddededge.com
   8  *
   9  *  This program is free software; you can redistribute  it and/or modify it
  10  *  under  the terms of  the GNU General  Public License as published by the
  11  *  Free Software Foundation;  either version 2 of the  License, or (at your
  12  *  option) any later version.
  13  *
  14  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  15  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  16  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  17  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  18  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  19  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  20  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  21  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  22  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  23  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24  *
  25  *  You should have received a copy of the  GNU General Public License along
  26  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  27  *  675 Mass Ave, Cambridge, MA 02139, USA.
  28  */
  29
  30 /* Specifics for the Au1xxx Programmable Serial Controllers, first
  31  * seen in the AU1550 part.
  32  */
  33 #ifndef _AU1000_PSC_H_
  34 #define _AU1000_PSC_H_
  35
  36 /* The PSC base addresses.  */
  37 #ifdef CONFIG_SOC_AU1550
  38 #define PSC0_BASE_ADDR          0xb1a00000
  39 #define PSC1_BASE_ADDR          0xb1b00000
  40 #define PSC2_BASE_ADDR          0xb0a00000
  41 #define PSC3_BASE_ADDR          0xb0b00000
  42 #endif
  43
  44 #ifdef CONFIG_SOC_AU1200
  45 #define PSC0_BASE_ADDR          0xb1a00000
  46 #define PSC1_BASE_ADDR          0xb1b00000
  47 #endif
  48
  49 /*
  50  * The PSC select and control registers are common to all protocols.
  51  */
  52 #define PSC_SEL_OFFSET          0x00000000
  53 #define PSC_CTRL_OFFSET         0x00000004
  54
  55 #define PSC_SEL_CLK_MASK        (3 << 4)
  56 #define PSC_SEL_CLK_INTCLK      (0 << 4)
  57 #define PSC_SEL_CLK_EXTCLK      (1 << 4)
  58 #define PSC_SEL_CLK_SERCLK      (2 << 4)
  59
  60 #define PSC_SEL_PS_MASK         0x00000007
  61 #define PSC_SEL_PS_DISABLED     0
  62 #define PSC_SEL_PS_SPIMODE      2
  63 #define PSC_SEL_PS_I2SMODE      3
  64 #define PSC_SEL_PS_AC97MODE     4
  65 #define PSC_SEL_PS_SMBUSMODE    5
  66
  67 #define PSC_CTRL_DISABLE        0
  68 #define PSC_CTRL_SUSPEND        2
  69 #define PSC_CTRL_ENABLE         3
  70
  71 /* AC97 Registers. */
  72 #define PSC_AC97CFG_OFFSET      0x00000008
  73 #define PSC_AC97MSK_OFFSET      0x0000000c
  74 #define PSC_AC97PCR_OFFSET      0x00000010
  75 #define PSC_AC97STAT_OFFSET     0x00000014
  76 #define PSC_AC97EVNT_OFFSET     0x00000018
  77 #define PSC_AC97TXRX_OFFSET     0x0000001c
  78 #define PSC_AC97CDC_OFFSET      0x00000020
  79 #define PSC_AC97RST_OFFSET      0x00000024
  80 #define PSC_AC97GPO_OFFSET      0x00000028
  81 #define PSC_AC97GPI_OFFSET      0x0000002c
  82
  83 #define AC97_PSC_SEL            (AC97_PSC_BASE + PSC_SEL_OFFSET)
  84 #define AC97_PSC_CTRL           (AC97_PSC_BASE + PSC_CTRL_OFFSET)
  85 #define PSC_AC97CFG             (AC97_PSC_BASE + PSC_AC97CFG_OFFSET)
  86 #define PSC_AC97MSK             (AC97_PSC_BASE + PSC_AC97MSK_OFFSET)
  87 #define PSC_AC97PCR             (AC97_PSC_BASE + PSC_AC97PCR_OFFSET)
  88 #define PSC_AC97STAT            (AC97_PSC_BASE + PSC_AC97STAT_OFFSET)
  89 #define PSC_AC97EVNT            (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET)
  90 #define PSC_AC97TXRX            (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET)
  91 #define PSC_AC97CDC             (AC97_PSC_BASE + PSC_AC97CDC_OFFSET)
  92 #define PSC_AC97RST             (AC97_PSC_BASE + PSC_AC97RST_OFFSET)
  93 #define PSC_AC97GPO             (AC97_PSC_BASE + PSC_AC97GPO_OFFSET)
  94 #define PSC_AC97GPI             (AC97_PSC_BASE + PSC_AC97GPI_OFFSET)
  95
  96 /* AC97 Config Register. */
  97 #define PSC_AC97CFG_RT_MASK     (3 << 30)
  98 #define PSC_AC97CFG_RT_FIFO1    (0 << 30)
  99 #define PSC_AC97CFG_RT_FIFO2    (1 << 30)
 100 #define PSC_AC97CFG_RT_FIFO4    (2 << 30)
 101 #define PSC_AC97CFG_RT_FIFO8    (3 << 30)
 102
 103 #define PSC_AC97CFG_TT_MASK     (3 << 28)
 104 #define PSC_AC97CFG_TT_FIFO1    (0 << 28)
 105 #define PSC_AC97CFG_TT_FIFO2    (1 << 28)
 106 #define PSC_AC97CFG_TT_FIFO4    (2 << 28)
 107 #define PSC_AC97CFG_TT_FIFO8    (3 << 28)
 108
 109 #define PSC_AC97CFG_DD_DISABLE  (1 << 27)
 110 #define PSC_AC97CFG_DE_ENABLE   (1 << 26)
 111 #define PSC_AC97CFG_SE_ENABLE   (1 << 25)
 112
 113 #define PSC_AC97CFG_LEN_MASK    (0xf << 21)
 114 #define PSC_AC97CFG_TXSLOT_MASK (0x3ff << 11)
 115 #define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1)
 116 #define PSC_AC97CFG_GE_ENABLE   (1)
 117
 118 /* Enable slots 3-12. */
 119 #define PSC_AC97CFG_TXSLOT_ENA(x)       (1 << (((x) - 3) + 11))
 120 #define PSC_AC97CFG_RXSLOT_ENA(x)       (1 << (((x) - 3) + 1))
 121
 122 /*
 123  * The word length equation is ((x) * 2) + 2, so choose 'x' appropriately.
 124  * The only sensible numbers are 7, 9, or possibly 11.  Nah, just do the
 125  * arithmetic in the macro.
 126  */
 127 #define PSC_AC97CFG_SET_LEN(x)  (((((x) - 2) / 2) & 0xf) << 21)
 128 #define PSC_AC97CFG_GET_LEN(x)  (((((x) >> 21) & 0xf) * 2) + 2)
 129
 130 /* AC97 Mask Register. */
 131 #define PSC_AC97MSK_GR          (1 << 25)
 132 #define PSC_AC97MSK_CD          (1 << 24)
 133 #define PSC_AC97MSK_RR          (1 << 13)
 134 #define PSC_AC97MSK_RO          (1 << 12)
 135 #define PSC_AC97MSK_RU          (1 << 11)
 136 #define PSC_AC97MSK_TR          (1 << 10)
 137 #define PSC_AC97MSK_TO          (1 << 9)
 138 #define PSC_AC97MSK_TU          (1 << 8)
 139 #define PSC_AC97MSK_RD          (1 << 5)
 140 #define PSC_AC97MSK_TD          (1 << 4)
 141 #define PSC_AC97MSK_ALLMASK     (PSC_AC97MSK_GR | PSC_AC97MSK_CD | \
 142                                  PSC_AC97MSK_RR | PSC_AC97MSK_RO | \
 143                                  PSC_AC97MSK_RU | PSC_AC97MSK_TR | \
 144                                  PSC_AC97MSK_TO | PSC_AC97MSK_TU | \
 145                                  PSC_AC97MSK_RD | PSC_AC97MSK_TD)
 146
 147 /* AC97 Protocol Control Register. */
 148 #define PSC_AC97PCR_RC          (1 << 6)
 149 #define PSC_AC97PCR_RP          (1 << 5)
 150 #define PSC_AC97PCR_RS          (1 << 4)
 151 #define PSC_AC97PCR_TC          (1 << 2)
 152 #define PSC_AC97PCR_TP          (1 << 1)
 153 #define PSC_AC97PCR_TS          (1 << 0)
 154
 155 /* AC97 Status register (read only). */
 156 #define PSC_AC97STAT_CB         (1 << 26)
 157 #define PSC_AC97STAT_CP         (1 << 25)
 158 #define PSC_AC97STAT_CR         (1 << 24)
 159 #define PSC_AC97STAT_RF         (1 << 13)
 160 #define PSC_AC97STAT_RE         (1 << 12)
 161 #define PSC_AC97STAT_RR         (1 << 11)
 162 #define PSC_AC97STAT_TF         (1 << 10)
 163 #define PSC_AC97STAT_TE         (1 << 9)
 164 #define PSC_AC97STAT_TR         (1 << 8)
 165 #define PSC_AC97STAT_RB         (1 << 5)
 166 #define PSC_AC97STAT_TB         (1 << 4)
 167 #define PSC_AC97STAT_DI         (1 << 2)
 168 #define PSC_AC97STAT_DR         (1 << 1)
 169 #define PSC_AC97STAT_SR         (1 << 0)
 170
 171 /* AC97 Event Register. */
 172 #define PSC_AC97EVNT_GR         (1 << 25)
 173 #define PSC_AC97EVNT_CD         (1 << 24)
 174 #define PSC_AC97EVNT_RR         (1 << 13)
 175 #define PSC_AC97EVNT_RO         (1 << 12)
 176 #define PSC_AC97EVNT_RU         (1 << 11)
 177 #define PSC_AC97EVNT_TR         (1 << 10)
 178 #define PSC_AC97EVNT_TO         (1 << 9)
 179 #define PSC_AC97EVNT_TU         (1 << 8)
 180 #define PSC_AC97EVNT_RD         (1 << 5)
 181 #define PSC_AC97EVNT_TD         (1 << 4)
 182
 183 /* CODEC Command Register. */
 184 #define PSC_AC97CDC_RD          (1 << 25)
 185 #define PSC_AC97CDC_ID_MASK     (3 << 23)
 186 #define PSC_AC97CDC_INDX_MASK   (0x7f << 16)
 187 #define PSC_AC97CDC_ID(x)       (((x) & 0x03) << 23)
 188 #define PSC_AC97CDC_INDX(x)     (((x) & 0x7f) << 16)
 189
 190 /* AC97 Reset Control Register. */
 191 #define PSC_AC97RST_RST         (1 << 1)
 192 #define PSC_AC97RST_SNC         (1 << 0)
 193
 194 /* PSC in I2S Mode. */
 195 typedef struct  psc_i2s {
 196         u32     psc_sel;
 197         u32     psc_ctrl;
 198         u32     psc_i2scfg;
 199         u32     psc_i2smsk;
 200         u32     psc_i2spcr;
 201         u32     psc_i2sstat;
 202         u32     psc_i2sevent;
 203         u32     psc_i2stxrx;
 204         u32     psc_i2sudf;
 205 } psc_i2s_t;
 206
 207 /* I2S Config Register. */
 208 #define PSC_I2SCFG_RT_MASK      (3 << 30)
 209 #define PSC_I2SCFG_RT_FIFO1     (0 << 30)
 210 #define PSC_I2SCFG_RT_FIFO2     (1 << 30)
 211 #define PSC_I2SCFG_RT_FIFO4     (2 << 30)
 212 #define PSC_I2SCFG_RT_FIFO8     (3 << 30)
 213
 214 #define PSC_I2SCFG_TT_MASK      (3 << 28)
 215 #define PSC_I2SCFG_TT_FIFO1     (0 << 28)
 216 #define PSC_I2SCFG_TT_FIFO2     (1 << 28)
 217 #define PSC_I2SCFG_TT_FIFO4     (2 << 28)
 218 #define PSC_I2SCFG_TT_FIFO8     (3 << 28)
 219
 220 #define PSC_I2SCFG_DD_DISABLE   (1 << 27)
 221 #define PSC_I2SCFG_DE_ENABLE    (1 << 26)
 222 #define PSC_I2SCFG_SET_WS(x)    (((((x) / 2) - 1) & 0x7f) << 16)
 223 #define PSC_I2SCFG_WS(n)        ((n & 0xFF) << 16)
 224 #define PSC_I2SCFG_WS_MASK      (PSC_I2SCFG_WS(0x3F))
 225 #define PSC_I2SCFG_WI           (1 << 15)
 226
 227 #define PSC_I2SCFG_DIV_MASK     (3 << 13)
 228 #define PSC_I2SCFG_DIV2         (0 << 13)
 229 #define PSC_I2SCFG_DIV4         (1 << 13)
 230 #define PSC_I2SCFG_DIV8         (2 << 13)
 231 #define PSC_I2SCFG_DIV16        (3 << 13)
 232
 233 #define PSC_I2SCFG_BI           (1 << 12)
 234 #define PSC_I2SCFG_BUF          (1 << 11)
 235 #define PSC_I2SCFG_MLJ          (1 << 10)
 236 #define PSC_I2SCFG_XM           (1 << 9)
 237
 238 /* The word length equation is simply LEN+1. */
 239 #define PSC_I2SCFG_SET_LEN(x)   ((((x) - 1) & 0x1f) << 4)
 240 #define PSC_I2SCFG_GET_LEN(x)   ((((x) >> 4) & 0x1f) + 1)
 241
 242 #define PSC_I2SCFG_LB           (1 << 2)
 243 #define PSC_I2SCFG_MLF          (1 << 1)
 244 #define PSC_I2SCFG_MS           (1 << 0)
 245
 246 /* I2S Mask Register. */
 247 #define PSC_I2SMSK_RR           (1 << 13)
 248 #define PSC_I2SMSK_RO           (1 << 12)
 249 #define PSC_I2SMSK_RU           (1 << 11)
 250 #define PSC_I2SMSK_TR           (1 << 10)
 251 #define PSC_I2SMSK_TO           (1 << 9)
 252 #define PSC_I2SMSK_TU           (1 << 8)
 253 #define PSC_I2SMSK_RD           (1 << 5)
 254 #define PSC_I2SMSK_TD           (1 << 4)
 255 #define PSC_I2SMSK_ALLMASK      (PSC_I2SMSK_RR | PSC_I2SMSK_RO | \
 256                                  PSC_I2SMSK_RU | PSC_I2SMSK_TR | \
 257                                  PSC_I2SMSK_TO | PSC_I2SMSK_TU | \
 258                                  PSC_I2SMSK_RD | PSC_I2SMSK_TD)
 259
 260 /* I2S Protocol Control Register. */
 261 #define PSC_I2SPCR_RC           (1 << 6)
 262 #define PSC_I2SPCR_RP           (1 << 5)
 263 #define PSC_I2SPCR_RS           (1 << 4)
 264 #define PSC_I2SPCR_TC           (1 << 2)
 265 #define PSC_I2SPCR_TP           (1 << 1)
 266 #define PSC_I2SPCR_TS           (1 << 0)
 267
 268 /* I2S Status register (read only). */
 269 #define PSC_I2SSTAT_RF          (1 << 13)
 270 #define PSC_I2SSTAT_RE          (1 << 12)
 271 #define PSC_I2SSTAT_RR          (1 << 11)
 272 #define PSC_I2SSTAT_TF          (1 << 10)
 273 #define PSC_I2SSTAT_TE          (1 << 9)
 274 #define PSC_I2SSTAT_TR          (1 << 8)
 275 #define PSC_I2SSTAT_RB          (1 << 5)
 276 #define PSC_I2SSTAT_TB          (1 << 4)
 277 #define PSC_I2SSTAT_DI          (1 << 2)
 278 #define PSC_I2SSTAT_DR          (1 << 1)
 279 #define PSC_I2SSTAT_SR          (1 << 0)
 280
 281 /* I2S Event Register. */
 282 #define PSC_I2SEVNT_RR          (1 << 13)
 283 #define PSC_I2SEVNT_RO          (1 << 12)
 284 #define PSC_I2SEVNT_RU          (1 << 11)
 285 #define PSC_I2SEVNT_TR          (1 << 10)
 286 #define PSC_I2SEVNT_TO          (1 << 9)
 287 #define PSC_I2SEVNT_TU          (1 << 8)
 288 #define PSC_I2SEVNT_RD          (1 << 5)
 289 #define PSC_I2SEVNT_TD          (1 << 4)
 290
 291 /* PSC in SPI Mode. */
 292 typedef struct  psc_spi {
 293         u32     psc_sel;
 294         u32     psc_ctrl;
 295         u32     psc_spicfg;
 296         u32     psc_spimsk;
 297         u32     psc_spipcr;
 298         u32     psc_spistat;
 299         u32     psc_spievent;
 300         u32     psc_spitxrx;
 301 } psc_spi_t;
 302
 303 /* SPI Config Register. */
 304 #define PSC_SPICFG_RT_MASK      (3 << 30)
 305 #define PSC_SPICFG_RT_FIFO1     (0 << 30)
 306 #define PSC_SPICFG_RT_FIFO2     (1 << 30)
 307 #define PSC_SPICFG_RT_FIFO4     (2 << 30)
 308 #define PSC_SPICFG_RT_FIFO8     (3 << 30)
 309
 310 #define PSC_SPICFG_TT_MASK      (3 << 28)
 311 #define PSC_SPICFG_TT_FIFO1     (0 << 28)
 312 #define PSC_SPICFG_TT_FIFO2     (1 << 28)
 313 #define PSC_SPICFG_TT_FIFO4     (2 << 28)
 314 #define PSC_SPICFG_TT_FIFO8     (3 << 28)
 315
 316 #define PSC_SPICFG_DD_DISABLE   (1 << 27)
 317 #define PSC_SPICFG_DE_ENABLE    (1 << 26)
 318 #define PSC_SPICFG_CLR_BAUD(x)  ((x) & ~((0x3f) << 15))
 319 #define PSC_SPICFG_SET_BAUD(x)  (((x) & 0x3f) << 15)
 320
 321 #define PSC_SPICFG_SET_DIV(x)   (((x) & 0x03) << 13)
 322 #define PSC_SPICFG_DIV2         0
 323 #define PSC_SPICFG_DIV4         1
 324 #define PSC_SPICFG_DIV8         2
 325 #define PSC_SPICFG_DIV16        3
 326
 327 #define PSC_SPICFG_BI           (1 << 12)
 328 #define PSC_SPICFG_PSE          (1 << 11)
 329 #define PSC_SPICFG_CGE          (1 << 10)
 330 #define PSC_SPICFG_CDE          (1 << 9)
 331
 332 #define PSC_SPICFG_CLR_LEN(x)   ((x) & ~((0x1f) << 4))
 333 #define PSC_SPICFG_SET_LEN(x)   (((x-1) & 0x1f) << 4)
 334
 335 #define PSC_SPICFG_LB           (1 << 3)
 336 #define PSC_SPICFG_MLF          (1 << 1)
 337 #define PSC_SPICFG_MO           (1 << 0)
 338
 339 /* SPI Mask Register. */
 340 #define PSC_SPIMSK_MM           (1 << 16)
 341 #define PSC_SPIMSK_RR           (1 << 13)
 342 #define PSC_SPIMSK_RO           (1 << 12)
 343 #define PSC_SPIMSK_RU           (1 << 11)
 344 #define PSC_SPIMSK_TR           (1 << 10)
 345 #define PSC_SPIMSK_TO           (1 << 9)
 346 #define PSC_SPIMSK_TU           (1 << 8)
 347 #define PSC_SPIMSK_SD           (1 << 5)
 348 #define PSC_SPIMSK_MD           (1 << 4)
 349 #define PSC_SPIMSK_ALLMASK      (PSC_SPIMSK_MM | PSC_SPIMSK_RR | \
 350                                  PSC_SPIMSK_RO | PSC_SPIMSK_TO | \
 351                                  PSC_SPIMSK_TU | PSC_SPIMSK_SD | \
 352                                  PSC_SPIMSK_MD)
 353
 354 /* SPI Protocol Control Register. */
 355 #define PSC_SPIPCR_RC           (1 << 6)
 356 #define PSC_SPIPCR_SP           (1 << 5)
 357 #define PSC_SPIPCR_SS           (1 << 4)
 358 #define PSC_SPIPCR_TC           (1 << 2)
 359 #define PSC_SPIPCR_MS           (1 << 0)
 360
 361 /* SPI Status register (read only). */
 362 #define PSC_SPISTAT_RF          (1 << 13)
 363 #define PSC_SPISTAT_RE          (1 << 12)
 364 #define PSC_SPISTAT_RR          (1 << 11)
 365 #define PSC_SPISTAT_TF          (1 << 10)
 366 #define PSC_SPISTAT_TE          (1 << 9)
 367 #define PSC_SPISTAT_TR          (1 << 8)
 368 #define PSC_SPISTAT_SB          (1 << 5)
 369 #define PSC_SPISTAT_MB          (1 << 4)
 370 #define PSC_SPISTAT_DI          (1 << 2)
 371 #define PSC_SPISTAT_DR          (1 << 1)
 372 #define PSC_SPISTAT_SR          (1 << 0)
 373
 374 /* SPI Event Register. */
 375 #define PSC_SPIEVNT_MM          (1 << 16)
 376 #define PSC_SPIEVNT_RR          (1 << 13)
 377 #define PSC_SPIEVNT_RO          (1 << 12)
 378 #define PSC_SPIEVNT_RU          (1 << 11)
 379 #define PSC_SPIEVNT_TR          (1 << 10)
 380 #define PSC_SPIEVNT_TO          (1 << 9)
 381 #define PSC_SPIEVNT_TU          (1 << 8)
 382 #define PSC_SPIEVNT_SD          (1 << 5)
 383 #define PSC_SPIEVNT_MD          (1 << 4)
 384
 385 /* Transmit register control. */
 386 #define PSC_SPITXRX_LC          (1 << 29)
 387 #define PSC_SPITXRX_SR          (1 << 28)
 388
 389 /* PSC in SMBus (I2C) Mode. */
 390 typedef struct  psc_smb {
 391         u32     psc_sel;
 392         u32     psc_ctrl;
 393         u32     psc_smbcfg;
 394         u32     psc_smbmsk;
 395         u32     psc_smbpcr;
 396         u32     psc_smbstat;
 397         u32     psc_smbevnt;
 398         u32     psc_smbtxrx;
 399         u32     psc_smbtmr;
 400 } psc_smb_t;
 401
 402 /* SMBus Config Register. */
 403 #define PSC_SMBCFG_RT_MASK      (3 << 30)
 404 #define PSC_SMBCFG_RT_FIFO1     (0 << 30)
 405 #define PSC_SMBCFG_RT_FIFO2     (1 << 30)
 406 #define PSC_SMBCFG_RT_FIFO4     (2 << 30)
 407 #define PSC_SMBCFG_RT_FIFO8     (3 << 30)
 408
 409 #define PSC_SMBCFG_TT_MASK      (3 << 28)
 410 #define PSC_SMBCFG_TT_FIFO1     (0 << 28)
 411 #define PSC_SMBCFG_TT_FIFO2     (1 << 28)
 412 #define PSC_SMBCFG_TT_FIFO4     (2 << 28)
 413 #define PSC_SMBCFG_TT_FIFO8     (3 << 28)
 414
 415 #define PSC_SMBCFG_DD_DISABLE   (1 << 27)
 416 #define PSC_SMBCFG_DE_ENABLE    (1 << 26)
 417
 418 #define PSC_SMBCFG_SET_DIV(x)   (((x) & 0x03) << 13)
 419 #define PSC_SMBCFG_DIV2         0
 420 #define PSC_SMBCFG_DIV4         1
 421 #define PSC_SMBCFG_DIV8         2
 422 #define PSC_SMBCFG_DIV16        3
 423
 424 #define PSC_SMBCFG_GCE          (1 << 9)
 425 #define PSC_SMBCFG_SFM          (1 << 8)
 426
 427 #define PSC_SMBCFG_SET_SLV(x)   (((x) & 0x7f) << 1)
 428
 429 /* SMBus Mask Register. */
 430 #define PSC_SMBMSK_DN           (1 << 30)
 431 #define PSC_SMBMSK_AN           (1 << 29)
 432 #define PSC_SMBMSK_AL           (1 << 28)
 433 #define PSC_SMBMSK_RR           (1 << 13)
 434 #define PSC_SMBMSK_RO           (1 << 12)
 435 #define PSC_SMBMSK_RU           (1 << 11)
 436 #define PSC_SMBMSK_TR           (1 << 10)
 437 #define PSC_SMBMSK_TO           (1 << 9)
 438 #define PSC_SMBMSK_TU           (1 << 8)
 439 #define PSC_SMBMSK_SD           (1 << 5)
 440 #define PSC_SMBMSK_MD           (1 << 4)
 441 #define PSC_SMBMSK_ALLMASK      (PSC_SMBMSK_DN | PSC_SMBMSK_AN | \
 442                                  PSC_SMBMSK_AL | PSC_SMBMSK_RR | \
 443                                  PSC_SMBMSK_RO | PSC_SMBMSK_TO | \
 444                                  PSC_SMBMSK_TU | PSC_SMBMSK_SD | \
 445                                  PSC_SMBMSK_MD)
 446
 447 /* SMBus Protocol Control Register. */
 448 #define PSC_SMBPCR_DC           (1 << 2)
 449 #define PSC_SMBPCR_MS           (1 << 0)
 450
 451 /* SMBus Status register (read only). */
 452 #define PSC_SMBSTAT_BB          (1 << 28)
 453 #define PSC_SMBSTAT_RF          (1 << 13)
 454 #define PSC_SMBSTAT_RE          (1 << 12)
 455 #define PSC_SMBSTAT_RR          (1 << 11)
 456 #define PSC_SMBSTAT_TF          (1 << 10)
 457 #define PSC_SMBSTAT_TE          (1 << 9)
 458 #define PSC_SMBSTAT_TR          (1 << 8)
 459 #define PSC_SMBSTAT_SB          (1 << 5)
 460 #define PSC_SMBSTAT_MB          (1 << 4)
 461 #define PSC_SMBSTAT_DI          (1 << 2)
 462 #define PSC_SMBSTAT_DR          (1 << 1)
 463 #define PSC_SMBSTAT_SR          (1 << 0)
 464
 465 /* SMBus Event Register. */
 466 #define PSC_SMBEVNT_DN          (1 << 30)
 467 #define PSC_SMBEVNT_AN          (1 << 29)
 468 #define PSC_SMBEVNT_AL          (1 << 28)
 469 #define PSC_SMBEVNT_RR          (1 << 13)
 470 #define PSC_SMBEVNT_RO          (1 << 12)
 471 #define PSC_SMBEVNT_RU          (1 << 11)
 472 #define PSC_SMBEVNT_TR          (1 << 10)
 473 #define PSC_SMBEVNT_TO          (1 << 9)
 474 #define PSC_SMBEVNT_TU          (1 << 8)
 475 #define PSC_SMBEVNT_SD          (1 << 5)
 476 #define PSC_SMBEVNT_MD          (1 << 4)
 477 #define PSC_SMBEVNT_ALLCLR      (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | \
 478                                  PSC_SMBEVNT_AL | PSC_SMBEVNT_RR | \
 479                                  PSC_SMBEVNT_RO | PSC_SMBEVNT_TO | \
 480                                  PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \
 481                                  PSC_SMBEVNT_MD)
 482
 483 /* Transmit register control. */
 484 #define PSC_SMBTXRX_RSR         (1 << 28)
 485 #define PSC_SMBTXRX_STP         (1 << 29)
 486 #define PSC_SMBTXRX_DATAMASK    0xff
 487
 488 /* SMBus protocol timers register. */
 489 #define PSC_SMBTMR_SET_TH(x)    (((x) & 0x03) << 30)
 490 #define PSC_SMBTMR_SET_PS(x)    (((x) & 0x1f) << 25)
 491 #define PSC_SMBTMR_SET_PU(x)    (((x) & 0x1f) << 20)
 492 #define PSC_SMBTMR_SET_SH(x)    (((x) & 0x1f) << 15)
 493 #define PSC_SMBTMR_SET_SU(x)    (((x) & 0x1f) << 10)
 494 #define PSC_SMBTMR_SET_CL(x)    (((x) & 0x1f) << 5)
 495 #define PSC_SMBTMR_SET_CH(x)    (((x) & 0x1f) << 0)
 496
 497 #endif /* _AU1000_PSC_H_ */