5 * Definitions for SMTC multitasking on MIPS MT cores
8 #include <asm/mips_mt.h>
11 * System-wide SMTC status information
14 extern unsigned int smtc_status
;
16 #define SMTC_TLB_SHARED 0x00000001
17 #define SMTC_MTC_ACTIVE 0x00000002
20 * TLB/ASID Management information
23 #define MAX_SMTC_TLBS 2
24 #define MAX_SMTC_ASIDS 256
29 typedef short asiduse
;
35 extern asiduse smtc_live_asid
[MAX_SMTC_TLBS
][MAX_SMTC_ASIDS
];
40 void smtc_get_new_mmu_context(struct mm_struct
*mm
, unsigned long cpu
);
42 void smtc_flush_tlb_asid(unsigned long asid
);
43 extern int mipsmt_build_cpu_map(int startslot
);
44 extern void mipsmt_prepare_cpus(void);
45 extern void smtc_smp_finish(void);
46 extern void smtc_boot_secondary(int cpu
, struct task_struct
*t
);
47 extern void smtc_cpus_done(void);
50 * Sharing the TLB between multiple VPEs means that the
51 * "random" index selection function is not allowed to
52 * select the current value of the Index register. To
53 * avoid additional TLB pressure, the Index registers
54 * are "parked" with an non-Valid value.
57 #define PARKED_INDEX ((unsigned int)0x80000000)
60 * Define low-level interrupt mask for IPIs, if necessary.
61 * By default, use SW interrupt 1, which requires no external
62 * hardware support, but which works only for single-core
65 #ifndef MIPS_CPU_IPI_IRQ
66 #define MIPS_CPU_IPI_IRQ 1
69 #endif /* _ASM_SMTC_MT_H */
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