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[MIPS] Discard .exit.text at linktime.
[deliverable/linux.git] / include / asm-mips / system.h
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
7 * Copyright (C) 1996 by Paul M. Antoine
8 * Copyright (C) 1999 Silicon Graphics
9 * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000 MIPS Technologies, Inc.
11 */
12 #ifndef _ASM_SYSTEM_H
13 #define _ASM_SYSTEM_H
14
15 #include <linux/types.h>
16 #include <linux/irqflags.h>
17
18 #include <asm/addrspace.h>
19 #include <asm/barrier.h>
20 #include <asm/cpu-features.h>
21 #include <asm/dsp.h>
22 #include <asm/ptrace.h>
23 #include <asm/war.h>
24
25
26 /*
27 * switch_to(n) should switch tasks to task nr n, first
28 * checking that n isn't the current task, in which case it does nothing.
29 */
30 extern asmlinkage void *resume(void *last, void *next, void *next_ti);
31
32 struct task_struct;
33
34 #ifdef CONFIG_MIPS_MT_FPAFF
35
36 /*
37 * Handle the scheduler resume end of FPU affinity management. We do this
38 * inline to try to keep the overhead down. If we have been forced to run on
39 * a "CPU" with an FPU because of a previous high level of FP computation,
40 * but did not actually use the FPU during the most recent time-slice (CU1
41 * isn't set), we undo the restriction on cpus_allowed.
42 *
43 * We're not calling set_cpus_allowed() here, because we have no need to
44 * force prompt migration - we're already switching the current CPU to a
45 * different thread.
46 */
47
48 #define switch_to(prev,next,last) \
49 do { \
50 if (cpu_has_fpu && \
51 (prev->thread.mflags & MF_FPUBOUND) && \
52 (!(KSTK_STATUS(prev) & ST0_CU1))) { \
53 prev->thread.mflags &= ~MF_FPUBOUND; \
54 prev->cpus_allowed = prev->thread.user_cpus_allowed; \
55 } \
56 if (cpu_has_dsp) \
57 __save_dsp(prev); \
58 next->thread.emulated_fp = 0; \
59 (last) = resume(prev, next, next->thread_info); \
60 if (cpu_has_dsp) \
61 __restore_dsp(current); \
62 } while(0)
63
64 #else
65 #define switch_to(prev,next,last) \
66 do { \
67 if (cpu_has_dsp) \
68 __save_dsp(prev); \
69 (last) = resume(prev, next, task_thread_info(next)); \
70 if (cpu_has_dsp) \
71 __restore_dsp(current); \
72 } while(0)
73 #endif
74
75 /*
76 * On SMP systems, when the scheduler does migration-cost autodetection,
77 * it needs a way to flush as much of the CPU's caches as possible.
78 *
79 * TODO: fill this in!
80 */
81 static inline void sched_cacheflush(void)
82 {
83 }
84
85 static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
86 {
87 __u32 retval;
88
89 if (cpu_has_llsc && R10000_LLSC_WAR) {
90 unsigned long dummy;
91
92 __asm__ __volatile__(
93 " .set mips3 \n"
94 "1: ll %0, %3 # xchg_u32 \n"
95 " .set mips0 \n"
96 " move %2, %z4 \n"
97 " .set mips3 \n"
98 " sc %2, %1 \n"
99 " beqzl %2, 1b \n"
100 " .set mips0 \n"
101 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
102 : "R" (*m), "Jr" (val)
103 : "memory");
104 } else if (cpu_has_llsc) {
105 unsigned long dummy;
106
107 __asm__ __volatile__(
108 " .set mips3 \n"
109 "1: ll %0, %3 # xchg_u32 \n"
110 " .set mips0 \n"
111 " move %2, %z4 \n"
112 " .set mips3 \n"
113 " sc %2, %1 \n"
114 " beqz %2, 1b \n"
115 " .set mips0 \n"
116 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
117 : "R" (*m), "Jr" (val)
118 : "memory");
119 } else {
120 unsigned long flags;
121
122 local_irq_save(flags);
123 retval = *m;
124 *m = val;
125 local_irq_restore(flags); /* implies memory barrier */
126 }
127
128 smp_mb();
129
130 return retval;
131 }
132
133 #ifdef CONFIG_64BIT
134 static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
135 {
136 __u64 retval;
137
138 if (cpu_has_llsc && R10000_LLSC_WAR) {
139 unsigned long dummy;
140
141 __asm__ __volatile__(
142 " .set mips3 \n"
143 "1: lld %0, %3 # xchg_u64 \n"
144 " move %2, %z4 \n"
145 " scd %2, %1 \n"
146 " beqzl %2, 1b \n"
147 " .set mips0 \n"
148 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
149 : "R" (*m), "Jr" (val)
150 : "memory");
151 } else if (cpu_has_llsc) {
152 unsigned long dummy;
153
154 __asm__ __volatile__(
155 " .set mips3 \n"
156 "1: lld %0, %3 # xchg_u64 \n"
157 " move %2, %z4 \n"
158 " scd %2, %1 \n"
159 " beqz %2, 1b \n"
160 " .set mips0 \n"
161 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
162 : "R" (*m), "Jr" (val)
163 : "memory");
164 } else {
165 unsigned long flags;
166
167 local_irq_save(flags);
168 retval = *m;
169 *m = val;
170 local_irq_restore(flags); /* implies memory barrier */
171 }
172
173 smp_mb();
174
175 return retval;
176 }
177 #else
178 extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
179 #define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
180 #endif
181
182 /* This function doesn't exist, so you'll get a linker error
183 if something tries to do an invalid xchg(). */
184 extern void __xchg_called_with_bad_pointer(void);
185
186 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
187 {
188 switch (size) {
189 case 4:
190 return __xchg_u32(ptr, x);
191 case 8:
192 return __xchg_u64(ptr, x);
193 }
194 __xchg_called_with_bad_pointer();
195 return x;
196 }
197
198 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
199 #define tas(ptr) (xchg((ptr),1))
200
201 #define __HAVE_ARCH_CMPXCHG 1
202
203 static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
204 unsigned long new)
205 {
206 __u32 retval;
207
208 if (cpu_has_llsc && R10000_LLSC_WAR) {
209 __asm__ __volatile__(
210 " .set push \n"
211 " .set noat \n"
212 " .set mips3 \n"
213 "1: ll %0, %2 # __cmpxchg_u32 \n"
214 " bne %0, %z3, 2f \n"
215 " .set mips0 \n"
216 " move $1, %z4 \n"
217 " .set mips3 \n"
218 " sc $1, %1 \n"
219 " beqzl $1, 1b \n"
220 "2: \n"
221 " .set pop \n"
222 : "=&r" (retval), "=R" (*m)
223 : "R" (*m), "Jr" (old), "Jr" (new)
224 : "memory");
225 } else if (cpu_has_llsc) {
226 __asm__ __volatile__(
227 " .set push \n"
228 " .set noat \n"
229 " .set mips3 \n"
230 "1: ll %0, %2 # __cmpxchg_u32 \n"
231 " bne %0, %z3, 2f \n"
232 " .set mips0 \n"
233 " move $1, %z4 \n"
234 " .set mips3 \n"
235 " sc $1, %1 \n"
236 " beqz $1, 1b \n"
237 "2: \n"
238 " .set pop \n"
239 : "=&r" (retval), "=R" (*m)
240 : "R" (*m), "Jr" (old), "Jr" (new)
241 : "memory");
242 } else {
243 unsigned long flags;
244
245 local_irq_save(flags);
246 retval = *m;
247 if (retval == old)
248 *m = new;
249 local_irq_restore(flags); /* implies memory barrier */
250 }
251
252 smp_mb();
253
254 return retval;
255 }
256
257 #ifdef CONFIG_64BIT
258 static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
259 unsigned long new)
260 {
261 __u64 retval;
262
263 if (cpu_has_llsc && R10000_LLSC_WAR) {
264 __asm__ __volatile__(
265 " .set push \n"
266 " .set noat \n"
267 " .set mips3 \n"
268 "1: lld %0, %2 # __cmpxchg_u64 \n"
269 " bne %0, %z3, 2f \n"
270 " move $1, %z4 \n"
271 " scd $1, %1 \n"
272 " beqzl $1, 1b \n"
273 "2: \n"
274 " .set pop \n"
275 : "=&r" (retval), "=R" (*m)
276 : "R" (*m), "Jr" (old), "Jr" (new)
277 : "memory");
278 } else if (cpu_has_llsc) {
279 __asm__ __volatile__(
280 " .set push \n"
281 " .set noat \n"
282 " .set mips3 \n"
283 "1: lld %0, %2 # __cmpxchg_u64 \n"
284 " bne %0, %z3, 2f \n"
285 " move $1, %z4 \n"
286 " scd $1, %1 \n"
287 " beqz $1, 1b \n"
288 "2: \n"
289 " .set pop \n"
290 : "=&r" (retval), "=R" (*m)
291 : "R" (*m), "Jr" (old), "Jr" (new)
292 : "memory");
293 } else {
294 unsigned long flags;
295
296 local_irq_save(flags);
297 retval = *m;
298 if (retval == old)
299 *m = new;
300 local_irq_restore(flags); /* implies memory barrier */
301 }
302
303 smp_mb();
304
305 return retval;
306 }
307 #else
308 extern unsigned long __cmpxchg_u64_unsupported_on_32bit_kernels(
309 volatile int * m, unsigned long old, unsigned long new);
310 #define __cmpxchg_u64 __cmpxchg_u64_unsupported_on_32bit_kernels
311 #endif
312
313 /* This function doesn't exist, so you'll get a linker error
314 if something tries to do an invalid cmpxchg(). */
315 extern void __cmpxchg_called_with_bad_pointer(void);
316
317 static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
318 unsigned long new, int size)
319 {
320 switch (size) {
321 case 4:
322 return __cmpxchg_u32(ptr, old, new);
323 case 8:
324 return __cmpxchg_u64(ptr, old, new);
325 }
326 __cmpxchg_called_with_bad_pointer();
327 return old;
328 }
329
330 #define cmpxchg(ptr,old,new) ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))
331
332 extern void set_handler (unsigned long offset, void *addr, unsigned long len);
333 extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len);
334 extern void *set_vi_handler (int n, void *addr);
335 extern void *set_except_vector(int n, void *addr);
336 extern unsigned long ebase;
337 extern void per_cpu_trap_init(void);
338
339 extern NORET_TYPE void die(const char *, struct pt_regs *);
340
341 static inline void die_if_kernel(const char *str, struct pt_regs *regs)
342 {
343 if (unlikely(!user_mode(regs)))
344 die(str, regs);
345 }
346
347 extern int stop_a_enabled;
348
349 /*
350 * See include/asm-ia64/system.h; prevents deadlock on SMP
351 * systems.
352 */
353 #define __ARCH_WANT_UNLOCKED_CTXSW
354
355 #define arch_align_stack(x) (x)
356
357 #endif /* _ASM_SYSTEM_H */
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