include/asm-ppc64/system.h

   1 #ifndef __PPC64_SYSTEM_H
   2 #define __PPC64_SYSTEM_H
   3
   4 /*
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version
   8  * 2 of the License, or (at your option) any later version.
   9  */
  10
  11 #include <linux/config.h>
  12 #include <linux/compiler.h>
  13 #include <asm/page.h>
  14 #include <asm/processor.h>
  15 #include <asm/hw_irq.h>
  16 #include <asm/synch.h>
  17
  18 /*
  19  * Memory barrier.
  20  * The sync instruction guarantees that all memory accesses initiated
  21  * by this processor have been performed (with respect to all other
  22  * mechanisms that access memory).  The eieio instruction is a barrier
  23  * providing an ordering (separately) for (a) cacheable stores and (b)
  24  * loads and stores to non-cacheable memory (e.g. I/O devices).
  25  *
  26  * mb() prevents loads and stores being reordered across this point.
  27  * rmb() prevents loads being reordered across this point.
  28  * wmb() prevents stores being reordered across this point.
  29  * read_barrier_depends() prevents data-dependent loads being reordered
  30  *      across this point (nop on PPC).
  31  *
  32  * We have to use the sync instructions for mb(), since lwsync doesn't
  33  * order loads with respect to previous stores.  Lwsync is fine for
  34  * rmb(), though.
  35  * For wmb(), we use sync since wmb is used in drivers to order
  36  * stores to system memory with respect to writes to the device.
  37  * However, smp_wmb() can be a lighter-weight eieio barrier on
  38  * SMP since it is only used to order updates to system memory.
  39  */
  40 #define mb()   __asm__ __volatile__ ("sync" : : : "memory")
  41 #define rmb()  __asm__ __volatile__ ("lwsync" : : : "memory")
  42 #define wmb()  __asm__ __volatile__ ("sync" : : : "memory")
  43 #define read_barrier_depends()  do { } while(0)
  44
  45 #define set_mb(var, value)      do { var = value; smp_mb(); } while (0)
  46 #define set_wmb(var, value)     do { var = value; smp_wmb(); } while (0)
  47
  48 #ifdef CONFIG_SMP
  49 #define smp_mb()        mb()
  50 #define smp_rmb()       rmb()
  51 #define smp_wmb()       eieio()
  52 #define smp_read_barrier_depends()  read_barrier_depends()
  53 #else
  54 #define smp_mb()        __asm__ __volatile__("": : :"memory")
  55 #define smp_rmb()       __asm__ __volatile__("": : :"memory")
  56 #define smp_wmb()       __asm__ __volatile__("": : :"memory")
  57 #define smp_read_barrier_depends()  do { } while(0)
  58 #endif /* CONFIG_SMP */
  59
  60 #ifdef __KERNEL__
  61 struct task_struct;
  62 struct pt_regs;
  63
  64 #ifdef CONFIG_DEBUGGER
  65
  66 extern int (*__debugger)(struct pt_regs *regs);
  67 extern int (*__debugger_ipi)(struct pt_regs *regs);
  68 extern int (*__debugger_bpt)(struct pt_regs *regs);
  69 extern int (*__debugger_sstep)(struct pt_regs *regs);
  70 extern int (*__debugger_iabr_match)(struct pt_regs *regs);
  71 extern int (*__debugger_dabr_match)(struct pt_regs *regs);
  72 extern int (*__debugger_fault_handler)(struct pt_regs *regs);
  73
  74 #define DEBUGGER_BOILERPLATE(__NAME) \
  75 static inline int __NAME(struct pt_regs *regs) \
  76 { \
  77         if (unlikely(__ ## __NAME)) \
  78                 return __ ## __NAME(regs); \
  79         return 0; \
  80 }
  81
  82 DEBUGGER_BOILERPLATE(debugger)
  83 DEBUGGER_BOILERPLATE(debugger_ipi)
  84 DEBUGGER_BOILERPLATE(debugger_bpt)
  85 DEBUGGER_BOILERPLATE(debugger_sstep)
  86 DEBUGGER_BOILERPLATE(debugger_iabr_match)
  87 DEBUGGER_BOILERPLATE(debugger_dabr_match)
  88 DEBUGGER_BOILERPLATE(debugger_fault_handler)
  89
  90 #ifdef CONFIG_XMON
  91 extern void xmon_init(int enable);
  92 #endif
  93
  94 #else
  95 static inline int debugger(struct pt_regs *regs) { return 0; }
  96 static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
  97 static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
  98 static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
  99 static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
 100 static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
 101 static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
 102 #endif
 103
 104 extern int set_dabr(unsigned long dabr);
 105 extern void _exception(int signr, struct pt_regs *regs, int code,
 106                        unsigned long addr);
 107 extern int fix_alignment(struct pt_regs *regs);
 108 extern void bad_page_fault(struct pt_regs *regs, unsigned long address,
 109                            int sig);
 110 extern void show_regs(struct pt_regs * regs);
 111 extern void low_hash_fault(struct pt_regs *regs, unsigned long address);
 112 extern int die(const char *str, struct pt_regs *regs, long err);
 113
 114 extern int _get_PVR(void);
 115 extern void giveup_fpu(struct task_struct *);
 116 extern void disable_kernel_fp(void);
 117 extern void flush_fp_to_thread(struct task_struct *);
 118 extern void enable_kernel_fp(void);
 119 extern void giveup_altivec(struct task_struct *);
 120 extern void disable_kernel_altivec(void);
 121 extern void enable_kernel_altivec(void);
 122 extern int emulate_altivec(struct pt_regs *);
 123 extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
 124 extern void cvt_df(double *from, float *to, struct thread_struct *thread);
 125
 126 #ifdef CONFIG_ALTIVEC
 127 extern void flush_altivec_to_thread(struct task_struct *);
 128 #else
 129 static inline void flush_altivec_to_thread(struct task_struct *t)
 130 {
 131 }
 132 #endif
 133
 134 static inline void flush_spe_to_thread(struct task_struct *t)
 135 {
 136 }
 137
 138 extern int mem_init_done;       /* set on boot once kmalloc can be called */
 139
 140 /* EBCDIC -> ASCII conversion for [0-9A-Z] on iSeries */
 141 extern unsigned char e2a(unsigned char);
 142
 143 extern struct task_struct *__switch_to(struct task_struct *,
 144                                        struct task_struct *);
 145 #define switch_to(prev, next, last)     ((last) = __switch_to((prev), (next)))
 146
 147 struct thread_struct;
 148 extern struct task_struct * _switch(struct thread_struct *prev,
 149                                     struct thread_struct *next);
 150
 151 extern int powersave_nap;       /* set if nap mode can be used in idle loop */
 152
 153 /*
 154  * Atomic exchange
 155  *
 156  * Changes the memory location '*ptr' to be val and returns
 157  * the previous value stored there.
 158  *
 159  * Inline asm pulled from arch/ppc/kernel/misc.S so ppc64
 160  * is more like most of the other architectures.
 161  */
 162 static __inline__ unsigned long
 163 __xchg_u32(volatile unsigned int *m, unsigned long val)
 164 {
 165         unsigned long dummy;
 166
 167         __asm__ __volatile__(
 168         EIEIO_ON_SMP
 169 "1:     lwarx %0,0,%3           # __xchg_u32\n\
 170         stwcx. %2,0,%3\n\
 171 2:      bne- 1b"
 172         ISYNC_ON_SMP
 173         : "=&r" (dummy), "=m" (*m)
 174         : "r" (val), "r" (m)
 175         : "cc", "memory");
 176
 177         return (dummy);
 178 }
 179
 180 static __inline__ unsigned long
 181 __xchg_u64(volatile long *m, unsigned long val)
 182 {
 183         unsigned long dummy;
 184
 185         __asm__ __volatile__(
 186         EIEIO_ON_SMP
 187 "1:     ldarx %0,0,%3           # __xchg_u64\n\
 188         stdcx. %2,0,%3\n\
 189 2:      bne- 1b"
 190         ISYNC_ON_SMP
 191         : "=&r" (dummy), "=m" (*m)
 192         : "r" (val), "r" (m)
 193         : "cc", "memory");
 194
 195         return (dummy);
 196 }
 197
 198 /*
 199  * This function doesn't exist, so you'll get a linker error
 200  * if something tries to do an invalid xchg().
 201  */
 202 extern void __xchg_called_with_bad_pointer(void);
 203
 204 static __inline__ unsigned long
 205 __xchg(volatile void *ptr, unsigned long x, unsigned int size)
 206 {
 207         switch (size) {
 208         case 4:
 209                 return __xchg_u32(ptr, x);
 210         case 8:
 211                 return __xchg_u64(ptr, x);
 212         }
 213         __xchg_called_with_bad_pointer();
 214         return x;
 215 }
 216
 217 #define xchg(ptr,x)                                                          \
 218   ({                                                                         \
 219      __typeof__(*(ptr)) _x_ = (x);                                           \
 220      (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
 221   })
 222
 223 #define tas(ptr) (xchg((ptr),1))
 224
 225 #define __HAVE_ARCH_CMPXCHG     1
 226
 227 static __inline__ unsigned long
 228 __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
 229 {
 230         unsigned int prev;
 231
 232         __asm__ __volatile__ (
 233         EIEIO_ON_SMP
 234 "1:     lwarx   %0,0,%2         # __cmpxchg_u32\n\
 235         cmpw    0,%0,%3\n\
 236         bne-    2f\n\
 237         stwcx.  %4,0,%2\n\
 238         bne-    1b"
 239         ISYNC_ON_SMP
 240         "\n\
 241 2:"
 242         : "=&r" (prev), "=m" (*p)
 243         : "r" (p), "r" (old), "r" (new), "m" (*p)
 244         : "cc", "memory");
 245
 246         return prev;
 247 }
 248
 249 static __inline__ unsigned long
 250 __cmpxchg_u64(volatile long *p, unsigned long old, unsigned long new)
 251 {
 252         unsigned long prev;
 253
 254         __asm__ __volatile__ (
 255         EIEIO_ON_SMP
 256 "1:     ldarx   %0,0,%2         # __cmpxchg_u64\n\
 257         cmpd    0,%0,%3\n\
 258         bne-    2f\n\
 259         stdcx.  %4,0,%2\n\
 260         bne-    1b"
 261         ISYNC_ON_SMP
 262         "\n\
 263 2:"
 264         : "=&r" (prev), "=m" (*p)
 265         : "r" (p), "r" (old), "r" (new), "m" (*p)
 266         : "cc", "memory");
 267
 268         return prev;
 269 }
 270
 271 /* This function doesn't exist, so you'll get a linker error
 272    if something tries to do an invalid cmpxchg().  */
 273 extern void __cmpxchg_called_with_bad_pointer(void);
 274
 275 static __inline__ unsigned long
 276 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
 277           unsigned int size)
 278 {
 279         switch (size) {
 280         case 4:
 281                 return __cmpxchg_u32(ptr, old, new);
 282         case 8:
 283                 return __cmpxchg_u64(ptr, old, new);
 284         }
 285         __cmpxchg_called_with_bad_pointer();
 286         return old;
 287 }
 288
 289 #define cmpxchg(ptr,o,n)\
 290         ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
 291         (unsigned long)(n),sizeof(*(ptr))))
 292
 293 /*
 294  * We handle most unaligned accesses in hardware. On the other hand
 295  * unaligned DMA can be very expensive on some ppc64 IO chips (it does
 296  * powers of 2 writes until it reaches sufficient alignment).
 297  *
 298  * Based on this we disable the IP header alignment in network drivers.
 299  */
 300 #define NET_IP_ALIGN   0
 301
 302 #define arch_align_stack(x) (x)
 303
 304 extern unsigned long reloc_offset(void);
 305
 306 #endif /* __KERNEL__ */
 307 #endif