include/asm-s390/smp.h

   1 /*
   2  *  include/asm-s390/smp.h
   3  *
   4  *  S390 version
   5  *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
   6  *    Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
   7  *               Martin Schwidefsky (schwidefsky@de.ibm.com)
   8  *               Heiko Carstens (heiko.carstens@de.ibm.com)
   9  */
  10 #ifndef __ASM_SMP_H
  11 #define __ASM_SMP_H
  12
  13 #include <linux/threads.h>
  14 #include <linux/cpumask.h>
  15 #include <linux/bitops.h>
  16
  17 #if defined(__KERNEL__) && defined(CONFIG_SMP) && !defined(__ASSEMBLY__)
  18
  19 #include <asm/lowcore.h>
  20 #include <asm/sigp.h>
  21 #include <asm/ptrace.h>
  22
  23 /*
  24   s390 specific smp.c headers
  25  */
  26 typedef struct
  27 {
  28         int        intresting;
  29         sigp_ccode ccode;
  30         __u32      status;
  31         __u16      cpu;
  32 } sigp_info;
  33
  34 extern void machine_restart_smp(char *);
  35 extern void machine_halt_smp(void);
  36 extern void machine_power_off_smp(void);
  37
  38 extern void smp_setup_cpu_possible_map(void);
  39 extern int smp_call_function_on(void (*func) (void *info), void *info,
  40                                 int nonatomic, int wait, int cpu);
  41 #define NO_PROC_ID              0xFF            /* No processor magic marker */
  42
  43 /*
  44  *      This magic constant controls our willingness to transfer
  45  *      a process across CPUs. Such a transfer incurs misses on the L1
  46  *      cache, and on a P6 or P5 with multiple L2 caches L2 hits. My
  47  *      gut feeling is this will vary by board in value. For a board
  48  *      with separate L2 cache it probably depends also on the RSS, and
  49  *      for a board with shared L2 cache it ought to decay fast as other
  50  *      processes are run.
  51  */
  52
  53 #define PROC_CHANGE_PENALTY     20              /* Schedule penalty */
  54
  55 #define raw_smp_processor_id()  (S390_lowcore.cpu_data.cpu_nr)
  56
  57 static inline __u16 hard_smp_processor_id(void)
  58 {
  59         __u16 cpu_address;
  60
  61         asm volatile("stap %0" : "=m" (cpu_address));
  62         return cpu_address;
  63 }
  64
  65 /*
  66  * returns 1 if cpu is in stopped/check stopped state or not operational
  67  * returns 0 otherwise
  68  */
  69 static inline int
  70 smp_cpu_not_running(int cpu)
  71 {
  72         __u32 status;
  73
  74         switch (signal_processor_ps(&status, 0, cpu, sigp_sense)) {
  75         case sigp_order_code_accepted:
  76         case sigp_status_stored:
  77                 /* Check for stopped and check stop state */
  78                 if (status & 0x50)
  79                         return 1;
  80                 break;
  81         case sigp_not_operational:
  82                 return 1;
  83         default:
  84                 break;
  85         }
  86         return 0;
  87 }
  88
  89 #define cpu_logical_map(cpu) (cpu)
  90
  91 extern int __cpu_disable (void);
  92 extern void __cpu_die (unsigned int cpu);
  93 extern void cpu_die (void) __attribute__ ((noreturn));
  94 extern int __cpu_up (unsigned int cpu);
  95
  96 #endif
  97
  98 #ifndef CONFIG_SMP
  99 static inline int
 100 smp_call_function_on(void (*func) (void *info), void *info,
 101                      int nonatomic, int wait, int cpu)
 102 {
 103         func(info);
 104         return 0;
 105 }
 106
 107 static inline void smp_send_stop(void)
 108 {
 109         /* Disable all interrupts/machine checks */
 110         __load_psw_mask(psw_kernel_bits & ~PSW_MASK_MCHECK);
 111 }
 112
 113 #define hard_smp_processor_id()         0
 114 #define smp_cpu_not_running(cpu)        1
 115 #define smp_setup_cpu_possible_map()    do { } while (0)
 116 #endif
 117
 118 extern union save_area *zfcpdump_save_areas[NR_CPUS + 1];
 119 #endif