include/asm-sh/hw_irq.h

   1 #ifndef __ASM_SH_HW_IRQ_H
   2 #define __ASM_SH_HW_IRQ_H
   3
   4 #include <linux/init.h>
   5 #include <asm/atomic.h>
   6
   7 extern atomic_t irq_err_count;
   8
   9 struct intc2_data {
  10         unsigned short irq;
  11         unsigned char ipr_offset, ipr_shift;
  12         unsigned char msk_offset, msk_shift;
  13         unsigned char priority;
  14 };
  15
  16 struct intc2_desc {
  17         unsigned long prio_base;
  18         unsigned long msk_base;
  19         unsigned long mskclr_base;
  20         struct intc2_data *intc2_data;
  21         unsigned int nr_irqs;
  22         struct irq_chip chip;
  23 };
  24
  25 void register_intc2_controller(struct intc2_desc *);
  26 void init_IRQ_intc2(void);
  27
  28 struct ipr_data {
  29         unsigned char irq;
  30         unsigned char ipr_idx;          /* Index for the IPR registered */
  31         unsigned char shift;            /* Number of bits to shift the data */
  32         unsigned char priority;         /* The priority */
  33 };
  34
  35 struct ipr_desc {
  36         unsigned long *ipr_offsets;
  37         unsigned int nr_offsets;
  38         struct ipr_data *ipr_data;
  39         unsigned int nr_irqs;
  40         struct irq_chip chip;
  41 };
  42
  43 void register_ipr_controller(struct ipr_desc *);
  44 void init_IRQ_ipr(void);
  45
  46 /*
  47  * Enable individual interrupt mode for external IPR IRQs.
  48  */
  49 void ipr_irq_enable_irlm(void);
  50
  51 typedef unsigned char intc_enum;
  52
  53 struct intc_vect {
  54         intc_enum enum_id;
  55         unsigned short vect;
  56 };
  57
  58 #define INTC_VECT(enum_id, vect) { enum_id, vect }
  59
  60 struct intc_prio {
  61         intc_enum enum_id;
  62         unsigned char priority;
  63 };
  64
  65 #define INTC_PRIO(enum_id, prio) { enum_id, prio }
  66
  67 struct intc_group {
  68         intc_enum enum_id;
  69         intc_enum *enum_ids;
  70 };
  71
  72 #define INTC_GROUP(enum_id, ids...) { enum_id, (intc_enum []) { ids, 0 } }
  73
  74 struct intc_mask_reg {
  75         unsigned long set_reg, clr_reg, reg_width;
  76         intc_enum enum_ids[32];
  77 };
  78
  79 struct intc_prio_reg {
  80         unsigned long reg, reg_width, field_width;
  81         intc_enum enum_ids[16];
  82 };
  83
  84 struct intc_sense_reg {
  85         unsigned long reg, reg_width, field_width;
  86         intc_enum enum_ids[16];
  87 };
  88
  89 struct intc_desc {
  90         struct intc_vect *vectors;
  91         unsigned int nr_vectors;
  92         struct intc_group *groups;
  93         unsigned int nr_groups;
  94         struct intc_prio *priorities;
  95         unsigned int nr_priorities;
  96         struct intc_mask_reg *mask_regs;
  97         unsigned int nr_mask_regs;
  98         struct intc_prio_reg *prio_regs;
  99         unsigned int nr_prio_regs;
 100         struct intc_sense_reg *sense_regs;
 101         unsigned int nr_sense_regs;
 102         struct irq_chip chip;
 103 };
 104
 105 #define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
 106 #define DECLARE_INTC_DESC(symbol, chipname, vectors, groups,            \
 107         priorities, mask_regs, prio_regs, sense_regs)                   \
 108 struct intc_desc symbol = {                                             \
 109         _INTC_ARRAY(vectors), _INTC_ARRAY(groups),                      \
 110         _INTC_ARRAY(priorities),                                        \
 111         _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs),                 \
 112         _INTC_ARRAY(sense_regs),                                        \
 113         .chip.name = chipname,                                          \
 114 }
 115
 116 void __init register_intc_controller(struct intc_desc *desc);
 117
 118 #endif /* __ASM_SH_HW_IRQ_H */