include/asm-x86/amd_iommu_types.h

   1 /*
   2  * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
   3  * Author: Joerg Roedel <joerg.roedel@amd.com>
   4  *         Leo Duran <leo.duran@amd.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18  */
  19
  20 #ifndef __AMD_IOMMU_TYPES_H__
  21 #define __AMD_IOMMU_TYPES_H__
  22
  23 #include <linux/types.h>
  24 #include <linux/list.h>
  25 #include <linux/spinlock.h>
  26
  27 /*
  28  * some size calculation constants
  29  */
  30 #define DEV_TABLE_ENTRY_SIZE            32
  31 #define ALIAS_TABLE_ENTRY_SIZE          2
  32 #define RLOOKUP_TABLE_ENTRY_SIZE        (sizeof(void *))
  33
  34 /* Length of the MMIO region for the AMD IOMMU */
  35 #define MMIO_REGION_LENGTH       0x4000
  36
  37 /* Capability offsets used by the driver */
  38 #define MMIO_CAP_HDR_OFFSET     0x00
  39 #define MMIO_RANGE_OFFSET       0x0c
  40
  41 /* Masks, shifts and macros to parse the device range capability */
  42 #define MMIO_RANGE_LD_MASK      0xff000000
  43 #define MMIO_RANGE_FD_MASK      0x00ff0000
  44 #define MMIO_RANGE_BUS_MASK     0x0000ff00
  45 #define MMIO_RANGE_LD_SHIFT     24
  46 #define MMIO_RANGE_FD_SHIFT     16
  47 #define MMIO_RANGE_BUS_SHIFT    8
  48 #define MMIO_GET_LD(x)  (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
  49 #define MMIO_GET_FD(x)  (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
  50 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
  51
  52 /* Flag masks for the AMD IOMMU exclusion range */
  53 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
  54 #define MMIO_EXCL_ALLOW_MASK  0x02ULL
  55
  56 /* Used offsets into the MMIO space */
  57 #define MMIO_DEV_TABLE_OFFSET   0x0000
  58 #define MMIO_CMD_BUF_OFFSET     0x0008
  59 #define MMIO_EVT_BUF_OFFSET     0x0010
  60 #define MMIO_CONTROL_OFFSET     0x0018
  61 #define MMIO_EXCL_BASE_OFFSET   0x0020
  62 #define MMIO_EXCL_LIMIT_OFFSET  0x0028
  63 #define MMIO_CMD_HEAD_OFFSET    0x2000
  64 #define MMIO_CMD_TAIL_OFFSET    0x2008
  65 #define MMIO_EVT_HEAD_OFFSET    0x2010
  66 #define MMIO_EVT_TAIL_OFFSET    0x2018
  67 #define MMIO_STATUS_OFFSET      0x2020
  68
  69 /* MMIO status bits */
  70 #define MMIO_STATUS_COM_WAIT_INT_MASK   0x04
  71
  72 /* feature control bits */
  73 #define CONTROL_IOMMU_EN        0x00ULL
  74 #define CONTROL_HT_TUN_EN       0x01ULL
  75 #define CONTROL_EVT_LOG_EN      0x02ULL
  76 #define CONTROL_EVT_INT_EN      0x03ULL
  77 #define CONTROL_COMWAIT_EN      0x04ULL
  78 #define CONTROL_PASSPW_EN       0x08ULL
  79 #define CONTROL_RESPASSPW_EN    0x09ULL
  80 #define CONTROL_COHERENT_EN     0x0aULL
  81 #define CONTROL_ISOC_EN         0x0bULL
  82 #define CONTROL_CMDBUF_EN       0x0cULL
  83 #define CONTROL_PPFLOG_EN       0x0dULL
  84 #define CONTROL_PPFINT_EN       0x0eULL
  85
  86 /* command specific defines */
  87 #define CMD_COMPL_WAIT          0x01
  88 #define CMD_INV_DEV_ENTRY       0x02
  89 #define CMD_INV_IOMMU_PAGES     0x03
  90
  91 #define CMD_COMPL_WAIT_STORE_MASK       0x01
  92 #define CMD_COMPL_WAIT_INT_MASK         0x02
  93 #define CMD_INV_IOMMU_PAGES_SIZE_MASK   0x01
  94 #define CMD_INV_IOMMU_PAGES_PDE_MASK    0x02
  95
  96 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
  97
  98 /* macros and definitions for device table entries */
  99 #define DEV_ENTRY_VALID         0x00
 100 #define DEV_ENTRY_TRANSLATION   0x01
 101 #define DEV_ENTRY_IR            0x3d
 102 #define DEV_ENTRY_IW            0x3e
 103 #define DEV_ENTRY_NO_PAGE_FAULT 0x62
 104 #define DEV_ENTRY_EX            0x67
 105 #define DEV_ENTRY_SYSMGT1       0x68
 106 #define DEV_ENTRY_SYSMGT2       0x69
 107 #define DEV_ENTRY_INIT_PASS     0xb8
 108 #define DEV_ENTRY_EINT_PASS     0xb9
 109 #define DEV_ENTRY_NMI_PASS      0xba
 110 #define DEV_ENTRY_LINT0_PASS    0xbe
 111 #define DEV_ENTRY_LINT1_PASS    0xbf
 112
 113 /* constants to configure the command buffer */
 114 #define CMD_BUFFER_SIZE    8192
 115 #define CMD_BUFFER_ENTRIES 512
 116 #define MMIO_CMD_SIZE_SHIFT 56
 117 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
 118
 119 /* constants for event buffer handling */
 120 #define EVT_BUFFER_SIZE         8192 /* 512 entries */
 121 #define EVT_LEN_MASK            (0x9ULL << 56)
 122
 123 #define PAGE_MODE_1_LEVEL 0x01
 124 #define PAGE_MODE_2_LEVEL 0x02
 125 #define PAGE_MODE_3_LEVEL 0x03
 126
 127 #define IOMMU_PDE_NL_0   0x000ULL
 128 #define IOMMU_PDE_NL_1   0x200ULL
 129 #define IOMMU_PDE_NL_2   0x400ULL
 130 #define IOMMU_PDE_NL_3   0x600ULL
 131
 132 #define IOMMU_PTE_L2_INDEX(address) (((address) >> 30) & 0x1ffULL)
 133 #define IOMMU_PTE_L1_INDEX(address) (((address) >> 21) & 0x1ffULL)
 134 #define IOMMU_PTE_L0_INDEX(address) (((address) >> 12) & 0x1ffULL)
 135
 136 #define IOMMU_MAP_SIZE_L1 (1ULL << 21)
 137 #define IOMMU_MAP_SIZE_L2 (1ULL << 30)
 138 #define IOMMU_MAP_SIZE_L3 (1ULL << 39)
 139
 140 #define IOMMU_PTE_P  (1ULL << 0)
 141 #define IOMMU_PTE_U  (1ULL << 59)
 142 #define IOMMU_PTE_FC (1ULL << 60)
 143 #define IOMMU_PTE_IR (1ULL << 61)
 144 #define IOMMU_PTE_IW (1ULL << 62)
 145
 146 #define IOMMU_L1_PDE(address) \
 147         ((address) | IOMMU_PDE_NL_1 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
 148 #define IOMMU_L2_PDE(address) \
 149         ((address) | IOMMU_PDE_NL_2 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
 150
 151 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
 152 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
 153 #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
 154 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
 155
 156 #define IOMMU_PROT_MASK 0x03
 157 #define IOMMU_PROT_IR 0x01
 158 #define IOMMU_PROT_IW 0x02
 159
 160 /* IOMMU capabilities */
 161 #define IOMMU_CAP_IOTLB   24
 162 #define IOMMU_CAP_NPCACHE 26
 163
 164 #define MAX_DOMAIN_ID 65536
 165
 166 /*
 167  * This structure contains generic data for  IOMMU protection domains
 168  * independent of their use.
 169  */
 170 struct protection_domain {
 171         spinlock_t lock; /* mostly used to lock the page table*/
 172         u16 id;          /* the domain id written to the device table */
 173         int mode;        /* paging mode (0-6 levels) */
 174         u64 *pt_root;    /* page table root pointer */
 175         void *priv;      /* private data */
 176 };
 177
 178 /*
 179  * Data container for a dma_ops specific protection domain
 180  */
 181 struct dma_ops_domain {
 182         struct list_head list;
 183
 184         /* generic protection domain information */
 185         struct protection_domain domain;
 186
 187         /* size of the aperture for the mappings */
 188         unsigned long aperture_size;
 189
 190         /* address we start to search for free addresses */
 191         unsigned long next_bit;
 192
 193         /* address allocation bitmap */
 194         unsigned long *bitmap;
 195
 196         /*
 197          * Array of PTE pages for the aperture. In this array we save all the
 198          * leaf pages of the domain page table used for the aperture. This way
 199          * we don't need to walk the page table to find a specific PTE. We can
 200          * just calculate its address in constant time.
 201          */
 202         u64 **pte_pages;
 203
 204         /* This will be set to true when TLB needs to be flushed */
 205         bool need_flush;
 206 };
 207
 208 /*
 209  * Structure where we save information about one hardware AMD IOMMU in the
 210  * system.
 211  */
 212 struct amd_iommu {
 213         struct list_head list;
 214
 215         /* locks the accesses to the hardware */
 216         spinlock_t lock;
 217
 218         /* Pointer to PCI device of this IOMMU */
 219         struct pci_dev *dev;
 220
 221         /*
 222          * Capability pointer. There could be more than one IOMMU per PCI
 223          * device function if there are more than one AMD IOMMU capability
 224          * pointers.
 225          */
 226         u16 cap_ptr;
 227
 228         /* physical address of MMIO space */
 229         u64 mmio_phys;
 230         /* virtual address of MMIO space */
 231         u8 *mmio_base;
 232
 233         /* capabilities of that IOMMU read from ACPI */
 234         u32 cap;
 235
 236         /* pci domain of this IOMMU */
 237         u16 pci_seg;
 238
 239         /* first device this IOMMU handles. read from PCI */
 240         u16 first_device;
 241         /* last device this IOMMU handles. read from PCI */
 242         u16 last_device;
 243
 244         /* start of exclusion range of that IOMMU */
 245         u64 exclusion_start;
 246         /* length of exclusion range of that IOMMU */
 247         u64 exclusion_length;
 248
 249         /* command buffer virtual address */
 250         u8 *cmd_buf;
 251         /* size of command buffer */
 252         u32 cmd_buf_size;
 253
 254         /* event buffer virtual address */
 255         u8 *evt_buf;
 256         /* size of event buffer */
 257         u32 evt_buf_size;
 258
 259         /* if one, we need to send a completion wait command */
 260         int need_sync;
 261
 262         /* default dma_ops domain for that IOMMU */
 263         struct dma_ops_domain *default_dom;
 264 };
 265
 266 /*
 267  * List with all IOMMUs in the system. This list is not locked because it is
 268  * only written and read at driver initialization or suspend time
 269  */
 270 extern struct list_head amd_iommu_list;
 271
 272 /*
 273  * Structure defining one entry in the device table
 274  */
 275 struct dev_table_entry {
 276         u32 data[8];
 277 };
 278
 279 /*
 280  * One entry for unity mappings parsed out of the ACPI table.
 281  */
 282 struct unity_map_entry {
 283         struct list_head list;
 284
 285         /* starting device id this entry is used for (including) */
 286         u16 devid_start;
 287         /* end device id this entry is used for (including) */
 288         u16 devid_end;
 289
 290         /* start address to unity map (including) */
 291         u64 address_start;
 292         /* end address to unity map (including) */
 293         u64 address_end;
 294
 295         /* required protection */
 296         int prot;
 297 };
 298
 299 /*
 300  * List of all unity mappings. It is not locked because as runtime it is only
 301  * read. It is created at ACPI table parsing time.
 302  */
 303 extern struct list_head amd_iommu_unity_map;
 304
 305 /*
 306  * Data structures for device handling
 307  */
 308
 309 /*
 310  * Device table used by hardware. Read and write accesses by software are
 311  * locked with the amd_iommu_pd_table lock.
 312  */
 313 extern struct dev_table_entry *amd_iommu_dev_table;
 314
 315 /*
 316  * Alias table to find requestor ids to device ids. Not locked because only
 317  * read on runtime.
 318  */
 319 extern u16 *amd_iommu_alias_table;
 320
 321 /*
 322  * Reverse lookup table to find the IOMMU which translates a specific device.
 323  */
 324 extern struct amd_iommu **amd_iommu_rlookup_table;
 325
 326 /* size of the dma_ops aperture as power of 2 */
 327 extern unsigned amd_iommu_aperture_order;
 328
 329 /* largest PCI device id we expect translation requests for */
 330 extern u16 amd_iommu_last_bdf;
 331
 332 /* data structures for protection domain handling */
 333 extern struct protection_domain **amd_iommu_pd_table;
 334
 335 /* allocation bitmap for domain ids */
 336 extern unsigned long *amd_iommu_pd_alloc_bitmap;
 337
 338 /* will be 1 if device isolation is enabled */
 339 extern int amd_iommu_isolate;
 340
 341 /* takes a PCI device id and prints it out in a readable form */
 342 static inline void print_devid(u16 devid, int nl)
 343 {
 344         int bus = devid >> 8;
 345         int dev = devid >> 3 & 0x1f;
 346         int fn  = devid & 0x07;
 347
 348         printk("%02x:%02x.%x", bus, dev, fn);
 349         if (nl)
 350                 printk("\n");
 351 }
 352
 353 /* takes bus and device/function and returns the device id
 354  * FIXME: should that be in generic PCI code? */
 355 static inline u16 calc_devid(u8 bus, u8 devfn)
 356 {
 357         return (((u16)bus) << 8) | devfn;
 358 }
 359
 360 #endif